WO2021114364A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2021114364A1
WO2021114364A1 PCT/CN2019/126838 CN2019126838W WO2021114364A1 WO 2021114364 A1 WO2021114364 A1 WO 2021114364A1 CN 2019126838 W CN2019126838 W CN 2019126838W WO 2021114364 A1 WO2021114364 A1 WO 2021114364A1
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Prior art keywords
electrode
main
sub
pixel electrode
pixel
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PCT/CN2019/126838
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English (en)
French (fr)
Inventor
曹武
张琪
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/627,349 priority Critical patent/US11281055B2/en
Publication of WO2021114364A1 publication Critical patent/WO2021114364A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • the 4-domain area design in a pixel unit is generally changed to an 8-domain area design, which has different driving voltage differences by setting The main domain zone 11 and sub-domain zone 12, the main domain zone 11 and the sub-domain zone 12 respectively contain 4 axially symmetrical domain zones.
  • the main domain zone 11 and sub-domain zone 12 respectively contain 4 axially symmetrical domain zones.
  • the PE electrode located in the main domain area 11 14 is provided with a metal shielding layer 15 around.
  • the metal shielding layer 15 is generally formed of an opaque material, which will cause the aperture ratio of the display panel to decrease.
  • the present application provides an array substrate to solve the technical problem that the metal shielding layer is generally formed of an opaque material, which will cause the aperture ratio of the display panel to decrease.
  • an array substrate which includes:
  • a plurality of scan lines arranged on the base substrate along the lateral direction and arranged side by side;
  • a plurality of data lines arranged on the base substrate along the longitudinal direction and arranged side by side;
  • each of the scan lines is arranged corresponding to a row of the pixel units
  • each of the data lines is arranged corresponding to a column of the pixel units, and two adjacent The data line defines the boundary of the pixel unit;
  • each of the pixel units has a main area and a sub-area
  • the pixel unit includes a main pixel electrode located in the main area and a sub-pixel electrode located in the sub-area, the main pixel electrode and the sub-pixel
  • the electrodes are arranged at intervals, and the sub-pixel electrode surrounds a portion of the main pixel electrode close to the data line.
  • the main pixel electrode includes a main electrode, and the main electrode defines a region where the main pixel electrode is located into a plurality of main domain regions, and each of the main domain regions is provided with a main
  • the sub-pixel electrode is a branch electrode electrically connected to the electrode;
  • the sub-pixel electrode includes an electrode backbone that defines the area where the sub-pixel electrode is located into a plurality of sub-domain regions, and each of the sub-domain regions is provided with the An electrode branch that is electrically connected to the electrode backbone.
  • the sub-pixel electrode includes a first split body and a second split body disposed on both sides of the first split body close to the data line, and the second split body extends along the data line.
  • the line extends in the length direction; a shielding area is formed between the first split body and the second split body, and the sub-pixel electrode is located in the shielding area.
  • the main pixel electrode includes a first main electrode and two divisions arranged at intervals, and the first main electrode defines the area where each division is located as two first main domain regions.
  • Each of the first main domain regions is provided with a first branch electrode electrically connected to the first main electrode.
  • the first split body includes two intersecting first electrode backbones, and the first main electrode limits the area where the first split body is located into four first subdomain regions, each Each of the first subdomain regions is provided with a first electrode branch electrically connected to the first electrode backbone.
  • the second sub-body includes sub-electrodes located on opposite sides of the main pixel electrode, and each sub-electrode includes two second sub-electrodes that define the area where the sub-electrodes are located.
  • the second electrode backbone of the domain region, each of the second subdomain regions is provided with a second electrode branch electrically connected to the second electrode backbone.
  • the main pixel electrode includes two intersecting second main electrodes, and the second main electrode limits the area where the main pixel electrode is located into four second main domain regions.
  • the second main domain regions are each provided with a second branch electrode electrically connected to the second main electrode.
  • the main pixel electrode includes two intersecting third main electrodes, and the third main electrode limits the area where the main pixel electrode is located into four third main domain regions;
  • the sub-pixel The electrode includes two split bodies respectively located on the two sides of the main pixel electrode close to the data line, and each split body includes a second sub-domain region defining the region where the split body is located.
  • the two separate bodies are arranged at intervals.
  • the two separate bodies are connected to each other, the sub-pixel electrode has a closed ring shape as a whole, and the main pixel electrode is located in a closed area defined by the sub-pixel electrode.
  • the data line includes a first side adjacent to the sub-pixel electrode, and the orthographic projection of the sub-pixel electrode on the base substrate covers the first side on the substrate. Orthographic projection on the bottom substrate.
  • the array substrate further includes a common electrode provided on the same layer as the scan line, and the orthographic projection of the branch electrode and the electrode branch on the base substrate is in line with the common electrode.
  • the orthographic projections on the base substrate do not overlap.
  • the branch electrodes are arranged obliquely and the edge lines of the branch electrodes form a first angle with the edge lines of the main electrodes; the electrode branches are arranged obliquely and the edge lines of the electrode branches A second included angle is formed with the edge line of the electrode backbone, and the first included angle and the second included angle are both 10 to 80 degrees.
  • the present application also provides a display panel, which includes a color filter substrate and an array substrate, and a liquid crystal layer is provided between the color filter substrate and the array substrate;
  • the array substrate includes:
  • a plurality of scan lines arranged on the base substrate along the lateral direction and arranged side by side;
  • a plurality of data lines arranged on the base substrate along the longitudinal direction and arranged side by side;
  • each of the scan lines is arranged corresponding to a row of the pixel units
  • each of the data lines is arranged corresponding to a column of the pixel units, and two adjacent The data line defines the boundary of the pixel unit;
  • each of the pixel units has a main area and a sub-area
  • the pixel unit includes a main pixel electrode located in the main area and a sub-pixel electrode located in the sub-area, the main pixel electrode and the sub-pixel
  • the electrodes are arranged at intervals, and the sub-pixel electrode surrounds a portion of the main pixel electrode close to the data line.
  • the main pixel electrode includes a main electrode, and the main electrode defines a region where the main pixel electrode is located into a plurality of main domain regions, and each of the main domain regions is provided with a main
  • the sub-pixel electrode is a branch electrode electrically connected to the electrode;
  • the sub-pixel electrode includes an electrode backbone that defines the area where the sub-pixel electrode is located into a plurality of sub-domain regions, and each of the sub-domain regions is provided with the An electrode branch that is electrically connected to the electrode backbone.
  • the sub-pixel electrode includes a first split body and a second split body disposed on both sides of the first split body close to the data line, and the second split body extends along the data line.
  • the line extends in the length direction; a shielding area is formed between the first split body and the second split body, and the sub-pixel electrode is located in the shielding area.
  • the main pixel electrode includes a first main electrode and two divisions arranged at intervals, and the first main electrode defines the area where each division is located as two first main domain regions.
  • Each of the first main domain regions is provided with a first branch electrode electrically connected to the first main electrode.
  • the first split body includes two intersecting first electrode backbones, and the first main electrode limits the area where the first split body is located into four first subdomain regions, each Each of the first subdomain regions is provided with a first electrode branch electrically connected to the first electrode backbone.
  • the second sub-body includes sub-electrodes located on opposite sides of the main pixel electrode, and each sub-electrode includes two second sub-electrodes that define the area where the sub-electrodes are located.
  • the second electrode backbone of the domain region, each of the second subdomain regions is provided with a second electrode branch electrically connected to the second electrode backbone.
  • the main pixel electrode includes two intersecting second main electrodes, and the second main electrode limits the area where the main pixel electrode is located into four second main domain regions.
  • the second main domain regions are each provided with a second branch electrode electrically connected to the second main electrode.
  • the physical keyboard input system includes a mobile terminal and a physical keyboard, and the physical keyboard is covered on the touch screen of the mobile terminal for The first touch information applied by the user on the button is converted into the second touch information applied to the touch screen;
  • the mobile terminal includes a detection device, a touch screen, a touch screen control chip and a processor, the detection device, the touch screen The processor is connected to the touch screen control chip at the same time.
  • This application achieves the purpose of using physical keys for text information input by directly covering the physical keyboard on the touch screen of the mobile terminal, and the physical keyboard does not need to be connected to a power source for driving, which achieves the effect of attaching and using, and reduces The cost and power consumption of mobile terminals.
  • FIG. 1 is a schematic diagram of the structure of a liquid crystal display panel in the background art of this application;
  • FIG. 2 is a schematic diagram of the structure of the array substrate in the first embodiment of this application.
  • FIG. 3 is a schematic diagram of the structure of the array substrate in the second embodiment of this application.
  • FIGS. 6 and 7 are schematic diagrams of the structure of the array substrate in the fourth embodiment of this application.
  • FIG. 8 is a schematic diagram of the structure of a display panel in an embodiment of the application.
  • Sub-pixel electrode 271, first sub-body; 2711, first electrode main body; 2712, first electrode branch; 272, second sub-body; 2721, second electrode main body; 2722, second electrode branch; 273.
  • the present application is directed to the existing array substrate, in order to shield the coupling capacitance formed between the data line and the pixel electrode located in the main domain area, the metal shielding layer is generally formed of opaque material, which will cause the aperture ratio of the display panel to decrease. technical problem. This application can solve the above-mentioned problems.
  • the array substrate 20 includes a base substrate 21, a plurality of scan lines 22 arranged side by side on the base substrate 21 in a transverse direction, and a plurality of scan lines 22 arranged in a longitudinal direction on the base substrate 21.
  • a plurality of data lines 23 arranged side by side on the base substrate 21 and a plurality of pixel units arrayed on the base substrate 21.
  • each of the scan lines 22 is arranged corresponding to a row of the pixel units
  • each of the data lines 23 is arranged corresponding to a column of the pixel units
  • two adjacent data lines 23 define the boundaries of the pixel units.
  • each pixel unit has a main area 24 and a sub-area 25.
  • the pixel unit includes a main pixel electrode 26 located in the main area 24 and a sub-pixel electrode 27 located in the sub-area 25.
  • the pixel electrode 26 and the sub-pixel electrode 27 are spaced apart, and the sub-pixel electrode 27 surrounds a portion of the main pixel electrode 26 close to the data line 23.
  • the sub-pixel electrode 27 is used to isolate and protect the interference between the main pixel electrode 26 and the data line 23, and prevent the data line 23 and the main pixel electrode 26 from being interfered.
  • a coupling capacitor is formed between them, so that the design of the metal shielding layer can be eliminated on the premise of preventing crosstalk problems, thereby greatly improving the aperture ratio and penetration rate of the array substrate 20.
  • the data line 23 includes a first side 231 disposed close to the sub-pixel electrode 27, and the orthographic projection of the sub-pixel electrode 27 on the base substrate 21 covers the first side 231.
  • the array substrate 20 is provided with a light shielding layer above the data line 23 to replace the light shielding effect of the black matrix, and the sub-pixel electrode 27 is connected to the second data line 23 corresponding to the light shielding layer.
  • One side 231 is overlapped to provide better shielding effect.
  • the data line 23 can be used to shield light, and the edge of the data line 23 can be shielded by the sub-pixel electrode 27, so that the design of the light shielding layer can be eliminated and the process is reduced. , To increase the aperture ratio of the array substrate 20.
  • the width of the overlapping portion of the sub-pixel electrode 27 and the data line 23 is 0.5-3 micrometers.
  • the main pixel electrode 26 includes a main electrode, and the main electrode defines the area where the main pixel electrode 26 is located into a plurality of main domain regions, and each of the main domain regions is provided with the main electrode Electrically connected branch electrode.
  • the sub-pixel electrode 27 includes an electrode backbone that defines the area where the sub-pixel electrode 27 is located into a plurality of sub-domain regions, and each of the sub-domain regions is provided with the electrode backbone.
  • the electrically connected electrode branches are provided.
  • the array substrate 20 further includes a common electrode 28 provided on the same layer as the scan line 22 and a source drain 29 provided on the same layer as the data line 23; the source drain 29 and the data line 23.
  • the main pixel electrode 26 and the sub-pixel electrode 27 are electrically connected to transmit the data signal of the data line 23 to the main pixel electrode 26 and the sub-pixel electrode 27.
  • the orthographic projection of the branch electrode and the electrode stem on the base substrate 21 does not coincide with the orthographic projection of the common electrode 28 on the base substrate 21, thereby preventing the common electrode 28 from causing an array
  • the aperture ratio of the substrate 20 decreases.
  • the branch electrode is arranged obliquely and the edge line of the branch electrode and the edge line of the main electrode form a first included angle a; the electrode branch is arranged obliquely and the edge line of the electrode branch is connected to the edge line of the main electrode.
  • the edge line of the electrode backbone forms a second included angle b, and the first included angle a and the second included angle b are both 10 to 80 degrees.
  • first included angle a and the second included angle b are both 20 to 70 degrees.
  • the distance between the electrode branches and the distance between the branch electrodes can be adjusted, so that the penetration rate of the main region 24 and the secondary region 25 can be adjusted.
  • the sub-pixel electrode 27 includes a first split body 271 and a second split body 272 disposed on both sides of the first split body 271 close to the data line 23.
  • the second sub-body 272 extends along the length direction of the data line 23; a shielding area is formed between the first sub-body 271 and the second sub-body 272, and the sub-pixel electrode 27 is located in the shielding area.
  • first sub-body 271, the second sub-body 272, and the main pixel electrode 26 can all be formed through the same manufacturing process.
  • the area where the main pixel electrode 26 is located includes 4 main domain areas, and the sub-pixel electrode 27 includes 8 sub-domain areas.
  • the main pixel electrode 26 includes a first main electrode 261 and two divisions arranged at intervals, and the first main electrode 261 limits the area where each division is located as two first main domain regions.
  • Each of the first main domain regions is provided with a first branch electrode 262 electrically connected to the first main electrode 261.
  • FIG. 2 only shows that the first main electrode 261 is arranged in the longitudinal direction, and the two subsections are arranged in the transverse direction. In actual implementation, it can also be arranged that the first main electrode 261 is arranged in the transverse direction. The sections are arranged longitudinally.
  • the first sub-body 271 includes two intersecting first electrode backbones 2711, and the first main electrode 261 limits the area where the first sub-body 271 is located into four first subdomain regions, each Each of the first subdomain regions is provided with a first electrode branch 2712 electrically connected to the first electrode backbone 2711.
  • the second sub-body 272 includes sub-electrodes located on opposite sides of the main pixel electrode 26, and each sub-electrode includes two second sub-domains that define the area where the sub-electrodes are located.
  • the second electrode backbone 2721 of the region, each of the second subdomain regions is provided with a second electrode branch 2722 electrically connected to the second electrode backbone 2721.
  • the area where the main pixel electrode 26 is located includes 4 main domain regions, and the sub-pixel electrode 27 includes 4 sub-domain regions.
  • the main pixel electrode 26 includes two intersecting second main electrodes 263, and the two intersecting second main electrodes 263 form a cross-shaped structure; the second main electrode 263 connects the main pixel
  • the area where the electrode 26 is located is defined as four second main domain regions, and each of the second main domain regions is provided with a second branch electrode 264 electrically connected to the second main electrode 263.
  • the second sub-body 272 of the sub-pixel electrode 27 is formed by extending both sides of the first sub-body 271 along the direction of the data line 23.
  • the main pixel electrode 26 includes two intersecting third main electrodes 265, and the third main electrode 265 defines the area where the main pixel electrode 26 is located.
  • the sub-pixel electrode 27 includes two separate bodies respectively located on the two sides of the main pixel electrode 26 close to the data line 23, and each of the separate bodies includes The region where the split body is located is defined as the third electrode backbone 273 of the two third subdomain regions.
  • the overall shape of the main pixel electrode 26 (the shape defined by the dotted line in FIGS. 4 to 7) can be square (as shown in FIG. 4), hourglass (as shown in FIG. 5), or spindle-shaped (as shown in FIG. 6), etc. .
  • the diversity of liquid crystal molecules can be improved to improve viewing angle characteristics and response speed.
  • the two separate bodies are arranged at intervals.
  • the two separate bodies are connected to each other, the sub-pixel electrode 27 is in a closed ring shape as a whole, and the main pixel electrode 26 is located in the sub-pixel. Within the enclosed area defined by the electrode 27.
  • the source and drain 29 can be extended to directly below the main pixel electrode 26, and the electrical properties of the main pixel electrode 26 and the source and drain 29 can be realized through via holes. It is connected to avoid a short circuit between the sub-pixel electrode 27 and the main pixel electrode 26.
  • the present application also provides a display panel.
  • the display panel includes a color filter substrate 30 and the array substrate 20 described in any one of the above embodiments.
  • a liquid crystal layer 40 is provided between the substrate 30 and the array substrate 20.
  • the beneficial effect of the present application is that the part of the main pixel electrode 26 close to the data line 23 is surrounded by the sub-pixel electrode 27, and the sub-pixel electrode 27 is used to isolate and protect the interference between the main pixel electrode 26 and the data line 23, and prevent the data line 23
  • a coupling capacitor is formed with the main pixel electrode 26, so that the design of the metal shielding layer can be eliminated on the premise of ensuring the crosstalk problem, thereby greatly improving the aperture ratio and transmittance of the array substrate 20.

Abstract

一种阵列基板（20）及显示面板，阵列基板（20）包括衬底基板（21）、沿横向设置的扫描线（22）、沿纵向设置的数据线（23）以及多个像素单元；其中，每一像素单元具有主区（24）和次区（25），像素单元包括位于主区（24）的主像素电极（26）和位于次区（25）的次像素电极（27），主像素电极（26）与次像素电极（27）间隔设置，次像素电极（27）包围主像素电极（26）靠近数据线（23）的部分。

Description

一种阵列基板及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
 背景技术
一般的VA型液晶显示面板中，为了更优的广视角体验，如图1所示，一般会采用将一个像素单元中的4畴区设计变为8畴区设计，通过设置具有不同驱动电压差的主畴区11和副畴区12，主畴区11和副畴区12分别含有4个轴对称的畴区，通过空间和液晶取向差异化的特性，使得正视和侧视时的差异减小，即改善侧视色偏等特性。在8畴区液晶显示面板中，为了屏蔽Data线13与位于主畴区11的PE电极14之间形成的耦合电容，从而避免电压变化导致显示不良，通常会在位于主畴区11的PE电极14四周设置金属屏蔽层15。
然而，金属屏蔽层15一般采用不透光的材料形成，会导致显示面板的开口率下降。
 技术问题
本申请提供一种阵列基板，以解决金属屏蔽层一般采用不透光的材料形成，会导致显示面板的开口率下降的技术问题。
 技术解决方案
第一方面，本申请提供一种阵列基板，其包括：
衬底基板；
沿横向设置于所述衬底基板上且并排设置的多条扫描线；
沿纵向设置于所述衬底基板上且并排设置的多条数据线；
阵列分布于所述衬底基板上的多个像素单元，每一所述扫描线与一行所述像素单元对应设置，每一所述数据线与一列所述像素单元对应设置，相邻两所述数据线界定出所述像素单元的边界；
其中，每一所述像素单元具有主区和次区，所述像素单元包括位于所述主区的主像素电极和位于所述次区的次像素电极，所述主像素电极与所述次像素电极间隔设置，所述次像素电极包围所述主像素电极靠近所述数据线的部分。
在一些实施例中，所述主像素电极包括主电极，所述主电极将所述主像素电极所在区域限定为多个主畴区，每一所述主畴区中均设置有与所述主电极电连接的支电极；所述次像素电极包括电极主干，所述电极主干将所述次像素电极所在区域限定为多个副畴区，每一所述副畴区中均设置有与所述电极主干电连接的电极支干。
在一些实施例中，所述次像素电极包括第一分体以及设置于所述第一分体靠近所述数据线的两侧上的第二分体，所述第二分体沿所述数据线的长度方向延伸；所述第一分体与所述第二分体之间形成屏蔽区，所述次像素电极位于所述屏蔽区。
在一些实施例中，所述主像素电极包括第一主电极和间隔设置的2个分部，所述第一主电极将每一所述分部所在区域均限定为2个第一主畴区，每一所述第一主畴区中均设置有与所述第一主电极电连接的第一支电极。
在一些实施例中，所述第一分体包括两条交叉设置的第一电极主干，所述第一主电极将所述第一分体所在区域限定为4个第一副畴区，每一所述第一副畴区中均设置有与所述第一电极主干电连接的第一电极支干。
在一些实施例中，所述第二分体包括分别位于所述主像素电极的相背两侧的分电极，每一所述分电极包括将所述分电极所在区域限定为2个第二副畴区的第二电极主干，每一所述第二副畴区中均设置有与所述第二电极主干电连接的第二电极支干。
在一些实施例中，所述主像素电极包括两条交叉设置的第二主电极，所述第二主电极将所述主像素电极所在区域限定为4个第二主畴区，每一所述第二主畴区中均设置有与所述第二主电极电连接的第二支电极。
在一些实施例中，所述主像素电极包括两条交叉设置的第三主电极，所述第三主电极将所述主像素电极所在区域限定为4个第三主畴区；所述次像素电极包括分别位于所述主像素电极靠近所述数据线的两侧上的两个分体，每一所述分体均包括将所述分体所在区域限定为2个第三副畴区的第三电极主干。
在一些实施例中，两个所述分体间隔设置。
在一些实施例中，两个所述分体相互连接，所述次像素电极整体呈封闭的环状，所述主像素电极位于所述次像素电极所限定的封闭区域内。
在一些实施例中，所述数据线包括靠近所述次像素电极设置的第一侧边，所述次像素电极在所述衬底基板上的正投影覆盖所述第一侧边在所述衬底基板上的正投影。
在一些实施例中，所述阵列基板还包括与所述扫描线同层设置的公共电极，所述支电极和所述电极支干在所述衬底基板上的正投影与所述公共电极在所述衬底基板上的正投影不重合。
在一些实施例中，所述支电极倾斜设置且所述支电极的边缘线与所述主电极的边缘线形成第一夹角；所述电极枝干倾斜设置且所述电极枝干的边缘线与所述电极主干的边缘线形成第二夹角，所述第一夹角和所述第二夹角均为10～80度。
第二方面，本申请还提供一种显示面板，其包括彩膜基板和阵列基板，所述彩膜基板与所述阵列基板之间设置有液晶层；所述阵列基板包括：
衬底基板；
沿横向设置于所述衬底基板上且并排设置的多条扫描线；
沿纵向设置于所述衬底基板上且并排设置的多条数据线；
阵列分布于所述衬底基板上的多个像素单元，每一所述扫描线与一行所述像素单元对应设置，每一所述数据线与一列所述像素单元对应设置，相邻两所述数据线界定出所述像素单元的边界；
其中，每一所述像素单元具有主区和次区，所述像素单元包括位于所述主区的主像素电极和位于所述次区的次像素电极，所述主像素电极与所述次像素电极间隔设置，所述次像素电极包围所述主像素电极靠近所述数据线的部分。
在一些实施例中，所述主像素电极包括主电极，所述主电极将所述主像素电极所在区域限定为多个主畴区，每一所述主畴区中均设置有与所述主电极电连接的支电极；所述次像素电极包括电极主干，所述电极主干将所述次像素电极所在区域限定为多个副畴区，每一所述副畴区中均设置有与所述电极主干电连接的电极支干。
在一些实施例中，所述次像素电极包括第一分体以及设置于所述第一分体靠近所述数据线的两侧上的第二分体，所述第二分体沿所述数据线的长度方向延伸；所述第一分体与所述第二分体之间形成屏蔽区，所述次像素电极位于所述屏蔽区。
在一些实施例中，所述主像素电极包括第一主电极和间隔设置的2个分部，所述第一主电极将每一所述分部所在区域均限定为2个第一主畴区，每一所述第一主畴区中均设置有与所述第一主电极电连接的第一支电极。
在一些实施例中，所述第一分体包括两条交叉设置的第一电极主干，所述第一主电极将所述第一分体所在区域限定为4个第一副畴区，每一所述第一副畴区中均设置有与所述第一电极主干电连接的第一电极支干。
在一些实施例中，所述第二分体包括分别位于所述主像素电极的相背两侧的分电极，每一所述分电极包括将所述分电极所在区域限定为2个第二副畴区的第二电极主干，每一所述第二副畴区中均设置有与所述第二电极主干电连接的第二电极支干。
在一些实施例中，所述主像素电极包括两条交叉设置的第二主电极，所述第二主电极将所述主像素电极所在区域限定为4个第二主畴区，每一所述第二主畴区中均设置有与所述第二主电极电连接的第二支电极。
 有益效果
相较于现有技术，本申请提供的实体键盘输入系统及其实体键盘输入方法中，所述实体键盘输入系统包括移动终端和实体键盘，所述实体键盘覆盖于移动终端的触摸屏上，用于将使用者施加于按键上的第一触碰信息转换为施加于所述触摸屏的第二触碰信息；所述移动终端包括检测装置、触摸屏、触摸屏控制芯片和处理器，所述检测装置、触摸屏和触摸屏控制芯片同时连接所述处理器。本申请通过直接将实体键盘覆盖在移动终端的触摸屏上，达到了采用实体按键进行文字信息输入的目的，并且实体键盘无需再连接电源来进行驱动，达到了即附即用的效果，而且降低了移动终端的成本和耗电量。
 附图说明
图1为本申请背景技术中液晶显示面板的结构示意图；
图2为本申请第一种实施方式中阵列基板的结构示意图；
图3为本申请第二种实施方式中阵列基板的结构示意图；
图4和图5为本申请第三种实施方式中阵列基板的结构示意图；
图6和图7为本申请第四种实施方式中阵列基板的结构示意图；
图8为本申请一实施方式中显示面板的结构示意图。
附图标记：
11、主畴区；12、副畴区；13、Data线；14、PE电极；15、金属屏蔽层；
20、阵列基板；21、衬底基板；22、扫描线；23、数据线；231、第一侧边；
24、主区；
25、次区；
26、主像素电极；261、第一主电极；262、第一支电极；263、第二主电极；264、第二支电极；265、第三主电极；266、第三支电极；
27、次像素电极；271、第一分体；2711、第一电极主干；2712、第一电极支干；272、第二分体；2721、第二电极主干；2722、第二电极支干；273、第三电极主干；
28、公共电极；29、源漏极；30、彩膜基板；40、液晶层。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请针对现有的阵列基板中，为了屏蔽数据线与位于主畴区的像素电极之间形成的耦合电容，金属屏蔽层一般采用不透光的材料形成，会导致显示面板的开口率下降的技术问题。本申请可以解决上述问题。
一种阵列基板20，如图2所示，所述阵列基板20包括衬底基板21、沿横向设置于所述衬底基板21上且并排设置的多条扫描线22、沿纵向设置于所述衬底基板21上且并排设置的多条数据线23，以及，阵列分布于所述衬底基板21上的多个像素单元。
其中，每一所述扫描线22与一行所述像素单元对应设置，每一所述数据线23与一列所述像素单元对应设置，相邻两所述数据线23界定出所述像素单元的边界。
具体的，每一所述像素单元具有主区24和次区25，所述像素单元包括位于所述主区24的主像素电极26和位于所述次区25的次像素电极27，所述主像素电极26与所述次像素电极27间隔设置，所述次像素电极27包围所述主像素电极26靠近所述数据线23的部分。
通过设计成主像素电极26靠近数据线23的部分被次像素电极27包围，利用次像素电极27隔离保护主像素电极26与数据线23之间的干扰，防止数据线23与主像素电极26之间形成耦合电容，从而可以在防止产生串扰问题的前提下，取消金属屏蔽层的设计，从而大幅度提升阵列基板20的开口率和穿透率。
具体的，所述数据线23包括靠近所述次像素电极27设置的第一侧边231，所述次像素电极27在所述衬底基板21上的正投影覆盖所述第一侧边231在所述衬底基板21上的正投影。
需要说明的是，对于本领域技术人员可知，一般阵列基板20上采用数据线23上方设置遮光层以代替黑色矩阵的遮光作用，而通过将所述次像素电极27与对应的数据线23的第一侧边231重叠设置，起到更好的屏蔽作用的同时，可以利用数据线23进行遮光，而通过次像素电极27对数据线23的边缘进行遮光，从而可以取消遮光层设计，减少工艺制程，提高阵列基板20的开口率。
在一实施方式中，所述次像素电极27与所述数据线23的重叠的部分的宽度为0.5～3微米。
具体的，所述主像素电极26包括主电极，所述主电极将所述主像素电极26所在区域限定为多个主畴区，每一所述主畴区中均设置有与所述主电极电连接的支电极。
具体的，所述次像素电极27包括电极主干，所述电极主干将所述次像素电极27所在区域限定为多个副畴区，每一所述副畴区中均设置有与所述电极主干电连接的电极支干。
具体的，所述阵列基板20还包括与所述扫描线22同层设置的公共电极28以及与所述数据线23同层设置的源漏极29；所述源漏极29与所述数据线23、所述主像素电极26以及所述次像素电极27电连接，以将所述数据线23的数据信号传输给所述主像素电极26和次像素电极27。
其中，所述支电极和所述电极支干在所述衬底基板21上的正投影与所述公共电极28在所述衬底基板21上的正投影不重合，从而防止公共电极28导致阵列基板20的开口率下降。
其中，所述支电极倾斜设置且所述支电极的边缘线与所述主电极的边缘线形成第一夹角a；所述电极枝干倾斜设置且所述电极枝干的边缘线与所述电极主干的边缘线形成第二夹角b，所述第一夹角a和所述第二夹角b均为10～80度。
进一步的，所述第一夹角a和所述第二夹角b均为20～70度。
通过调整电极支干和支电极的朝向，从而可以调整电极支干的间距和支电极的间距，从而可以调整主区24和次区25的穿透率。
如图2和图3所示，所述次像素电极27包括第一分体271以及设置于所述第一分体271靠近所述数据线23的两侧上的第二分体272，所述第二分体272沿所述数据线23的长度方向延伸；所述第一分体271与所述第二分体272之间形成屏蔽区，所述次像素电极27位于所述屏蔽区。
需要说明的是，所述第一分体271、第二分体272以及所述主像素电极26均可以通过同一道制程形成。
在第一种实施方式中，如图2所示，所述主像素电极26所在区域包括4个主畴区，所述次像素电极27包括8个副畴区。
具体的，所述主像素电极26包括第一主电极261和间隔设置的2个分部，所述第一主电极261将每一所述分部所在区域均限定为2个第一主畴区，每一所述第一主畴区中均设置有与所述第一主电极261电连接的第一支电极262。
需要说明的是，图2中仅示意了第一主电极261沿纵向设置，两个分部沿横向排布的情况，实际实施中，也可以设置为第一主电极261沿横向设置，两个分部沿纵向排布。
具体的，所述第一分体271包括两条交叉设置的第一电极主干2711，所述第一主电极261将所述第一分体271所在区域限定为4个第一副畴区，每一所述第一副畴区中均设置有与所述第一电极主干2711电连接的第一电极支干2712。
进一步的，所述第二分体272包括分别位于所述主像素电极26的相背两侧的分电极，每一所述分电极包括将所述分电极所在区域限定为2个第二副畴区的第二电极主干2721，每一所述第二副畴区中均设置有与所述第二电极主干2721电连接的第二电极支干2722。
在第二种实施方式中，如图3所示，所述主像素电极26所在区域包括4个主畴区，所述次像素电极27包括4个副畴区。
具体的，所述主像素电极26包括两条交叉设置的第二主电极263，两个相互交叉的第二主电极263形成“十”字形结构；所述第二主电极263将所述主像素电极26所在区域限定为4个第二主畴区，每一所述第二主畴区中均设置有与所述第二主电极263电连接的第二支电极264。
具体的，所述次像素电极27的第二分体272由所述第一分体271的两侧边缘沿数据线23方向延伸而成。
在一实施方式中，如图4和图7所示，所述主像素电极26包括两条交叉设置的第三主电极265，所述第三主电极265将所述主像素电极26所在区域限定为4个第三主畴区；所述次像素电极27包括分别位于所述主像素电极26靠近所述数据线23的两侧上的两个分体，每一所述分体均包括将所述分体所在区域限定为2个第三副畴区的第三电极主干273。
其中，所述主像素电极26的整体形状（图4至图7中虚线所限定的形状）可以为方形（如图4）、沙漏状（如图5）或纺锤状（如图6）等形状。
通过对主像素电极26和次像素电极27的形状和图形比例进行设计，可以提高改善液晶分子多样性，以改善视角特性和响应速度。
在第三种实施方式中，如图4和图5所示，两个所述分体间隔设置。
在第四种实施方式中，如图6和图7所示，两个所述分体相互连接，所述次像素电极27整体呈封闭的环状，所述主像素电极26位于所述次像素电极27所限定的封闭区域内。
需要说明的是，次像素电极27整体呈封闭的环状时，可以将源漏极29延伸至主像素电极26的正下方后，通过过孔实现主像素电极26与源漏极29的电性连接，以避免次像素电极27与主像素电极26之间发生短路。
基于上述阵列基板20，本申请还提供一种显示面板，如图8所示，所述显示面板包括彩膜基板30和如上述任一项实施方式中所述的阵列基板20，所述彩膜基板30与所述阵列基板20之间设置有液晶层40。
本申请的有益效果为：通过将主像素电极26靠近数据线23的部分被次像素电极27包围，利用次像素电极27隔离保护主像素电极26与数据线23之间的干扰，防止数据线23与主像素电极26之间形成耦合电容，从而可以在保证串扰问题的前提下，取消金属屏蔽层的设计，从而大幅度提升阵列基板20的开口率和穿透率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。

Claims (20)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    沿横向设置于所述衬底基板上且并排设置的多条扫描线；
    沿纵向设置于所述衬底基板上且并排设置的多条数据线；
    阵列分布于所述衬底基板上的多个像素单元，每一所述扫描线与一行所述像素单元对应设置，每一所述数据线与一列所述像素单元对应设置，相邻两所述数据线界定出所述像素单元的边界；
    其中，每一所述像素单元具有主区和次区，所述像素单元包括位于所述主区的主像素电极和位于所述次区的次像素电极，所述主像素电极与所述次像素电极间隔设置，所述次像素电极包围所述主像素电极靠近所述数据线的部分。
  2. 根据权利要求1所述的阵列基板，其中，所述主像素电极包括主电极，所述主电极将所述主像素电极所在区域限定为多个主畴区，每一所述主畴区中均设置有与所述主电极电连接的支电极；所述次像素电极包括电极主干，所述电极主干将所述次像素电极所在区域限定为多个副畴区，每一所述副畴区中均设置有与所述电极主干电连接的电极支干。
  3. 根据权利要求2所述的阵列基板，其中，所述次像素电极包括第一分体以及设置于所述第一分体靠近所述数据线的两侧上的第二分体，所述第二分体沿所述数据线的长度方向延伸；所述第一分体与所述第二分体之间形成屏蔽区，所述次像素电极位于所述屏蔽区。
  4. 根据权利要求3所述的阵列基板，其中，所述主像素电极包括第一主电极和间隔设置的2个分部，所述第一主电极将每一所述分部所在区域均限定为2个第一主畴区，每一所述第一主畴区中均设置有与所述第一主电极电连接的第一支电极。
  5. 根据权利要求3所述的阵列基板，其中，所述第一分体包括两条交叉设置的第一电极主干，所述第一主电极将所述第一分体所在区域限定为4个第一副畴区，每一所述第一副畴区中均设置有与所述第一电极主干电连接的第一电极支干。
  6. 根据权利要求5所述的阵列基板，其中，所述第二分体包括分别位于所述主像素电极的相背两侧的分电极，每一所述分电极包括将所述分电极所在区域限定为2个第二副畴区的第二电极主干，每一所述第二副畴区中均设置有与所述第二电极主干电连接的第二电极支干。
  7. 根据权利要求3所述的阵列基板，其中，所述主像素电极包括两条交叉设置的第二主电极，所述第二主电极将所述主像素电极所在区域限定为4个第二主畴区，每一所述第二主畴区中均设置有与所述第二主电极电连接的第二支电极。
  8. 根据权利要求2所述的阵列基板，其中，所述主像素电极包括两条交叉设置的第三主电极，所述第三主电极将所述主像素电极所在区域限定为4个第三主畴区；所述次像素电极包括分别位于所述主像素电极靠近所述数据线的两侧上的两个分体，每一所述分体均包括将所述分体所在区域限定为2个第三副畴区的第三电极主干。
  9. 根据权利要求8所述的阵列基板，其中，两个所述分体间隔设置。
  10. 根据权利要求8所述的阵列基板，其中，两个所述分体相互连接，所述次像素电极整体呈封闭的环状，所述主像素电极位于所述次像素电极所限定的封闭区域内。
  11. 根据权利要求1所述的阵列基板，其中，所述数据线包括靠近所述次像素电极设置的第一侧边，所述次像素电极在所述衬底基板上的正投影覆盖所述第一侧边在所述衬底基板上的正投影。
  12. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括与所述扫描线同层设置的公共电极，所述支电极和所述电极支干在所述衬底基板上的正投影与所述公共电极在所述衬底基板上的正投影不重合。
  13. 根据权利要求2所述的阵列基板，其中，所述支电极倾斜设置且所述支电极的边缘线与所述主电极的边缘线形成第一夹角；所述电极枝干倾斜设置且所述电极枝干的边缘线与所述电极主干的边缘线形成第二夹角，所述第一夹角和所述第二夹角均为10～80度。
  14. 一种显示面板，其中，所述显示面板包括彩膜基板和阵列基板，所述彩膜基板与所述阵列基板之间设置有液晶层；所述阵列基板包括：
    衬底基板；
    沿横向设置于所述衬底基板上且并排设置的多条扫描线；
    沿纵向设置于所述衬底基板上且并排设置的多条数据线；
    阵列分布于所述衬底基板上的多个像素单元，每一所述扫描线与一行所述像素单元对应设置，每一所述数据线与一列所述像素单元对应设置，相邻两所述数据线界定出所述像素单元的边界；
    其中，每一所述像素单元具有主区和次区，所述像素单元包括位于所述主区的主像素电极和位于所述次区的次像素电极，所述主像素电极与所述次像素电极间隔设置，所述次像素电极包围所述主像素电极靠近所述数据线的部分。
  15. 根据权利要求14所述的显示面板，其中，所述主像素电极包括主电极，所述主电极将所述主像素电极所在区域限定为多个主畴区，每一所述主畴区中均设置有与所述主电极电连接的支电极；所述次像素电极包括电极主干，所述电极主干将所述次像素电极所在区域限定为多个副畴区，每一所述副畴区中均设置有与所述电极主干电连接的电极支干。
  16. 根据权利要求15所述的显示面板，其中，所述次像素电极包括第一分体以及设置于所述第一分体靠近所述数据线的两侧上的第二分体，所述第二分体沿所述数据线的长度方向延伸；所述第一分体与所述第二分体之间形成屏蔽区，所述次像素电极位于所述屏蔽区。
  17. 根据权利要求16所述的显示面板，其中，所述主像素电极包括第一主电极和间隔设置的2个分部，所述第一主电极将每一所述分部所在区域均限定为2个第一主畴区，每一所述第一主畴区中均设置有与所述第一主电极电连接的第一支电极。
  18. 根据权利要求16所述的显示面板，其中，所述第一分体包括两条交叉设置的第一电极主干，所述第一主电极将所述第一分体所在区域限定为4个第一副畴区，每一所述第一副畴区中均设置有与所述第一电极主干电连接的第一电极支干。
  19. 根据权利要求18所述的显示面板，其中，所述第二分体包括分别位于所述主像素电极的相背两侧的分电极，每一所述分电极包括将所述分电极所在区域限定为2个第二副畴区的第二电极主干，每一所述第二副畴区中均设置有与所述第二电极主干电连接的第二电极支干。
  20. 根据权利要求16所述的显示面板，其中，所述主像素电极包括两条交叉设置的第二主电极，所述第二主电极将所述主像素电极所在区域限定为4个第二主畴区，每一所述第二主畴区中均设置有与所述第二主电极电连接的第二支电极。
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