WO2021109582A1

WO2021109582A1 - Magnetic memory and preparation method therefor

Info

Publication number: WO2021109582A1
Application number: PCT/CN2020/103232
Authority: WO
Inventors: 孟皓; 迟克群
Original assignee: 浙江驰拓科技有限公司
Priority date: 2019-12-05
Filing date: 2020-07-21
Publication date: 2021-06-10
Also published as: CN112928135B; CN112928135A

Abstract

Provided are a magnetic memory and a preparation method therefor. The magnetic memory comprises at least one hybrid storage array, the hybrid storage array comprising an STT-MRAM array and an SOT-MRAM array arranged adjacent to each other, wherein the STT-MRAM array comprises STT-MRAM storage units arranged in an array, the SOT-MRAM array comprises SOT-MRAM storage units arranged in an array, and the STT-MRAM storage units and the SOT-MRAM storage units have the same laminated structure. The magnetic memory of the present invention can not only fulfil the long-term storage requirement of a large amount of data, but also fulfil the frequent erasure and writing of the large amount of data.

Description

Magnetic memory and preparation method thereof

Technical field

The present invention relates to the technical field of magnetic memory, in particular to a magnetic memory and a preparation method thereof.

Background technique

With the development of memory technology, based on the traditional SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory, dynamic random access memory), a new type of memory has emerged— —MRAM (Magnetic Random Access Memory) has a longer service life than solid-state hard disks, better data non-volatility than SRAM and DRAM, and higher device density than SRAM, which has the potential to replace current memory.

However, no matter which type of memory, it can not only meet the long-term storage of large amounts of data, but also meet the frequent erasing and writing of large amounts of data. Therefore, it is necessary to propose a new type of memory to meet the application requirements of multiple scenarios.

Summary of the invention

In view of this, the present invention provides a magnetic memory and a preparation method thereof, which have multiple storage characteristics, which can not only meet the long-term storage of a large amount of data, but also meet the frequent erasing and writing of a large amount of data.

In a first aspect, the present invention provides a magnetic memory including at least one hybrid memory array, the hybrid memory array including an STT-MRAM array and a SOT-MRAM array arranged adjacently, wherein:

The STT-MRAM array includes STT-MRAM storage units arranged in an array, the SOT-MRAM array includes SOT-MRAM storage units arranged in an array, and the STT-MRAM storage unit is connected to the SOT-MRAM storage unit. The units have the same stacked structure.

Optionally, the STT-MRAM memory cell includes a first magnetic tunnel junction (MTJ), the SOT-MRAM memory cell includes a second magnetic tunnel junction (MTJ), and the first magnetic tunnel junction and the second magnetic tunnel junction The magnetic tunnel junction has the same laminated structure.

Optionally, the diameter size of the first magnetic tunnel junction of all STT-MRAM memory cells in the STT-MRAM array is the same; the diameter size of the second magnetic tunnel junction of all SOT-MRAM memory cells in the SOT-MRAM array the same.

Optionally, the diameters of the first magnetic tunnel junctions of the STT-MRAM memory cells in the same column or row in the STT-MRAM array are the same, and from the farthest column or row to the SOT-MRAM array. In the nearest column or row of the SOT-MRAM array, the diameter of the first magnetic tunnel junction of the STT-MRAM memory cell in each column or row gradually becomes smaller;

The diameters of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.

Optionally, the STT-MRAM array is divided into adjacently arranged STT-MRAM first sub-array and STT-MRAM second sub-array, wherein the STT-MRAM second sub-array is similar to the SOT-MRAM array Next, the diameters of the first magnetic tunnel junctions of all STT-MRAM memory cells in the first sub-array of STT-MRAM are the same; those of STT-MRAM memory cells in the same column or row in the second sub-array of STT-MRAM The diameters of the first magnetic tunnel junctions are the same, and from the column or row farthest from the SOT-MRAM array to the column or row closest to the SOT-MRAM array, the size of each column or row of STT-MRAM memory cells The diameter of the first magnetic tunnel junction gradually becomes smaller;

Optionally, the STT-MRAM memory cell further includes a first top electrode coupled to the first magnetic tunnel junction, and the first top electrode includes a first prefabricated layer and a first functional layer that are stacked, and the The first prefabricated layer is in contact with the first magnetic tunnel junction;

The SOT-MRAM memory cell further includes a second top electrode coupled to the second magnetic tunnel junction, and the second top electrode includes a second prefabricated layer and a second functional layer that are stacked and arranged, and the second prefabricated layer In contact with the second magnetic tunnel junction.

Optionally, the cross-sectional shape and size of the first prefabricated layer are the same as the first magnetic tunnel junction, and the cross-sectional shape and size of the second prefabricated layer are the same as the second magnetic tunnel junction;

The cross-sectional shape of the first functional layer is circular, and the diameter of the first functional layer is greater than or equal to the diameter of the first magnetic tunnel junction; the cross-sectional shape of the second functional layer is rectangular And the width of the second functional layer is greater than or equal to the diameter of the second magnetic tunnel junction.

Optionally, the materials of the first prefabricated layer and the second prefabricated layer are the same, and are selected from one of Pt, Ta, W, Au, and Cu;

The first functional layer and the second functional layer are made of the same material, and are selected from one of Pt, Ta, W, Au, and Cu.

Optionally, when the magnetic memory includes a plurality of hybrid storage arrays, the plurality of hybrid storage arrays are arranged in sequence, and the array arrangement of each hybrid storage array is the same, and the STT-MRAM arrays in different hybrid storage arrays are The size of the SOT-MRAM array varies.

In a second aspect, the present invention provides a method for manufacturing a magnetic memory, the method including:

Depositing a magnetic tunnel junction multilayer film on the substrate and depositing a top electrode prefabricated layer material film on the magnetic tunnel junction multilayer film;

At least one array of prefabricated structures is formed on the substrate by photolithography and etching, the array of prefabricated structures includes a first array of prefabricated structures and a second array of prefabricated structures that are arranged adjacently, and the first array of prefabricated structures is used to form STT -MRAM array, the second prefabricated structure array is used to form a SOT-MRAM array, wherein the first prefabricated structure array includes first prefabricated units arranged in an array, and the first prefabricated units include first magnetic tunnel junctions And a first prefabricated layer on the first magnetic tunnel junction, the second prefabricated structure array includes second prefabricated units arranged in an array, the second prefabricated unit includes a second magnetic tunnel junction and a second magnetic tunnel junction The second prefabricated layer;

Filling the voids in the prefabricated structure array with an insulating medium, and performing surface planarization treatment to form a flat surface, the flat surface being located above the first prefabricated layer and the second prefabricated layer;

Forming holes and grooves above the first prefabricated layer and the second prefabricated layer by photolithography and etching;

A material film of the top electrode functional layer is deposited to fill the holes, and the material film of the top electrode functional layer is chemically mechanically polished or etched to form a first functional layer above the first prefabricated layer. A second functional layer is formed on the second prefabricated layer.

The magnetic memory provided by the present invention utilizes the different storage characteristics of the STT-MRAM array and the SOT-MRAM array, which can not only meet the long-term storage of a large amount of data, but also meet the frequent erasing and writing of a large amount of data. At the same time, since the STT-MRAM memory cell and the SOT-MRAM memory cell adopt the same layered structure and have good process compatibility, the magnetic memory provided by the embodiment of the present invention is easy to manufacture.

Description of the drawings

FIG. 1 is a schematic structural diagram of a storage unit of a magnetic memory according to an embodiment of the present invention;

2 is a top view of the array distribution of the magnetic memory (only the magnetic tunnel junction is shown) according to an embodiment of the present invention;

FIG. 3 is a top view of the array distribution of the magnetic memory (showing the top electrode above the magnetic tunnel junction) according to an embodiment of the present invention;

4 is a functional view of a storage area of a magnetic memory according to an embodiment of the present invention;

5 is a top view of an array distribution of a magnetic memory (only the magnetic tunnel junction is shown) according to an embodiment of the present invention;

6 is a top view of an array distribution of a magnetic memory (showing the top electrode above the magnetic tunnel junction) according to an embodiment of the present invention;

Fig. 7 is a functional view of a storage area of a magnetic memory according to an embodiment of the present invention;

FIG. 8 is a top view of an array distribution of a magnetic memory (only the magnetic tunnel junction is shown) according to an embodiment of the present invention;

9 is a top view of an array distribution of a magnetic memory (showing the top electrode above the magnetic tunnel junction) according to an embodiment of the present invention;

10 is a functional view of a storage area of a magnetic memory according to an embodiment of the present invention;

11 is a functional view of a storage area of a magnetic memory according to another embodiment of the present invention;

12A to 12E are structural schematic diagrams of each step of a method for manufacturing a magnetic memory according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

Example one

An embodiment of the present invention provides a magnetic memory including a hybrid memory array, the hybrid memory array includes an STT-MRAM array and a SOT-MRAM array that are arranged adjacently, wherein,

A memory cell is selected from the STT-MRAM array and the SOT-MRAM array for illustration. As shown in FIG. 1, in this embodiment, the STT-MRAM memory cell includes a first magnetic tunnel junction (MTJ) 10 and a coupling On the first top electrode 11 of the first magnetic tunnel junction, the first magnetic tunnel junction 10 includes a first reference layer 101, a first barrier layer 102 and a first free layer 103, and the first top electrode 11 includes a first prefab layer 111 And the first functional layer 112, the first prefabricated layer 111 is in contact with the first free layer 103, and the first prefabricated layer 111 is used to prevent the first free layer 103 from being oxidized during the preparation process.

The SOT-MRAM memory cell includes a second magnetic tunnel junction (MTJ) 20 and a second top electrode 21 coupled to the second magnetic tunnel junction. The second magnetic tunnel junction 20 includes a second reference layer 201 and a second barrier layer. 202 and a second free layer 203. The second top electrode 21 includes a second prefabricated layer 211 and a second functional layer 212. The second prefabricated layer 211 is in contact with the second free layer 203. The second prefabricated layer 211 is used to prevent the second free The layer 203 is oxidized during the preparation process.

Further, the cross-sectional shape and size of the first prefabricated layer 111 are the same as those of the first magnetic tunnel junction 10, and the cross-sectional shape and size of the second prefabricated layer 211 are the same as those of the second magnetic tunnel junction 20 . The cross-sectional shape of the first functional layer 112 is circular, and the diameter of the first functional layer 112 is greater than or equal to the diameter of the first magnetic tunnel junction 10; the cross-sectional shape of the second functional layer 212 The cross-sectional shape is rectangular, and the width of the second functional layer 212 is greater than or equal to the diameter of the second magnetic tunnel junction 20. The first prefabricated layer 111 and the second prefabricated layer 211 are made of the same material, and are selected from one of Pt, Ta, W, Au and Cu; the first functional layer 112 and the second functional layer 212 The material is the same, selected from one of Pt, Ta, W, Au and Cu.

The magnetic memory provided by the embodiment of the present invention utilizes the different storage characteristics of the STT-MRAM array and the SOT-MRAM array, which can not only meet the long-term storage of a large amount of data, but also meet the frequent erasing and writing of a large amount of data. At the same time, since the STT-MRAM memory cell and the SOT-MRAM memory cell adopt the same layered structure and have good process compatibility, the magnetic memory provided by the embodiment of the present invention is easy to manufacture.

Further, since the diameter of the magnetic tunnel junction in the memory cell directly affects the storage characteristics of the memory cell, in the embodiment of the present invention, referring to FIGS. 2 and 3, FIG. 2 shows the magnetic memory of the present embodiment (only showing magnetic A top view of the tunnel junction), and FIG. 3 shows a top view of the magnetic memory (showing the top electrode above the magnetic tunnel junction) of this embodiment. The first magnetic tunnel junctions of all STT-MRAM memory cells in the STT-MRAM array are etched into a cylindrical shape, and the diameters of the first magnetic tunnel junctions of all STT-MRAM memory cells are the same; all SOTs in the SOT-MRAM array -The second magnetic tunnel junction of the MRAM memory cell is etched into a cylindrical shape, and the diameter of the second magnetic tunnel junction of all the SOT-MRAM memory cells is the same. Generally, the diameter of the first magnetic tunnel junction of the STT-MRAM memory cell is larger than the diameter of the second magnetic tunnel junction of the SOT-MRAM memory cell.

The magnetic memory provided by the first embodiment above, because the STT-MRAM array has the characteristics of high density and non-volatility, the STT-MRAM array forms a "data storage area" for storage that requires a large number of read operations and a small amount of write operations. Scenarios, such as storing "programs" or "models", and the SOT-MRAM array has a high service life and non-volatile characteristics, which can form a "high-frequency erasing area" for storage that requires a large number of write operations Scenarios such as storing "calculation data". The magnetic memory is shown in the view of the storage area. As shown in Figure 4, the magnetic memory includes a data storage area and a high-frequency erasing area.

Example two

In another embodiment of the present invention, the magnetic memory includes a hybrid memory array, and the hybrid memory array includes an STT-MRAM array and a SOT-MRAM array arranged adjacently, wherein,

In the embodiment of the present invention, the stacked structure of the STT-MRAM memory cell and the SOT-MRAM memory cell is the same as that of the first embodiment, and will not be repeated here. Please refer to FIGS. 5 and 6. FIG. 5 shows a top view of the magnetic memory of this embodiment (showing only the magnetic tunnel junction), and FIG. 6 shows the magnetic memory of this embodiment (showing the top electrode above the magnetic tunnel junction) Top view. The diameter of the first magnetic tunnel junction of the STT-MRAM memory cells in the same column in the STT-MRAM array is the same, and from the column farthest from the SOT-MRAM array to the column closest to the SOT-MRAM array, the STT- The diameter size of the first magnetic tunnel junction of the MRAM memory cell gradually becomes smaller; the diameter size of the second magnetic tunnel junction of all SOT-MRAM memory cells in the SOT-MRAM array is the same. Generally, the diameter size of the column of STT-MRAM memory cells closest to the SOT-MRAM array in the STT-MRAM array is still larger than the diameter size of the SOT-MRAM memory cells.

In Figures 5 and 6, the STT-MRAM array and the SOT-MRAM array are arranged horizontally. It can be understood that when the STT-MRAM array and the SOT-MRAM array are arranged vertically, the STT-MRAM in the same row in the STT-MRAM array The diameter size of the first magnetic tunnel junction of the memory cell is the same, and from the row farthest from the SOT-MRAM array to the row closest to the SOT-MRAM array, the diameter size of the first magnetic tunnel junction of each row of the STT-MRAM memory cell Gradually become smaller; the diameter of the second magnetic tunnel junction of all SOT-MRAM memory cells in the SOT-MRAM array is the same.

In the magnetic memory provided by the second embodiment above, the SOT-MRAM array can form a "high-frequency erasing area" for storing frequently erased data. The memory cells of the STT-MRAM array gradually become smaller in diameter from left to right. Therefore, the non-volatility is weakened from left to right, the erasing speed is accelerated, and the service life is increased. That is, the leftmost side has the strongest non-volatility, the slowest erasing speed and the shortest service life, and the rightmost side has the worst non-volatility, the fastest erasing speed and the shortest service life. Therefore, the STT-MRAM array forms a "multiplex area" whose performance gradually changes from left to right. When the data is not frequently erased and written, the data is stored on the leftmost side of the "multiplex area"; when it is necessary to store frequently erased and written data When the data is stored, it is first stored in the "high frequency erasing area", and then stored on the right side of the "multiplexing area". The magnetic memory is shown in the view of the storage area. As shown in FIG. 7, the magnetic memory includes a multiplexing area and a high-frequency erasing area.

Example three

In the embodiment of the present invention, the stacked structure of the STT-MRAM memory cell and the SOT-MRAM memory cell is the same as that of the first embodiment, and will not be repeated here. Please refer to FIGS. 8 and 9. FIG. 8 shows a top view of the magnetic memory of this embodiment (showing only the magnetic tunnel junction), and FIG. 9 shows the magnetic memory of this embodiment (showing the top electrode above the magnetic tunnel junction) Top view. The STT-MRAM array is divided into adjacently arranged STT-MRAM first sub-array and STT-MRAM second sub-array, wherein the STT-MRAM second sub-array is adjacent to the SOT-MRAM array, and the STT-MRAM second sub-array is adjacent to the SOT-MRAM array. The diameter size of the first magnetic tunnel junction of all STT-MRAM memory cells in the first sub-array of MRAM is the same; the diameter size of the first magnetic tunnel junction of the STT-MRAM memory cells in the same column in the second sub-array of STT-MRAM The same, and from the column farthest from the SOT-MRAM array to the column closest to the SOT-MRAM array, the diameter size of the first magnetic tunnel junction of the STT-MRAM memory cell in each column gradually becomes smaller; The diameter size of the second magnetic tunnel junction of all SOT-MRAM memory cells in the SOT-MRAM array is the same. Generally, the diameter size of the column of STT-MRAM memory cells closest to the SOT-MRAM array in the STT-MRAM array is still larger than the diameter size of the SOT-MRAM memory cells.

In Figures 8 and 9, the STT-MRAM array and the SOT-MRAM array are arranged horizontally. It can be understood that when the STT-MRAM array and the SOT-MRAM array are arranged vertically, the second sub-array of STT-MRAM in the same row The diameters of the first magnetic tunnel junctions of STT-MRAM memory cells are the same, and from the row farthest from the SOT-MRAM array to the row closest to the SOT-MRAM array, the first magnetic tunnel junction of each row of STT-MRAM memory cells The diameter size of SOT-MRAM gradually becomes smaller; the diameter size of the second magnetic tunnel junction of all SOT-MRAM memory cells in the SOT-MRAM array is the same.

In the magnetic memory provided by the third embodiment, the SOT-MRAM array can form a "high-frequency erasing area" for storing frequently erasable data, with high service life, high erasing speed, non-volatility, and data density. Moderate characteristics; the first sub-array of STT-MRAM forms a "data storage area" for storing data for a long time. It has the characteristics of strong non-volatility, high data density, long service life, and medium erasing speed; STT- The second sub-array of MRAM forms a "multiplexing area". The function of the "multiplexing area" is between the "high-frequency erasing area" and the "data storage area", which can be flexibly multiplexed. When the amount of data storage increases, It can serve as a "data storage area"; when the demand for frequent erasing and writing increases, it can serve as a "high-frequency erasing area." The magnetic memory is shown as a view of the storage area. As shown in Figure 10, the magnetic memory includes a data storage area, a multiplexing area, and a high-frequency erasing area.

In addition, if it is assumed that the entire storage area of the magnetic memory is realized by a hybrid memory array, it is conceivable that the array scale of the STT-MRAM array and SOT-MRAM array in the hybrid memory array will definitely be very large. Therefore, the magnetic memory adopts distributed Design, the magnetic memory includes multiple hybrid memory arrays, each hybrid memory array includes adjacently arranged STT-MRAM array and SOT-MRAM array, wherein the STT-MRAM array includes STT-MRAM memory cells arranged in an array The SOT-MRAM array includes SOT-MRAM memory cells arranged in an array, and the STT-MRAM memory cells and the SOT-MRAM memory cells have the same layered structure. For the description of the structure of each hybrid storage array, reference may be made to the above three embodiments, which will not be repeated here.

Based on the magnetic memory of the third embodiment, when the magnetic memory includes multiple hybrid storage arrays, and each hybrid storage array can form the storage area shown in FIG. 10, the final view of the storage area of the magnetic storage is shown in FIG. 11.

It is understandable that when the magnetic storage includes multiple hybrid storage arrays, the entire storage area of the magnetic storage is formed by the multiple hybrid storage arrays. Under the premise that the storage area of the magnetic storage is the same, each hybrid storage array can make its own The scale becomes smaller. Therefore, the advantage of this distributed design is that the "high-frequency erasing area" is closer to the "data storage area" and the "multiplexing area". When the stored data changes from "frequent erasing" to "long-term erasing" In the “Save” type, the data can be transferred more conveniently; at the same time, the distributed design has more layout flexibility and can be more convenient to optimize design functions, for example: the three functional areas of different hybrid storage arrays occupy The ratio and performance can be different. The addition of "reuse area" is more suitable for application scenarios where the data storage time is short and the saved data will be frequently changed. The addition of "data storage area" is more suitable for long data storage time and saved data. Application scenarios that will not be changed for a long time.

Another embodiment of the present invention provides a method for manufacturing a magnetic memory, the method including:

Step S1, depositing a magnetic tunnel junction multilayer film on a substrate and depositing a top electrode prefabricated layer material film on the magnetic tunnel junction multilayer film;

In this embodiment, as shown in FIG. 12A, a substrate 300 is provided. In the substrate 300, necessary bottom electrodes can be pre-embedded, and a first magnetic material layer 301 for forming a reference layer is sequentially deposited on the substrate 300 to form a potential The insulating oxide material layer 302 of the barrier layer, the second magnetic material layer 303 used to form the free layer, and the first heavy metal material layer 304 used to form the top electrode prefabricated layer, where a heavy metal material layer 304 can be deposited to prevent the second The magnetic material layer 303 is oxidized and serves as a connection between the top electrode functional layer and the free layer. The first magnetic material layer 301 may be a single layer of ferromagnetic material, or it may be composed of multiple layers of ferromagnetic materials or synthetic ferromagnetic materials. The insulating oxide material layer 302 includes MgO, AlO and other oxides. The second magnetic material layer 303 can be composed of a single layer of ferromagnetic layer or multiple layers of ferromagnetic material, or a layer of MgO and other materials can be grown on top to form a double layer. In the barrier structure, the first heavy metal material layer 304 may be composed of materials such as Pt, Ta, W, Au, and Cu.

Step S2, forming at least one prefabricated structure array on the substrate by photolithography and etching. The prefabricated structure array includes a first prefabricated structure array and a second prefabricated structure array arranged adjacently. The first prefabricated structure array is used for To form an STT-MRAM array, the second prefabricated structure array is used to form a SOT-MRAM array, wherein the first prefabricated structure array includes first prefabricated units arranged in an array, and the first prefabricated units include first A magnetic tunnel junction and a first prefabricated layer on the first magnetic tunnel junction, the second prefabricated structure array includes second prefabricated units arranged in an array, and the second prefabricated unit includes a second magnetic tunnel junction and a second magnetic The second prefabricated layer on the tunnel junction;

As shown in FIG. 12B, the first magnetic material layer, the insulating oxide material layer, the second magnetic material layer, and the first heavy metal material layer are etched using photolithography and etching processes, which are generally etched into a cylindrical shape. , The cylindrical magnetic tunnel junction and the top electrode prefabricated layer above are obtained. A

magnetic tunnel junction

40 and 50 are respectively selected from the first prefabricated structure array and the second prefabricated structure array for illustration. The magnetic tunnel junction 40 It includes a first reference layer 401, a first barrier layer 402, and a first free layer 403 stacked from bottom to top. The first prefabricated layer above is 411. The magnetic tunnel junction 50 includes a second reference layer stacked from bottom to top. Layer 501, second barrier layer 502, second free layer 503, the second prefabricated layer above it is 511, the actual process is batch production, and multiple magnetic tunnel junctions are obtained at the same time, and the magnetic tunnel junctions are arranged at intervals Yes, the magnetic tunnel junction 40 is used to further form the STT-MRAM memory cell, and the magnetic tunnel junction 50 is used to further form the SOT-MRAM memory cell. In this embodiment, the

magnetic tunnel junctions

40 and 50 adopt the same shape and size, and both are cylindrical. Actually, the specific shape and size can be adjusted as needed, and the two can adopt different shapes and sizes.

In addition, it should be noted that since the STT-MRAM memory cell does not require strip-shaped heavy metal electrodes, the integration density is higher than that of the SOT-MRAM memory cell, so in the process of film etching to become an MTJ cylinder, it is used to make the MTJ of STT-MRAM. The pitch of the cylinders can be smaller than the pitch of the MTJ cylinders used to make SOT-MRAM.

Step S3: Fill the voids in the prefabricated structure array with an insulating medium, and perform a surface planarization treatment to form a flat surface, the flat surface being located above the first prefabricated layer and the second prefabricated layer;

As shown in FIG. 12C, an insulating medium 200 is used to fill the gaps between the magnetic tunnel junctions. The insulating medium generally includes materials such as SiN, SiO, SiON, etc., and the first prefabricated layer 411 and the second prefabricated layer are combined by a chemical mechanical polishing method. The insulating medium above 511 is planarized. After the planarization process, the insulating medium 200 still remains above the first prefabricated layer 411 and the second prefabricated layer 511. Therefore, it is necessary to ensure that the insulating medium 200 has a sufficient filling height.

Step S4, forming holes and grooves above the first prefabricated layer and the second prefabricated layer by photolithography and etching;

As shown in FIG. 12D, using photolithography and etching processes, openings are formed in the insulating medium retained above the first prefabricated layer 411, and grooves are formed in the insulating medium retained above the second prefabricated layer 511, and the etching Stop on the surfaces of the first prefabricated layer 411 and the second prefabricated layer 511, and may also be appropriately over-etched so that the first prefabricated layer 411 and the second prefabricated layer 511 can be fully exposed. Wherein, the opening adopts the same shape as the magnetic tunnel junction 40 used to prepare the STT-MRAM memory cell, so it is etched into a circular hole, and the size of the opening is greater than or equal to the magnetic tunnel used to prepare the STT-MRAM memory cell. The size of the junction 40, in this embodiment, the size of the opening is equal to the size of the magnetic tunnel junction; the slot is etched into a rectangular slot, and the width of the slot is greater than or equal to the size of the magnetic tunnel junction 50 used to prepare the SOT-MRAM memory cell In this embodiment, the slot size is equal to the size of the magnetic tunnel junction. During specific etching, the process flow of etching round holes and rectangular grooves may not be performed at the same step, and the required electrodes may be fabricated separately.

Step S5, deposit a top electrode functional layer material film to fill the holes, and perform chemical mechanical polishing or etching on the top electrode functional layer material film to form a first functional layer above the first prefabricated layer , And forming a second functional layer above the second prefabricated layer.

As shown in FIG. 12E, the top electrode functional layer material film is deposited. The top electrode functional layer and the top electrode prefabricated layer can be made of the same material, which is heavy metals such as Pt, Ta, W, and is filled with openings and grooves. The layer material film is chemically mechanically polished or etched. It is necessary to ensure the isolation between adjacent memory cells. The top electrode functional layer 412 of the STT-MRAM memory cell is formed in the opening and the SOT- is formed in the groove. The top electrode functional layer 512 of the MRAM memory cell, and the top electrode functional layer 512 serves as a spin orbit moment providing layer. Of course, according to actual electrode preparation requirements, a certain continuity of the top electrode of a part of the magnetic tunnel junction can also be retained.

The preparation method of the magnetic memory provided by the embodiment of the present invention utilizes the characteristics of the similar processes of STT-MRAM and SOT-MRAM. The reference layer, barrier layer, free layer and top electrode can use the same set of material systems, and can pass through a single film It is made by deposition, which reduces the complexity of the process.

It is also noted that the size of the tunnel junction used to prepare STT-MRAM and the size of the tunnel junction used to prepare SOT-MRAM can be adjusted according to needs. When the size of the tunnel junction used to prepare STT-MRAM is larger, the size of the tunnel junction is higher. The thermal stability of the tunnel junction used to prepare SOT-MRAM is small, the thermal stability is small, but the flip rate is faster and the flip current density is low. Combining tunnel junctions of different sizes can increase the storage time of the storage part for storing data for a long time in the magnetic memory, speed up the writing rate of the frequently written data part, and reduce the writing current density. Changing the size will not affect the specific preparation method, so I will not repeat it here.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A magnetic memory, which is characterized by comprising at least one hybrid storage array, the hybrid storage array comprising adjacently arranged STT-MRAM array and SOT-MRAM array, wherein,

The STT-MRAM array includes STT-MRAM storage units arranged in an array, the SOT-MRAM array includes SOT-MRAM storage units arranged in an array, and the STT-MRAM storage unit is connected to the SOT-MRAM storage unit. The units have the same stacked structure.
The magnetic memory of claim 1, wherein the STT-MRAM memory cell includes a first magnetic tunnel junction (MTJ), the SOT-MRAM memory cell includes a second magnetic tunnel junction (MTJ), and the The first magnetic tunnel junction and the second magnetic tunnel junction have the same laminated structure.
The magnetic memory according to claim 2, wherein the diameter of the first magnetic tunnel junction of all STT-MRAM memory cells in the STT-MRAM array is the same; all SOT-MRAM memory cells in the SOT-MRAM array The diameter of the second magnetic tunnel junction of the unit is the same.
The magnetic memory according to claim 2, wherein:

The diameters of the first magnetic tunnel junctions of the STT-MRAM memory cells in the same column or row in the STT-MRAM array are the same, and from the column or row farthest from the SOT-MRAM array to the SOT-MRAM The diameter size of the first magnetic tunnel junction of the STT-MRAM memory cell in the nearest column or row of the array becomes gradually smaller;

The diameters of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.
The magnetic memory according to claim 2, wherein the STT-MRAM array is divided into adjacently arranged STT-MRAM first sub-array and STT-MRAM second sub-array, wherein the second STT-MRAM The sub-array is adjacent to the SOT-MRAM array, and the diameters of the first magnetic tunnel junctions of all STT-MRAM memory cells in the first sub-array of STT-MRAM are the same; and the same in the second sub-array of STT-MRAM The diameters of the first magnetic tunnel junctions of the STT-MRAM memory cells in the columns or rows are the same, and from the column or row farthest from the SOT-MRAM array to the column or row closest to the SOT-MRAM array, each The diameter of the first magnetic tunnel junction of the column or row of STT-MRAM memory cells gradually becomes smaller;

The diameter and size of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.
The magnetic memory according to claim 2, wherein:

The STT-MRAM memory cell further includes a first top electrode coupled to the first magnetic tunnel junction, the first top electrode includes a first prefabricated layer and a first functional layer that are stacked and arranged, and the first prefabricated layer In contact with the first magnetic tunnel junction;

The SOT-MRAM memory cell further includes a second top electrode coupled to the second magnetic tunnel junction. The second top electrode includes a second prefabricated layer and a second functional layer that are stacked and arranged. The second prefabricated layer In contact with the second magnetic tunnel junction.
The magnetic memory according to claim 6, wherein the cross-sectional shape and size of the first prefabricated layer are the same as those of the first magnetic tunnel junction, and the cross-sectional shape and size of the second prefabricated layer are the same as those of the first magnetic tunnel junction. The second magnetic tunnel junction is the same;

The cross-sectional shape of the first functional layer is circular, and the diameter of the first functional layer is greater than or equal to the diameter of the first magnetic tunnel junction; the cross-sectional shape of the second functional layer is rectangular And the width of the second functional layer is greater than or equal to the diameter of the second magnetic tunnel junction.
7. The magnetic memory according to claim 6, wherein the first prefabricated layer and the second prefabricated layer are made of the same material, and are selected from one of Pt, Ta, W, Au, and Cu;

The first functional layer and the second functional layer are made of the same material, and are selected from one of Pt, Ta, W, Au, and Cu.
The magnetic memory according to claim 1, wherein when the magnetic memory includes a plurality of hybrid memory arrays, the plurality of hybrid memory arrays are arranged in sequence, and the array arrangement of each hybrid memory array is the same but different The size of the STT-MRAM array and the SOT-MRAM array in the hybrid storage array are different.
A preparation method of a magnetic memory, characterized in that the method comprises:

Depositing a magnetic tunnel junction multilayer film on the substrate and depositing a top electrode prefabricated layer material film on the magnetic tunnel junction multilayer film;

At least one array of prefabricated structures is formed on the substrate by photolithography and etching, the array of prefabricated structures includes a first array of prefabricated structures and a second array of prefabricated structures that are arranged adjacently, and the first prefabricated structure array is used to form STT -MRAM array, the second prefabricated structure array is used to form a SOT-MRAM array, wherein the first prefabricated structure array includes first prefabricated units arranged in an array, and the first prefabricated units include first magnetic tunnel junctions And a first prefabricated layer on the first magnetic tunnel junction, the second prefabricated structure array includes second prefabricated units arranged in an array, the second prefabricated unit includes a second magnetic tunnel junction and a second magnetic tunnel junction The second prefabricated layer;

Filling the voids in the prefabricated structure array with an insulating medium, and performing a surface flattening treatment to form a flat surface, the flat surface being located above the first prefabricated layer and the second prefabricated layer;

Forming holes and grooves above the first prefabricated layer and the second prefabricated layer by photolithography and etching;

A material film of the top electrode functional layer is deposited to fill the holes, and the material film of the top electrode functional layer is chemically mechanically polished or etched to form a first functional layer above the first prefabricated layer. A second functional layer is formed on the second prefabricated layer.