CN112466874B - In-plane read-write ferroelectric memory array with close-packed structure and preparation method thereof - Google Patents
In-plane read-write ferroelectric memory array with close-packed structure and preparation method thereof Download PDFInfo
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- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
The invention belongs to the technical field of storage, and particularly relates to an in-plane read-write ferroelectric memory array with a close-packed structure and a preparation method thereof. The invention relates to an in-plane read-write ferroelectric memory array, wherein word lines are integrated in a ferroelectric memory unit layer, bit lines comprise a first bit line layer and a second bit line layer which are arranged outside the ferroelectric memory unit layer, each bit line layer is provided with a plurality of bit lines and a plurality of gaps which are arranged along a first direction, and the gaps comprise a first gap group and a second gap group which are alternately arranged. The first conductive column array is connected with the word line layer and the first bit line layer, and the second conductive column array is connected with the word line layer and the second bit line layer, which are arranged in a staggered manner. Memory elements are arranged in the gap region between each conductive pillar and the adjacent word line cross point. The ferroelectric memory structure has the advantages of no damage to the memory function of the memory layer device, improved memory capacity, and 4F size of memory cells in N-layer word line layer2the/N and the F are characteristic sizes, are suitable for high-density devices, and are simple to prepare and low in cost.
Description
Technical Field
The invention belongs to the technical field of storage, and particularly relates to an in-plane read-write ferroelectric memory array with a close-packed structure and a preparation method thereof.
Background
The traditional ferroelectric memory uses two polarization states of ferroelectric material to realize non-volatile memory information. In recent years, we invented a new ferroelectric memory using the domain wall conduction principle of ferroelectric materials (chinese patent application nos. cn201510036526.x, CN201510036586.1, CN201610098138.9, and U.S. patent publication No. 9685216B 2). The invention provides a storage mechanism different from the traditional ferroelectric memory principle, an external in-plane electric field is utilized to invert local electric domains, and a conductive channel is formed at the junction of the local electric domains and the peripheral non-inverted electric domains, so that the resistance of a device is instantly reduced, and the conductive channel is kept unchanged after the electric field is cancelled, so that the non-destructive reading current can be realized by applying smaller voltage. When a reverse electric field large enough is applied to return the locally inverted electric domain to the initial state, the domain wall conductive channel disappears and the read current is small. The logic state "1" or "0" of the memory cell can be known by the magnitude of the read current.
For memory devices, how to implement in-plane dense packing and interconnection of high-density three-dimensional memory architecture thereof has been a focus of high attention in the industry. FIG. 1 is a schematic perspective view of a three-dimensional Crossbar memory array as is known in the art. The memory array comprises a plurality of first electrodes 2 arranged in a first direction, a plurality of second electrodes 4 arranged in a second direction, and a plurality of first memory members 3, wherein the second direction is perpendicular to the first direction. The second electrode 4 is disposed on the first electrode 2. The first memory element 3 is disposed at the intersection of the second electrode 2 and the first electrode 4. When the Feature size (Feature size) of the process is F, the minimum size of the memory cell of the three-dimensional memory array is 4F2。
The three-dimensional memory array may further include a plurality of third electrodes 6 arranged in a first direction on the second electrodes 4 and a plurality of fourth electrodes 8 arranged in a second direction on the third electrodes, the second memory element being at the intersection of the third and fourth electrodes such that when the three-dimensional memory array has N layers of memory cells stacked, the memory cell has an equivalent minimum size of 4F2/N。
However, the structure has higher requirement on the uniformity of the device, and due to the clamping structure of the upper electrode and the lower electrode, the information reading and writing are realized by applying an electric field in the out-of-plane vertical direction. The process preparation is very difficult, the contact problem is easy to occur, and the device is unstablePerformance degradation, etc., and the structure requires more patterning steps (including deposition, photolithography, etching, etc.) per layer, which is expensive. In addition, how to realize 4F for a dense memory for in-plane reading and writing, i.e., applying an information reading and writing electric field direction along an in-plane horizontal direction2Closely spaced interconnection techniques are not currently available.
Disclosure of Invention
In view of the above, the present invention is to provide an in-plane read-write ferroelectric memory with a close-packed structure and a method for manufacturing the same, so as to implement 4F of the in-plane read-write ferroelectric memory2The interconnection of high-density storage reduces the manufacturing difficulty, reduces the preparation cost and improves the performance of the device.
The invention provides an in-plane read-write ferroelectric memory array with a close-packed structure, which comprises the following structures:
the word line layer is arranged on the same layer with the memory structure unit and is provided with a plurality of word lines and a plurality of gaps which are alternately arranged along a first direction, and the gaps comprise a first gap group and a second gap group; the first gap group and the second gap group are a plurality of alternately arranged grooves formed on the surface of the ferroelectric memory material by etching, the grooves of the first gap group and the second gap group are arranged in a staggered manner, conductive media are filled in the grooves, and the conductive media are connected with the conductive columns; the conductive pillars include a first conductive pillar array and a second conductive pillar array;
a first bit line layer arranged above the first conductive pillar array and including a plurality of bit lines arranged in a second direction perpendicular to the first direction, wherein a first memory device is arranged in a cross point gap region between the first conductive pillar and a word line adjacent to the first conductive pillar in the word line layer;
and the second bit line layer is arranged above or below the second conductive column array, and is a plurality of bit lines arranged along the second direction, namely the first bit lines and the second bit lines are staggered and parallel, and a second storage device is arranged in a gap area between the second conductive column and a word line cross point adjacent to the second conductive column in the word line layer.
The memory array of the invention further comprises a plurality of conductive plugs arranged repeatedly, wherein each conductive plug is configured between the corresponding first conductive pillar and the first word line layer cross point.
In the invention, each conductive plug is formed by filling a conductive medium in the ferroelectric material groove, and the resistance of the conductive medium and the ferroelectric material contact layer is smaller.
In the present invention, the conductive plug is generally but not limited to a square, and the conductive post is but not limited to a rectangular parallelepiped or a cylinder.
In the invention, the first storage device and the second storage device are made of the same material and are positioned in the same layer to realize 4F together2The conductive plugs are closely stacked, and are better in contact with the adjacent word lines and the adjacent conductive plugs, and the contact resistance is smaller.
In the present invention, the material of the first and second memory elements comprises a dielectric material.
In the present invention, the dielectric material is selected from lithium niobate, lithium tantalate, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, or a combination thereof.
In the present invention, an insulating layer is further included, and the insulating layer is disposed in a remaining space between the word line layer, the first bit line layer, the second bit line layer, the first conductive pillar array, and the second conductive pillar array.
In the invention, the initial activation direction of the memory cell device is directed from the word line to the first bit line or the second bit line, and the read-write signal is biased in the memory cell region between the word line and the intersection of a selected bit line in the first bit line layer and the second bit line layer.
In the invention, the memory structure unit and the word line layer are vertically stacked to form an N-layer memory structure, and the equivalent minimum size of the memory unit is 4F2/N。
The invention also provides a preparation method of the in-plane read-write ferroelectric memory array with the close-packed structure, which comprises the following steps:
when the second bit line layer is disposed above the second conductive pillar array, the specific steps are as follows:
forming a plurality of word lines and a plurality of plug grooves of a first group and a second group on a substrate ferroelectric single crystal wafer by a mask etching method, and configuring an electrode film;
forming a flat insulating layer covering the surface of the word line layer by using a film growth and chemical mechanical polishing technology;
forming a first group of plug contact holes and configuring a first layer of bit line electrodes;
forming a flat insulating layer covering the surface of the word line layer by using a film growth and chemical mechanical polishing technology;
forming a first group of plug contact holes and arranging a second layer of horizontal line electrode.
When the second bit line layer is disposed under the second conductive pillar array, the specific steps are as follows:
forming a second level line electrode;
forming a flat insulating layer covering the surface of the word line layer by using a film growth and chemical mechanical polishing technology;
bonding the ferroelectric single chip, forming a plurality of word lines, a plurality of plug grooves connected with the second bit line layer electrode column through holes and the first bit line layer electrode column through holes by a mask etching method, and configuring an electrode film for the word lines and the second bit line layer electrode column through holes;
forming a flat insulating layer covering the surface of the word line layer by using a film growth and chemical mechanical polishing technology;
forming contact holes connected with the bit lines of the first layer, and arranging an electrode layer to form an electrode of the second layer.
The invention has the beneficial effects that:
since the word line layer memory material of the present invention can be single crystal, and the read/write operation is accomplished by applying an in-plane electric field, the plurality of conductive pillars are completed in the same patterning step (or at most two patterning steps), and thus the plurality of memory cells formed by the conductive pillars, the memory members, and the corresponding word lines have the same characteristics. The electrode material of the memory cell of the lower word line and the upper bit line can be prepared in one step, thereby reducing the contact problem caused by thermal expansion and the like caused by multiple steps, realizing high-density storage, and simultaneously preventing the reliability and the efficiency of the lower memory layer from being reduced.
Drawings
The present invention will be further described with reference to the drawings, wherein like or similar elements are designated by like reference numerals.
FIG. 1 is a schematic diagram of a high-interest out-of-plane read-write Crossbar three-dimensional memory structure array.
FIG. 2 is a schematic three-dimensional interconnect structure of an in-plane read/write high density memory array according to a first embodiment of the present invention.
FIG. 3 is a schematic top view of an in-plane read/write high density memory array according to a first embodiment of the present invention.
FIG. 4 is a cross-sectional view of the in-plane read-write memory array of FIG. 3 taken along line S1-S1' in accordance with the first embodiment of the present invention.
FIG. 5 is a cross-sectional view of the in-plane read-write memory array of FIG. 3 taken along line S2-S2' in accordance with the first embodiment of the present invention.
FIG. 6 is a cross-sectional (left) and top-down (right) schematic views of an in-plane read/write memory cell shown in FIG. 4 with a dashed box N according to the first embodiment of the present invention.
Fig. 7 a-7 d illustrate a method of making the embodiment of fig. 2.
FIG. 8 is a schematic three-dimensional interconnect of high density memory array with in-plane read and write according to yet another embodiment of the invention.
FIG. 9 is a top view of the read/write memory array of FIG. 8 in accordance with another embodiment of the present invention.
Fig. 10 a-10 d illustrate a method of making the embodiment of fig. 8.
Detailed Description
The present invention will be further described with reference to the following examples, but the present invention is not limited to these examples.
In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the dimensional proportional relationship between the portions in the drawings does not reflect the actual dimensional proportional relationship.
In the following embodiments, for clarity of description, the electric domain direction or the polarization direction is exemplarily given, but it should be understood that the electric domain direction or the polarization direction of the ferroelectric memory is not limited to the direction shown in the illustrated embodiments.
Example 1
Fig. 2 is a schematic perspective view of the memory device of embodiment 1, wherein a second bit line layer is disposed above the second conductive pillar array. For clarity, portions of the device and barrier layers, including the ferroelectric material of the first word line layer, are omitted from fig. 2. FIG. 3 is a top view of a memory array according to a first embodiment of the invention. For clarity and ease of illustration, the memory elements below the middle insulating layer and its bit line layers BL11, BL21, BL14, BL24 are not shown in fig. 3. The cross-sectional view of the bitmap 3 in FIG. 4 taken along the line S1-S1 ', and the cross-sectional view of the bitmap 3 in FIG. 5 taken along the line S2-S2'. In order to see the working principle of the device more clearly, fig. 6 shows a partial cross-sectional view (left) and a top view (right) of the device of the part N of the wire frame in fig. 4, and for clarity, the insulating layer is not drawn in fig. 6.
Referring to fig. 2, 3, and 4, the memory array structure of this embodiment includes: two bit line layers 1stBL、2ndBL, a word line layer WL, two sets of conductive plugs 101 and 103 and two sets of conductive pillar arrays 1011 and 1031 connected to the conductive plugs, two sets of memory arrays 102 and 104, and an insulating layer 301.
A plurality of word lines WL1, WL2, wl3 are sequentially arranged on one word line layer WL along a first direction, a first group 101 or a second group 103 of conductive plug arrays are sequentially arranged between two adjacent word lines along the first direction, and the first group 101 and the second group 103 of conductive plug arrays are alternately arranged along a second direction, which is perpendicular to the first direction.
A conductive post is connected to each conductive plug above it, forming conductive post array 1011 and conductive posts 1031.
Bit line layer 2ndBL is arranged at 1stAbove the bit line layer, there are a plurality of bit lines BL21, BL22, BL23, BL24 … connected to a portion of the conductive pillar 1031 and arranged in sequence along the second direction, each conductive plug 103 has a conductive pillar 1031 connected thereto, and is configured with a bit line connected to the conductive pillar, a gap region formed by crossing between the conductive plug 101 and an adjacent word line surface is a ferroelectric memory device 104, and for clarity, not all bit lines and conductive pillars are drawn in fig. 3.
The ferroelectric memory device materials include, but are not limited to, lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, and doped materials thereof.
The word line, the bit line, the conductive plug and the conductive column are made of conductive materials including but not limited to copper, gold, silver, titanium, chromium and cobalt, and the contact between the conductive plug, the word line and the ferroelectric memory unit is good.
In this embodiment, the initial polarization direction 201 of the ferroelectric material is directed from the word line to the conductive plugs 101 and/or 103.
In this embodiment, insulating layer 301 is disposed on bit line layer 1stBL、2ndBL, word line layer, remaining space between ferroelectric memory cells 102 and 104 and conductive pillar arrays 1011 and 1031. Specifically, the insulating layer between the ferroelectric memory devices may be the ferroelectric material itself, but the remaining space-filling insulating material may include, but is not limited to, aluminum oxide, hafnium oxide, silicon oxynitride, silicon nitride, or silicon oxide.
In this embodiment, a cross-section and a top view of a memory cell between a conductive plug connected between a word line WL1 and a bit line BL11 are shown in fig. 6. When a bias voltage V which is larger than the coercive voltage Vc of the device is applied to the bit line BL11, part of electric domains in the device are inverted, a conductive domain wall 202 is formed between an inverted electric domain and an un-inverted electric domain, and at the moment, a reading voltage is applied to the BL11 to obtain a low resistance state 1; when a bias voltage V larger than the coercive voltage Vc of the device is applied to the word line WL1, an inverted domain returns to the initial state, the conductive domain wall disappears, and then a reading voltage is applied to BL11 to obtain a high-resistance state 0.
In this embodiment, the ferroelectric single crystal layer memory material may be selected from one or more of: lithium tantalate salt LiTaO3Lithium niobate salt LiNbO3Bismuth ferrite BiFeO3Doped with MgO and Mn2O5Or Fe2O3Lithium tantalate salt LiTaO3Lithium niobate salt LiNbO3Bismuth ferrite BiFeO3And so on. Wherein the MgO and Mn are doped2O5Or Fe2O3Lithium tantalate salt LiTaO3Lithium niobate salt LiNbO3The doping amount of (b) may be 0 to 10 mol% (e.g., 1 mol% or 4 mol%).
The ferroelectric single crystal layer may be a ferroelectric single crystal (e.g., LiTaO)3) Or a ferroelectric thin film layer epitaxial on a suitable substrate (such as SrTiO single crystal plate)3A layer of BiFeO is epitaxially grown on the substrate3The single crystal thin film as a ferroelectric single crystal layer).
In this embodiment, the electrode layer and the connecting wire electrode material filling the contact hole are selected to have high temperature resistance and low resistivity, and may be, but not limited to, one or more selected from the following materials: TiN, Pt, PtSi, NiSi, TiW, Ta, Ti, W, Mo, Al, Cu, Cr or SrRuO3，RuO2Etc.;
hereinafter, a method for fabricating a memory array of the first embodiment will be described, and fig. 7a to 7d are schematic top views of a method for fabricating a three-dimensional memory array according to the first embodiment of the invention, and some components are omitted in some of the drawings for clarity and convenience of description.
Firstly, preparing an original substrate ferroelectric single crystal wafer with a smooth and flat surface and no pollution, coating photoresist on the surface in a spinning mode, transferring a designed bump pattern to the original substrate through pattern transfer technologies such as optical exposure, electron beam exposure, ion beam exposure or nano imprinting, growing a layer of hard mask material, remaining the hard mask pattern on the original substrate through a lift-off technology, etching the ferroelectric single crystal wafer through a dry etching or wet etching technology, leaving a ferroelectric bump, removing the hard mask material, and forming a word line and a plug groove; see fig. 7 a;
then, preparing an electrode film, and leaving the conductive layers of the word line electrode part and the plug part by a similar method; by means of thin-film growth techniques, such as PECVD (plasma enhanced chemical vapour deposition) techniques, a layer of SiO 50 to 3000 nm thick is grown on a starting substrate2Thin film, polishing SiO using CMP technique2The film reaches the target thickness and the surface is ensured to be smooth and flat; see fig. 7 b;
optionally, in growing SiO2Previously growing a protective film, e.g. of Si3N4Or HSQ.
Secondly, etching contact holes at the first group of plugs 101 by using a mask, preparing the mask again and filling electrode materials to obtain a first layer of bit line electrodes; see fig. 7 c;
repeating the process shown in fig. 7c to obtain a second layer line electrode; see fig. 7 d;
in embodiments of the invention, the particular shape of the domain wall 202 formed is not limited by the illustrated shape, which is limiting of embodiments of the invention.
Example 2
Fig. 8 is a schematic perspective view of a memory device according to another embodiment of the invention, wherein a second bit line layer is disposed under the second conductive pillar array. For clarity, portions of the device and barrier layers are omitted from fig. 8, including the ferroelectric material of the second word line layer. Fig. 9 is a schematic top view of a memory array according to a first embodiment of the invention. For clarity and ease of illustration, FIG. 9 does not show the intervening insulating layers and memory elements of word line layers other than the first word line layer.
Referring to fig. 8 and 9, the memory array structure of this embodiment includes: two upper and lower bit line layers 1stBL、2ndBL, a word line layer WL in the middle, two sets of conductive plugs 101 and 103 and two sets of conductive pillar arrays 1011 and 1031 connected to the conductive plugs, two sets of memory arrays 102 and 104 and an insulating layer 301.
A plurality of word lines WL1, WL2, WL3 are sequentially arranged on a word line layer along a first direction, a first group 101 or a second group 103 of conductive plug arrays are sequentially arranged between two adjacent word lines along the first direction, and the groups of the conductive plug arrays 101 and 103 are alternately arranged along a second direction, wherein the second direction is perpendicular to the first direction.
A conductive post is attached to the top of each conductive plug 101 and 103 to form conductive post array 1011 and conductive post 1031.
Bit line layer 2ndBL is disposed below the word line layer and connected to a portion of the conductive pillar 1031, and has a plurality of bit lines BL21, BL22, BL23, BL24 … arranged in sequence along the second direction, each conductive plug 103 has the conductive pillar 1031 connected thereto, and is disposed with the bit line connected to the conductive pillar, a ferroelectric memory device 104 is disposed between the conductive plug 101 and the adjacent word line, and for clarity, all the bit lines and the conductive pillars are not drawn in fig. 9.
The ferroelectric memory device material includes, but is not limited to, lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, and doped materials thereof.
The word lines, bit lines, conductive plugs and conductive columns are made of conductive materials, including but not limited to copper, gold, silver, titanium, chromium, cobalt, titanium nitride and tungsten, and the contact between the conductive plugs, the word lines and the ferroelectric memory cells is good.
In this embodiment, insulating layer 301 is disposed on bit line layer 1stBL、2ndBL, word line layer, remaining space between ferroelectric memory cells 102 and 104 and conductive pillar arrays 1011 and 1031. Specifically, the insulating layer between the ferroelectric memory devices may be the ferroelectric material itself, but the remaining space-filling insulating material may include, but is not limited to, aluminum oxide, hafnium oxide, silicon oxynitride, silicon nitride, or silicon oxide.
In this embodiment, the ferroelectric single crystal layer material may be selected from one or more of the following:lithium tantalate salt LiTaO3Lithium niobate salt LiNbO3Bismuth ferrite BiFeO3MgO and Mn2O doped5Or Fe2O3Lithium tantalate salt LiTaO3Lithium niobate salt LiNbO3Bismuth ferrite BiFeO3And so on. Wherein the MgO and Mn are doped2O5Or Fe2O3Lithium tantalate salt LiTaO of3Lithium niobate salt LiNbO3The doping amount of (c) may be 0 to 10 mol% (e.g., 1 mol% or 4 mol%).
The ferroelectric single crystal layer may be a ferroelectric single crystal sheet (e.g., LiTaO)3) Or a ferroelectric thin film layer epitaxial on a suitable substrate (such as SrTiO single crystal plate)3A layer of BiFeO is extended on the substrate3The single crystal thin film as a ferroelectric single crystal layer).
In this embodiment, the electrode layer and the connecting wire electrode material filling the contact hole are selected to have high temperature resistance and low resistivity, and may be, but not limited to, one or more selected from the following materials: TiN, Pt, PtSi, NiSi, TiW, Ta, Ti, W, Mo, Al, Cu, Cr or SrRuO3，RuO2Etc.;
hereinafter, a method for fabricating a memory array according to a first embodiment will be described, and fig. 10a to 10d are schematic top views of a method for fabricating a three-dimensional memory array according to a first embodiment of the present invention, and some components are omitted from some of the drawings for clarity and convenience of description.
Firstly, preparing an original silicon substrate with a smooth and flat surface and no pollution, coating photoresist on the surface in a spinning mode, transferring a designed word line layer pattern to the original substrate through pattern transfer technologies such as optical exposure, electron beam exposure, ion beam exposure or nano imprinting, growing a layer of conductive material, and leaving a hard mask pattern on the original substrate through a lift-off technology to form a lower word line layer; see fig. 10 a;
then, a layer of SiO 50 to 3000 nm thick is grown on the substrate using a thin film growth technique, such as PECVD (plasma enhanced chemical vapor deposition) technique2Thin film, polishing SiO using CMP technique2The thickness of the film reaches a target thickness and the surface of the film is ensured to be smooth and flat;
by bonding to SiO2Bonding a layer of ferroelectric single crystal film on the surface, coating photoresist on the surface in a spinning mode, transferring the designed patterns of the word line, the plug 103 and the plug 101 to an original substrate by using pattern transfer technologies such as optical exposure, electron beam exposure, ion beam exposure or nano imprinting, growing a layer of hard mask material, remaining the hard mask pattern on the original substrate by using a lift off technology, etching the ferroelectric single crystal wafer by using a dry etching or wet etching technology, and removing the hard mask material to form the grooves of the word line, the plug 103 and the plug 101 and the ferroelectric memory unit;
connecting the plug 101 with the bottom bit line by drilling holes, coating photoresist on the surface, transferring the designed plug 101 pattern to the substrate by pattern transfer techniques such as optical exposure, electron beam exposure, ion beam exposure or nano-imprinting, growing a layer of hard mask material, leaving the hard mask pattern on the substrate by lift-off, and etching the residual ferroelectric single crystal layer and SiO by dry etching2Layer, left behind through SiO2Forming a through hole from the layer to the bottom bit line layer, and removing the hard mask material to form a plug 101 through hole; see FIG. 10 b;
then, preparing an electrode film, and leaving the conductive layers of the word line electrode part, the plug and the through hole part by a similar method;
growing a layer of SiO 50-3000 nm thick on the substrate again by using thin film growth technique, such as PECVD (plasma enhanced chemical vapor deposition) technique2Thin film, polishing SiO using CMP technique2The film reaches the target thickness and ensures its surface smooth and flat, see fig. 10 c;
finally, by using the similar method, after masking, contact holes are etched at the first group of plugs 103, after a layer of electrode material is grown, a mask is prepared again and the electrode material is filled, and then another 1 can be obtainedstA bit line electrode; see fig. 10 d.
It should be understood by those skilled in the art that the number of word line layers, word lines, bit lines, and conductive pillars and plugs is not limited by the present invention.
In the description above, components of various embodiments described using directional terms and the like represent directions shown in the drawings or directions that can be understood by those skilled in the art. These directional terms are used for relative description and clarification and are not intended to limit the orientation of any embodiment to a particular direction or orientation.
The above examples mainly illustrate the structure and fabrication method of the in-plane close-packed ferroelectric three-dimensional interconnect memory of the present invention. Although only a few embodiments of the present invention have been described, those skilled in the art will appreciate that the present invention may be embodied in many other forms without departing from the spirit and scope thereof. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and various modifications and substitutions may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (10)
1. An in-plane read-write ferroelectric memory array of a closely-packed structure, the structure comprising:
the memory structure comprises a first word line layer and a second word line layer, wherein the first word line layer and the memory structure unit are arranged on the same layer, the word line layer is provided with a plurality of word lines and a plurality of gaps which are alternately arranged along a first direction, and the gaps comprise a first gap group and a second gap group; the first gap group and the second gap group are a plurality of alternately arranged grooves formed on the surface of the ferroelectric memory material by etching, the grooves of the first gap group and the second gap group are arranged in a staggered manner, conductive media are filled in the grooves, and the conductive media are connected with the conductive columns; the conductive pillars include a first conductive pillar array and a second conductive pillar array;
a first bit line layer arranged above the first conductive pillar array and including a plurality of bit lines arranged in a second direction perpendicular to the first direction, wherein a first memory device is arranged in a cross point gap region between the first conductive pillar and a word line adjacent to the first conductive pillar in the word line layer;
and the second bit line layer is arranged above or below the second conductive column array, and is a plurality of bit lines arranged along the second direction, namely the first bit lines and the second bit lines are staggered and parallel, and a second storage device is arranged in a gap area between the second conductive column and a word line cross point adjacent to the second conductive column in the word line layer.
2. The in-plane read-write ferroelectric memory array of claim 1, further comprising a plurality of conductive plugs arranged in a repeating pattern, each conductive plug disposed on the word line layer and connected to a corresponding conductive pillar.
3. The in-plane read-write ferroelectric memory array of claim 2, wherein each conductive plug is filled with a conductive medium, the conductive medium having a relatively low resistance with respect to the contact layer of ferroelectric material.
4. The in-plane read-write ferroelectric memory array of claim 3, wherein the conductive plugs are square in shape and the conductive pillars are cuboids or cylinders.
5. The in-plane read-write ferroelectric memory array of claim 1, wherein the first memory device and the second memory device are of the same material and are located in the same layer to collectively implement 4F2The conductive plugs are closely stacked, and are better in contact with the adjacent word lines and the adjacent conductive plugs, and the contact resistance is smaller.
6. The in-plane read-write ferroelectric memory array of claim 5, wherein the material between the first memory element and the second memory element comprises a dielectric material; the dielectric material is selected from lithium niobate, lithium tantalate, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, or a combination thereof.
7. The in-plane read-write ferroelectric memory array of claim 1, further comprising an insulating layer disposed in remaining spaces between the word line layer, the first bit line layer, the second bit line layer, the first conductive pillar array, and the second conductive pillar array.
8. An in-plane read-write ferroelectric memory array as claimed in claim 1, wherein the initial activation direction of the memory cell devices is directed from a word line to either a first bit line or a second bit line, and read and write signals are biased in the memory cell regions between the word line and the intersection of a selected one of said first and second bit line layers.
9. The in-plane read-write ferroelectric memory array of claim 1, wherein the memory structure cells are vertically stacked with the word line layers in an N-level memory architecture, and the memory cells have an equivalent minimum dimension of 4F2/N。
10. A method of manufacturing an in-plane read-write ferroelectric memory array as claimed in any one of claims 1 to 9, characterized by:
when the second bit line layer is disposed above the second conductive pillar array, the specific steps are as follows:
forming a plurality of word lines and a plurality of plug grooves of a first group and a second group on a substrate ferroelectric single crystal wafer by a mask etching method, and configuring an electrode film;
forming a flat insulating layer covering the surface of the word line layer by using a film growth and chemical mechanical polishing technology;
forming a first group of plug contact holes and configuring a first layer of bit line electrodes;
forming a flat insulating layer covering the surface of the word line layer by using a film growth and chemical mechanical polishing technology;
forming a first group of plug contact holes and configuring a second layer of horizontal line electrodes;
when the second bit line layer is disposed under the second conductive pillar array, the specific steps are as follows:
forming a second horizon electrode;
forming a flat insulating layer covering the surface of the word line layer by using a film growth and chemical mechanical polishing technology;
bonding the ferroelectric single chip, forming a plurality of word lines, a plurality of plug grooves connected with the second bit line layer electrode column through holes and the first bit line layer electrode column through holes by a mask etching method, and configuring an electrode film for the word lines and the second bit line layer electrode column through holes;
forming a flat insulating layer covering the surface of the word line layer by using a film growth and chemical mechanical polishing technology;
forming a contact hole connected with the first layer of bit line, and configuring a layer of electrode to form a second layer of electrode.
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