CN116615033A - Magnetic random access memory, manufacturing method thereof and electronic equipment - Google Patents

Magnetic random access memory, manufacturing method thereof and electronic equipment Download PDF

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Publication number
CN116615033A
CN116615033A CN202310733749.6A CN202310733749A CN116615033A CN 116615033 A CN116615033 A CN 116615033A CN 202310733749 A CN202310733749 A CN 202310733749A CN 116615033 A CN116615033 A CN 116615033A
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China
Prior art keywords
random access
access memory
magnetic random
magnetic
sot
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Inventor
冯春辉
张丛
范晓飞
刘宏喜
曹凯华
王戈飞
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Zhizhen Storage Beijing Technology Co ltd
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Zhizhen Storage Beijing Technology Co ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The embodiment of the application provides a magnetic random access memory, a manufacturing method thereof and electronic equipment, and belongs to the technical field of semiconductor integrated circuits. The magnetic random access memory comprises at least two layers of stacked structures, each of the at least two layers of stacked structures comprises at least one magnetic random access memory structure, the magnetic random access memory structures in adjacent two layers of stacked structures are arranged in a crossing mode, each magnetic random access memory structure comprises an SOT bottom electrode layer and at least one Magnetic Tunnel Junction (MTJ) arranged on the first surface of the SOT bottom electrode layer, and the first surface of the SOT bottom electrode layer of each magnetic random access memory structure faces the same direction. The magnetic random access memory provided by the embodiment of the application has a three-dimensional storage structure, and the storage density of the magnetic random access memory can be better improved through at least two layers of stacked structures; through SOT effect, realize faster data write-in, effectively improve erasable number of times.

Description

Magnetic random access memory, manufacturing method thereof and electronic equipment
Technical Field
The application relates to the technical field of semiconductor integrated circuits, in particular to a magnetic random access memory, a manufacturing method thereof and electronic equipment.
Background
With the continuous development of memory technology and electronic technology, random access memory has been widely used, which may be independent or integrated into devices using random access memory, such as processors, application specific integrated circuits, or systems on chip.
The magnetic memory (Magnetic Random Access Memory, MRAM) has the characteristics of high speed, low power consumption, non-volatility, radiation resistance and the like, and is expected to further break through the working bottleneck of the traditional silicon-based electronic device in the 'post-molar age'. In MRAM, a magnetic tunnel junction MTJ is the most critical part of the whole memory, and the core is a multi-layer sandwich structure composed of a magnetic free layer, a tunneling layer and a magnetic fixed layer. Third generation Spin-Orbit Torque magnetoresistive random access memories (Spin-Orbit Torque-Magnetic Random Access Memory, SOT-MRAM) utilize magnetic moment flipping for random access. SOT-MRAM has the advantages of high-speed reading and writing capability, high integration level, unlimited repeated writing and the like, and has wide development space and market prospect. However, as technology advances, the demand for memory storage density is increasing.
At present, with the gradual ending of moore's law, it becomes more and more difficult to increase the storage density of a memory chip through device miniaturization.
Disclosure of Invention
An object of an embodiment of the present application is to provide a magnetic random access memory capable of improving the memory density of a memory chip.
In order to achieve the above object, an embodiment of the present application provides a magnetic random access memory, which includes at least two stacked structures, each of the at least two stacked structures including at least one magnetic random access memory structure, the magnetic random access memory structures in adjacent two stacked structures being arranged to cross, wherein each of the magnetic random access memory structures includes an SOT bottom electrode layer and at least one magnetic tunnel junction MTJ arranged on a first surface of the SOT bottom electrode layer, and the first surfaces of the SOT bottom electrode layers of each of the magnetic random access memory structures face in the same direction.
Optionally, the magnetic random access memory structures in the adjacent two-layer stacked structure are vertically crossed.
Optionally, when the each layer of stacked structure includes a plurality of magnetic random access structures, the plurality of magnetic random access structures of the each layer of stacked structure are arranged in parallel.
Optionally, when the magnetic random access memory structure includes a plurality of magnetic tunnel junctions MTJ, for each of the magnetic random access memory structures, a distance between the plurality of magnetic tunnel junctions MTJ is a preset distance, and the preset distance is a shortest distance for cleaning a sidewall of a film layer of the plurality of magnetic tunnel junctions MTJ.
Optionally, each magnetic tunnel junction MTJ includes, from bottom to top, a free layer, a barrier layer, a reference layer, and a pinned layer with the first surface of the SOT bottom electrode layer of each magnetic random access memory structure facing upward.
Alternatively, when the magnetic random access memory is an in-plane horizontal magnetization inversion type magnetic random access memory, for each magnetic random access memory structure, the free layer magnetization of the selected magnetic tunnel junction MTJ of the magnetic random access memory structure is inverted by a write current applied to the SOT bottom electrode layer of the magnetic random access memory structure to write data into the selected magnetic tunnel junction MTJ.
Optionally, when the mram is of an out-of-plane perpendicular magnetization inversion type, for each of the mram structures, a magnetic moment of a selected MTJ of the mram structure is deviated from a preset angle in a perpendicular direction by an external magnetic field, and then a free layer of the selected MTJ is magnetized and inverted by a spin transfer torque generated by a write current applied to a SOT bottom electrode layer of the mram structure, so as to write data into the selected MTJ of the MTJ, and the external magnetic field is a magnetic field generated by a preset current applied to a SOT bottom electrode layer of any one of the mram structures adjacent to the mram structure.
Optionally, the magnetic random access memory further comprises a top electrode layer arranged above each magnetic tunnel junction MTJ, the data of the selected magnetic tunnel junction MTJ being read by a read current applied to the top electrode layer.
Optionally, the magnetic random access memory further comprises a gating circuit arranged on each magnetic tunnel junction MTJ for enabling selection of the magnetic tunnel junction MTJ by control of the gating circuit.
The embodiment of the application also provides a manufacturing method of the magnetic random access memory, which comprises the following steps: fabricating a first layer stack structure, depositing at least one SOT bottom electrode layer on a substrate wafer material, and growing at least one Magnetic Tunnel Junction (MTJ) on a first surface of each SOT bottom electrode layer of the at least one SOT bottom electrode layer; manufacturing a second layer stack structure, etching at least one groove at a preset position of the first layer stack structure, growing an SOT bottom electrode layer of the second layer stack structure at each groove, and growing at least one Magnetic Tunnel Junction (MTJ) on the first surface of each SOT bottom electrode layer; and repeating the fabrication process of the second layer stack structure when the magnetic random access memory comprises more than two layers of stack structures, wherein SOT bottom electrode layers in adjacent two layers of stack structures are arranged in a crossing manner.
Optionally, the SOT bottom electrode layers in the adjacent two-layer stacked structure are vertically crossed.
Alternatively, when each layer of the stacked structure includes a plurality of SOT bottom electrode layers, the plurality of SOT bottom electrode layers of each layer of the stacked structure are arranged in parallel.
Optionally, when the magnetic random access memory structure includes a plurality of magnetic tunnel junctions MTJ, for each magnetic random access memory structure, a distance between the plurality of magnetic tunnel junctions MTJ is a preset distance, and the preset distance is a shortest distance for performing sidewall cleaning on film layers of the plurality of magnetic tunnel junctions MTJ.
The embodiment of the application also provides electronic equipment, which comprises a processor and the magnetic random access memory coupled with the processor.
Through the technical scheme, the magnetic random access memory provided by the embodiment of the application has a three-dimensional storage structure, and the storage density of the magnetic random access memory can be better improved through the at least two-layer stacked structure; through SOT effect, realize faster data write-in, effectively improve erasable number of times.
Additional features and advantages of embodiments of the application will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the embodiments of the application. In the drawings:
FIG. 1 is a schematic side view of a magnetic random access memory according to an embodiment of the present application;
FIG. 2 is a schematic top view of the exemplary MRAM of FIG. 1;
FIG. 3 is a schematic diagram of an exemplary in-plane horizontally magnetized magnetic random access memory;
FIG. 4 is a schematic diagram of a structure of an exemplary out-of-plane perpendicular magnetization magnetic random access memory;
FIG. 5 is a schematic diagram illustrating the principle of flipping an out-of-plane perpendicular magnetization magnetic random access memory;
FIG. 6 is a flow chart of a method for manufacturing a magnetic random access memory according to an embodiment of the application;
FIG. 7A is a schematic diagram illustrating fabrication of a first layer stack structure;
FIG. 7B is a schematic diagram illustrating an example grown second layer structure; and
fig. 7C is a schematic diagram illustrating fabrication of a second layer stack structure.
Description of the reference numerals
10-stacked structure; 11-SOT bottom electrode layer;
12-magnetic tunnel junction MTJ; 13-top electrode layer.
Detailed Description
The following describes the detailed implementation of the embodiments of the present application with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the application, are not intended to limit the application.
Before explaining the embodiments of the present application in detail, a brief description of related techniques related to the embodiments of the present application will be given.
The basic cell structure of Spin-Orbit Torque-magnetoresistive random access memory (SOT-MRAM) includes a Magnetic Tunnel Junction (MTJ), a heavy metal layer or ferromagnetic layer, and two access transistors. The magnetic tunnel junction MTJ may include a free layer, a barrier layer, a reference layer, and a pinning layer from bottom to top, and a heavy metal or antiferromagnetic layer may be disposed under the free layer of the magnetic tunnel junction MTJ, and a current flowing through the heavy metal or antiferromagnetic layer can induce a moment to reverse the magnetization direction of the free layer of the magnetic tunnel junction MTJ, thereby implementing magnetic (data) writing. Under this technology, the problem of the writing speed of the magnetic random access memory is solved based on the writing of the SOT effect, but the area of the magnetic random access memory is increased due to the spin orbit coupling layer, and the basic unit structure of the SOT-MRAM comprises two access transistors, namely a writing transistor and a reading transistor, so that at least 3 ports are needed for data reading and writing operations, thereby causing the problem of lower storage density of the magnetic random access memory.
The storage density of the magnetic random access memory can be increased by increasing the magnetic tunnel junction MTJ. For example, two magnetic tunnel junctions MTJ are connected in parallel on the SOT bottom electrode layer, so that 2bit data can be stored, the two parallel magnetic tunnel junctions MTJ can share an access transistor, a heavy metal layer, a bidirectional gate, etc., the use efficiency can be improved, the use of the access transistor, the heavy metal layer, the bidirectional gate is reduced, the area of a memory cell can be saved, and the storage density of the data can be improved.
Furthermore, at least two storage structures with different sizes can be arranged on one spin orbit torque line, each storage structure has different writing currents when writing operation is performed, different combination states of the storage structures can be obtained by controlling the writing currents, the states of the storage structures are changed into states corresponding to the writing states, and the storage capacity and the storage density of the SOT-MRAM (solid-state optical random access memory) on a unit area can be greatly improved.
The solution has limitation on improving the storage density of the magnetic random access memory, and the embodiment of the application provides a novel magnetic random access memory with a three-dimensional storage structure, which can better improve the storage density of the magnetic random access memory.
Fig. 1 is a schematic side view of a magnetic random access memory according to an embodiment of the present application, where the magnetic random access memory includes at least two stacked layers 10, and each stacked layer 10 of the at least two stacked layers 10 includes at least one magnetic random access memory structure, and the magnetic random access memory structures in two adjacent stacked layers 10 are disposed in a crossing manner. Wherein the magnetic random access memory structure comprises an SOT bottom electrode layer 11 and at least one magnetic tunnel junction MTJ12 arranged on a first surface of the SOT bottom electrode layer 11, the first surface of the SOT bottom electrode layer 11 of each magnetic random access memory structure facing in the same direction.
For convenience of description, in the following explanation of the embodiment of the present application, the layers of each of the magnetic random access memory structure and the SOT bottom electrode layer 11 thereof, and the magnetic tunnel junction MTJ12 may be defined, for example, the layers of the magnetic random access memory structure, the SOT bottom electrode layer 11 thereof, and the magnetic tunnel junction MTJ12, and the corresponding layers of the magnetic random access memory structure of the layer stack structure 10, the SOT bottom electrode layer 11 of any one of the magnetic random access memory structures of the layer stack structure 10, and the magnetic tunnel junction MTJ12 will not be explained in detail.
The magnetic random access memory provided by the embodiment of the application has a three-dimensional storage structure, and the storage density of the magnetic random access memory can be better improved through the at least two-layer stacked structure 10.
The magnetic random access memory structures in the adjacent two-layer stacked structure 10 are preferably arranged in a vertically crossed manner.
Preferably, when each of the stacked structures 10 includes a plurality of magnetic random access memory structures, the plurality of magnetic random access memory structures of each of the stacked structures 10 are arranged in parallel.
Preferably, for each magnetic random access memory structure, when the magnetic random access memory structure includes a plurality of magnetic tunnel junctions MTJ12, the distance between the plurality of magnetic tunnel junctions MTJ12 is a preset distance, and the preset distance is the shortest distance for cleaning the sidewalls of the film layers of the plurality of magnetic tunnel junctions MTJ12.
Further preferably, the magnetic random access memory according to the embodiment of the application is a three-dimensional memory structure, so that the horizontal distance between adjacent magnetic tunnel junctions MTJ12 on different layers is smaller than the adjacent distance between a plurality of magnetic tunnel junctions MTJ12 arranged on the same layer SOT bottom electrode layer 11, thereby facilitating device miniaturization and integration and further improving the memory density.
Referring to fig. 1, 2 and 3, a first embodiment of the present application improves the storage density of the mram by using a multi-layer stack 10 (fig. 3 shows only two layers of stacks 10). The magnetic random access memory comprises a two-layer stack 10, each layer stack 10 of the two-layer stack 10 comprising at least one magnetic random access memory structure. Referring to fig. 1, the upper stacked structure 10 includes, for example, two (and more) mram structures, and the lower stacked structure 10 includes, for example, one mram structure; referring to fig. 1 and 2, the magnetic random access memory structures in the adjacent two-layer stacked structure 10 are vertically crossed; referring to fig. 1 and 3, the magnetic random access memory structure includes an SOT bottom electrode layer 11 and at least one magnetic tunnel junction MTJ12 disposed on a first surface of the SOT bottom electrode layer (also referred to as a spin-orbit coupling layer) 11, the first surface of the SOT bottom electrode layer 11 of each magnetic random access memory structure facing in the same direction. The plurality of magnetic random access memory structures of each layer of the stacked structure 10 (e.g., the stacked structure 10 of the upper layer) are arranged in parallel.
As described above, the prior art can connect two magnetic tunnel junctions MTJ12 in parallel on the SOT bottom electrode layer 11 to increase the storage density. Referring to fig. 1 and 3, in the first embodiment of the present application, two parallel magnetic tunnel junctions MTJ12 may be disposed on two SOT bottom electrode layers 11 of an upper stacked structure 10, and one magnetic tunnel junction MTJ12 may be disposed on each of the SOT bottom electrode layers 11 of a lower stacked structure 10, so that the horizontal distance between the memory cells of two (adjacent different layers) magnetic tunnel junctions MTJ12 is shorter than the horizontal distance between the memory cells of the same layer under the condition that the predetermined distance between the memory cells of the magnetic tunnel junctions MTJ12 is ensured, and the memory density of the magnetic random access memory may be improved.
Preferably, a plurality of magnetic tunnel junctions MTJ12 are deposited on a predetermined position of the SOT bottom electrode layer 11 with the first surface of the SOT bottom electrode layer 11 of each magnetic random access memory structure facing upward, and each magnetic tunnel junction MTJ12 may include a free layer, a barrier layer, a reference layer, and a pinned layer from bottom to top.
By way of illustration, the free layer and the reference layer may be composed of magnetic materials, and the random access memory MRAM uses the magnetic moment directions of the free layer and the reference layer for data writing to enable information storage. For example, when the magnetic moment directions of the free layer and the reference layer are the same (or parallel), the tunneling resistance of the magnetic tunnel junction MTJ12 is in a low resistance state (e.g., corresponding to writing "0"), and when the magnetic moment directions of the free layer and the reference layer are opposite (or antiparallel), the tunneling resistance of the magnetic tunnel junction MTJ12 is in a high state (e.g., corresponding to writing "1"). SOT-MRAM is based on a spin orbit coupling layer, and uses spin current induced by current (also called as write current) to generate spin transfer torque, so as to control the reversal of the magnetic moment direction of a free layer, and realize data writing.
Referring to fig. 1, 2 and 3, when the magnetic tunnel junction MTJ12 is fabricated, the shape of the magnetic tunnel junction MTJ12 may be made elliptical or rectangular by photolithographic patterning, so that the easy magnetization direction of the magnetic tunnel junction MTJ12 may be defined in a direction perpendicular to the writing current, and an in-plane horizontal magnetization inversion Type magnetic random access memory, i.e., type-Y SOT-MRAM (may also be referred to as Type-Y SOT-MRAM) may be formed, and the current applied to the SOT bottom electrode layer 11 may directly determine the magnetization inversion direction of the free layer of the magnetic tunnel junction MTJ12, without external magnetic field assistance, thereby achieving data writing.
Preferably, when the magnetic random access memory is an in-plane horizontal magnetization inversion type magnetic random access memory, for each magnetic random access memory structure, the free layer magnetization of the selected magnetic tunnel junction MTJ12 of the magnetic random access memory structure is inverted by a write current applied to the SOT bottom electrode layer 11 of the magnetic random access memory structure to write data into the selected magnetic tunnel junction MTJ12.
By way of example, please refer to the Type-Y SOT-MRAM shown in fig. 3, for each magnetic random access memory structure, the free layer magnetization of a selected magnetic tunnel junction MTJ12 of the magnetic random access memory structure is flipped by a write current applied to the SOT bottom electrode layer 11 of the magnetic random access memory structure to write data into the selected magnetic tunnel junction MTJ12. Multiple magnetic random access structures of the multi-layer stack 10 may be written simultaneously.
In the first embodiment of the present application, under the condition of ensuring the preset distance of the magnetic tunnel junctions MTJ12, the horizontal distance of each two magnetic tunnel junctions MTJ12 is shorter than the horizontal distance of each two magnetic tunnel junctions MTJ12 of the two-dimensional (one-layer magnetic random access memory structure) magnetic random access memory, and the three-dimensional space is fully utilized to improve the storage density of the magnetic random access memory.
Referring to fig. 4, the embodiment of the present application improves the storage density of the mram by using the multi-layer stack 10 (only two layers are shown in fig. 4). The magnetic random access memory comprises a stack of more than two layers 10, each layer 10 comprising at least one magnetic random access memory structure. For example, the uppermost stacked structure 10 includes, for example, a plurality of magnetic random access structures, and the lowermost stacked structure 10 includes, for example, a plurality of magnetic random access structures; the magnetic random access memory structures in the adjacent two-layer stacked structure 10 are vertically crossed; the magnetic random access memory structure comprises an SOT bottom electrode layer 11 and at least one magnetic tunnel junction MTJ12 arranged on a first surface of the SOT bottom electrode layer 11, the first surface of the SOT bottom electrode layer 11 of each magnetic random access memory structure facing in the same direction. An out-of-plane perpendicular magnetization flip Type magnetic random access memory, i.e., a Type-Z SOT-MRAM (may also be referred to as a Type-Z SOT-MRAM) is formed, with perpendicular magnetic anisotropy. The plurality of magnetic random access memory structures of each layer of stacked structure 10 are arranged in parallel.
Referring to fig. 1 and 4, preferably, when the mram is an out-of-plane perpendicular magnetization inversion type mram, for each of the mram structures, a magnetic moment of a selected MTJ12 of the mram structure is deviated from a perpendicular direction by a predetermined angle by an external magnetic field, and then a free layer magnetization of the selected MTJ12 is inverted by a spin transfer torque generated by a write current applied to the SOT bottom electrode layer 11 of the mram structure, so that data is written to the selected MTJ12, and the external magnetic field is a magnetic field generated by a predetermined current applied to the SOT bottom electrode layer 11 of any one of the mram structures 10 adjacent to the mram structure.
Referring to fig. 4 and 5, taking data writing to the selected MTJ12 of the lower layer as an example, after a preset current is added to the SOT bottom electrode layer 11 (also called spin-orbit coupling layer) of a random access memory structure of the upper stack structure 10, a horizontal right directional oersted magnetic field, i.e., the external magnetic field, is generated according to the right-hand rule; the external magnetic field causes the magnetic moment of the magnetic tunnel junction MTJ12 selected by the (magnetic random access memory structure of the) underlying stack structure 10 to deviate from the vertical direction by a predetermined angle in the horizontal direction perpendicular to the magnetic moment of the free layer; applying a write current to the SOT bottom electrode layer 11 of the selected magnetic tunnel junction MTJ12, and enabling the generated spin current to realize the directional inversion of the magnetic moment of the free layer of the selected magnetic tunnel junction MTJ 12; further, application of a write current to the SOT bottom electrode layer (also known as a spin-orbit coupling layer) 11 of (the magnetic random access memory structure of) the underlying stack 10 also generates a magnetic field, which in turn generates a fixed magnetic field to the magnetic tunnel junction MTJ12 of its overlying or underlying stack 10 to effect a directional inversion of the selected magnetic tunnel junction MTJ12 of the overlying layer. Therefore, the magnetic random access memory of the embodiment of the application can realize data storage without an external magnetic field.
Wherein the preset current may be a current less than the write current, and the preset current may generate a magnetic field (i.e., an external magnetic field of the magnetic tunnel junction MTJ12 of the adjacent layer) without flipping the magnetic tunnel junction MTJ12 of the present layer. Further preferably, embodiments of the present application may write to the magnetic tunnel junction MTJ12 of different layers separately or simultaneously. When the preset current for generating the external magnetic field is smaller than the write current, the preset current only generates the magnetic field and does not turn over the corresponding magnetic tunnel junction MTJ12 so as to realize the respective writing; when the preset current for generating the external magnetic field is the write current, the preset current can generate the external magnetic field and turn over the corresponding magnetic tunnel junction MTJ12 to realize simultaneous writing.
The conventional Type-Z SOT-MRAM requires external magnetic field assistance for completing deterministic inversion of the free layer of the magnetic tunnel junction MTJ12, but the second embodiment of the application can effectively solve the problem of field-free inversion of the Type-Z SOT-MRAM device by means of the SOT effect and the oersted field generated by the adjacent vertical structure. In the magnetic random access memory structure, under the condition that the preset distance of the Magnetic Tunnel Junctions (MTJs) 12 is ensured, the horizontal distance between two adjacent Magnetic Tunnel Junctions (MTJs) 12 is shorter than that between two Magnetic Tunnel Junctions (MTJs) 12 of a two-dimensional (one-layer magnetic random access memory structure) magnetic random access memory, so that the storage density of the magnetic random access memory is improved, and the variability of the Magnetic Tunnel Junctions (MTJs) 12 in the magnetic random access memory structure is less influenced by the shape, so that the miniaturization and integration of devices are facilitated, and the storage density is further improved.
Referring to fig. 1, the magnetic random access memory according to the preferred embodiment of the present application further includes a top electrode layer 13 disposed above each of the magnetic tunnel junctions MTJ12, and the data of the selected magnetic tunnel junction MTJ12 is read by a read current applied to the top electrode layer 13.
The preferred magnetic random access memory of the embodiment of the present application further comprises a gating circuit arranged on each magnetic tunnel junction MTJ12 for enabling selection of the magnetic tunnel junction MTJ12 by control of the gating circuit.
For example, the gating circuit may include word and bit select lines disposed on each of the magnetic tunnel junctions MTJ12, the selection of the magnetic tunnel junctions MTJ12 being accomplished by a combination of control of the word and bit select lines of each of the magnetic tunnel junctions MTJ12.
Accordingly, the magnetic random access memory according to the embodiment of the application has a three-dimensional memory structure, and the memory density of the magnetic random access memory can be improved better through the at least two-layer stacked structure 10. The embodiment of the application also provides a stacking structure 10 of the two magnetic random access memories, namely a Type-Y Type SOT-MRAM and a Type-Z Type SOT-MRAM. According to the embodiment of the application, faster data writing is realized through the SOT effect, and the erasable frequency is effectively improved; further realizes directional inversion of magnetic moment of the free layer of the magnetic tunnel junction MTJ12, and ensures reliability of data storage.
Fig. 6 is a flowchart of a method for manufacturing a magnetic random access memory according to an embodiment of the application, referring to fig. 1 and 6, the method for manufacturing a magnetic random access memory may include the following steps:
step S110: a first layer stack 10 is fabricated.
Step S110 may include: at least one SOT bottom electrode layer 11 is deposited on the substrate wafer material, and at least one magnetic tunnel junction MTJ12 is grown on a first surface of each SOT bottom electrode layer 11 of the at least one SOT bottom electrode layer 11.
By way of example, at least one SOT bottom electrode layer 11 and magnetic tunnel junction MTJ12 layer are deposited on the substrate wafer material (e.g., a free layer, barrier layer, reference layer may be grown sequentially on the first surface of the corresponding SOT bottom electrode layer 11); the magnetic tunnel junction MTJ12 is formed by photolithography, etching, and the like. An SOT bottom electrode layer 11 and at least one magnetic tunnel junction MTJ12 at a first surface of the SOT bottom electrode layer 11 constitute a magnetic random access memory structure, and at least one magnetic random access memory structure constitutes a first layer stack structure 10 (bottom layer stack structure 10), as shown in FIG. 7A.
Preferably, an insulating layer SiO deposition is performed on the first layer stack structure 10, and then a polishing process is performed on the surface of the first layer stack structure 10 by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) or the like.
Step S110: a second layer stack 10 is fabricated.
Step S120 may include: at least one groove is etched at a preset position of the first layer stack structure 10, an SOT bottom electrode layer 11 of the second layer stack structure 10 is grown at each groove, and at least one magnetic tunnel junction MTJ12 is grown on a first surface of each SOT bottom electrode layer 11.
Wherein the SOT bottom electrode layers 11 in adjacent two stacked structures 10 are arranged crosswise.
The SOT bottom electrode layers 11 in the adjacent two-layer stacked structure 10 are preferably arranged vertically in a crossing manner.
By way of example, at least one recess (e.g., a rectangular parallelepiped recess) is etched in the SiO material of the first layer stack 10 by photolithography, etching, etc., and the material from which the second layer stack 10 is made is grown, as shown in fig. 7B. The above-described grooves are used for growing the SOT bottom electrode layer 11 of the second layer stack 10, and the SOT bottom electrode layers 11 in the two layer stack 10 are arranged vertically intersecting. Preferably, the surface of the structure is ground and polished by a CMP process to planarize the surface.
Similar to the fabrication of the first layer stack structure 10 in step S110, one SOT bottom electrode layer 11 and magnetic tunnel junction MTJ12 layer are grown at each recess (e.g., a reference layer, a barrier layer, and a free layer may be grown sequentially on the first surface of the corresponding SOT bottom electrode layer 11); the magnetic tunnel junction MTJ12 is formed by photolithography, etching, and the like. An SOT bottom electrode layer 11 and at least one magnetic tunnel junction MTJ12 at a first surface of the SOT bottom electrode layer 11 form a magnetic random access memory structure, at least one magnetic random access memory structure forming a second layer stack structure 10, as shown in FIG. 7C.
Step S130: when the mram includes more than two stacked layers 10, the fabrication process of the second stacked layers 10 is repeated.
Preferably, when each layer of the stacked structure 10 includes a plurality of SOT bottom electrode layers 11, the plurality of SOT bottom electrode layers 11 of each layer of the stacked structure 10 are arranged in parallel.
Preferably, for each magnetic random access memory structure, when the magnetic random access memory structure includes a plurality of magnetic tunnel junctions MTJ12, the distance between the plurality of magnetic tunnel junctions MTJ12 is a preset distance, and the preset distance is the shortest distance for cleaning the sidewalls of the film layers of the plurality of magnetic tunnel junctions MTJ12.
Further preferably, the magnetic random access memory according to the embodiment of the application is a three-dimensional memory structure, so that the horizontal distance between adjacent magnetic tunnel junctions MTJ12 in different layers of magnetic random access memory structures is smaller than the distance between adjacent magnetic tunnel junctions MTJ12 arranged on the same layer of SOT bottom electrode layer 11, thereby facilitating device miniaturization and integration and further improving the memory density.
It should be noted that, the structure of the mram formed by the method of manufacturing the embodiment of the present application may refer to the foregoing embodiment, and will not be described herein again.
The embodiment of the application also provides electronic equipment, which comprises a processor and the magnetic random access memory coupled with the processor.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims (14)

1. A magnetic random access memory is characterized in that the magnetic random access memory comprises at least two layers of stacked structures, each layer of stacked structure comprises at least one magnetic random access memory structure, the magnetic random access memory structures in two adjacent layers of stacked structures are arranged in a crossing way,
wherein each magnetic random access memory structure comprises an SOT bottom electrode layer and at least one Magnetic Tunnel Junction (MTJ) arranged on a first surface of the SOT bottom electrode layer, the first surface of the SOT bottom electrode layer of each magnetic random access memory structure faces in the same direction.
2. The mram of claim 1, wherein the mram structures in the two adjacent layers of stacked structures are vertically interleaved.
3. The mram of claim 1, wherein when the each layer of stacked structures comprises a plurality of mram structures, the plurality of mram structures of each layer of stacked structures are arranged in parallel.
4. The magnetic random access memory of claim 1, wherein for each of the magnetic random access memory structures, when the magnetic random access memory structure includes a plurality of Magnetic Tunnel Junctions (MTJs), the distance between the plurality of Magnetic Tunnel Junctions (MTJs) is a predetermined distance,
the preset distance is the shortest distance for cleaning the side wall of the film layers of the Magnetic Tunnel Junctions (MTJs).
5. The mram of claim 1, wherein each magnetic tunnel junction MTJ comprises, from bottom to top, a free layer, a barrier layer, a reference layer, and a pinned layer with a first surface of the SOT bottom electrode layer of each magnetic random access memory structure facing upward.
6. The magnetic random access memory of claim 5 wherein, when the magnetic random access memory is an in-plane horizontal magnetization flip type magnetic random access memory,
for each magnetic random access memory structure, switching the free layer magnetization of a selected magnetic tunnel junction MTJ of the magnetic random access memory structure by a write current applied to the SOT bottom electrode layer of the magnetic random access memory structure to write data to the selected magnetic tunnel junction MTJ.
7. The magnetic random access memory of claim 5 wherein, when the magnetic random access memory is an out-of-plane perpendicular magnetization flip type magnetic random access memory,
for each magnetic random memory structure, the magnetic moment of the selected magnetic tunnel junction MTJ of the magnetic random memory structure perpendicular to the free layer is deviated from the perpendicular direction by a preset angle through an external magnetic field, then the free layer magnetization of the selected magnetic tunnel junction MTJ is reversed through spin transfer torque generated by write current applied to the SOT bottom electrode layer of the magnetic random memory structure to write data into the selected magnetic tunnel junction MTJ,
the external magnetic field is a magnetic field generated by a preset current applied to the SOT bottom electrode layer of any one of the stacked structures adjacent to the magnetic random access memory structure.
8. The magnetic random access memory of claim 1 further comprising a top electrode layer disposed over each of the magnetic tunnel junctions MTJ,
the data of the selected magnetic tunnel junction MTJ is read by a read current applied to the top electrode layer.
9. The magnetic random access memory of claim 1, further comprising a gating circuit disposed on each magnetic tunnel junction MTJ for effecting selection of a magnetic tunnel junction MTJ by control of the gating circuit.
10. A method of manufacturing a magnetic random access memory, the method comprising:
fabricating a first layer stack structure, depositing at least one SOT bottom electrode layer on a substrate wafer material, and growing at least one Magnetic Tunnel Junction (MTJ) on a first surface of each SOT bottom electrode layer of the at least one SOT bottom electrode layer;
manufacturing a second layer stack structure, etching at least one groove at a preset position of the first layer stack structure, growing an SOT bottom electrode layer of the second layer stack structure at each groove, and growing at least one Magnetic Tunnel Junction (MTJ) on the first surface of each SOT bottom electrode layer; and
when the magnetic random access memory comprises more than two layers of stacked structures, repeating the manufacturing process of the second layer of stacked structures,
wherein SOT bottom electrode layers in two adjacent layers of stacked structures are arranged in a crossing way.
11. The method of claim 10, wherein the SOT bottom electrode layers in the adjacent two-layer stack structure are arranged vertically intersecting.
12. The method of claim 10, wherein when each of the stacked structures includes a plurality of SOT bottom electrode layers, the plurality of SOT bottom electrode layers of each of the stacked structures are arranged in parallel.
13. The method of manufacturing a magnetic random access memory according to claim 10, wherein, for each magnetic random access memory structure, when the magnetic random access memory structure includes a plurality of Magnetic Tunnel Junctions (MTJs), a distance between the plurality of Magnetic Tunnel Junctions (MTJs) is a predetermined distance,
the preset distance is the shortest distance for cleaning the side wall of the film layers of the Magnetic Tunnel Junctions (MTJs).
14. An electronic device comprising a processor and the magnetic random access memory of any of claims 1-9 coupled to the processor.
CN202310733749.6A 2023-06-20 2023-06-20 Magnetic random access memory, manufacturing method thereof and electronic equipment Pending CN116615033A (en)

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CN202310733749.6A CN116615033A (en) 2023-06-20 2023-06-20 Magnetic random access memory, manufacturing method thereof and electronic equipment

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Application Number Priority Date Filing Date Title
CN202310733749.6A CN116615033A (en) 2023-06-20 2023-06-20 Magnetic random access memory, manufacturing method thereof and electronic equipment

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CN116615033A true CN116615033A (en) 2023-08-18

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