CN116096212A - Method for manufacturing multi-bit magnetic memory cell and memory cell - Google Patents

Abstract

The invention provides a manufacturing method of a multi-bit magnetic memory cell, a multi-bit magnetic memory cell and a memory, wherein the method comprises the following steps: forming a spin-orbit torque layer; at least one magnetic tunnel junction for storing data and at least one magnetic body for providing a leakage magnetic field to the magnetic tunnel junction are formed on the spin-orbit torque layer, so that asymmetry of the magnetic tunnel junction is enhanced.

Description

Method for manufacturing multi-bit magnetic memory cell and memory cell

Technical Field

The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a multi-bit magnetic memory cell and a memory cell.

Background

With the continuous shrinking of semiconductor process dimensions, moore's law slows down, and the increase in leakage current and interconnect delay become bottlenecks in conventional CMOS memories. Finding new generation memory technology solutions has become an important point in integrated circuit research, where magnetic random access memory cells are receiving widespread attention. Compared with the traditional device, the magnetic random access memory (Magnetic random access memory, MRAM) has the advantages of unlimited erasing times, non-volatility, high reading and writing speed, irradiation resistance and the like, is hopeful to become a general memory, and is an ideal device for constructing a next-generation nonvolatile memory and in-memory calculation. To further increase the storage density of SPIN-orbit torque devices, researchers have proposed a quasi-two-terminal structure of NAND-SPIN that enables multi-bit data storage by fabricating two or more Magnetic Tunnel Junctions (MTJs) on the same SPIN-orbit torque layer. While the number of transistors required for the overall structure is reduced because the magnetic tunnel junction shares transistors connected to the spin-orbit torque layer, the design effectively increases the storage density.

For this structure, researchers have proposed a corresponding data writing scheme. One such writing scheme is to erase all magnetic tunnel junctions to a first state using SPIN-orbit torque (Spin orbit torque, SOT) current, and then write part of the magnetic tunnel junctions to a second state using SPIN-orbit torque (Spin transfer torque, STT) current, with the read margin and power consumption of the NAND-SPIN limiting the improvement in performance.

Disclosure of Invention

It is an object of the present invention to provide a method for fabricating a multi-bit magnetic memory cell that increases the read margin and reduces power consumption. It is another object of the present invention to provide a multi-bit magnetic memory cell.

In order to achieve the above object, one aspect of the present invention discloses a method for manufacturing a multi-bit magnetic memory cell, comprising:

forming a spin-orbit torque layer;

at least one magnetic tunnel junction for storing data and at least one magnetic body for providing a leakage magnetic field to the magnetic tunnel junction such that asymmetry of the magnetic tunnel junction is enhanced are formed on the spin-orbit torque layer.

Preferably, the method further comprises:

a protective dielectric layer is formed over the at least one magnetic tunnel junction and the at least one magnetic body.

Preferably, the method further comprises:

breakdown the magnetic body.

Preferably, the magnetic body includes a first ferromagnetic layer, a second ferromagnetic layer, an insulating layer, and a third ferromagnetic layer sequentially disposed from top to bottom, the third ferromagnetic layer being formed on the spin-orbit torque layer;

the method further comprises:

etching at least one of the first ferromagnetic layer, the second ferromagnetic layer, the insulating layer and the third ferromagnetic layer of the magnetic body to form a first hollow region;

a magnetic material or a protective medium is deposited in the first hollow region.

Preferably, the method further comprises:

etching away the magnetic body to form a second hollow area;

and depositing a magnetic material in the second hollow region.

Preferably, the number of the magnetic tunnel junctions and the magnetic bodies is plural;

wherein one or more of the magnetic tunnel junctions and one or more of the magnetic bodies are disposed apart in a direction of a spin-orbit torque current input from the spin-orbit torque layer.

Preferably, the method comprises the steps of,

one or two of the magnetic tunnel junctions and one or two of the magnetic bodies are arranged at intervals along the direction of the spin-orbit-torque current inputted from the spin-orbit-torque layer.

Preferably, the method further comprises:

providing a first electrode on top of the magnetic tunnel junction;

a second electrode is provided on top of at least one of the magnetic bodies.

Preferably, the method further comprises:

and connecting the second electrode of the magnetic body with the second electrode with a data writing module, wherein the data writing module is used for determining a writing current path of a corresponding magnetic tunnel junction according to data to be written, and writing spin-orbit torque current through a current input end of the second electrode or the spin-orbit torque layer on the writing current path so as to write the data to be written into the corresponding magnetic tunnel junction.

The application also discloses a multi-bit magnetic memory cell which is manufactured by the manufacturing method.

The manufacturing method of the multi-bit magnetic memory cell forms a spin-orbit torque layer; at least one magnetic tunnel junction for storing data and at least one magnetic body for providing a leakage magnetic field for the magnetic tunnel junction are formed on the spin-orbit torque layer. The invention increases the magnetic tunnel junction capable of providing the leakage magnetic field, so that the magnetic tunnel junction for storing data is influenced by the magnetic body, the writing asymmetry of a storage unit is enhanced, the reading margin is increased, the STT writing power consumption is reduced, and the high reliability and the low power consumption performance optimization of the NAND-SPIN are realized.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art multi-bit magnetic memory cell;

FIG. 2 is a flow chart of an embodiment of a method of fabricating a multi-bit magnetic memory cell of the present invention;

FIG. 3 is a flow chart showing a method of fabricating a multibit magnetic memory cell of the present invention, including S300;

FIG. 4 is a flow chart showing a method of fabricating a multibit magnetic memory cell of the present invention including S400;

FIG. 5 is a schematic diagram of a magnetic tunnel junction and magnetic body of an embodiment of a method of fabricating a multi-bit magnetic memory cell of the present invention;

FIG. 6 is a flow chart of partial etching of a magnetic body according to an embodiment of a method of fabricating a multibit magnetic memory cell of the present invention;

FIG. 7 is a schematic diagram of partial etching of a magnetic body according to an embodiment of a method of fabricating a multibit magnetic memory cell of the present invention;

FIG. 8 is a flow chart illustrating the overall etching of the magnetic body in accordance with an embodiment of the method for fabricating a multibit magnetic memory cell of the present invention;

FIG. 9 is a schematic diagram of the overall etching of a magnetic body according to an embodiment of a method for fabricating a multibit magnetic memory cell of the present invention;

FIGS. 10 and 11 are schematic diagrams showing two arrangements of magnetic tunnel junctions and magnetic bodies according to embodiments of the method of fabricating a multibit magnetic memory cell of the present invention;

FIG. 12 is a flow chart illustrating a method of fabricating a multibit magnetic memory cell of the present invention in which a first electrode is disposed;

FIG. 13 is a schematic diagram showing a method for fabricating a multibit magnetic memory cell of the present invention with a first electrode disposed thereon;

FIG. 14 is a flow chart illustrating a method of fabricating a multibit magnetic memory cell of the present invention in which a first electrode and a second electrode are disposed;

FIG. 15 is a schematic diagram showing a method for fabricating a multibit magnetic memory cell of the present invention in which a first electrode and a second electrode are disposed;

FIG. 16 is a flow chart illustrating a method of fabricating a multibit magnetic memory cell of the present invention, including S900;

fig. 17 shows a schematic diagram of a computer device suitable for use in implementing embodiments of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In one or more embodiments of the present invention, NAND-SPIN refers to a multi-bit memory cell in which two or more magnetic tunnel junctions are fabricated on the same SPIN-orbit torque layer.

In one or more embodiments of the present invention, TST (trigger-spin) writing refers to writing of memory cell data by applying an SOT current and an STT current simultaneously or in an overlapping manner.

It should be noted that in one or more embodiments of the present invention, the VCMA effect (Voltage-controlled magnetic anisotropy effect) refers to increasing or decreasing the device's critical switching current by applying a Voltage across a particular device (e.g., a magnetic tunnel junction) such that the device's anisotropy increases or decreases.

In the prior art, for data writing in a multi-bit magnetic memory cell, all magnetic tunnel junctions are typically erased or written to the AP (Antiparallel) state by an SOT current, and then written to the P (Parallel) state by an STT current. When the data writing asymmetry increases, for example, the critical switching current from the P-state to the AP-state increases, which means that the read margin increases; the critical switching current from AP state to P state decreases, which means that the STT current write power consumption decreases and the overall power consumption decreases.

The patent CN 108538328B discloses a NAND-SPIN data writing scheme. In this patent, simultaneous or overlapping application of SOT current in conjunction with STT current enables data writing. The final state of the memory cell is determined by the STT current direction. By extension, the required STT critical current can be increased or decreased by adjusting the SOT current. Similarly, this patent also suffers from the problem of increasing the asymmetry and the number of operating steps by means of the scheme of TST.

As shown in fig. 1, patent CN201710812254.7, "a high density magnetic memory device," discloses a NAND-SPIN structure. However, the structure does not involve any design for increasing the writing asymmetry, the reading margin and the writing power consumption have larger optimization space, and each MTJ is used as a data storage MTJ.

In summary, increasing asymmetry is an effective means of improving NAND-SPIN performance. When the data writing asymmetry increases, for example, the critical flip current from the second state to the first state increases, which means that the read margin increases; the critical switching current from the first state to the second state decreases, which means that the STT current write power consumption decreases and the overall power consumption decreases. The invention provides a multi-bit magnetic memory cell with a magnetic tunnel junction providing a leakage magnetic field, which increases the writing asymmetry of the memory cell, improves the data reading and writing performance of the multi-bit magnetic memory cell, increases the reading margin and reduces the power consumption. Compared with the prior art, the write asymmetry is enhanced through the VCMA effect, the write asymmetry is enhanced through the magnetic body, the preparation process of the magnetic body is compatible with the preparation process of the MTJ, and the VCMA effect is not required to be considered, so that the magnetic memory unit does not need to accurately regulate and control the interface quality during preparation, and also does not need to be provided with a related circuit structure for controlling the strength of the VCMA effect.

Based on this, according to one aspect of the present invention, a method of fabricating a multi-bit magnetic memory cell is disclosed. As shown in fig. 2, in this embodiment, the method includes:

s100: forming a spin-orbit torque layer C;

s200: at least one magnetic tunnel junction M for storing data and at least one magnetic body N for providing a leakage magnetic field to the magnetic tunnel junction M are formed on the spin-orbit torque layer C such that asymmetry of the magnetic tunnel junction M is enhanced. The manufacturing method of the multi-bit magnetic memory cell forms a spin-orbit torque layer C; at least one magnetic tunnel junction M for storing data and at least one magnetic body N for providing a leakage magnetic field to the magnetic tunnel junction M are formed on the spin-orbit torque layer C, the magnetic body N having a size larger than that of the magnetic tunnel junction M. The magnetic tunnel junction M for storing data is influenced by the magnetic body N by adding the magnetic tunnel junction M capable of providing a leakage magnetic field, so that the writing asymmetry of a storage unit is increased, the reading margin is increased, the STT writing power consumption is reduced, and the high reliability and low power consumption performance optimization of the NAND-SPIN are realized.

Preferably, the magnetic body N and the magnetic tunnel junction M may be formed by a single process to reduce the process complexity of manufacturing the magnetic memory cell. On this basis, it is more preferable that the size of the magnetic body N formed simultaneously with the magnetic tunnel junction M is made larger than the size of the magnetic tunnel junction M so that the magnetic body N can form a strong leakage magnetic field to enhance the asymmetry of the magnetic tunnel junction M.

Specifically, the magnetic layer in the magnetic tunnel junction M is a ferromagnetic material B5, so that the magnetic layer or layers in the magnetic tunnel junction M may exhibit a certain magnetic property (leakage field, leakage magnetic field, or dipole interaction, dipolar interaction, or stray field) to the outside. Even after the pinned layer A1 is fabricated, the leakage field that appears outside the magnetic tunnel junction M is difficult to completely eliminate. Therefore, the magnetic body N formed simultaneously with the magnetic tunnel junction M also exhibits a leakage magnetic field to the outside, and the effect of the leakage magnetic field is more remarkable when the distance between the magnetic tunnel junction M and the magnetic body N is closer. Therefore, the magnetic tunnel junction M is influenced by the leakage magnetic field of the magnetic body N, the anisotropy of one side is reduced, the power consumption is reduced while potential barrier breakdown caused by overlarge write voltage is avoided, the anisotropy of the magnetic tunnel junction M is overcome in a coordinated manner without inputting STT current, the STT asymmetry is increased, and the reading margin is increased.

It will be appreciated that the leakage field of the magnetic body N is related to the direction of the magnetic moment of the magnetic body N (which may be analogous to a reference magnetic return line), and that the magnetic tunnel junction M around the magnetic body N is subject to an equivalent magnetic field that resembles a magnetic return line. Therefore, the asymmetry of STT writing can be enhanced by modulating M and N so that the M energy of the magnetic tunnel junction in the AP state and the P state is unequal.

In a preferred embodiment, as shown in fig. 3, the method further comprises:

s300: a protective dielectric layer is formed over the at least one magnetic tunnel junction M and the at least one magnetic body N.

It will be appreciated that forming the protective dielectric layer over the magnetic tunnel junction M and the magnetic body N, the protective dielectric layer being formed of an insulating material, maintains isolation between the magnetic tunnel junction M and the magnetic body N and also maintains the stability of the magnetic tunnel junction M and the magnetic body N without toppling.

In a preferred embodiment, as shown in fig. 4, the method further comprises:

s400: breakdown of the magnetic body N.

It is understood that after the magnetic body N is molded, the magnetic body N may be subjected to breakdown treatment to reduce the magnetic resistance of the magnetic body N and increase the leakage magnetic field strength.

In an alternative embodiment, the magnetic tunnel junction M includes a pinned layer A1, a fixed layer A2, a barrier layer A3, and a free layer A4 sequentially disposed from top to bottom, the free layer A4 being formed on the spin-orbit torque layer C. The magnetic body N includes a first ferromagnetic layer B1, a second ferromagnetic layer B2, an insulating layer B3, and a third ferromagnetic layer B4, which are sequentially disposed from top to bottom, as shown in fig. 5. As shown in fig. 6, the method further comprises:

s510: at least one of the first ferromagnetic layer B1, the second ferromagnetic layer B2, the insulating layer B3, and the third ferromagnetic layer B4 of the magnetic body N is etched away to form a first hollow region.

S520: a magnetic material B5 or a protective medium is deposited in the first hollow region.

It is understood that, as shown in fig. 7, after the magnetic body N is obtained, at least one of the first ferromagnetic layer B1, the second ferromagnetic layer B2, the insulating layer B3, and the third ferromagnetic layer B4 of the magnetic body N may be etched by a photolithography process or the like to form a first hollow region, and the magnetic material B5 or the protective medium may be deposited in the first hollow region to increase the magnetic field strength of the leakage magnetic field formed to the surrounding magnetic tunnel junction M.

In another alternative embodiment, as shown in fig. 8, the method further comprises:

s610: and etching away the magnetic body N to form a second hollow area.

S620: a magnetic material B5 is deposited in the second hollow region.

It will be appreciated that after the magnetic body N is obtained, as shown in fig. 9, all layers of the magnetic body N may be etched by a photolithography process or the like to form a cavity, i.e., a second hollow region, and then the second hollow region is filled with the magnetic material B5 to form a leakage magnetic field to the surrounding magnetic tunnel junction M through the filled magnetic material B5. In this alternative embodiment, since the second hollow region is entirely filled with the magnetic material B5, the magnetic field strength of the formed leakage magnetic field is relatively strong, and the size of the magnetic body N can be reduced to reduce the cost.

In a preferred embodiment, the number of the magnetic tunnel junctions M and the magnetic bodies N is plural.

Wherein one or more of the magnetic tunnel junctions M and one or more of the magnetic bodies N are arranged apart in a direction of a spin-orbit torque current inputted from the spin-orbit torque layer C.

It will be appreciated that by spacing the magnetic body N from the magnetic tunnel junction M, the magnetic tunnel junction M in the memory cell can be affected by the leakage field of the magnetic body N.

Preferably, the plurality of magnetic tunnel junctions M and the plurality of magnetic bodies N may be arranged as follows: one or two of the magnetic tunnel junctions M and one or two of the magnetic bodies N are arranged at intervals in the direction of the spin-orbit-torque current inputted from the spin-orbit-torque layer C. In a specific example, the magnetic tunnel junctions M and the magnetic bodies N may be alternately arranged, for example … … nm … …, where M represents the magnetic bodies N and N represents the magnetic tunnel junctions M, as shown in fig. 10. In another specific example, the magnetic tunnel junctions M and the magnetic bodies N may be alternately arranged, for example … … NNMNNM … …, as shown in fig. 11. Of course, in other embodiments, the magnetic tunnel junctions M and the magnetic bodies N may be arranged in a similar manner to MMNNMMNN, and those skilled in the art may determine the arrangement of the magnetic tunnel junctions M and the magnetic bodies N according to actual needs, which is not limited in the present invention.

In a preferred embodiment, each of the magnetic tunnel junctions M is less than 2 times the size of the magnetic body N from the nearest magnetic body N.

It will be appreciated that the plurality of magnetic tunnel junctions M and the plurality of magnetic bodies N may be arranged in a variety of ways, preferably such that each magnetic tunnel junction M is spaced from its nearest magnetic body N by less than 2 times the size of the magnetic body N, i.e. less than 2 times the size of the magnetic tunnel junction M in the horizontal direction, to ensure that each magnetic tunnel junction M is affected by the leakage magnetic field of the magnetic body N. Of course, in practical applications, those skilled in the art may determine the distance between the magnetic tunnel junction M and the nearest magnetic body N according to practical situations, which is only illustrated herein by way of example and not limitation in the present application.

In a preferred embodiment, as shown in fig. 12, the method further comprises:

s700: a first electrode is arranged on top of the magnetic tunnel junction M.

It will be appreciated that the magnetic tunnel junction M is used to store data, and when writing data to the magnetic tunnel junction M, a write current needs to be input to the magnetic tunnel junction M to make the resistance state of the magnetic tunnel junction M correspond to the write current, thereby achieving the purpose of data writing. By providing a first electrode on top of the magnetic tunnel junction M, the magnetic tunnel junction M may be connected to an external data writing module through the first electrode, and the data writing module may input a data write current to the magnetic tunnel junction M through the first electrode. The first electrode can also be used for reading the resistance state of the magnetic tunnel junction M, and the data reading module of the multi-bit magnetic memory can input a reading signal to the magnetic tunnel junction M through the first electrode, and the resistance state of the magnetic tunnel junction M is determined through the change of the reading signal, so that the data stored in the magnetic tunnel junction M is determined.

As shown in fig. 13, a first electrode may be disposed on top of the magnetic tunnel junction M, and the first electrode may be connected to the data writing module or the data reading module through a switching element such as a transistor, and the data writing module or the data reading module may be controlled to input a corresponding data writing current or reading signal to the magnetic tunnel junction M by controlling on or off of the switching element through a control signal.

In a preferred embodiment, as shown in fig. 14, the method further comprises:

s800: a second electrode is provided on top of at least one of the magnetic bodies N.

It will be appreciated that the magnetic body N is used to provide a leakage magnetic field for the magnetic tunnel junction M, so that the top of the magnetic body N may or may not be provided with an electrode. In this preferred embodiment, a second electrode is provided on top of at least one magnetic body N. The magnetic body N with the second electrode can be used as a bottom electrode of the magnetic tunnel junction M, i.e. as an input or output of the SOT current, on the one hand, and as a part of the SOT current input path of the magnetic tunnel junction M, e.g. MNM, when arranged, on the other hand, the magnetic body N with the second electrode can be used to input a current to the magnetic body N via the second electrode to increase the strength of the leakage magnetic field formed by the magnetic body N.

As shown in fig. 15, a second electrode may be provided on top of the magnetic body N, and the second electrode may be connected to a switching element such as a transistor, and the on or off of the switching element may be controlled by a control signal, thereby controlling an input current or an SOT current flowing through the magnetic body N.

In a preferred embodiment, as shown in fig. 16, the method further comprises:

s900: and connecting the second electrode of the magnetic body N with the second electrode with a data writing module, wherein the data writing module is used for determining a write current path of a corresponding magnetic tunnel junction M according to data to be written, and writing spin-orbit torque current through a current input end of the second electrode or the spin-orbit torque layer C on the write current path so as to write the data to be written into the corresponding magnetic tunnel junction M.

It can be understood that the writing current path of the corresponding magnetic tunnel junction M can be determined according to the data to be written, and the SOT current input end and the output end of the writing current path can be the spin-orbit torque layer C or the magnetic body N with the second electrode.

It is understood that the magnetic tunnel junction M may include a pinned layer A1, a fixed layer A2, a barrier layer A3, and a free layer A4 sequentially disposed from top to bottom. The resistance of the magnetic tunnel junction M depends on the magnetization directions of the fixed layer A2 and the free layer A4, and the magnetization directions of the free layer A4 and the fixed layer A2 are determined by the magnetic moment directions. When the magnetic moment directions of the fixed layer A2 and the free layer A4 are the same, the magnetic tunnel junction M is in a low resistance state (low resistance state), and when the magnetic moment directions of the fixed layer A2 and the free layer A4 are opposite, the magnetic tunnel junction M is in a high resistance state (high resistance state). The high resistance state and the low resistance state of the magnetic tunnel junction M may be respectively associated with different data in advance, for example, the high resistance state is associated with data "1" and the low resistance state is associated with data "0", and then a current or a voltage is input to the magnetic tunnel junction M through the reading circuit, and it may be determined whether the resistance state of the magnetic tunnel junction M is the resistance state of the high resistance state or the low resistance state according to a change of the current or the voltage, and it may be determined whether the data stored in the magnetic tunnel junction M is "1" or "0" according to the resistance state of the magnetic tunnel junction M. The ranges of the high resistance state and the low resistance state are determined as common technical means in the art, and a person skilled in the art can determine the resistance ranges of the high resistance state and the low resistance state of the magnetic tunnel junction M according to common general knowledge, which is not described herein.

In an alternative embodiment, the magnetic tunnel junction M may further comprise at least one of an interposer, a seed layer, and a capping layer. The arrangement of each layer structure may be one or more layers according to actual requirements, and a person skilled in the art may arrange the arrangement sequence of each layer structure of the magnetic tunnel junction M from top to bottom according to requirements, which is not limited in the present invention.

Alternatively, the shape of the magnetic tunnel junction M on the spin-orbit torque layer C may be any one of a cube, a cylinder, a cube, or an elliptic cylinder. The bottom surface shape of at least one magnetic tunnel junction M disposed on the spin-orbit torque layer C, i.e., the lower surface of the free layer A4, is coupled with the spin-orbit torque layer C.

Preferably, the spin-orbit torque layer C may be rectangular, such that the top surface area of the spin-orbit torque layer C is larger than the area occupied by at least one magnetic tunnel junction M disposed on the spin-orbit torque layer C, even though the at least one magnetic tunnel junction M may be disposed on the spin-orbit torque layer C with the outer edge of the at least one magnetic tunnel junction M located inside the outer edge of the spin-orbit torque layer C. The spin orbit moment layer C is preferably selected from a heavy metal strip film, an antiferromagnetic strip film, a topological insulator or the like.

Preferably, the materials of the first electrode and the second electrode may be any one of tantalum Ta, aluminum Al, gold Au, or copper Cu.

Preferably, the materials of the free layer A4 and the fixed layer A2 may be ferromagnetic metals, and the material of the barrier layer A3 may be an oxide. The magnetic tunnel junction M has perpendicular magnetic anisotropy, or in-plane magnetic anisotropy, or an intermediate state therebetween. The ferromagnetic metal can be a mixed metal material formed by at least one of cobalt iron CoFe, cobalt iron boron CoFeB or nickel iron NiFe, and the proportion of the mixed metal materials can be the same or different. The oxide may be one of magnesia MgO or alumina Al2O3, etc. for generating tunneling magneto-resistance effect. In practical applications, ferromagnetic metals and oxides may be used as well, and the invention is not limited in this regard.

The free layer A4 of the magnetic tunnel junction M is fixedly contacted with the spin-orbit moment layer C, each layer of the magnetic tunnel junction M and the spin-orbit moment layer C can be plated on a substrate in sequence from bottom to top by the traditional methods of ion beam epitaxy, atomic layer deposition or magnetron sputtering, and then the magnetic tunnel junction M is prepared and formed by the traditional nano device processing technologies of photoetching, etching, and the like.

In this embodiment, the magnetic tunnel junction M includes a pinned layer A1, a fixed layer A2, a free layer A4 in contact with the spin-orbit torque layer C, and a barrier layer A3 provided between the fixed layer A2 and the free layer A4, and the magnetic tunnel junction M includes only one free layer A4. In other embodiments, the free layer A4 may be provided in multiple, i.e., more than two, free layers A4. The magnetic tunnel junction M includes a top fixed layer A2, a plurality of free layers A4, and a barrier layer A3 provided between every two adjacent layers, the lowermost free layer A4 being disposed in contact with the spin-orbit torque layer C. For example, in one specific example, when a two-layer free layer A4 is included, the magnetic memory cell structure may include a spin-orbit torque layer C, a second free layer A4, a barrier layer A3, a first free layer A4, a barrier layer A3, a fixed layer A2, and a pinned layer A1, which are sequentially disposed on the spin-orbit torque layer C.

Based on the same principle, the embodiment also discloses a multi-bit magnetic memory cell. The multi-bit magnetic memory cell is fabricated by the fabrication method described in this embodiment.

Since the principle of solving the problem by the unit is similar to that of the above method, the implementation of the unit can be referred to the implementation of the method, and will not be described herein.

Based on the same principle, the embodiment also discloses a multi-bit magnetic memory. The multi-bit magnetic memory comprises a plurality of multi-bit magnetic memory cells as described in this embodiment arranged in an array.

The multi-bit magnetic memory, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technique. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of applications for multi-bit magnetic memory include, but are not limited to, random Access Memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.

Since the principle of solving the problem of the multi-bit magnetic memory is similar to that of the multi-bit magnetic memory cell, the implementation of the multi-bit magnetic memory can be referred to the implementation of the multi-bit magnetic memory cell, and the description thereof is omitted herein.

Based on the same principle, the embodiment also discloses a computer device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor.

The processor and/or the memory comprise a multi-bit magnetic storage unit as described in this embodiment.

The multi-bit magnetic memory cell illustrated in the above embodiments may be provided in particular in a product device having a certain function. A typical implementation device is a computer device, which may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

In a typical example the computer device comprises in particular a memory, a processor and a computer program stored on the memory and executable on the processor, said processor and/or said memory comprising a multi-bit magnetic storage unit as described in the present embodiment.

Reference is now made to FIG. 17, which illustrates a schematic diagram of a computer device suitable for use in practicing embodiments of the present application.

As shown in fig. 17, the computer device includes a Central Processing Unit (CPU) 601, which can execute various appropriate works and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603. In the RAM603, various programs and data required for system operation are also stored. The CPU601, ROM602, and RAM603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, mouse, etc.; an output portion 607 including a Cathode Ray Tube (CRT), a liquid crystal feedback device (LCD), and the like, and a speaker, and the like; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The drive 610 is also connected to the I/O interface 605 as needed. Removable media 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on drive 610 as needed, so that a computer program read therefrom is mounted as needed as storage section 608.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.

Claims (10)

1. A method of fabricating a multi-bit magnetic memory cell, comprising:

forming a spin-orbit torque layer;

at least one magnetic tunnel junction for storing data and at least one magnetic body for providing a leakage magnetic field to the magnetic tunnel junction such that asymmetry of the magnetic tunnel junction is enhanced are formed on the spin-orbit torque layer.

2. The method of fabricating a multi-bit magnetic memory cell of claim 1, further comprising:

a protective dielectric layer is formed over the at least one magnetic tunnel junction and the at least one magnetic body.

3. The method of fabricating a multi-bit magnetic memory cell of claim 1, further comprising:

breakdown the magnetic body.

4. The method of fabricating a multibit magnetic memory cell according to claim 1 or 3, wherein the magnetic body comprises a first ferromagnetic layer, a second ferromagnetic layer, an insulating layer, and a third ferromagnetic layer sequentially disposed from top to bottom, the third ferromagnetic layer being formed on the spin-orbit-torque layer;

the method further comprises:

etching at least one of the first ferromagnetic layer, the second ferromagnetic layer, the insulating layer and the third ferromagnetic layer of the magnetic body to form a first hollow region;

a magnetic material or a protective medium is deposited in the first hollow region.

5. A method of fabricating a multi-bit magnetic memory cell according to claim 1 or 3, further comprising:

etching away the magnetic body to form a second hollow area;

and depositing a magnetic material in the second hollow region.

6. The method of claim 1, wherein the number of magnetic tunnel junctions and the magnetic bodies is a plurality;

wherein one or more of the magnetic tunnel junctions and one or more of the magnetic bodies are disposed apart in a direction of a spin-orbit torque current input from the spin-orbit torque layer.

7. The method of manufacturing a multi-bit magnetic memory cell of claim 6, wherein,

one or two of the magnetic tunnel junctions and one or two of the magnetic bodies are arranged at intervals along the direction of the spin-orbit-torque current inputted from the spin-orbit-torque layer.

8. The method of fabricating a multi-bit magnetic memory cell of claim 1, further comprising:

providing a first electrode on top of the magnetic tunnel junction;

a second electrode is provided on top of at least one of the magnetic bodies.

9. The method of fabricating a multi-bit magnetic memory cell of claim 1, further comprising:

and connecting the second electrode of the magnetic body with the second electrode with a data writing module, wherein the data writing module is used for determining a writing current path of a corresponding magnetic tunnel junction according to data to be written, and writing spin-orbit torque current through a current input end of the second electrode or the spin-orbit torque layer on the writing current path so as to write the data to be written into the corresponding magnetic tunnel junction.

10. A multi-bit magnetic memory cell fabricated by the method of any one of claims 1-9.

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