CN111293138A - Three-dimensional MRAM memory structure and manufacturing method thereof - Google Patents
Three-dimensional MRAM memory structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a three-dimensional MRAM memory structure and a manufacturing method thereof, wherein the structure comprises: the first storage layer comprises a CMOS circuit substrate, a magnetic tunneling junction device, a source line metal layer, a word line metal layer and a bit line metal layer; the first connection circuit layer is used for providing read-write signals of the storage layers and providing a signal connection path between two adjacent storage layers; a plurality of second memory layers directly formed on the first connection circuit layers, and a plurality of second connection circuit layers between the adjacent second memory layers. Compared with the traditional process, the invention does not need the steps of single-layer chip flow, grinding and thinning, alignment welding and the like in a Through Silicon Via (TSV) process, directly prepares the multilayer memory circuit on the same substrate through orderly stacking of semiconductor materials and metal wiring layers, and has the manufacturing process compatible with a CMOS process.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a three-dimensional MRAM storage structure and a manufacturing method thereof.
Background
As portable computing devices and wireless communication devices increase in use, memory devices may require higher density, lower power consumption, and/or non-volatility. The magnetic memory device may be capable of satisfying the above-mentioned technical requirements.
Many electronic devices contain electronic memory. The electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is capable of storing data when power is lost, whereas volatile memory is not capable of storing data when power is lost. Magnetoresistive Random Access Memory (MRAM) is a promising candidate for next generation electronic memory due to its advantages over current electronic memories. MRAM is generally faster and has better endurance than current non-volatile memories such as flash random access memory. MRAM generally has similar performance and density compared to current volatile memories, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), but MRAM has lower power consumption. Since the MTJ device has high operation speed and low power consumption and is used to replace a capacitor of a DRAM, the MTJ device can be applied to an image device and a mobile device having low power consumption and high speed.
The magnetoresistive device has a low resistance when the spin directions (i.e., the directions of magnetic fluxes) of the two magnetic layers are the same as each other, and a high resistance when the spin directions are opposite to each other. In this way, bit data can be written to the magnetoresistive memory device using a change in cell resistance that changes depending on the magnetization state of the magnetic layer. A magnetoresistive memory having an MTJ structure will be described by way of example. In an MTJ memory cell having a structure composed of a ferromagnetic layer/insulating layer/ferromagnetic layer, when electrons that have passed through a first ferromagnetic layer pass through an insulating layer serving as a tunneling barrier (tunneling barrier), the tunneling probability changes depending on the magnetization direction of a second ferromagnetic layer. That is, when the magnetization directions of the two ferromagnetic layers are parallel, the tunneling current is maximized, and when they are antiparallel, the tunneling current is minimized. For example, it can be considered that when the resistance is high, data "1" is written, and when the resistance is low, data "0" is written. When a current flows through the magnetic layer, the current will be polarized, forming a spin-polarized current. Spin electrons transfer spin momentum to a magnetic moment of a free magnetic layer, so that the magnetic moment of the spin magnetic layer obtains spin momentum and then changes direction, which is called spin transfer torque, and thus, the STT-MRAM realizes information writing by spin current.
The core of the STT-MRAM memory cell remains an MTJ, consisting of two ferromagnetic layers of different thickness and a nonmagnetic spacer layer of a few nanometers thick. Through external circuitry, current can pass through the MTJ from a direction perpendicular to the MJT surface. When a current passes through a thicker ferromagnetic layer (called the fixed magnetic layer), the electrons are spin polarized, with the spin direction being the magnetic moment direction of the fixed magnetic layer. If the thickness of the intermediate nonmagnetic spacer layer is small enough to ensure a high degree of polarization, spin-polarized electrons can transfer their spin angular momentum to the thinner ferromagnetic layer (called the free magnetic layer), changing the magnetization equilibrium state of the free magnetic layer. The fixed magnetic layer, which plays the role of the "polarizable layer", is generally thick (tens of nanometers), has a large saturation magnetization, and its equilibrium state is unchanged. In contrast, the free magnetic layer to be subjected to the spin torque effect is generally thin and has a small saturation magnetization, and therefore, its magnetic moment vector can freely change its orientation according to the polarization direction of the spin electron in the spin current. The STT-MRAM memory unit has simple structure, no additional write information line with magnetic casing, minimized preparation process, reduced cross section area, high memory density and fast memory speed, and can meet the design requirement of high performance computer system.
With the gradual termination of moore's law, it becomes increasingly difficult to increase the memory density of memory chips through device scaling. At present, all MRAM memory chips put into production are single-layer memory chips, and the memory density of the chips can be remarkably improved and the application range of the MRAM memory chips can be expanded through the effective stacking of a plurality of layers of memory circuits.
The 3D stacking techniques that have been proposed so far are mostly done by TSV (through silicon via) techniques. The memory layer substrate stacked in the technical scheme needs to be thinned to be less than 100um from the back, so that the process difficulty is high; the TSV occupies a large area, and the density of storage bits is limited; when each layer of memory chip is welded, a bonding pad needs to be prepared, and accurate welding is guaranteed, so that the process yield is limited; the interconnection lines between the memory layers are long, increasing the parasitic capacitance/inductance.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional MRAM memory structure and a method for fabricating the same, which are used to solve the problems of the prior art that 3D stacking needs to be implemented by through silicon vias, the process difficulty is large, and the density of memory bits is limited.
To achieve the above and other related objects, the present invention provides a method for fabricating a three-dimensional MRAM memory structure, the method comprising: 1) providing a CMOS circuit substrate, and forming a magnetic tunneling junction device on the CMOS circuit substrate, wherein the first end of the magnetic tunneling junction device is connected with the drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit substrate; 2) preparing a source line metal layer, a word line metal layer and a bit line metal layer, wherein the source line metal layer, the word line metal layer and the bit line metal layer are isolated by interlayer dielectric layers, and the source line metal layer, the word line metal layer and the bit line metal layer are respectively connected with a source electrode of the MOS tube, a grid electrode of the MOS tube and a second end of the magnetic tunneling junction device through holes to form a first storage layer; 3) preparing a first connection circuit layer on the first storage layer, wherein the first connection circuit layer is used for providing read-write signals of the storage layers and providing a signal connection path between two adjacent storage layers; 4) forming a semiconductor material layer on the first connection circuit layer, manufacturing a CMOS circuit layer based on the semiconductor material layer, manufacturing a magnetic tunneling junction device on the CMOS circuit layer, then repeating the step 2) to form a second storage layer, and then repeating the step 3) to form a second connection circuit layer on the second storage layer; 5) repeating step 4) a plurality of times to form a three-dimensional MRAM memory structure.
Preferably, the CMOS circuit substrate includes one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate.
Preferably, the flexible substrate comprises one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate, and polyethylene naphthalate.
Preferably, step 2) comprises: 2-1) forming a first dielectric layer covering the CMOS circuit substrate and the magnetic tunneling junction device, forming a first through hole in the first dielectric layer, wherein the first through hole is communicated with the source electrode of the MOS tube, forming a first electrode layer on the first dielectric layer and in the first through hole, and patterning the first electrode layer to form the source line metal layer; 2-2) forming a second dielectric layer covering the source line metal layer, forming a second through hole in the second dielectric layer and the first dielectric layer, wherein the second through hole is communicated with the grid electrode of the MOS tube, forming a second electrode layer on the second dielectric layer and in the second through hole, and patterning the second electrode layer to form the word line metal layer; 2-3) forming a third dielectric layer covering the word line metal layer, forming a third through hole in the third dielectric layer, the second dielectric layer and the first dielectric layer, wherein the third through hole is communicated with the second end of the magnetic tunneling junction device, forming a third electrode layer on the third dielectric layer and in the third through hole, and patterning the third electrode layer to form the bit line metal layer.
Preferably, in step 4), a semiconductor material layer is formed on the first connection circuit layer by using a chemical vapor deposition method or an atomic layer deposition method, and the material of the semiconductor material layer includes one of silicon, germanium, silicon carbide and a group iii-v compound.
Preferably, the magnetic tunneling junction device includes a first metal connection layer, a first metal transition layer, a fixed magnetic layer, a tunneling layer, a free magnetic layer, a second metal transition layer, and a second metal connection layer, which are sequentially stacked, and the first metal connection layer is connected to a drain of an MOS transistor of the CMOS circuit.
Preferably, the material of the fixed magnetic layer includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material.
Preferably, the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
The present invention also provides a three-dimensional MRAM memory structure, comprising: the first storage layer comprises a CMOS circuit substrate, a magnetic tunneling junction device, a source line metal layer, a word line metal layer and a bit line metal layer, wherein the magnetic tunneling junction device is formed on the CMOS circuit substrate, the first end of the magnetic tunneling junction device is connected with the drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit substrate, the source line metal layer, the word line metal layer and the bit line metal layer are isolated by interlayer dielectric layers, and the source line metal layer, the word line metal layer and the bit line metal layer are respectively connected with the source electrode of the MOS tube, the grid electrode of the MOS tube and the second end of the magnetic tunneling junction device through holes; the first connection circuit layer is formed on the first storage layer and used for providing read-write signals of the storage layers and providing a signal connection path between two adjacent storage layers; the second storage layers comprise a CMOS circuit layer, a magnetic tunneling junction device, a source line metal layer, a word line metal layer and a bit line metal layer, the magnetic tunneling junction device is located on the CMOS circuit layer, the first end of the magnetic tunneling junction device is connected with the drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit layer, the source line metal layer, the word line metal layer and the bit line metal layer are isolated by interlayer dielectric layers, and the source line metal layer, the word line metal layer and the bit line metal layer are respectively connected with the source electrode of the MOS tube, the grid electrode of the MOS tube and the second end of the magnetic tunneling junction device through holes; and the second connecting circuit layers are positioned between the adjacent second storage layers and used for providing read-write signals of the storage layers and providing signal connecting paths between the two adjacent storage layers.
Preferably, the CMOS circuit substrate includes one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate.
Preferably, the flexible substrate comprises one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate, and polyethylene naphthalate.
Preferably, the CMOS circuit layer is a CMOS circuit layer based on a semiconductor material layer, and the material of the semiconductor material layer includes one of silicon, germanium, silicon carbide and a iii-v compound.
Preferably, the magnetic tunneling junction device includes a first metal connection layer, a first metal transition layer, a fixed magnetic layer, a tunneling layer, a free magnetic layer, a second metal transition layer, and a second metal connection layer, which are sequentially stacked, and the first metal connection layer is connected to a drain of an MOS transistor of the CMOS circuit.
Preferably, the material of the fixed magnetic layer includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material.
Preferably, the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
As described above, the three-dimensional MRAM memory structure and the manufacturing method thereof of the present invention have the following advantages:
compared with the traditional process, the invention does not need the steps of single-layer chip flow, grinding and thinning, alignment welding and the like in a Through Silicon Via (TSV) process, directly prepares the multilayer memory circuit on the same substrate through orderly stacking of semiconductor materials and metal wiring layers, and has the manufacturing process compatible with a CMOS process.
Drawings
FIGS. 1-14 are schematic structural diagrams illustrating steps of a method for fabricating a three-dimensional MRAM memory structure according to the invention.
Description of the element reference numerals
10 CMOS circuit substrate
101 CMOS circuit layer
102 drain electrode
103 source electrode
104 grid
201 first metal connection layer
202 first metal transition layer
203 fixed magnetic layer
204 tunneling layer
205 free magnetic layer
206 second metal transition layer
207 second metal connection layer
208 dielectric layer
301 first dielectric layer
302 first via
303 source line metal layer
304 second dielectric layer
305 second through hole
306 word line metal layer
307 third dielectric layer
308 third through hole
309 bit line metal layer
401 first connection circuit layer
501 CMOS circuit layer
601 second connection circuit layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 14, the present embodiment provides a method for fabricating a three-dimensional MRAM memory structure, the method comprising:
as shown in fig. 1 to fig. 2, step 1) is performed first, a CMOS circuit substrate is provided, and a magnetic tunnel junction device is formed on the CMOS circuit substrate, where a first end of the magnetic tunnel junction device is connected to a drain 102 of an MOS transistor of the CMOS circuit substrate.
The CMOS circuit substrate comprises one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate.
In one embodiment, the CMOS circuit substrate 10 may include a SOI substrate-based CMOS circuit layer 102 and a planarized dielectric layer 208 overlying the CMOS circuit layer 102.
In another embodiment, the CMOS circuit substrate may also include a flexible substrate, a CMOS circuit layer located on the flexible substrate, and a flexible dielectric layer covering the CMOS circuit layer, wherein a surface roughness of the flexible dielectric layer is less than 0.2 nm. For example, the flexible substrate comprises one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate, and polyethylene naphthalate. The flexible substrate is adopted, the formed magnetic tunnel junction device is thinner and lighter than the existing magnetic tunnel junction device made of the solid ferromagnetic material, the formed MRAM is suitable for the application of a flexible circuit, the macroscopic morphology of the flexible substrate is basically not required, for example, the flexible substrate can be in a circular shape, an oval shape, a polygonal shape or any other required shape, the processing technology of the flexible substrate is simpler, and the magnetic tunnel junction device made of the solid ferromagnetic material has greater advantages compared with the existing magnetic tunnel junction device made of the solid ferromagnetic material.
The magnetic tunneling junction device comprises a first metal connecting layer 201, a first metal transition layer 202, a fixed magnetic layer 203, a tunneling layer 204, a free magnetic layer 205, a second metal transition layer 206 and a second metal connecting layer 207 which are sequentially stacked, wherein the first metal connecting layer 201 is connected with a drain electrode 102 of a MOS (metal oxide semiconductor) tube of the CMOS circuit.
The material of the first metal connection layer 201 may be one of W, Cu and Al.
The first metal connection layer 201 of this embodiment is formed on a flat flexible dielectric layer, and the first metal connection layer 201 may be subjected to planarization processing to obtain the first metal connection layer 201 with a flat surface, so as to improve the flatness of the subsequent first metal transition layer 202.
In one embodiment, the material of the fixed magnetic layer 203 includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer 205 includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material.
In another embodiment, the fixed magnetic layer 203 may be a two-dimensional magnetic material, and the material of the fixed magnetic layer 203 includes CrGeTe3And CrI3In one embodiment, the fixed magnetic layer 203 of the present invention is made of two-dimensional magnetic material, so that a thinner and lighter magnetic tunnel junction device can be obtained.
The free magnetic layer 205 may be a two-dimensional ferromagnetic material layer, and the material of the free magnetic layer 205 may be CrGeTe3And CrI3One kind of (1). The free magnetic layer 205 of the present invention is a two-dimensional ferromagnetic material layer with a small thickness, which can improve the magnetization orientation speed of the magnetic tunnel junction device on one hand, and can obtain a thinner magnetic tunnel junction device on the other hand.
The tunneling layer 204 is a two-dimensional insulating material layer with a single crystal structure, for example, the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene, and oxidized graphene. The two-dimensional insulating material layer with very thin thickness is selected for the tunneling layer 204 of the embodiment, the consistency of the tunneling layer 204 is very good, and the tunneling probability can be greatly improved while the quality and the function of the tunneling layer 204 are ensured.
As shown in fig. 3 to 11, then, step 2) is performed to prepare a source line metal layer 303, a word line metal layer 306 and a bit line metal layer 309, the source line metal layer 303, the word line metal layer 306 and the bit line metal layer 309 are isolated by an interlayer dielectric layer, and the source line metal layer 303, the word line metal layer 306 and the bit line metal layer 309 are respectively connected to the source 103 of the MOS transistor, the gate 104 of the MOS transistor and the second end of the magnetic tunneling junction device through via holes to form a first storage layer. It should be noted that, in the memory chip, besides the memory cell, there are corresponding signal read/write circuits, such as a comparator, an amplifier, etc., at the periphery of the memory cell, and this embodiment is not shown in the drawings.
Specifically, the step 2) includes:
as shown in fig. 3 to 5, step 2-1 is performed first to form a first dielectric layer 301 covering the CMOS circuit substrate and the magnetic tunnel junction device, where the first dielectric layer 301 may be silicon dioxide (SiO)2) Silicon nitride (Si)3N4) Or silicon oxynitride (SiO)xNy) And forming a first through hole 302 in the first dielectric layer 301 by using a photolithography process and an etching process, wherein the first through hole 302 is communicated with the source electrode 103 of the MOS transistor, forming a first electrode layer on the first dielectric layer 301 and in the first through hole 302, for example, by using a metal deposition process, and patterning and etching the first electrode layer to form the source line metal layer 303. Of course, the source line metal layer 303 may be formed by a metal lift-off process (lift-off). Firstly, making a patterned photoresist, then depositing a metal layer, and then removing the photoresist and the metal layer on the upper surface of the photoresist. Meanwhile, the second dielectric layer 304, the word line metal layer 306, the third dielectric layer 307, the bit line metal layer 309, and the like, which are described below, may also be fabricated by using the above-described process.
As shown in fig. 6 to 8, step 2-2) is then performed to form a second dielectric layer 304 covering the source line metal layer 303, form a second via 305 in the second dielectric layer 304 and the first dielectric layer 301, where the second via 305 is communicated with the gate 104 of the MOS transistor, form a second electrode layer on the second dielectric layer 304 and in the second via 305, and pattern the second electrode layer to form the word line metal layer 306.
As shown in fig. 9 to 11, step 2-3) is performed to form a third dielectric layer 307 covering the word line metal layer 306, form a third via hole 308 in the third dielectric layer 307, the second dielectric layer 304 and the first dielectric layer 301, the third via hole 308 is communicated with the second end of the magnetic tunnel junction device, form a third electrode layer on the third dielectric layer 307 and in the third via hole 308, and pattern the third electrode layer to form the bit line metal layer 309.
As shown in fig. 12, step 3) is performed to prepare a first connection circuit layer 401 on the first memory layer, where the first connection circuit layer 401 is used to provide read/write signals for the memory layers and provide a signal connection path between two adjacent memory layers.
As shown in fig. 13, step 4) is performed, a semiconductor material layer is formed on the first connection circuit layer 401, then a CMOS circuit layer 501 is formed based on the semiconductor material layer, and a magnetic tunnel junction device is formed on the CMOS circuit layer, and then step 2) is repeated to form a second storage layer, including:
first, a first dielectric layer 301 covering the CMOS circuit layer 501 and the magnetic tunnel junction device is formed, where the first dielectric layer 301 may be silicon dioxide (SiO)2) Silicon nitride (Si)3N4) Or silicon oxynitride (SiO)xNy) And forming a first through hole 302 in the first dielectric layer 301 by using a photolithography process and an etching process, wherein the first through hole 302 is communicated with the source 103 of the MOS transistor, forming a first electrode layer on the first dielectric layer 301 and in the first through hole 302, for example, by using a metal deposition process, and patterning and etching the first electrode layer to form the MOS transistorThe source line metal layer 303. Of course, the source line metal layer 303 may be formed by a metal lift-off process (lift-off). Firstly, making a patterned photoresist, then depositing a metal layer, and then removing the photoresist and the metal layer on the upper surface of the photoresist. Meanwhile, the second dielectric layer 304, the word line metal layer 306, the third dielectric layer 307, the bit line metal layer 309, and the like, which are described below, may also be fabricated by using the above-described process.
Then, a second dielectric layer 304 covering the source line metal layer 303 is formed, a second through hole 305 is formed in the second dielectric layer 304 and the first dielectric layer 301, the second through hole 305 is communicated with the gate 104 of the MOS transistor, a second electrode layer is formed on the second dielectric layer 304 and in the second through hole 305, and the second electrode layer is patterned to form the word line metal layer 306.
Then, a third dielectric layer 307 covering the word line metal layer 306 is formed, a third via hole 308 is formed in the third dielectric layer 307, the second dielectric layer 304 and the first dielectric layer 301, the third via hole 308 is communicated with the second end of the magnetic tunnel junction device, a third electrode layer is formed on the third dielectric layer 307 and in the third via hole 308, and the third electrode layer is patterned to form the bit line metal layer 309.
Next, step 3) is repeated to form a second connection circuit layer 601 on the second memory layer. The second connection circuit layer 601 is used for providing read/write signals of the memory layers and providing a signal connection path between two adjacent memory layers.
In one embodiment, a semiconductor material layer may be formed on the first connection circuit layer 401 by using a chemical vapor deposition method or an atomic layer deposition method, and the material of the semiconductor material layer may include one of silicon, germanium, silicon carbide, and a iii-v compound.
In another embodiment, the semiconductor material layer is a two-dimensional semiconductor material layer, the two-dimensional semiconductor material layer may be made of materials such as MoS2, WS2, black phosphorus, and the like, and may be made by a chemical vapor deposition method or an atomic layer deposition method, preferably, by an atomic layer deposition method, in this example, the two-dimensional semiconductor material layer is used, so that in the preparation process of the CMOS circuit layer 501, the preparation process only needs to be performed at a temperature lower than 400-500 ℃, and high-temperature processing at a temperature higher than 400-500 ℃ is not required, the structure of the magnetic tunneling junction device that has been manufactured below is not damaged, the stability of the performance of the magnetic tunneling junction device is greatly improved, and the production yield is improved.
As shown in fig. 14, step 5) is finally performed, and step 4) is repeated a plurality of times to form a three-dimensional MRAM memory structure, as shown in fig. 14.
As shown in fig. 14, the present embodiment further provides a three-dimensional MRAM memory structure, including: the first storage layer comprises a CMOS circuit substrate, a magnetic tunneling junction device, a source line metal layer 303, a word line metal layer 306 and a bit line metal layer 309, wherein the magnetic tunneling junction device is formed on the CMOS circuit substrate, a first end of the magnetic tunneling junction device is connected with a drain electrode 102 of an MOS (metal oxide semiconductor) transistor of the CMOS circuit substrate, the source line metal layer 303, the word line metal layer 306 and the bit line metal layer 309 are isolated by interlayer dielectric layers, and the source line metal layer 303, the word line metal layer 306 and the bit line metal layer 309 are respectively connected with a source electrode 103 of the MOS transistor, a grid electrode 104 of the MOS transistor and a second end of the magnetic tunneling junction device through holes; a first connection circuit layer 401 formed on the first memory layer for providing a read/write signal of the memory layer and providing a signal connection path between two adjacent memory layers; the memory comprises a plurality of second storage layers, wherein each second storage layer comprises a CMOS circuit layer 501, a magnetic tunneling junction device, a source line metal layer 303, a word line metal layer 306 and a bit line metal layer 309, the magnetic tunneling junction device is located on the CMOS circuit layer 501, a first end of the magnetic tunneling junction device is connected with a drain electrode 102 of an MOS (metal oxide semiconductor) tube of the CMOS circuit layer 501, the source line metal layer 303, the word line metal layer 306 and the bit line metal layer 309 are isolated by interlayer dielectric layers, and the source line metal layer 303, the word line metal layer 306 and the bit line metal layer 309 are respectively connected with a source electrode 103 of the MOS tube, a grid electrode 104 of the MOS tube and a second end of the magnetic tunneling junction device through; a plurality of second connection circuit layers 601, located between adjacent second memory layers, for providing read/write signals of the memory layers and providing signal connection paths between two adjacent memory layers.
The CMOS circuit substrate comprises one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate. For example, the flexible substrate comprises one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate, and polyethylene naphthalate.
In one embodiment, the CMOS circuit layer 501 is a CMOS circuit layer based on a semiconductor material layer, which includes one of silicon, germanium, silicon carbide and iii-v compound.
In another embodiment, the semiconductor material layer is a two-dimensional semiconductor material layer, the two-dimensional semiconductor material layer may be made of materials such as MoS2, WS2, black phosphorus, and the like, and may be made by a chemical vapor deposition method or an atomic layer deposition method, preferably, by an atomic layer deposition method, in this example, the two-dimensional semiconductor material layer is used, so that in the process of making the CMOS device layer, the two-dimensional semiconductor material layer is only required to be made at a temperature lower than 400-500 ℃, and high-temperature processing at a temperature of 400-500 ℃ is not required, the structure of the magnetic tunneling junction device that has been made below is not damaged, the stability of the performance of the magnetic tunneling junction device is greatly improved, and the production yield is improved.
The magnetic tunneling junction device comprises a first metal connecting layer 201, a first metal transition layer 202, a fixed magnetic layer 203, a tunneling layer 204, a free magnetic layer 205, a second metal transition layer 206 and a second metal connecting layer 207 which are sequentially stacked, wherein the first metal connecting layer 201 is connected with a drain electrode 102 of a MOS (metal oxide semiconductor) tube of the CMOS circuit.
The material of the fixed magnetic layer 203 includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer 205 includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material.
The tunneling layer 204 is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene, and oxidized graphene.
As described above, the three-dimensional MRAM memory structure and the manufacturing method thereof of the present invention have the following advantages:
compared with the traditional process, the invention does not need the steps of single-layer chip flow, grinding and thinning, alignment welding and the like in a Through Silicon Via (TSV) process, directly prepares the multilayer memory circuit on the same substrate through orderly stacking of semiconductor materials and metal wiring layers, and has the manufacturing process compatible with a CMOS process.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (15)
1. A method of fabricating a three-dimensional MRAM memory structure, the method comprising:
1) providing a CMOS circuit substrate, and forming a magnetic tunneling junction device on the CMOS circuit substrate, wherein the first end of the magnetic tunneling junction device is connected with the drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit substrate;
2) preparing a source line metal layer, a word line metal layer and a bit line metal layer, wherein the source line metal layer, the word line metal layer and the bit line metal layer are isolated by interlayer dielectric layers, and the source line metal layer, the word line metal layer and the bit line metal layer are respectively connected with a source electrode of the MOS tube, a grid electrode of the MOS tube and a second end of the magnetic tunneling junction device through holes to form a first storage layer;
3) preparing a first connection circuit layer on the first storage layer, wherein the first connection circuit layer is used for providing read-write signals of the storage layers and providing a signal connection path between two adjacent storage layers;
4) forming a semiconductor material layer on the first connection circuit layer, manufacturing a CMOS circuit layer based on the semiconductor material layer, manufacturing a magnetic tunneling junction device on the CMOS circuit layer, then repeating the step 2) to form a second storage layer, and then repeating the step 3) to form a second connection circuit layer on the second storage layer;
5) repeating step 4) a plurality of times to form a three-dimensional MRAM memory structure.
2. The method of claim 1, wherein: the CMOS circuit substrate comprises one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate.
3. The method of claim 2, wherein: the flexible substrate comprises one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate and polyethylene naphthalate.
4. The method of claim 1, wherein: the step 2) comprises the following steps:
2-1) forming a first dielectric layer covering the CMOS circuit substrate and the magnetic tunneling junction device, forming a first through hole in the first dielectric layer, wherein the first through hole is communicated with the source electrode of the MOS tube, forming a first electrode layer on the first dielectric layer and in the first through hole, and patterning the first electrode layer to form the source line metal layer;
2-2) forming a second dielectric layer covering the source line metal layer, forming a second through hole in the second dielectric layer and the first dielectric layer, wherein the second through hole is communicated with the grid electrode of the MOS tube, forming a second electrode layer on the second dielectric layer and in the second through hole, and patterning the second electrode layer to form the word line metal layer;
2-3) forming a third dielectric layer covering the word line metal layer, forming a third through hole in the third dielectric layer, the second dielectric layer and the first dielectric layer, wherein the third through hole is communicated with the second end of the magnetic tunneling junction device, forming a third electrode layer on the third dielectric layer and in the third through hole, and patterning the third electrode layer to form the bit line metal layer.
5. The method of claim 1, wherein: and 4) forming a semiconductor material layer on the first connecting circuit layer by adopting a chemical vapor deposition method or an atomic layer deposition method, wherein the material of the semiconductor material layer comprises one of silicon, germanium-silicon, silicon carbide and III-V compounds.
6. The method of claim 1, wherein: the magnetic tunneling junction device comprises a first metal connecting layer, a first metal transition layer, a fixed magnetic layer, a tunneling layer, a free magnetic layer, a second metal transition layer and a second metal connecting layer which are sequentially stacked, wherein the first metal connecting layer is connected with a drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit.
7. The method of claim 6, wherein: the material of the fixed magnetic layer comprises one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer comprises one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material.
8. The method of claim 6, wherein: the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer comprises one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
9. A three-dimensional MRAM memory structure, comprising:
the first storage layer comprises a CMOS circuit substrate, a magnetic tunneling junction device, a source line metal layer, a word line metal layer and a bit line metal layer, wherein the magnetic tunneling junction device is formed on the CMOS circuit substrate, the first end of the magnetic tunneling junction device is connected with the drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit substrate, the source line metal layer, the word line metal layer and the bit line metal layer are isolated by interlayer dielectric layers, and the source line metal layer, the word line metal layer and the bit line metal layer are respectively connected with the source electrode of the MOS tube, the grid electrode of the MOS tube and the second end of the magnetic tunneling junction device through holes;
the first connection circuit layer is formed on the first storage layer and used for providing read-write signals of the storage layers and providing a signal connection path between two adjacent storage layers;
the second storage layers comprise a CMOS circuit layer, a magnetic tunneling junction device, a source line metal layer, a word line metal layer and a bit line metal layer, the magnetic tunneling junction device is located on the CMOS circuit layer, the first end of the magnetic tunneling junction device is connected with the drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit layer, the source line metal layer, the word line metal layer and the bit line metal layer are isolated by interlayer dielectric layers, and the source line metal layer, the word line metal layer and the bit line metal layer are respectively connected with the source electrode of the MOS tube, the grid electrode of the MOS tube and the second end of the magnetic tunneling junction device through holes;
and the second connecting circuit layers are positioned between the adjacent second storage layers and used for providing read-write signals of the storage layers and providing signal connecting paths between the two adjacent storage layers.
10. The three-dimensional MRAM memory structure of claim 9, wherein: the CMOS circuit substrate comprises one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate.
11. The three-dimensional MRAM memory structure of claim 10, wherein: the flexible substrate comprises one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate and polyethylene naphthalate.
12. The three-dimensional MRAM memory structure of claim 9, wherein: the CMOS circuit layer is based on a semiconductor material layer, and the material of the semiconductor material layer comprises one of silicon, germanium-silicon, silicon carbide and III-V group compounds.
13. The three-dimensional MRAM memory structure of claim 9, wherein: the magnetic tunneling junction device comprises a first metal connecting layer, a first metal transition layer, a fixed magnetic layer, a tunneling layer, a free magnetic layer, a second metal transition layer and a second metal connecting layer which are sequentially stacked, wherein the first metal connecting layer is connected with a drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit.
14. The three-dimensional MRAM memory structure of claim 13, wherein: the material of the fixed magnetic layer comprises one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer comprises one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material.
15. The three-dimensional MRAM memory structure of claim 13, wherein: the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer comprises one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
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