CN116471847A - In-plane ultra-high density ferroelectric memory array and preparation method thereof - Google Patents
In-plane ultra-high density ferroelectric memory array and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention belongs to the technical field of storage, and particularly relates to an in-plane ultra-high density ferroelectric memory array and a preparation method thereof. The invention discloses an in-plane densely-arranged read-write ferroelectric memory cell and electrodes which are periodically arranged, wherein the electrodes are led out through three-dimensional interconnection conductive columns, and three-dimensional interconnection word lines comprising out-of-plane first and second word line layers are respectively connected with a first and third conductive column array; the three-dimensional interconnection bit line comprising an out-of-plane first bit line layer and a second bit line layer is respectively connected with the second conductive column array and the fourth conductive column array; parallel electrodes are distributed in the word line layer and the bit line layer and are mutually perpendicular to form a cross bar array, and the in-plane intersection point is a ferroelectric memory unit and is positioned in a gap area of the adjacent electrodes in the plane, so that high-density data can be read and written. The in-plane close-packed ferroelectric memory array of the invention can improve the memory density to 2F at most 2 F is the characteristic process dimension of semiconductor manufacture, is suitable for manufacturing ultra-high density memory devices, and has simple preparation and low cost。
Description
Technical Field
The invention belongs to the technical field of storage, and particularly relates to an in-plane ultra-high density ferroelectric memory array and a preparation method thereof.
Background
In 1963, tarui and Moll first proposed the concept of ferroelectric memories, and conventional ferroelectric memories were mainly divided into two types, one being a transistor and capacitor connection structure (1T 1C), and the other being a field effect transistor (FeFET) using a ferroelectric material as a gate dielectric layer, both of which store information according to two polarization states of the ferroelectric material. In recent years, river safety et al have invented novel ferroelectric memories based on erasable conductive domain walls (chinese patent applications nos. cn2015136526. X, CN201510036586.1, CN201610098138.9 and U.S. patent publication No. 9685216B 2) based on the study of two-dimensional structure ferroelectric domain walls, wherein domain walls are interfaces between electric domains having different polarization directions in a ferroelectric, and have optical, electrical and magnetic physical properties that are distinct from those of a bulk material. The resistance value is much smaller than that of the ferroelectric insulating block due to the structural change of the energy band at the domain wall, etc. The polarization direction of the electric domains between the electrodes is regulated and controlled by applying an electric field between the electrodes, and a parallel or anti-parallel domain structure is formed with the peripheral non-inverted electric domains, so that the conductive domain walls are written or erased, the written domain walls remain after the external field is cancelled, and the nonvolatile storage of the written information can be realized; and simultaneously, a switching domain wall current is generated, so that the nondestructive current reading of information is realized.
Based on the ferroelectric memory of this domain wall conduction in-plane read-write, jiangsecure et al have invented a ferroelectric memory with 4F 2 An in-plane read-write ferroelectric memory array of a close-packed structure and a method of manufacturing the same (Chinese patent application No. CN 202011234815.8) includes a word line layer located in a plane of memory cells, and a first bit line layer and a second bit line layer disposed outside the word line layer. The word line layer has a plurality of parallel line electrodes alternately arranged along a first direction, and ferroelectric memory cells and bit line arrays are distributed between the parallel lines. The bit line array is connected with the first bit line array and the second bit line array outside the plane through conductive columns respectively. The first bit line layer is configured above the first conductive pillar array, the second bit line layer is configured above or below the second conductive pillar array, and the first bit line layer and the second bit line layer are both composed of bit lines arranged along a second direction, wherein the second direction is perpendicular to the first direction. The intersection point of the word line and the bit line is the selected in-plane ferroelectric memory cell, and information can be read and written. Characteristic dimensions of the process (FeNature size) is F, the minimum size of the in-plane read-write ferroelectric memory is 4F 2 . In-plane high-density information storage is realized, and a schematic diagram is shown in fig. 1. In this structure, the memory devices are disposed in the cross point region of the conductive pillar bit line array and the word line, and the gap region between them is divided into a first gap group and a second gap group, which are alternately arranged, and are filled with ferroelectric medium, and cannot be all used as memory devices. In addition, the polarization direction of the ferroelectric material substrate is parallel to the electric field direction in the structure, so that the information reading and writing direction can only be along the second direction of bit line arrangement in the bit line layer. Therefore, the storage density of the structure can be further improved.
Disclosure of Invention
In view of the above, the present invention is directed to an in-plane ultra-high density ferroelectric memory array and a method for manufacturing the same, wherein the in-plane close-packed read-write ferroelectric memory array and electrodes are periodically arranged, and all the electrodes are led out through three-dimensional interconnection conductive columns. The in-plane close-packed ferroelectric memory array and the three-dimensional interconnection structure thereof can improve in-plane storage density to 2F at most 2 The method is applicable to manufacturing ultra-high density memory devices, and is simple in preparation and low in cost.
The invention provides an in-plane ultra-high density ferroelectric memory array, which structurally comprises: a ferroelectric material substrate, two word line layers, two bit line layers, four sets of conductive pillar arrays, four sets of conductive plugs, and four sets of ferroelectric memory cells;
the two word line layers are a first word line layer and a second word line layer, the two bit line layers are a first bit line layer and a second bit line layer, the four groups of conductive pillar arrays are a first conductive pillar array, a second conductive pillar array, a third conductive pillar array and a fourth conductive pillar array, the four groups of conductive plugs are a first conductive plug, a second conductive plug, a third conductive plug and a fourth conductive plug, and the four groups of ferroelectric memory cells are a first memory device, a second memory device, a third memory device and a fourth memory device;
the in-plane memory unit consists of conductive plugs and ferroelectric memory units in gap areas, wherein the conductive plugs are densely arranged in each row and each column, and the row and column densely arranged direction of the conductive plugs is not parallel to the direction of spontaneous polarization of a ferroelectric memory material substrate projected in the plane, namely, the included angle between the direction of the substrate ferroelectric polarization projected in the plane and the direction of each row and each column of the conductive plugs is more than 0 degree and less than 90 degrees;
the conductive plugs are continuously and periodically arranged in the plane according to the sequence of the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, and each four continuous conductive plugs form an arrangement period;
a first word line layer disposed over the first conductive pillar array, the word line layer having a plurality of word lines arranged along a first direction; the first conductive post is connected with the first conductive plug in the plane;
a first bit line layer disposed above or below the second conductive pillar array, having a plurality of bit lines arranged in a second direction, the number being a multiple of 4, the second direction being perpendicular to the first direction, the second conductive pillar being connected to a second conductive plug in the plane, the second conductive plug and a gap region of the first conductive plug adjacent thereto being provided with a first memory device;
a second word line layer disposed above or below the third conductive pillar array, having a plurality of word lines arranged along the first direction, the third conductive pillar being connected to a third conductive plug in the plane, a second memory device being disposed in a gap region between the third conductive plug and a second conductive plug adjacent thereto;
a second bit line layer disposed above or below the fourth conductive pillar array and having a plurality of bit lines arranged along the second direction, the fourth conductive pillar being connected to a fourth conductive plug in the plane, a third memory device being disposed in a gap region between the fourth conductive plug and a third conductive plug adjacent thereto; a fourth memory device is arranged in the gap region between the fourth conductive plug and the first conductive plug adjacent to the fourth conductive plug;
the read-write signal is biased in a memory cell region between the first word line layer, the second word line layer, and a selected word line and bit line intersection of the first bit line layer and the second bit line layer.
The ferroelectric memory array comprises a plurality of conductive plugs which are repeatedly arranged, wherein the conductive plugs are a plurality of grooves etched on the surface of a ferroelectric memory material, and conductive medium is filled in the grooves to serve as electrodes, and each conductive plug is connected with a corresponding conductive column.
In the invention, the conductive plugs are filled with conductive medium, and the resistance of the contact layer between the conductive medium and the ferroelectric material is small.
In the present invention, the conductive plugs are generally but not limited to cubes, and the conductive posts may be rectangular or cylindrical.
In the invention, a certain included angle exists between each row and each column of each row where the conductive plug is located and the initial polarization of the ferroelectric memory material in-plane projection direction, and the included angle ranges from more than 0 degrees to less than 90 degrees, and is preferably 45 degrees.
In the invention, the gap size or the memory cell size between the conductive plugs is larger than or equal to 1nm and smaller than or equal to 500nm, and the side length of the conductive plugs is preferably larger than the gap size.
In the invention, the materials of the first memory device, the second memory device, the third memory device and the fourth memory device are the same and are positioned in the same layer, and the highest 2F can be realized 2 Close-packed, better contacted with adjacent conductive plugs and smaller contact resistance.
In the invention, ferroelectric storage medium materials of the storage device are selected from lithium niobate, lithium tantalate, bismuth ferrite, barium titanate, lead zirconate titanate, hafnium oxide film materials, monocrystalline materials or combinations thereof, and through applying writing voltage between selected word lines or bit lines and higher than coercive voltage of electric domain inversion, the ferroelectric domain local inversion between adjacent electrode gaps is realized, and a parallel or antiparallel domain structure is formed with a reference electric domain which is not inverted at the bottom or the periphery, so that logic '0' or '1' information can be stored in a nonvolatile manner; the domain wall has smaller resistance than ferroelectric memory medium material, and can be erased and written along with the formation of parallel or antiparallel domain structure, when a read voltage is applied and is smaller than the coercive voltage of electric domain inversion, a larger switching current can be generated, and the written parallel or antiparallel electric domain information can be identified.
In the present invention, the memory array further includes an insulating layer including silicon oxide, silicon nitride, and aluminum oxide, where the insulating layer is disposed in the remaining space between the first word line layer, the first bit line layer, the second word line layer, the second bit line layer, the first conductive pillar array, the second conductive pillar array, the third conductive pillar array, and the fourth conductive pillar array.
In the invention, all or part of the first word line layer, the first bit line layer, the second word line layer, the second bit line layer, the first conductive pillar array, the second conductive pillar array, the third conductive pillar array and the fourth conductive pillar array are distributed above or below the plane of the ferroelectric memory medium.
The invention provides a preparation method of an in-plane read-write ferroelectric memory array, which comprises the following steps:
when the first word line layer is configured above the first conductive pillar array, the first bit line layer is configured above the second conductive pillar array, the second word line layer is configured above the third conductive pillar array, and the second bit line layer is configured above the fourth conductive pillar array, the specific steps are as follows:
the ferroelectric single-chip substrate is etched by a mask to form conductive plug grooves which are repeatedly arranged, the size of the grooves is larger than the distance between the grooves by multiple exposure and the like, and electrode materials are filled in the grooves.
Filling electrode materials in the grooves by using film growth, electroplating and chemical mechanical polishing technologies, and then depositing an insulating film layer on the surface of the ferroelectric medium;
forming a first conductive plug contact hole and configuring a first layer of word line electrode;
forming a flat insulating layer covering the surface of the first word line layer by using film growth and chemical mechanical polishing technology;
forming a second conductive plug contact hole and configuring a first layer of layer line electrode;
forming a flat insulating layer covering the surface of the first bit line layer by using film growth and chemical mechanical polishing technology;
forming a third conductive plug contact hole and configuring a second layer word line electrode;
forming a flat insulating layer covering the surface of the second word line layer by using film growth and chemical mechanical polishing technology;
a fourth conductive plug contact hole is formed and a second layer of bit line electrode is disposed.
Compared with the prior art, the invention has the beneficial effects that:
unlike the existing 4F 2 The invention relates to a ferroelectric memory array with a close-packed structure, which is characterized in that an in-plane close-packed read-write ferroelectric memory array and electrodes are arranged periodically, and all the electrodes are led out through three-dimensional interconnection conductive columns. And the row-column close-packed direction of the in-plane electrodes is not parallel to the in-plane projection direction of spontaneous polarization of the ferroelectric memory material substrate, namely, the included angle between the in-plane projection direction of the ferroelectric polarization of the substrate and each row direction of each row of the conductive plugs is larger than 0 degree and smaller than 90 degrees, and is preferably 45 degrees. The existence of the included angle can lead the electric field between any two adjacent electrodes to generate components in the polarization direction, thereby realizing the reading and writing of electric domains between any two adjacent electrodes and improving the storage density to 2F 2 。
Drawings
The above and other objects and advantages of the present invention will become more fully apparent from the following detailed description taken in conjunction with the accompanying drawings, in which identical or similar elements are designated by the same reference numerals.
FIG. 1 shows a conventional 4F 2 A schematic of the structure of a closely packed ferroelectric memory array.
Fig. 2 is a schematic three-dimensional interconnection perspective view of an in-plane ultra-high density ferroelectric memory array according to a first embodiment of the present invention.
Fig. 3 is a schematic top view of an in-plane ultra-high density ferroelectric memory array according to a first embodiment of the present invention, wherein (a) is an in-plane memory cell, and (b), (c), (d), and (e) are a first word line layer, a first bit line layer, a second word line layer, and a second bit line layer, respectively.
Fig. 4 is a schematic cross-sectional view of the in-plane ultra-high density ferroelectric memory array of fig. 3 (e) along the S1-S1' line according to the first embodiment of the present invention.
Fig. 5 is a schematic diagram of a top view (a) and a left view (b) of an in-plane read-write memory cell of the dashed box N in fig. 4 according to the first embodiment of the present invention.
Fig. 6 is a schematic diagram of the operation of the in-plane memory cell of fig. 5 according to the first embodiment of the present invention, wherein (a) is a top view and (b) is a cross-sectional view taken along the line S2-S2' in fig. 6 (a).
Fig. 7 a-7 g are schematic diagrams of a process flow for fabricating the in-plane ultra-high density ferroelectric memory array of fig. 2.
Fig. 8 is a solid-state in-plane Scanning Electron Microscope (SEM) image of a four-bit memory device structure with four-terminal electrodes.
Fig. 9 is an electrical domain imaging diagram of a four domain wall in-plane pressure electron microscope (PFM) for writing (a) and erasing (b) a four-bit memory device with four-terminal electrodes.
Fig. 10 is a current-voltage (I-V) test chart of the four-bit memory device shown in fig. 9.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description set forth herein is intended to be illustrative only of some, but not all embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without any inventive effort, based on the method proposed by the present invention are within the scope of the protection of the present invention.
In the drawings, thicknesses or pitches of layers and regions are exaggerated for clarity, and dimensional relationships between the portions shown in the drawings do not reflect actual dimensional relationships.
In the following embodiments, the electric domain direction or polarization direction is exemplarily given for clarity of description, but it should be understood that the electric domain direction or polarization direction of the ferroelectric memory is not limited to the directions shown in the embodiments as shown in the drawings.
Fig. 2 is a schematic perspective view of an in-plane ultra-high density ferroelectric memory array and its three-dimensional interconnection according to a first embodiment of the present invention, fig. 3 is a schematic top view of an in-plane read-write high density memory array according to the first embodiment of the present invention, and fig. 4 is a schematic cross-sectional view of the in-plane read-write memory array along S1-S1' line in fig. 3 (e). Referring to fig. 2, 3 and 4, the memory array structure of this embodiment mainly includes a ferroelectric material substrate 00, two word line layers WL1 and WL2, two bit line layers BL1 and BL2, four sets of conductive pillars 11, 22, 33, 44, four sets of conductive plugs 10, 20, 30, 40, four sets of memory cell arrays 12, 23, 34 and 41, and an insulating layer 000. For clarity, not all word lines, bit lines, and conductive pillars are depicted in fig. 3 and 4.
In the present invention, the ferroelectric memory medium material of the memory device is selected from lithium niobate, lithium tantalate, bismuth ferrite, barium titanate, lead zirconate titanate, hafnium oxide thin film material, single crystal material, or a combination thereof.
The word line layers are two, namely a first word line layer WL1 and a second word line layer WL2, and the bit line layers are two, namely a first bit line layer BL1 and a second bit line layer BL2. The word line layers and the bit line layers are alternately arranged outside the substrate surface, and WL1, BL1, WL2 and BL2 are arranged from the first layer to the fourth layer in sequence.
The first word line layer WL1 is located at the first layer, is connected to a part of the conductive pillars 11, and has a plurality of word lines WL11, WL12, wl13 sequentially arranged along the first direction, and each first conductive plug 10 has the first conductive pillar 11 connected thereto and is configured with the word lines connected to the conductive pillars. The conductive plugs 40 and 20 adjacent to the first conductive plug 10 have a memory cell in the gap region, the memory cell 41 is in the gap region between the first conductive plug 10 and the fourth conductive plug 40, and the memory cell 12 is in the gap region between the first conductive plug 10 and the second conductive plug 20.
The first bit line layer BL1 is located at the second layer, is connected to a portion of the conductive pillars 22, and has a plurality of bit lines BL11, BL12, BL13 arranged sequentially along a second direction, which is perpendicular to the first direction. Each of the second conductive plugs 20 has a second conductive post 22 connected thereto and is configured with a bit line connected to the conductive post. The conductive plugs 10 and 30 adjacent to the second conductive plug 20 have a memory cell in the gap region, the memory cell 12 is in the gap region between the second conductive plug 20 and the first conductive plug 10, and the memory cell 23 is in the gap region between the second conductive plug 20 and the third conductive plug 30.
The second word line layer WL2 is located at the third layer, is connected to a part of the conductive pillars 33, and has a plurality of word lines WL21, WL22, wl23 sequentially arranged along the first direction, and each third conductive plug 30 has the third conductive pillar 33 connected thereto and is configured with the word lines connected to the conductive pillars. The conductive plugs 20 and 40 adjacent to the third conductive plug 30 have a memory cell in the gap region, the memory cell 23 is in the gap region between the third conductive plug 30 and the second conductive plug 20, and the memory cell 34 is in the gap region between the third conductive plug 30 and the fourth conductive plug 40.
The second bit line layer BL2 is located on the fourth layer, is connected to a portion of the conductive pillars 44, and has a plurality of bit lines BL21, BL22, BL23 arranged sequentially in the second direction, and each of the fourth conductive plugs 40 has a fourth conductive pillar 44 connected thereto and is configured with a bit line connected to the conductive pillar. The conductive plugs 30 and 10 adjacent to the fourth conductive plug 40 have a memory cell in the gap region between the fourth conductive plug 40 and the third conductive plug 30, and the memory cell 34 in the gap region between the fourth conductive plug 40 and the first conductive plug 10, and the memory cell 41 in the gap region between the fourth conductive plug 40 and the first conductive plug 10.
The word line, bit line, conductive plug and conductive column are made of conductive materials including but not limited to copper, gold, silver, titanium, chromium and cobalt, and the conductive plug is well contacted with the ferroelectric memory cell.
The insulating layer 000 is disposed in the remaining space between the word line layers WL1 and WL2, the bit line layers BL1 and BL2, the conductive pillar arrays 11, 22, 33, 44, and includes silicon oxide, silicon nitride, and aluminum oxide.
In this embodiment, the dashed box N in fig. 4 is a memory cell between conductive plugs connected to the word line WL14 and the bit line BL18, and fig. 5 is a top view (a) and a cross-sectional view (b) of the memory cell, and the working principle of the memory cell is shown in fig. 6. When a writing voltage V larger than a coercive voltage Vc of the device is applied to a word line WL14, partial electric domains in the device are reversed, a conductive domain wall 102 is formed between the reversed electric domain 202 and the non-reversed electric domain 101, and at the moment, a reading voltage (larger than 0V and smaller than Vc) is applied to WL11, so that a low-resistance state '1' can be obtained; when a write voltage-V smaller than the coercive voltage-Vc of the device is reversely applied to the bit line BL18, the inversion domain is returned to the initial state, the conductive domain wall disappears, and the WL14 can obtain a high-resistance state of 0 by applying a read voltage.
In this embodiment, the electrode material of the selected electrode layer and the connecting line filling the contact hole is resistant to high temperature and low in resistivity, and may be, but not limited to, one or more selected from the following materials: tiN, pt, ptSi, niSi, tiW, ta, taN, ti, W, mo, al, cu, cr, ir, irO 2 ，SrRuO 3 ，RuO 2 ；
Hereinafter, a method for manufacturing a memory array according to a first embodiment will be described, and fig. 7a to 7g are schematic top views illustrating a method for manufacturing a three-dimensional memory array according to the first embodiment of the present invention, and some components are omitted in some of the drawings for clarity and convenience of description.
Firstly, preparing a smooth and flat pollution-free original substrate ferroelectric single crystal wafer or film, spin-coating photoresist on the surface, transferring the designed memory cell bump pattern onto the original substrate by using pattern transfer technologies such as optical exposure, electron beam exposure, ion beam exposure or nano imprinting, growing a layer of hard mask material, leaving the hard mask pattern on the original substrate by using a stripping technology (liftoff), etching the ferroelectric single crystal film by using a dry etching or wet etching technology, leaving the ferroelectric bump, and removing the hard mask material to form a plug groove; see fig. 7a and 7b. In fig. 7a, the side length of the in-plane electrode is equal to the gap size, i.e. the feature process size F of semiconductor manufacturing, and in order to ensure that adjacent electrodes have overlapping regions in the polarization direction, the side length of the conductive plug is preferably larger than the gap size, as shown in fig. 7b. From fig. 7a to 7b, multiple exposure methods and the like can be adopted. In addition, a certain included angle exists between each column of each row where the conductive plug is located and the initial polarization of the ferroelectric memory material in-plane projection direction, and the included angle ranges from more than 0 degrees to less than 90 degrees, preferably 45 degrees;
then, preparing a layer of electrode film, and leaving the conductive layer of the plug part by a similar method;
growing a layer of SiO 50 to 3000 nm thick on the original substrate by using a thin film growth technique such as PECVD (plasma enhanced chemical vapor deposition) technique 2 Film, polishing SiO using CMP technique 2 The film reaches the target thickness and ensures the smooth and flat surface; see fig. 7c;
optionally, in growing SiO 2 Previously growing a protective film, e.g. Si 3 N 4 Or photoresist (HSQ);
secondly, etching a contact hole at the first conductive plug 10 by using a mask, preparing the mask again and filling electrode materials, thus obtaining a first layer of word line electrode; see fig. 7d;
repeating the process shown in FIG. 7d to obtain a first layer of bit line electrode, a second layer of word line electrode and a second layer of bit line electrode; see fig. 7e, 7f, 7g.
In the embodiments of the present invention, the specific shape of the domain walls formed is not limited by the illustrated shape of the embodiments of the present invention.
In the present invention, all or part of the first word line layer WL1, the first bit line layer BL1, the second word line layer WL2, the second bit line layer BL2, the first conductive pillar array 11, the second conductive pillar array 22, the third conductive pillar array 33, and the fourth conductive pillar array 44 may be distributed below the ferroelectric memory medium plane.
In order to verify the feasibility of the close-packed structure proposed by the invention, a memory device with four-terminal electrodes is designed, and the structure of the memory device is shown in fig. 8, wherein (a) is a structural diagram, and (b) is a real-object SEM (SEM) diagram. The device consists of A, B, C, D four electrodes buried in a ferroelectric material substrate 00, wherein appropriate voltages are applied to two ends of adjacent electrodes to form inversion domains opposite to the polarization direction of the substrate, so that domain walls are generated, and the device can be erased by applying reverse voltages, and the four-bit device is shown in figure 9, wherein the four-bit device is used for writing (a) and erasing (b) PFM pictures of the four domain walls. The I-V test curves between the electrodes are shown in FIG. 10, wherein (a), (b), (c) and (d) sequentially correspond to the test conditions of the AB, AD, CD and BC electrodes, thereby realizing four-bit storage, and based on the four-bit storage characteristic, the four-terminal devices are densely arranged on a plane, so that the in-plane ultra-high density ferroelectric memory array provided by the invention can be obtained.
It will be appreciated by those of ordinary skill in the art that the present invention is not limited to the number, spatial location and order of the word line layers, word lines, bit lines and conductive pillars and conductive plugs.
In the above description, components of various embodiments described using directional terms and similar terms represent directions shown in the drawings or directions that can be understood by those skilled in the art. These directional terms are used for relative description and clarity and are not intended to limit the orientation of any embodiment to a particular direction or orientation.
The above examples mainly illustrate the preparation method of the in-plane ultra-high density ferroelectric memory array and the three-dimensional interconnection thereof according to the present invention. Although only a few embodiments of the present invention have been described, those skilled in the art will appreciate that the present invention can be embodied in many other forms without departing from the spirit or scope thereof. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is intended to cover various modifications and substitutions without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An in-plane ultra-high density ferroelectric memory array is characterized by comprising a ferroelectric material substrate, two word line layers, two bit line layers, four groups of conductive pillar arrays, four groups of conductive plugs and four groups of ferroelectric memory cells;
the two word line layers are a first word line layer and a second word line layer, the two bit line layers are a first bit line layer and a second bit line layer, the four groups of conductive pillar arrays are a first conductive pillar array, a second conductive pillar array, a third conductive pillar array and a fourth conductive pillar array, the four groups of conductive plugs are a first conductive plug, a second conductive plug, a third conductive plug and a fourth conductive plug, and the four groups of ferroelectric memory cells are a first memory device, a second memory device, a third memory device and a fourth memory device;
the in-plane memory unit consists of conductive plugs and ferroelectric memory units in gap areas, wherein the conductive plugs are densely arranged in each row and each column, and the row and column densely arranged direction of the conductive plugs is not parallel to the direction of spontaneous polarization of a ferroelectric memory material substrate projected in the plane, namely, the included angle between the direction of the substrate ferroelectric polarization projected in the plane and the direction of each row and each column of the conductive plugs is more than 0 degree and less than 90 degrees;
the conductive plugs are continuously and periodically arranged in the plane according to the sequence of the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, and each four continuous conductive plugs form an arrangement period;
a first word line layer disposed over the first conductive pillar array, the word line layer having a plurality of word lines arranged along a first direction; the first conductive post is connected with the first conductive plug in the plane;
a first bit line layer disposed above or below the second conductive pillar array, having a plurality of bit lines arranged in a second direction, the second direction being perpendicular to the first direction, the second conductive pillar being connected to a second conductive plug in the plane, the second conductive plug and a gap region of the first conductive plug adjacent thereto being provided with a first memory device;
a second word line layer disposed above or below the third conductive pillar array, having a plurality of word lines arranged along the first direction, the third conductive pillar being connected to a third conductive plug in the plane, a second memory device being disposed in a gap region between the third conductive plug and a second conductive plug adjacent thereto;
a second bit line layer disposed above or below the fourth conductive pillar array and having a plurality of bit lines arranged along the second direction, the fourth conductive pillar being connected to a fourth conductive plug in the plane, a third memory device being disposed in a gap region between the fourth conductive plug and a third conductive plug adjacent thereto; a fourth memory device is arranged in the gap region between the fourth conductive plug and the first conductive plug adjacent to the fourth conductive plug;
the read-write signal is biased in a memory cell region between the first word line layer, the second word line layer, and a selected word line and bit line intersection of the first bit line layer and the second bit line layer.
2. The in-plane ultra-high density ferroelectric memory array according to claim 1, wherein said conductive plugs are a plurality of grooves etched on the surface of the ferroelectric material substrate, and the grooves are filled with a conductive medium as an electrode, and the contact layer between the conductive medium and the ferroelectric material has a small resistance.
3. The in-plane ultra-high density ferroelectric memory array according to claim 1, wherein the conductive plugs are in the shape of cubes and the conductive pillars are rectangular or cylindrical.
4. The in-plane ultra-high density ferroelectric memory array of claim 1, wherein each column of each row of conductive plugs is at an angle of 45 ° to the in-plane projection direction of the initial polarization of the ferroelectric material.
5. The in-plane ultra-high density ferroelectric memory array according to claim 1, wherein a gap size or a memory cell size between the conductive plugs is 1nm or more and 500nm or less, and a side length of the conductive plugs is larger than the gap size.
6. The in-plane ultra-high density ferroelectric memory array of claim 1, wherein the ferroelectric memory media of the first, second, third and fourth memory devices are the same material and are in the same layer up to 2F 2 And (5) closely stacking.
7. The in-plane ultra-high density ferroelectric memory array according to claim 6, wherein the ferroelectric memory medium material of the memory device is selected from the group consisting of lithium niobate, lithium tantalate, bismuth ferrite, barium titanate, lead zirconate titanate, hafnium oxide thin film material, single crystal material, and combinations thereof, and logic "0" or "1" information can be stored in a nonvolatile manner by applying a write voltage between selected word lines or bit lines, which is greater than the coercive voltage of electric domain inversion, to achieve local inversion of ferroelectric domains in memory cells located between adjacent electrode gaps, and forming a parallel or antiparallel domain structure with a bottom or peripheral non-inversion reference electric domain; the domain wall has a smaller resistance than ferroelectric memory medium material, and can be non-volatile erased and written along with the formation of parallel or antiparallel domain structures, when a read voltage is applied and is smaller than the coercive voltage of domain inversion, a larger switching current can be generated, and written parallel or antiparallel domain logic information can be identified.
8. The in-plane ultra-high density ferroelectric memory array of claim 1, further comprising an insulating layer of one or a combination of silicon oxide, silicon nitride, or aluminum oxide materials; the insulating layer is disposed in a remaining space between the first word line layer, the first bit line layer, the second word line layer, the second bit line layer, the first conductive pillar array, the second conductive pillar array, the third conductive pillar array, and the fourth conductive pillar array.
9. The in-plane ultra-high density ferroelectric memory array of claim 1, wherein all or part of the first word line layer, the first bit line layer, the second word line layer, the second bit line layer, the first array of conductive pillars, the second array of conductive pillars, the third array of conductive pillars, and the fourth array of conductive pillars are distributed above or below the plane of the ferroelectric memory medium.
10. A method of fabricating an in-plane read-write ferroelectric memory array as claimed in any one of claims 1 to 9, characterized in that:
when the first word line layer is configured above the first conductive pillar array, the first bit line layer is configured above the second conductive pillar array, the second word line layer is configured above the third conductive pillar array, and the second bit line layer is configured above the fourth conductive pillar array, the specific steps are as follows:
forming conductive plug grooves which are repeatedly arranged on a ferroelectric material substrate through mask etching, so that the groove size is larger than the groove spacing; filling electrode materials in the grooves by using film growth, electroplating and chemical mechanical polishing technologies;
then depositing an insulating film layer on the surface of the ferroelectric medium;
forming a first conductive plug contact hole and configuring a first layer of word line electrode;
forming a flat insulating layer covering the surface of the first word line layer by using film growth and chemical mechanical polishing technology;
forming a second conductive plug contact hole and configuring a first layer of layer line electrode;
forming a flat insulating layer covering the surface of the first bit line layer by using film growth and chemical mechanical polishing technology;
forming a third conductive plug contact hole and configuring a second layer word line electrode;
forming a flat insulating layer covering the surface of the second word line layer by using film growth and chemical mechanical polishing technology;
a fourth conductive plug contact hole is formed and a second layer of bit line electrode is disposed.
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