CN102034804B - Multilayer stacked storage and manufacture method thereof - Google Patents
Multilayer stacked storage and manufacture method thereof Download PDFInfo
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Abstract
The invention discloses a multilayer stacked storage and a manufacture method thereof. A storage chip comprises a gating unit, a peripheral circuit and at least two storage unit layers, and the storage chip comprises at least two kinds of storage units. During the data storage, the data type requiring processing is judged through the peripheral circuit, and then a command is sent to select the special type of storage to make the best of various storage units and realize the optimization of the storage in various properties. During the actual application, one storage chip can replace a plurality of storage chips so as to achieve the purposes of lowering the cost and improving the property.
Description
Technical field
The invention belongs to technical field of semiconductors, relate to a kind of memory, relate in particular to a kind of memory of multiple-level stack; Simultaneously, the invention still further relates to the manufacture method of the memory of above-mentioned multiple-level stack.
Background technology
Information technology is current mainstay of the national economy industry, and semiconductor technology is again the foundation stone of information technology, and semiconductor memory is the core component of semiconductor system.Since nearly half a century, the development of semiconductor memory is maked rapid progress, and has successively emerged various types of memory devices.Current, most widely used memory device has following several: dynamic memory (DRAM), static memory (SRAM), disk, flash memory (FLASH) etc.These memories have characteristics and strong point separately, are bringing into play irreplaceable effect in every field.In addition, emerging memory technology is also constantly being emerged in large numbers, and the memory of very powerful and exceedingly arrogant phase transition storage (PCRAM), Memister (RRAM) and the conversion of magnetoresistive memory (MRAM) constant resistance is exactly outstanding representative wherein now.
Although the development along with semiconductor technology, memory technology has also obtained significant progress, the performance of aspects such as power consumption, density and speed is more and more stronger, yet, nonetheless, current do not have a kind of general memory all to have in all fields outstanding performance can to satisfy all memory functions yet.Therefore, tend adopts the polylith storage chip to obtain preferably combination property simultaneously in an electronic system, for example in the electronic product that comprises PC and smart mobile phone, all be to adopt the mixed mode such as DRAM+ mass storage (FLASH or disk) to carry out the data storage, the purpose of this mixed mode is exactly the high speed of the fully comprehensively non-volatile and DRAM of FLASH and unlimited erasable number of times, finally realizes the optimization of electronic system performance.Yet the performance of the system by adopting multiple storage chip still can't reach best state, and cost is also relatively high.Do not have at present a kind of unified memory module and can substitute above-mentioned mixed mode, if a kind of high performance unified pattern can be arranged, the performance of memory will further promote so, and the structure of electronic system also will further be simplified, and cost also will further reduce.
Summary of the invention
Technical problem to be solved by this invention is: a kind of memory of multiple-level stack is provided, can promotes the performance of memory.
In addition, the present invention also provides a kind of manufacture method of memory of multiple-level stack.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of memory of multiple-level stack comprises gating unit, peripheral circuit and two-layer at least memory cell layers in the memory chip, and comprises at least two types memory cell in the memory chip.In data storage procedure, judge the data type of required processing by peripheral circuit, send subsequently the memory of Instruction Selection particular type, make between the various memory cells and learn from other's strong points to offset one's weaknesses, realize the optimization of memory various aspects of performance, in the application of reality, a storage chip can replace the polylith storage chip, reaches the purpose that reduces cost and improving performance.
As a preferred embodiment of the present invention, memory chip has multilayered memory layer and corresponding gate tube with it.
As a preferred embodiment of the present invention, comprise at least two types memory cell in the memory.
As a preferred embodiment of the present invention, in data storage procedure, carry out the data Storage and Processing for the dissimilar memory cell of dissimilar the data, the judgement of data type and processing are to realize by comprising control module in the peripheral circuit, control module can be judged the type of required deal with data, sends subsequently the specific memory cell of Instruction Selection and carries out the data storage.Described peripheral circuit judges that the flow process of the data type of required processing one of comprises the steps: judge whether the data storage needs high speed storing; If then select the memory cell of high speed storing type; Judge whether data manipulation is frequent, if then select the memory cell of high tired type; Judge whether longer-term storage of data, if select the memory module of high data retention ability type; Otherwise select the memory module of low data holding ability type.
As a preferred embodiment of the present invention, share peripheral circuit between the multilayered memory unit.
As a preferred embodiment of the present invention, polytype memory cell characteristics separately obtain performance and utilize in this multiple-level stack memory, finally have the performance more powerful than single storage chip, chip piece can substitute the polylith storage chip in actual applications, realizes unified memory module.
As a preferred embodiment of the present invention, memory cell is volatile memory, or is nonvolatile memory.The preferably phase transition storage of the memory cell that each layer comprises, or resistance random access memory, or magnetoresistive memory, or dynamic random access memory, or static random access memory, or flash memory, or ferroelectric memory.
A kind of manufacturing comprises the method for the multiple-level stack memory of polytype memory cell, it is characterized in that comprising following steps:
A, make first kind memory cell in the brilliant first of circle, and make the brilliant first of circle have smooth surface, also with peripheral circuit and the gating unit corresponding with memory cell, wherein peripheral circuit comprises reading and writing, wipes drive circuit and data decision circuitry and instruction issue circuitry on the brilliant first of circle;
B, make the memory of Second Type and supporting gating unit in the brilliant second of circle, planarization is carried out on the brilliant second of circle surface;
C, utilize the two memories circle crystalline substance that the brilliant bonding technology of low temperature circle will above-mentioned discrete manufacturing to be bonded to together, and make the connection of each layer electricity;
D, anneal under the following temperature of 400 degree, the redundance circle of peeling off the brilliant second of circle is brilliant, and being stripped from the round crystalline substance that gets off can recycle and reuse, and peels off rear the round crystalline substance of the multiple-level stack that obtains to be carried out flatening process;
E, repetition B are to two steps of D, carry out the memory stacking technique of multilayer, until obtain the abundant memory number of plies, after multiple-level stack is complete, with peripheral circuit, the memory cell between each layer can be shared peripheral circuit, in the repetitive process in specific layer, needn't all adopt the Second Type memory cell, can be the memory cell of other types;
F, lead-in wire and encapsulation.
As a preferred embodiment of the present invention, in the storage chip use procedure, at first judge the type of required deal with data, the operation of being correlated with by the specific memory cell of the Instruction Selection of peripheral circuit subsequently by peripheral circuit.
As a preferred embodiment of the present invention, contain sandwich construction and polytype memory in the memory of multiple-level stack; The method is that the memory circle crystalline substance of discrete manufacturing is combined by bonding.
As a preferred embodiment of the present invention, step C and D) the high technology temperature of the brilliant bonding of low temperature circle that adopts is lower than 400 degree.
A kind of manufacturing comprises the method for the multiple-level stack memory of polytype memory cell, comprises following step:
A, at first make higher memory array and the peripheral circuit of high technology temperature in the brilliant first of circle;
B, utilize the brilliant bonding technology of circle, semiconductor lamella is bonded on the brilliant first of above-mentioned circle after the planarization, comprise the doped layer of having processed through the high temperature impurity activation on the semiconductor lamella;
C, employing semiconductor technology are made the gate tube array at above-mentioned semiconductor lamella, make corresponding with it second layer memory array and word/bit line;
D, filled media, and carry out flatening process;
E, repeating step B-D make the memory chip that obtains multiple-level stack, and in the repetitive process, the memory cell that needn't all adopt step C to adopt can be the memory cell of other types;
As a preferred embodiment of the present invention, in the above-mentioned step, make first the higher storage array of high technology temperature, the lower memory array of high technology temperature of rear manufacturing is not so that follow-up technological temperature affects the performance of the memory device of having made.
As a preferred embodiment of the present invention, contain sandwich construction and polytype memory in the memory of multiple-level stack.
Beneficial effect of the present invention is: the multiple-level stack memory that the present invention proposes is the advantage of various types of memory comprehensively, adopts a storage chip just can reach or above the effect of polylith chip hybrid pattern, thus the storage of realization More General Form.According to the demand of reality, in application, bring into play fully the advantage of various types of memory, make the memory of multiple-level stack possess superior combination property, in addition, the memory of multiple-level stack will be realized the growth of several times on density.Final memory is not only significantly promoted in performance, and memory unit density cost is descended significantly, has reduced the kind that adopts memory in the electronic system, all has obvious advantage on cost and performance.
In this memory chip, not only comprise the stacked structure of multi-lager semiconductor memory, also comprise polytype memory cell, namely in chip piece, just comprised multiple storage chip, realize accurate " unification " pattern.In data handling procedure, by the judgement of required deal with data type, select specific memory cell to carry out the data storage, give full play to the advantage of the various memory chips of memory inside, reach maximum effect.In addition, the memory of multiple-level stack obviously has huge advantage (sandwich construction is the density of boost device exponentially) in density, because exempted the line of overlength, three-dimensional stacking memory also will significantly be promoted on the performance of the aspects such as speed, power consumption.
This memory not only has the structure (therefore possessing advantage in density) of multilayer, possesses multiple memory cell simultaneously in single storage chip, thereby has realized accurate " unification " pattern storage, can substitute existing " mixing " pattern.In the application of reality, the data type of required processing is judged and selected by the peripheral circuit in the chip, send instruction, select suitable Storage Unit Type to carry out the data Storage and Processing; Integrated by multilayer, multilayered memory unit realized learning from other's strong points to offset one's weaknesses between the various memory cell contained in the storage chip of multiple-level stack, makes memory possess powerful combination property.
For example in a certain electronic system, some data need to be read regularly, and these data just need to be stored in the memory cell that reading speed is fast, low in energy consumption and fatigue properties are good so; And some jumbo data does not need often to read, and so just can deposit in the jumbo nonvolatile memory, and these memories does not often possess advantage on speed and power consumption.In a word, can classify according to data type, dissimilar data are deposited in the different memory cell.In existing electronic system, the realization of said process is to realize by the mixed mode of number of different types memory cell, and adopts the present invention, just can realize the comprehensive function of the polylith chip of mixed mode with chip piece, and significantly promote density.
Description of drawings
Figure 1A is the structural representation with layer stereo stacked memory, describes (only be local signal shown in the figure, do not draw peripheral circuit, gate tube etc., also non-equal proportion is drawn) as an example of 1 layer of MARAM, 2 layers of RRAM and 1 layer of PCRAM example.
Figure 1B is the cell schematics of three kinds of different memories relating among Figure 1A.
Fig. 1 C-1F is for making the process chart of this structure.
Fig. 2 A-C has the schematic diagram that the module of arbitration functions is judged when data are processed.
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Embodiment one
The structural representation of the electric resistance transition memory with multiple-level stack structure shown in Figure 1A, with this better explanation, but do not represent the present invention and be exactly this kind structure shown in Figure 1A, can change now memory the number of plies, kind, size, arrange and structure, these be not the restriction key element of the present invention.
Can see that from Figure 1A device has the stacked structure of multilayer, comprise one deck MRAM layer 101, two-layer RRAM layer 102 and one deck PCRAM layer 103.Above-mentioned each layer not only comprises resistive memory cell, also comprises corresponding with it gating unit (although do not draw at figure, not representing does not have).In addition, not only comprise magnetoresistive memory units and gating unit on 101 layers, generally also include peripheral circuit, peripheral circuit is shared by each layer, plays gating, operation effect to above-mentioned four layers of memory, also has judgement, arrangement effect to data.
It is respectively the structural representation of MRAM, RRAM and three kinds of memory cells of PCRAM shown in Figure 1B.
The upper magnet electrode layer 15 of MRAM, insulator layer 14 and lower magnet electrode layer 13 consist of a simple memory cell, generally speaking, the direction of magnetization of lower magnet electrode layer 13 is fixed, and by controlling the direction of current flowing in the upper magnet electrode layer, the direction of magnetization of magnet electrode layer in the change, and then change the resistance of whole device cell: if namely upper magnet electrode layer and lower floor are in the same way, the resistance of device will reduce, and is the logical zero state just; If upper magnet electrode layer and lower floor are reverse, the resistance of device will increase, and is the logical one state just.Obviously in Figure 1A, in 101 layers, there is the state of two mram cells to be " 1 ", there is the state of a unit to be " 0 " (illustrating).The characteristics of MRAM are to have the speed that is exceedingly fast, and shortcoming is that density is lower, and cost is higher, is suitable as the fast storage of low capacity.
The structure of RRAM is made of upper/lower electrode (24 and 26) and metal oxide 25, upper/lower electrode is generally noble metal, carry out the data storage by the metal oxide 25 with strong associated effect the resistance conversion that applies signal of telecommunication generation, for example high resistant is logical one, and low-resistance is logical zero.Structure, the manufacturing process of RRAM are simple, and cost is low, but erasable number of times is very poor, not too are fit to be often used in the product of frequent operation use, and but are fit to jumbo data storage.
The structure of PCRAM and RRAM broadly similar, also be to be consisted of by electrode pair and memory cell, because the power consumption of PCRAM constantly reduces along with the dwindling of size of unit, therefore as a rule, except upper/lower electrode 33,36, have the volume that side wall 34 limits phase-change material 35 toward contact, thereby phase-change material 35 and the contact area of bottom electrode 33 are diminished greatly, obtain better performance, be limited in simultaneously the diffusion of phase-change material in the heating process.The structure of PCRAM and manufacturing process are also very simple, and cost is also lower, and data holding ability and fatigue properties tool are good, and be right lower to the tolerance of high-temperature technology.
In sum, above-mentioned three kinds of memories are each has something to recommend him in every respect, can form good complementation, if can integrate, will greatly promote the combination property of storage chip.
In fact, not only being confined to three kinds of above-mentioned memories, also is so for the memory of other types, only is convenient clear in order to set forth at this, take above-mentioned three kinds of memories as the example explanation.In the application of reality, equally can the memories such as the memories such as DRAM or SRAM and FLASH is integrated, form above-mentioned multiple-level stack structure, this obviously within protection scope of the present invention, does not repeat them here yet.
See also Figure 1A-Fig. 1 F, the present invention has disclosed a kind of manufacture method of electric resistance transition memory of multiple-level stack, comprises the steps:
[step 1] at first makes peripheral circuit (Fig. 1 C does not show) and mram cell array in silicon base 11, and the structure of mram cell 16 as shown in Figure 1B.Wherein peripheral circuit not only comprises reading and writing, wipes circuit, also comprises to judge and transmission instruction circuit part that the MRAM array is made of mram memory cell and MOSFET gate tube, and the MOSFET gate tube does not draw in the drawings yet.Realization planarization after manufacturing is finished is shown in Fig. 1 C.
[step 2] passes through semiconductor technology, above above-mentioned 101 layers, form one deck silicon layer (monocrystalline or polycrystalline), as the basis of making gate tube, after mixing, silicon base 21 forms PN junction or Schottky barrier (need add metal level), PN junction or Schottky barrier will be used for making gating unit in follow-up step, shown in Fig. 1 D.
[step 3] makes the RRAM unit above the gating unit of correspondence, possess sandwich structure, and cellular construction carries out electric isolation by dielectric material 12 between each unit as shown in Figure 1B.
[step 4] repeating step 2 and 3 forms second layer RRAM layer, shown in Fig. 1 E.
[step 5] forms PN junction or Schottky barrier after silicon base third is mixed, PN junction or Schottky barrier will be used for making gating unit in follow-up step.
[step 6] transferred to the above-mentioned memory array that in step 4 obtain with the top layer of silicon base third with the surface silicon of PN junction or Schottky barrier by bonding method and listed (shown in Fig. 1 F), removes unnecessary silicon base and (can adopt and peel off or reduction.
[step 7] obtains making gating unit and corresponding phase change memory array by semiconductor technology on the silicon base at above-mentioned bonding, and phase-change memory cell possesses sidewall structure.
[step 8] is by encapsulating the multiple-level stack memory that just obtains containing one deck MRAM, multilayer RRAM and one deck phase transition storage, shown in Figure 1A.Obviously, the type of the memory that adopts in the above-mentioned processing step and the stacking number of plies can change according to the actual needs, here are concise and to the point illustrating.
[step 9] in the memory of the multiple-level stack that obtains, the speed of MRAM is fast, yet density is low; The characteristics of RRAM are simple in structure, and are therefore stronger to the tolerance of technological temperature because adopt metal oxide as storage medium material, namely can tolerate higher technological temperature.And comparatively speaking, higher technological temperature may damage for phase transition storage, and therefore, corresponding high temperature manufacturing process is placed on the technique front end
[step 10] practical application.Phase transition storage is compared RRAM in reliability with erasable number of times and is had larger advantage, can remedy to a great extent the deficiency of high density, low-cost RRAM device performance, remedy simultaneously the density inferior position of MRAM, finally, the memory of the multiple-level stack that obtains not only has the density of superelevation, also has preferably combination property and lower cost.Therefore, in actual mechanical process, peripheral circuit can need judge whether high speed device to data, if so, adopts MRRAM, if not, then adopt the RRAM device to carry out the data storage.Concrete judge that flow process can judge at first that data are stored for: described peripheral circuit and whether need high speed storing; If then select the memory cell of high speed storing type; Otherwise, judge whether data manipulation is frequent, if then select the memory cell of high tired type; Otherwise, judge whether longer-term storage of data, if select the memory module of high data retention ability type; Otherwise select the memory module of low data holding ability type.
In sum, the multiple-level stack memory that the present invention proposes is the advantage of various types of memory comprehensively, adopts a storage chip just can reach or above the effect of polylith chip hybrid pattern, thus the storage of realization More General Form.According to the demand of reality, in application, bring into play fully the advantage of various types of memory, make the memory of multiple-level stack possess superior combination property, in addition, the memory of multiple-level stack will be realized the growth of several times on density.Final memory is not only significantly promoted in performance, and memory unit density cost is descended significantly, has reduced the kind that adopts memory in the electronic system, all has obvious advantage on cost and performance.
Embodiment two
In the present embodiment, the manufacture method of multilayer stacked resistance transit storage of the present invention comprises the steps:
[step 1] makes peripheral circuit and two-layer DRAM accumulation layer in the brilliant first of circle, and this two-layer DRAM unit will use as memory at a high speed.
[step 2] is by adopting low temperature process to make polysilicon in the brilliant first of circle, make polysilicon diode and the phase change memory array of correspondence with it by semiconductor technology, the phase change memory that obtains the polysilicon diode gating through filling and the planarization manufacturing of dielectric material, described polysilicon diode can be the PN diode, also can be Schottky diode.
[step 3] continues deposit spathic silicon on the round crystalline substance of Multilayer Memory obtained above, makes follow-up accumulation layer, until reach the desired number of plies.
[step 4] lead packages.
[step 5] practical application.DRAM is its speed and is close to unlimited erasable number of times than the advantage of phase transition storage, and the advantage of phase transition storage is its high density and non-volatile, on same round crystalline substance that DRAM and phase transition storage is integrated, to in same storage chip, have DRAM at a high speed and be close in the unlimited erasable number of times, also possess high density and non-volatile characteristics, in consumer electronics, important using value will be arranged.Simultaneously, the stack of DRAM and phase transition storage will obtain larger density at the area of same chip.In actual applications, can at first judge by peripheral circuit whether the data of required processing need frequent operation, if so, select DRAM partly to store, if not then selecting phase transition storage.
Embodiment three
The present invention has disclosed a kind of manufacture method of electric resistance transition memory of multiple-level stack, comprises the steps:
[step 1] at first makes peripheral circuit and RRAM array in the silicon base first, and wherein peripheral circuit not only comprises reading and writing, wipes circuit, also comprises to judge and transmission instruction circuit part that the RRAM array is made of RRAM memory cell and gate tube.Realization planarization after manufacturing is finished.
[step 2] forms PN junction or Schottky barrier after silicon base second is mixed, PN junction or Schottky barrier will be used for making gating unit in follow-up step.
[step 3] transferred to the top layer of silicon base second above-mentioned on the array that the silicon base first obtains with the surface silicon of PN junction or Schottky barrier by bonding method, remove unnecessary silicon base and (can adopt and peel off or reduction.
After [step 4] planarization, obtain making gating unit and corresponding RRAM array by semiconductor technology on the silicon base at above-mentioned bonding.
[step 5] repeating step 2 is to step 4, until obtain abundant RRAM accumulation layer.
[step 6] forms PN junction or Schottky barrier after silicon base third is mixed, PN junction or Schottky barrier will be used for making gating unit in follow-up step.
[step 7] transferred to the top layer of silicon base third above-mentioned on the array that step 5 obtains with the surface silicon of PN junction or Schottky barrier by bonding method, remove unnecessary silicon base and (can adopt and peel off or reduction.Obtain making gating unit and corresponding phase change memory array by semiconductor technology on the silicon base at above-mentioned bonding.
[step 8] repeating step 6 is to step 7, until obtain abundant PCRAM accumulation layer.
[step 9] just obtains containing the multiple-level stack memory of multilayer RRAM and multilayered phase change memory by encapsulation.The type of the memory that obviously, adopts in the above-mentioned processing step and the stacking number of plies can change according to the actual needs.
In [step 9] actual application, peripheral circuit can judge that data type selects to select PCRAM or RRAM to carry out data storages, and the standard of judgement can be set by user oneself.As, described peripheral circuit judges that the flow process of the data type of required processing one of comprises the steps: judge whether the data storage needs high speed storing; If then select the memory cell of high speed storing type; Judge whether data manipulation is frequent, if then select the memory cell of high tired type; Judge whether longer-term storage of data, if select the memory module of high data retention ability type; Otherwise select the memory module of low data holding ability type.
In application, peripheral circuit selects the memory cell of adequate types to carry out data storage and processing according to the data deterministic process that is similar among Fig. 2 A-C.
As, judge at first whether the data storage needs high speed storing; If then select the memory cell of high speed storing type; Otherwise, judge whether data read frequent, if then select the memory cell of high tired type; Otherwise, select high data to manage the memory module of type.
Obviously, in actual applications, memory chip has the storage chip type of varying number and kind, in simple electronic system, perhaps only need judgements (for example whether high speed, whether frequent, shown in 2B and 2C) just can select data type; And in the electronic system of complexity, just may have two or more storage chips, then corresponding judgement just seems more complex.
Although in this method of having demonstrated concentrated judgement, it may be noted that this can adjust according to the actual needs, even can in storage chip, stay next option to set up the standard of judgement on their own for the user, not to limit feature of the present invention at this.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment and change is possible, and the various parts of the replacement of embodiment and equivalence are known for those those of ordinary skill in the art.Those skilled in the art are noted that in the situation that does not break away from spirit of the present invention or substantive characteristics, and the present invention can be with other form, structure, layout, ratio, and realize with other assembly, material and parts.In the situation that does not break away from the scope of the invention and spirit, can carry out other distortion and change to disclosed embodiment here.
Claims (16)
1. the memory of a multiple-level stack is characterized in that: memory chip comprises peripheral circuit and two-layer at least memory cell layers and corresponding gating unit with it, comprises at least two types memory cell in the described memory chip;
In data storage procedure, described peripheral circuit is judged the data type of required processing, and the memory cell according to judged result transmission Instruction Selection particular type carries out the data storage subsequently.
2. the memory of multiple-level stack according to claim 1 is characterized in that:
In data storage procedure, carry out data storage or processing for the dissimilar memory cell of dissimilar the data.
3. the memory of multiple-level stack according to claim 1 is characterized in that:
Comprise control module in the described peripheral circuit, control module can be judged the type of required deal with data, sends instruction according to judged result subsequently, selects corresponding memory cell to carry out the data storage.
4. according to claim 1 to the memory of one of 3 described multiple-level stacks, it is characterized in that:
Described peripheral circuit judges that the flow process of the data type of required processing one of comprises the steps:
Judge whether the data storage needs high speed storing; If then select the memory cell of high speed storing type;
Judge whether data manipulation is frequent, if then select the memory cell of high tired type;
Judge whether longer-term storage of data, if select the memory module of high data retention ability type; Otherwise select the memory module of low data holding ability type.
5. according to claim 1 to the memory of one of 3 described multiple-level stacks, it is characterized in that:
Share peripheral circuit between the multilayered memory elementary layer.
6. according to claim 1 to the memory of one of 3 described multiple-level stacks, it is characterized in that:
Described memory cell is volatile memory, or is nonvolatile memory.
7. according to claim 1 to the memory of one of 3 described multiple-level stacks, it is characterized in that:
The type of the memory cell that each layer comprises is phase transition storage, or resistance random access memory, or magnetoresistive memory, or dynamic random access memory, or static random access memory, or flash memory, or ferroelectric memory.
8. method of making the multiple-level stack memory is characterized in that the method comprises following steps:
A, make first kind memory cell at the first circle crystalline substance, and make the first circle crystalline substance have smooth surface, also with peripheral circuit and the gating unit corresponding with memory cell, wherein peripheral circuit comprises reading and writing, wipes drive circuit and data decision circuitry and instruction issue circuitry on the first circle crystalline substance;
B, make to set the memory of type and supporting gating unit at the second circle crystalline substance, planarization is carried out on the brilliant surface of the second circle;
C, utilize the two memories circle crystalline substance that the brilliant bonding technology of low temperature circle will above-mentioned discrete manufacturing to be bonded to together, and make the connection of each layer electricity;
D, anneal under the following temperature of 400 degree, it is brilliant to peel off the brilliant redundance circle of the second circle, peels off rear the multiple-level stack circle crystalline substance that obtains to be carried out flatening process;
E, repetition B carry out the memory stacking technique of multilayer to three steps of D, until obtain the memory number of plies of setting, after multiple-level stack was complete, with peripheral circuit, the memory cell between each layer was shared peripheral circuit in specific layer; In the repetitive process, the type of memory is identical or different among the step B;
F, lead-in wire and encapsulation.
9. the method for manufacturing multiple-level stack memory according to claim 8 is characterized in that:
In the storage chip use procedure, at first judge the data type of required processing by peripheral circuit, subsequently according to judged result, the operation of being correlated with by the specific memory cell of the Instruction Selection of peripheral circuit.
10. the method for manufacturing multiple-level stack memory according to claim 8 is characterized in that:
Contain sandwich construction and polytype memory in the memory of multiple-level stack.
11. the method for manufacturing multiple-level stack memory according to claim 8 is characterized in that:
With the brilliant discrete manufacturing of memory circle, combine by bonding method subsequently, form sandwich construction.
12. the method for manufacturing multiple-level stack memory according to claim 8 is characterized in that:
The technological temperature of the brilliant bonding of low temperature circle that step C, step D adopt is lower than 400 degree.
13. a method of making the multiple-level stack memory is characterized in that, described method comprises following step:
S1, at first make higher memory array and the peripheral circuit of high technology temperature at the first circle crystalline substance;
S2, utilize the brilliant bonding technology of circle, semiconductor lamella is bonded on above-mentioned the first circle crystalline substance after the planarization, comprise the doped layer of having processed through the high temperature impurity activation on the semiconductor lamella;
S3, employing semiconductor technology are made the gate tube array at above-mentioned semiconductor lamella, make corresponding with it second layer memory array and word/bit line;
S4, filled media, and carry out flatening process;
S5, repeating step S2-S4 make the memory chip that obtains multiple-level stack, and the type of memory of the memory of making in the repetitive process and S3 step is identical or different.
14. the method for manufacturing multiple-level stack memory according to claim 13 is characterized in that:
In the above-mentioned step, make first the higher memory array of high technology temperature, the lower memory array of high technology temperature of rear manufacturing.
15. the method for manufacturing multiple-level stack memory according to claim 13 is characterized in that:
Contain sandwich construction and polytype memory in the memory of multiple-level stack.
16. the method for manufacturing multiple-level stack memory according to claim 13 is characterized in that:
The top layer semiconductor of transferring on the first circle crystalline substance by bonding method contains doped layer, and impurity is processed through the activation of high temperature.
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| CN103399545B (en) * | 2013-07-29 | 2015-09-02 | 北京四方继保自动化股份有限公司 | A kind of real-time database administration module for dcs |
| CN103811051B (en) * | 2014-02-17 | 2017-01-11 | 上海新储集成电路有限公司 | Hierarchical memory array and working method thereof |
| CN108694979B (en) * | 2017-04-06 | 2023-08-01 | 群联电子股份有限公司 | Data writing method, memory control circuit unit and memory storage device |
| EP3844810A4 (en) | 2018-11-30 | 2022-06-01 | Yangtze Memory Technologies Co., Ltd. | Bonded memory device and fabrication methods thereof |
| WO2021035436A1 (en) * | 2019-08-23 | 2021-03-04 | Micron Technology, Inc. | Temperature-based memory management |
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