CN108694979B

CN108694979B - Data writing method, memory control circuit unit and memory storage device

Info

Publication number: CN108694979B
Application number: CN201710221175.9A
Authority: CN
Inventors: 胡俊洋
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2017-04-06
Filing date: 2017-04-06
Publication date: 2023-08-01
Anticipated expiration: 2037-04-06
Also published as: CN108694979A

Abstract

The invention provides a data writing method for a rewritable nonvolatile memory module, which comprises the following steps: recording a plurality of characteristic parameters corresponding to a plurality of data to be programmed; according to the characteristic parameters, sorting the data, and identifying normal read data in the data; and programming the data identified as normally read into a first physical programming unit of the rewritable non-volatile memory module, wherein a time for reading the data from the first physical programming unit is shorter than a time for reading the data from a second physical programming unit of the rewritable non-volatile memory module. Therefore, the reading performance of the data can be effectively improved.

Description

Data writing method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a data writing method for a rewritable nonvolatile memory module, a memory control circuit unit and a memory storage device.

Background

Digital cameras, mobile phones and MP3 have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Because the rewritable non-volatile memory has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high reading and writing speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. Solid state disk is a memory storage device using flash memory module as storage medium. Therefore, the flash memory industry has recently become a very popular ring in the electronics industry.

In a NAND flash memory module, the physical programming unit consists of a plurality of memory cells arranged on the same word line. Depending on the number of bits that each memory Cell can store, the NAND-type flash memory module may be classified into a single Level Cell (Single Level Cell, SLC) NAND-type flash memory module, a Multi Level Cell (MLC) NAND-type flash memory module, and a third Level Cell (Trinary Level Cell, TLC) NAND-type flash memory module, wherein each memory Cell of the SLC NAND-type flash memory module may store 1 bit of data (i.e., "1" and "0"), each memory Cell of the MLC NAND-type flash memory module may store 2 bits of data, and each memory Cell of the TLC NAND-type flash memory module may store 3 bits of data.

Since each memory cell of the SLC NAND-type flash memory module can store 1 bit of data, in the SLC NAND-type flash memory module, several memory cells arranged on the same word line correspond to one physical programming unit.

For SLC NAND-type flash memory modules, the floating gate memory layer of each memory cell of an MLC NAND-type flash memory module may store 2 bits of data, where each memory state (i.e., "11," "10," "01," and "00") includes a least significant bit (Least Significant Bit, LSB) and a most significant bit (Most Significant Bit, MSB). For example, the value of the 1 st bit from the left side in the memory state is LSB, and the value of the 2 nd bit from the left side is MSB. Therefore, several memory cells arranged on the same word line may constitute 2 physical program cells, wherein the physical program cell constituted by LSBs of these memory cells is called a lower physical program cell (low physical programming unit), and the physical program cell constituted by MSBs of these memory cells is called an upper physical program cell (upper physical programming unit). In particular, when an error occurs in the upper physical program unit, the data stored in the lower physical program unit may be lost.

Similarly, each memory cell in a TLC NAND-type flash memory module may store 3 bits of data, where each memory state (i.e., "111", "110", "101", "100", "011", "010", "001", and "000") includes the LSB of the 1 st bit from the left, the middle significant bit (Center Significant Bit, CSB) of the 2 nd bit from the left, and the MSB of the 3 rd bit from the left. Therefore, several memory cells arranged on the same word line may constitute 3 physical program cells, wherein the physical program cells composed of LSBs of the memory cells are referred to as lower physical program cells, the physical program cells composed of CSBs of the memory cells are referred to as middle physical program cells, and the physical program cells composed of MSBs of the memory cells are referred to as upper physical program cells. In particular, in TLC NAND-type flash memory modules, to ensure that data on one word line can be stably stored, three times of programming must be performed on the word line. For example, after the first programming is performed on the memory cells on the first word line, the memory cells on the first word line are in a first state (first state). The memory cells on the first word line are programmed again while the memory cells on the second word line are programmed. At this time, the memory cell on the first word line is in a fuzzy state (foggy state). Then, the memory cells on the first and second word lines are programmed again while the memory cells on the third word line are programmed, and at this time, the memory cells on the first word line are in a good state (fine state). Furthermore, the memory cells on the second and third word lines are programmed again at the same time as the memory cells on the fourth word line are programmed. At this time, the memory cells on the second word line are in good condition, so that the data in the memory cells on the first word line can be ensured to be stably stored.

As the number of bits that can be stored per memory cell increases, so does the time to identify the memory state of each memory cell. Therefore, how to effectively improve the efficiency of executing the read command and shorten the time for reading the data is a subject of attention of those skilled in the art.

Disclosure of Invention

The invention provides a data writing method, a memory control circuit unit and a memory storage device, which effectively improve the reading efficiency of a rewritable nonvolatile memory module.

An exemplary embodiment of the present invention provides a data writing method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erasing units, each of the physical erasing units has a plurality of physical programming units, the physical programming units are at least divided into a first physical programming unit and a second physical programming unit, and a time for reading data from the first physical programming unit is shorter than a time for reading data from the second physical programming unit. The data writing method comprises the following steps: recording a plurality of characteristic parameters corresponding to a plurality of data; according to the characteristic parameters, identifying the first data in the plurality of data as constant reading data; and a first physical programming unit for programming the first data into a first physical erasing unit among the plurality of physical erasing units.

In an exemplary embodiment of the invention, the data writing method further includes sorting the plurality of data according to the characteristic parameter to generate a writing sequence corresponding to the plurality of data; and programming the plurality of data into the first physical erasing unit according to the writing sequence.

In an exemplary embodiment of the present invention, the data writing method further includes configuring a plurality of logical addresses to map at least part of the plurality of physical programming units, wherein the plurality of data is stored to one of the plurality of logical addresses respectively. And, the step of recording the characteristic parameters corresponding to the data includes: establishing a reading count table, and recording the reading times of each logic address in the reading count table; and taking the reading times of the logic addresses storing the data as characteristic parameters corresponding to the data respectively.

In an exemplary embodiment of the present invention, the step of sorting the data according to the characteristic parameters to generate a writing sequence corresponding to the data includes: obtaining a number of reads of a logical address storing such data from a read count table; and according to the read times of the logic addresses storing the data, arranging the logic addresses storing the data to generate the writing sequence.

In an exemplary embodiment of the present invention, the data writing method further includes: and programming the second data into the second physical program unit of the first physical erasing unit, wherein the reading times of the logic address storing the first data are larger than the reading times of the logic address storing the second data.

In an exemplary embodiment of the invention, the step of programming the first data into the first physical programming unit of the first physical erasing unit according to the writing sequence includes: programming first data into the first physical erase unit using a single layer memory cell pattern; and programming the second data into a second physical programming unit of the first physical erasing unit, comprising: the second data is programmed into the first physical erase unit using the multi-level memory cell pattern.

In an exemplary embodiment of the present invention, the data writing method further includes: selecting at least two physical erasing units from the physical erasing units to execute effective data collection operation; and reading the data from the at least two physical erase units.

In an exemplary embodiment of the present invention, the data writing method further includes: a plurality of write instructions are received from the host system, wherein the write instructions respectively indicate one of the logical addresses to store the data.

In an exemplary embodiment of the invention, the characteristic parameter of the corresponding data is a number of times of reading the corresponding data, a reading frequency of the corresponding data, or a reading time interval of the corresponding data.

An exemplary embodiment of the present invention provides a memory control circuit unit including a host interface, a memory interface, and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, the entity programming units are at least divided into a first entity programming unit and a second entity programming unit, and the time for reading data from the first entity programming unit is shorter than the time for reading data from the second entity programming unit. The memory management circuit is connected to the host interface and the memory interface, and is used for recording a plurality of characteristic parameters corresponding to a plurality of data, and according to the characteristic parameters, identifying the first data in the plurality of data as normal read data. In addition, the memory management circuit further issues an instruction sequence to program the first data into a first physical programming unit of a first physical erasing unit among the plurality of physical erasing units.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to sort the plurality of data according to the characteristic parameters to generate a writing sequence corresponding to the plurality of data, and program the plurality of data into the first physical erasing unit according to the writing sequence.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to configure a plurality of logical addresses to map at least a portion of the plurality of physical programming units, wherein the plurality of data is stored to one of the plurality of logical addresses, respectively. In addition, in the operation of recording the characteristic parameters corresponding to the data, the memory management circuit establishes a reading count table, records the reading times of each logic address in the reading count table, and takes the reading times of the logic addresses storing the data as the characteristic parameters corresponding to the data respectively.

In an exemplary embodiment of the present invention, in the operation of sorting the data according to the characteristic parameters to generate the write sequence corresponding to the data, the memory management circuit obtains the read times of the logical addresses storing the data from the read count table, and arranges the logical addresses storing the data according to the read times of the logical addresses storing the data to generate the write sequence.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to program the second data into the second physical program unit of the first physical erase unit, wherein the number of times of reading the logical address storing the first data is greater than the number of times of reading the logical address storing the second data.

In an exemplary embodiment of the invention, the memory management circuit uses a single-layer memory cell mode to program the first data into the first physical erase unit, and uses a multi-layer memory cell mode to program the second data into the first physical erase unit.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to select at least two physical erase units from among the physical erase units to perform an effective data collection operation and to read the data from the at least two physical erase units.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to receive a plurality of write commands from the host system, wherein the write commands respectively indicate to store the data to one of the logical addresses.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, the entity programming units are at least divided into a first entity programming unit and a second entity programming unit, and the time for reading data from the first entity programming unit is shorter than the time for reading data from the second entity programming unit. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module and is used for recording a plurality of characteristic parameters corresponding to a plurality of data, and according to the characteristic parameters, the first data in the plurality of data is identified as normal read data. In addition, the memory management circuit is also used for programming the first data into a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to sort the plurality of data according to the characteristic parameters to generate a writing sequence corresponding to the plurality of data, and program the plurality of data into the first physical erasing unit according to the writing sequence.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to configure a plurality of logical addresses to map at least a portion of the plurality of physical programming units, wherein the plurality of data is stored to one of the plurality of logical addresses respectively. In addition, in the operation of recording the characteristic parameters corresponding to the data, the memory control circuit unit establishes a reading count table, records the reading times of each logic address in the reading count table, and takes the reading times of the logic addresses storing the data as the characteristic parameters corresponding to the data respectively.

In an exemplary embodiment of the present invention, in the operation of sorting the data according to the characteristic parameters to generate the write sequence corresponding to the data, the memory control circuit unit obtains the read times of the logical addresses storing the data from the read count table, and arranges the logical addresses storing the data according to the read times of the logical addresses storing the data to generate the write sequence.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to program the second data into the second physical program unit of the first physical erase unit, wherein the number of times of reading the logical address storing the first data is greater than the number of times of reading the logical address storing the second data.

In an exemplary embodiment of the invention, the memory control circuit unit programs the first data into the first physical erase unit using a single-layer memory cell mode, and programs the second data into the first physical erase unit using a multi-layer memory cell mode.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select at least two physical erase units from among the physical erase units to perform an effective data collection operation and to read the data from the at least two physical erase units.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to receive a plurality of write commands from the host system, wherein the write commands respectively indicate to store the data to one of the logical addresses.

Based on the above, the data writing method, the memory control circuit unit and the memory storage device of the present exemplary embodiment are to sort the order of writing data according to the characteristics of the data when performing the writing operation, so as to program the normally read data into the physical programming unit with a faster reading speed, thereby effectively improving the reading performance.

In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram of a host system and a memory storage device according to an example embodiment;

FIG. 2 is a schematic diagram of a computer, an input/output device and a memory storage device according to an example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment;

FIG. 4 is a schematic block diagram of a memory storage device according to an example embodiment;

FIGS. 5A and 5B are schematic diagrams illustrating a memory cell memory architecture and a physical erase unit according to an example embodiment;

FIG. 6 is a schematic block diagram of a memory control circuit unit according to an example embodiment;

FIGS. 7 and 8 are schematic diagrams illustrating exemplary management entity blocks according to the first exemplary embodiment;

FIG. 9 is an example of a read count table according to an example embodiment of the invention;

FIG. 10 is an example of executing a write instruction according to an example embodiment of the present invention;

FIG. 11 is an example of an active data collection operation according to an example embodiment of the invention;

FIG. 12 is a flowchart of a data writing method according to an exemplary embodiment of the invention.

Reference numerals illustrate:

10: memory storage device

11: host system

12: input/output (I/O) device

110: system bus

111: processor and method for controlling the same

112: random Access Memory (RAM)

113: read-only memory (ROM)

114: data transmission interface

20: motherboard

201: portable disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with keyboard body

209: screen

210: horn with horn body

30: memory storage device

31: host system

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

410 (0) to 410 (N): physical erasing unit

502: memory management circuit

504: host interface

506: memory interface

508: buffer memory

510: power management circuit

512: error checking and correcting circuit

602: data area

604: idle zone

606: system area

608: substitution region

LBA (0) to LBA (H): logical block address

LZ (0) to LZ (M): logic area

D0 to D5: data

900: reading counter

901: logical address field

902: reading number field

S1201: recording characteristic parameters corresponding to the data

S1203: identifying the normal read data among the data according to the characteristic parameters corresponding to the data

S1205: a step of programming the data identified as being normally read into the lower physical programming unit

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.

Fig. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment, and fig. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are all connected to a system bus 110.

In the present exemplary embodiment, host system 11 is coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication Storage, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as an SD card 32, a CF card 33 or an embedded storage device 34. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (eMMC) 341 and/or an embedded multi-chip package storage device (embedded Multi Chip Package, eMCP) 342, which directly connect the memory module to the substrate of the host system.

FIG. 4 is a schematic block diagram of a host system and a memory storage device according to an example embodiment.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

In the present exemplary embodiment, the connection interface unit 402 is compliant with the serial advanced attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may be a Memory Stick (MS) interface standard, a Multi-Chip Package (Multi-Chip Package) interface standard, a Multi-Media Card (MMC) interface standard, an embedded Multi-Media Card (Embedded Multimedia Card, eMMC) interface standard, a universal Flash Memory (Universal Flash Storage, UFS) interface standard, an embedded Chip Package (embedded Multi Chip Package, emmp) interface standard, a Flash Memory (Compact Flash) interface standard, or other integrated Flash drive standard, which are compliant with the parallel advanced accessory (Parallel Advanced Technology Attachment, PATA) standard, the institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, the High-Speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) standard, the universal serial bus (Universal Serial Bus, USB) standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Secure Digital (SD) interface standard, the Memory Stick (Memory Stick) interface standard, the Multi-Chip Package (Multi-Chip Package) interface standard, the Multi-Media Card (MMC) interface standard, the Flash Memory Card (Flash) interface standard, the Flash Memory Flash (32, the Flash) interface standard, or other integrated Flash drive standard. In the present exemplary embodiment, the connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed outside a single chip including the memory control circuit unit.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404, and is used to store data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase cells 410 (0) to 410 (N). For example, the physical erase units 410 (0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each physical erasing unit is provided with a plurality of physical programming units, wherein the physical programming units belonging to the same physical erasing unit can be independently written and simultaneously erased. However, it should be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units or any other physical programming units.

In more detail, a physical erased cell is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. The physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. Each physical programming unit typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundant bit region is used for storing system data (e.g., control information and error correction codes). In the present exemplary embodiment, the data bit area of each physical programming unit includes 8 physical access addresses, and one physical access address has a size of 512 bytes (bytes). However, in other exemplary embodiments, a greater or lesser number of physical access addresses may be included in the data bit region, and the present invention is not limited to the size and number of physical access addresses. For example, in an exemplary embodiment, the physical erasing unit is a physical block, and the physical programming unit is a physical page or a physical sector, but the invention is not limited thereto.

In the present example embodiment, the rewritable nonvolatile memory module 406 is a third level memory cell (Trinary Level Cell, TLC) NAND flash memory module (i.e., a flash memory module that can store 3 data bits in one memory cell). However, the present invention is not limited thereto, and the rewritable nonvolatile memory module 406 may be a Multi Level Cell (MLC) NAND type flash memory module (i.e. a flash memory module capable of storing 2 data bits in one memory Cell) or other memory modules having the same characteristics.

FIGS. 5A and 5B are schematic diagrams illustrating an exemplary memory cell memory architecture and a physical erase unit according to the present exemplary embodiment.

Referring to fig. 5A, the memory state of each memory cell of the rewritable nonvolatile memory module 406 can be identified as "111", "110", "101", "100", "011", "010", "001" or "000" (as shown in fig. 5A), wherein the 1 st bit from the left is LSB, the 2 nd bit from the left is CSB and the 3 rd bit from the left is MSB. In addition, several memory cells arranged on the same word line may constitute 3 physical program cells, wherein the physical program cell constituted by LSBs of the memory cells is referred to as a first physical program cell (hereinafter also referred to as a lower physical program cell), the physical program cell constituted by MSBs of the memory cells is referred to as a second physical program cell (hereinafter also referred to as an upper physical program cell), and the physical program cell constituted by CSBs of the memory cells is referred to as a third physical program cell (hereinafter also referred to as a middle physical program cell).

Referring to FIG. 5B, a physical erase unit is formed by a plurality of physical program unit groups, wherein each physical program unit group includes a lower physical program unit, a middle physical program unit and an upper physical program unit formed by a plurality of memory cells arranged on the same word line. For example, in the physical erase unit, the 0 th physical program unit belonging to the lower physical program unit, the 1 st physical program unit belonging to the middle physical program unit, and the 2 nd physical program unit belonging to the upper physical program unit are regarded as one physical program unit group. Similarly, the 3 rd, 4 th and 5 th physical programming units are considered as a physical programming unit group, and other physical programming units are also divided into a plurality of physical programming unit groups according to the method. That is, in the exemplary embodiment of fig. 5B, there are 258 physical program units in total, and since the lower physical program unit, the middle physical program unit and the upper physical program unit formed by the memory units arranged on the same word line form one physical program unit group, the physical erase unit of fig. 5B can be divided into 86 physical program unit groups in total. However, it should be noted that the present invention is not limited to the number of the physical program units or the physical program unit groups in the physical erase unit.

It should be noted that, in the present exemplary embodiment, the speed of reading data from the lower physical programming unit is faster than the speed of reading data from the middle physical programming unit and the upper physical programming unit.

FIG. 6 is a schematic block diagram of a memory control circuit unit according to an example embodiment.

Referring to fig. 6, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506, a buffer memory 508, a power management circuit 510 and an error checking and correcting circuit 512.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating.

In the exemplary embodiment, the control instructions of the memory management circuitry 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a ROM (not shown), and the control commands are burned into the ROM. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

FIGS. 7 and 8 are schematic diagrams illustrating an exemplary erase unit of a management entity according to an exemplary embodiment.

It should be understood that, in describing the operation of the physically erased cells of the rewritable nonvolatile memory module 406, it is a logical concept to operate the physically erased cells by words such as "extract", "group", "divide", "associate" and the like. That is, the physical locations of the physical erase units of the rewritable nonvolatile memory module are not changed, but the physical erase units of the rewritable nonvolatile memory module are logically operated.

Referring to FIG. 7, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410 (0) -410 (N) into a data area 602, an idle area 604, a system area 606 and a replacement area 608.

The physical erase units logically belonging to the data area 602 and the spare area 604 are used to store data from the host system 11. Specifically, the physically erased cells of the data area 602 are considered physically erased cells of the stored data, and the physically erased cells of the spare area 604 are physically erased cells of the data area 602. That is, when a write command and data to be written are received from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) will use the physical erase unit extracted from the spare area 604 to write data to replace the physical erase unit of the data area 602.

The physical erase unit logically belonging to the system area 606 is used for recording system data. For example, the system data includes the manufacturer and model of the rewritable nonvolatile memory module, the number of physical erased cells of the rewritable nonvolatile memory module, the number of physical programmed cells of each physical erased cell, etc.

The physically erased cells logically belonging to the replacement area 608 are used for the replacement process of the bad physically erased cells to replace the damaged physically erased cells. Specifically, if the replacement area 608 still has normal physical erase units and the physical erase units of the data area 602 are damaged, the memory control circuit unit 404 (or the memory management circuit 502) extracts the normal physical erase units from the replacement area 608 to replace the damaged physical erase units.

In particular, the number of physically erased cells in the data area 602, the spare area 604, the system area 606, and the replacement area 608 may vary according to different memory specifications. In addition, it should be understood that during operation of the memory device 10, the grouping relationship of physical erase units associated with the data area 602, the spare area 604, the system area 606, and the replacement area 608 dynamically changes. For example, when the physically erased cells in the spare area 604 are damaged and replaced by physically erased cells of the replacement area 608, the physically erased cells of the replacement area 608 are associated with the spare area 604.

Referring to FIG. 8, the memory control circuit unit 404 (or the memory management circuit 502) configures logical block addresses LBA (0) -LBA (H) to map physical erase units of the data area 602, wherein each logical block address has a plurality of logical addresses to map physical program units of corresponding physical erase units. When the host system 11 wants to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) extracts a physical erase unit from the spare area 604 as an active physical erase unit to write data, so as to replace the physical erase unit of the data area 602. When the physical erase unit is full, the memory control circuit unit 404 (or the memory management circuit 502) extracts the empty physical erase unit from the spare area 604 as the active physical erase unit, so as to continue writing the update data corresponding to the write command from the host system 11. In addition, when the number of available physical erase units in the spare area 604 is less than the predetermined value, the memory control circuit unit 404 (or the memory management circuit 502) performs a garbage collection (garbage collection) operation (also referred to as an active data collection operation) to sort the active data in the data area 602, so as to re-associate the physical erase units in the data area 602, which do not store the active data, to the spare area 604.

In order to identify which physical programming unit the data of each logical address is stored in, in the present example embodiment, the memory control circuit 404 (or the memory management circuit 502) records the mapping relationship between the logical address and the physical programming unit. For example, in the present example embodiment, the memory control circuit 404 (or the memory management circuit 502) stores a logical-to-physical mapping table in the rewritable nonvolatile memory module 406 to record the physical programming units mapped by each logical address. The memory control circuit 404 (or the memory management circuit 502) loads the logical-to-physical mapping table into the buffer memory 508 for maintenance when data is to be accessed, and writes or reads data according to the logical-to-physical mapping table.

It should be noted that, since the capacity of the buffer memory 508 is limited, the mapping table recording the mapping relationship of all logical addresses cannot be stored, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) groups the logical block addresses LBA (0) to LBA (H) into a plurality of logical zones LZ (0) to LZ (M), and configures a logical-entity mapping table for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) wants to update the mapping of a certain logical block address, the logical-to-physical mapping table corresponding to the logical area to which the logical block address belongs is loaded into the buffer 508 to be updated. Specifically, if the logical-to-physical mapping table corresponding to the logical area to which the logical block address belongs is not cached in the buffer memory 508 (i.e., the logical-to-physical mapping table cached in the buffer memory 508 does not record the mapping of the logical block address to be updated), the memory control circuit unit 404 (or the memory management circuit 502) performs a mapping table swap operation (mapping table swapping operation) to restore the logical-to-physical mapping table cached in the buffer memory 508 to the rewritable nonvolatile memory module 406, and loads the logical-to-physical mapping table mapped with the logical block address to be updated into the buffer memory 508.

In another example embodiment of the invention, the control instructions of the memory management circuit 502 may also be stored in program code form in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a driving code, and when the memory control circuit 404 is enabled, the microprocessor unit executes the driving code segment to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. Wherein the memory cell management circuit is configured to manage physical erase units of the rewritable nonvolatile memory module 406; the memory write circuit is configured to issue a write command to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406; the memory read circuit is configured to issue a read command to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406; the memory erase circuit is configured to issue an erase command to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.

Referring to fig. 6 again, the host interface 504 is connected to the memory management circuit 502 and is used to connect to the connection interface unit 402 for receiving and identifying the commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the present exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it must be understood that the present invention is not limited thereto and that the host interface 504 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, UHS-I interface standards, UHS-II interface standards, SD standards, MS standards, MMC standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 506 is coupled to the memory management circuitry 502 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 506.

The buffer memory 508 is connected to the memory management circuit 502 and is used for temporarily storing temporary data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

The power management circuit 510 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.

The error checking and correcting circuit 512 is connected to the memory management circuit 502 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. For example, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 512 generates a corresponding error checking and correcting Code (Error Checking and Correcting Code, ECC Code) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error checking and correcting Code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error checking and correcting code corresponding to the data is read at the same time, and the error checking and correcting circuit 512 performs an error checking and correcting procedure on the read data according to the error checking and correcting code.

Operations performed by the memory management circuit 502, the host interface 504, the memory interface 506, the buffer memory 508, the power management circuit 510, and the error checking and correction circuit 512 are described below and may also be referred to as being performed by the memory control circuit unit 404.

In the present exemplary embodiment, when executing the write command from the host system 11, the memory management circuit 502 identifies the frequently read data (hereinafter also referred to as frequently read data) according to the characteristic parameters corresponding to the data to be written, and programs the frequently read data into the next physical programming unit. Here, the normal read data is data that reflects more frequently read data than other data (hereinafter also referred to as very read data) depending on the characteristic parameter. For example, the memory management circuit 502 sorts the data according to the characteristic parameters corresponding to the data to be written and generates a writing sequence corresponding to the data, and then programs the sorted data into the rewritable nonvolatile memory module 406 according to the writing sequence.

For example, in the present exemplary embodiment, the memory management circuit 502 establishes a read count table to record the number of reads of each logical address, and uses the number of reads of the logical address of the stored data as the characteristic parameter of the data. That is, the memory management circuit 502 sorts the data to be stored according to the read times of each logical address storing the data to generate a corresponding write sequence, and programs the data into the rewritable nonvolatile memory module 406 according to the write sequence.

FIG. 9 is an example of a read count table according to an example embodiment of the invention.

Referring to fig. 9, the read count table 900 includes a logical address field 901 and a read count field 902. The logical address field 901 records the number of each logical address, and the read count field 902 records the number of reads of the corresponding logical address. For example, each time the host system 11 gives a read instruction to a logical address, the number of reads corresponding to the logical address is increased by 1. In the present exemplary embodiment, after the memory storage device 10 is powered on, the memory management circuit 502 loads the read count table 900 from the rewritable nonvolatile memory module 406 and updates the read count table 900 according to the read command issued by the host system 11; and before powering down the memory storage device 10, the memory management circuit 502 will restore the read count table 900 to the rewritable nonvolatile memory module 406. For example, the read count table 900 may be stored in the system area 606.

It should be understood that although the number of times of reading the logical address is taken as the characteristic parameter of the corresponding data in the present exemplary embodiment, the present invention is not limited thereto, and the reading frequency and the reading time interval of the logical address may be taken as the characteristic parameter of the corresponding data in another exemplary embodiment.

In the present exemplary embodiment, when the memory storage device 10 receives a write command and data to be stored from the host system 11, the memory management circuit 502 temporarily stores the data into the buffer 508. Then, the memory storage device 10 obtains the corresponding read times from the read count table 900 according to the logical address indicated by the write command, and arranges the data to be stored according to the obtained read times. In particular, according to the arrangement sequence, the data stored to the logic address with higher reading times is programmed to the lower entity programming unit, so that the speed of reading the data from the logic address which is always read can be greatly improved when the reading instruction is executed, and the time for executing the reading instruction is shortened.

FIG. 10 is an example of executing a write instruction according to an example embodiment of the invention.

Referring to fig. 10, assume that the memory storage device 10 receives one or more write instructions from the host system 11 and the write instructions instruct to sequentially store the data D0 to the logical address LA0, the data D1 to the logical address LA1, the data D2 to the logical address LA2, the data D3 to the logical address LA3, the data D4 to the logical address LA4 and the data D5 to the logical address LA5.

In this example, the memory management circuit 502 temporarily stores the data D0-D5 in the buffer 508, and obtains the read times of the logical addresses LA 0-LA 5 from the read count table 900 according to the write command. As shown in fig. 9, the number of times of reading of logical address LA0 is 0, the number of times of reading of logical address LA1 is 5, the number of times of reading of logical address LA2 is 300, the number of times of reading of logical address LA3 is 10, the number of times of reading of logical address LA4 is 20, and the number of times of reading of logical address LA5 is 10. Accordingly, the memory management circuit 502 adjusts the order of the original write commands (i.e., logical address LA0, logical address LA1, logical address LA2, logical address LA3, logical address LA4, logical address LA 5) to the new write order (i.e., logical address LA2, logical address LA3, logical address LA0, logical address LA4, logical address LA5, logical address LA 1). Then, the memory management circuit 502 extracts a physical erase unit (e.g., the physical erase unit 410 (F), hereinafter referred to as a first physical erase unit) from the spare area 604, and sequentially programs the data D2 (hereinafter referred to as a first data) stored to the logical address to the 0 th physical program unit of the physical erase unit 410 (F), the data D3 stored to the logical address to the 1 st physical program unit of the physical erase unit 410 (F), and the data D0 (hereinafter referred to as a second data) stored to the logical address to the 2 nd physical program unit of the physical erase unit 410 (F). Here, the 0 th to 2 nd physical programming units may also be referred to as a first physical programming unit group. Then, the memory management circuit 502 programs the data D4 stored to the logical address to the 3 rd physical programming unit of the physical erasing unit 410 (F), the data D5 stored to the logical address to the 4 th physical programming unit of the physical erasing unit 410 (F), and the data D1 stored to the logical address to the 5 th physical programming unit of the physical erasing unit 410 (F). The 3 rd to 5 th physical programming units may be referred to as a first physical programming unit group. That is, in this example, according to the number of times of reading the logical addresses, the data D2 and D4 stored in the two logical addresses with the largest number of times of reading are programmed to the lower physical programming unit, the data D3 and D5 stored in the two logical addresses with the next largest number of times of reading are programmed to the middle physical programming unit, and the data D0 and D1 stored in the two logical addresses with the smaller number of times of reading are programmed to the upper physical programming unit.

The example of fig. 10 is based on the data identified as read-only being programmed in the same physical programming unit group with other data, however, the invention is not limited thereto. In another example embodiment, the memory management circuit 502 may also program the data D2 and the data D4 into the physical program unit group using a single level memory cell mode (SLC mode), a lower physical program unit program mode (lower physical programming unit programming mode), or a hybrid program mode (mixture programming mode), and program the data D3, the data D5, the data D0, and the data D1 into the physical program unit group using a multi-level memory cell mode. Here, if the rewritable nonvolatile memory module 406 is used in a single-layer memory cell mode, only one bit of data is stored per memory cell. If the rewritable nonvolatile memory module 406 is used in the following physical programming mode, only the physical programming units belonging to the lower physical programming unit in the rewritable nonvolatile memory module 406 may be programmed, and the upper physical programming unit corresponding to the lower physical programming unit may not be programmed. If the rewritable nonvolatile memory module 406 is used in the hybrid programming mode, the valid data (or real data) is programmed into the physical programming unit belonging to the lower physical programming unit, but not into the physical programming unit belonging to the upper physical programming unit. In addition, if the rewritable nonvolatile memory module 406 is used in the hybrid programming mode, invalid data (or dummy data) corresponding to valid data (or real data) is programmed into the physical programming unit belonging to the upper physical programming unit.

The example of fig. 10 is to rearrange the writing order of the data to be stored when executing the writing instruction, however, the present invention is not limited thereto, and the data read more often may be programmed into the lower physical programming unit in this way when executing the valid data collection operation.

FIG. 11 is an example of an efficient data collection operation according to an example embodiment of the invention.

Referring to FIG. 11, it is assumed that the physical erasing unit 410 (0), the physical erasing unit 410 (1) and the physical erasing unit 410 (2) are selected for performing the effective data collection operation, and the physical erasing unit 410 (0) stores the effective data D0 belonging to the logical address LA0 and the effective data D1 belonging to the logical address LA1, the physical erasing unit 410 (1) stores the effective data D2 belonging to the logical address LA2, and the physical erasing unit 410 (2) stores the effective data D belonging to the logical address LA5, wherein the dotted line portion represents the invalid data.

In this example, the memory management circuit 502 reads the data D0, D1, D2 and D5 from the physical erase unit 410 (0), the physical erase unit 410 (1) and the physical erase unit 410 (2), temporarily stores the data D0, D1, D2 and D5 in the buffer 508, and obtains the read times of the logical addresses LA0, LA1, LA2 and LA5 from the read count table 900 according to the logical-physical mapping table. As shown in fig. 9, the number of reads of logical address LA0 is 0, the number of reads of logical address LA1 is 5, the number of reads of logical address LA2 is 300, and the number of reads of logical address LA5 is 10. Accordingly, the memory management circuit 502 adjusts the original read data sequence (i.e., logical address LA0, logical address LA1, logical address LA2, logical address LA 5) to the new write sequence (i.e., logical address LA2, logical address LA1, logical address LA0, logical address LA 5). Then, the memory management circuit 502 extracts a physical erase unit (e.g., the physical erase unit 410 (f+1)) from the spare area 604, and sequentially programs the data D2 stored to the logical address to the 0 th physical program unit of the physical erase unit 410 (F), the data D1 stored to the logical address to the 1 st physical program unit of the physical erase unit 410 (F), the data D0 stored to the logical address to the 2 nd physical program unit of the physical erase unit 410 (F), and the data D5 stored to the logical address to the 3 rd physical program unit of the physical erase unit 410 (F). That is, in this example, according to the number of times of reading the logical addresses, the data D2 and the data D5 stored in the two logical addresses having the largest number of times of reading are programmed to the lower physical programming unit, the data D1 stored in the logical address having the next largest number of times of reading is programmed to the middle physical programming unit and the data D0 stored in the logical address having the smaller number of times of reading is programmed to the upper physical programming unit.

In the examples of fig. 10 and 11, the time for executing the read command can be effectively shortened by adjusting the sequence of writing data according to the characteristic parameters (e.g. the number of times of reading the logical address) of the corresponding data before programming the data, and programming the normally read data into the lower physical programming unit with a faster reading speed.

It should be understood that, in the examples shown in fig. 10 and 11, the write command and the valid data collection operation are executed, and the write sequence is directly adjusted according to the read times of the logical addresses, so as to program the normally read data into the lower physical programming unit with a faster read speed. However, in another exemplary embodiment, the memory management circuit 502 may also identify the corresponding data as the data that is read normally only when the number of times of reading the logical address is greater than the predetermined threshold value, and adjust the writing sequence to program the data into the lower physical programming unit with a faster reading speed.

Furthermore, although in the examples of fig. 10 and 11, the memory management circuit 502 sequentially adjusts the writing order according to the reading times of the logical addresses, the present invention is not limited thereto, and in another example embodiment, the memory management circuit 502 may only identify the normal read data and program the normal read data into the lower physical programming unit with a faster reading speed, and other normal read data may not be ordered according to the reading times of the logical addresses. That is, when the data to be written is recognized as very read data, the memory management circuit 502 can program the data into the upper physical program unit, the middle physical program unit or the lower physical program unit. For example, if the frequently read data is identified and the physical programming unit of the predetermined program is not the next physical programming unit, the memory management circuit 502 will program the data identified as the frequently read data into the next physical programming unit and fill the physical programming unit of the predetermined program with dummy data.

Referring to fig. 12, when a plurality of data is to be programmed, in step S1201, the memory management circuit 502 records characteristic parameters corresponding to the data. As described above, for example, the memory management circuit 502 establishes the read count table 900 to record the number of times of reading the logical addresses, and uses the number of times of reading the logical addresses storing the data as the characteristic parameters corresponding to the data.

In step S1203, the normal read data among the data is identified according to the characteristic parameters corresponding to the data, and in step S1205, the memory management circuit 502 programs the data identified as the normal read data into the next physical programming unit.

In summary, the data writing method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the present invention rearrange the order of writing data according to the characteristics of the data, so as to program the data that is read more often into the physical programming unit with a faster reading speed, thereby effectively improving the reading performance.

Although the present invention has been described with reference to the above embodiments, it should be understood that the present invention is not limited thereto, and that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A data writing method, for a rewritable nonvolatile memory module having a plurality of physical erase units, each physical erase unit of the plurality of physical erase units having a plurality of physical program units, the plurality of physical program units being divided into at least a lower physical program unit, a middle physical program unit, and an upper physical program unit, a time for reading data from the lower physical program unit being shorter than a time for reading data from the upper physical program unit and the middle physical program unit, the data writing method comprising:

recording a plurality of characteristic parameters corresponding to a plurality of data;

according to the plurality of characteristic parameters, identifying first data in the plurality of data as frequently read data, wherein the frequently read data is read more frequently than second data in the plurality of data; and

programming the first data into a first physical erase unit among the plurality of physical erase units, and programming the second data into the first physical erase unit, wherein the first data is programmed into a physical program unit belonging to the lower physical program unit among the first physical erase unit,

Wherein programming the first data into the first physical erased cell includes programming the first data into the physical programmed cell using a single layer memory cell pattern,

wherein programming the second data into the first physically erased cell includes programming the second data into the first physically erased cell using a multi-level memory cell pattern.

2. The data writing method according to claim 1, characterized by further comprising: according to the characteristic parameters, sorting the data to generate a writing sequence corresponding to the data; and programming the plurality of data into the first physical erase unit of the plurality of physical erase units according to the writing sequence.

3. The data writing method according to claim 2, characterized by further comprising:

configuring a plurality of logical addresses to map at least a portion of the plurality of physical programming units, wherein the plurality of data is stored to one of the plurality of logical addresses separately,

wherein the step of recording the plurality of characteristic parameters corresponding to the plurality of data comprises:

Establishing a reading count table, and recording the reading times of each logic address in the logic addresses in the reading count table; and

the reading times of the logic addresses storing the plurality of data are respectively used as the plurality of characteristic parameters corresponding to the plurality of data.

4. The data writing method as claimed in claim 3, wherein said step of sorting said plurality of data according to said plurality of characteristic parameters to generate said writing order corresponding to said plurality of data comprises:

acquiring the reading times of the logic addresses storing the plurality of data from the reading count table; and

and according to the reading times of the logic addresses for storing the plurality of data, arranging the logic addresses for storing the plurality of data to generate the writing sequence.

5. The method for writing data according to claim 1, wherein,

wherein the number of times of reading the logical address storing the first data is larger than the number of times of reading the logical address storing the second data.

6. The data writing method according to claim 2, characterized by further comprising:

selecting at least two physical erasing units from the plurality of physical erasing units to execute effective data collection operation; and

And reading the plurality of data from the at least two physical erasing units.

7. The data writing method according to claim 3, further comprising:

a plurality of write instructions are received from a host system, wherein the plurality of write instructions each indicate to store the plurality of data to one of the logical addresses.

8. The data writing method according to claim 1, wherein the plurality of characteristic parameters corresponding to the plurality of data are a number of times of reading corresponding to the plurality of data, a frequency of reading corresponding to the plurality of data, or a reading time interval corresponding to the plurality of data.

9. A memory control circuit unit, comprising:

a host interface for connecting to a host system;

a memory interface for connecting to a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erasing units, each physical erasing unit of the plurality of physical erasing units has a plurality of physical programming units, the plurality of physical programming units are at least divided into a lower physical programming unit, a middle physical programming unit and an upper physical programming unit, and the time for reading data from the lower physical programming unit is shorter than the time for reading data from the upper physical programming unit and the middle physical programming unit; and

A memory management circuit connected to the host interface and the memory interface,

wherein the memory management circuit is used for recording a plurality of characteristic parameters corresponding to a plurality of data, and identifying a first data in the plurality of data as constant read data according to the plurality of characteristic parameters, wherein the constant read data is read more frequently than a second data in the plurality of data,

wherein the memory management circuit is further configured to issue at least one sequence of instructions to program the first data into a first physical erased cell of the plurality of physical erased cells and to program the second data into the first physical erased cell, wherein the first data is programmed into a physical programmed cell of the first physical erased cell that belongs to the lower physical programmed cell,

the memory management circuit programs the first data into the physical programming unit by using a single-layer memory unit mode and programs the second data into the first physical erasing unit by using a multi-layer memory unit mode.

10. The memory control circuit unit of claim 9, wherein the memory management circuit is further configured to sort the plurality of data according to the plurality of characteristic parameters to generate a write sequence corresponding to the plurality of data; and programming the plurality of data into the first physical erase unit of the plurality of physical erase units according to the writing sequence.

11. The memory control circuit unit of claim 10, wherein the memory management circuit is further configured to configure a plurality of logical addresses to map at least a portion of the plurality of physical programming units, wherein the plurality of data is stored to one of the plurality of logical addresses separately,

in the operation of recording the plurality of characteristic parameters corresponding to the plurality of data, the memory management circuit establishes a read count table in which the number of times of reading of each of the logical addresses is recorded, and the number of times of reading of the logical addresses storing the plurality of data is respectively taken as the plurality of characteristic parameters corresponding to the plurality of data.

12. The memory control circuit unit according to claim 11, wherein in the operation of sorting the plurality of data according to the plurality of characteristic parameters to generate the write order corresponding to the plurality of data, the memory management circuit obtains the number of times of reading of the logical addresses storing the plurality of data from the read count table, and arranges the logical addresses storing the plurality of data according to the number of times of reading of the logical addresses storing the plurality of data to generate the write order.

13. The memory control circuit unit of claim 9, wherein,

14. The memory control circuit unit of claim 10, wherein the memory management circuit is further configured to select at least two physical erase units from among the plurality of physical erase units to perform an effective data collection operation, and to read the plurality of data from the at least two physical erase units.

15. The memory control circuit unit of claim 11, wherein the memory management circuit is further configured to receive a plurality of write instructions from the host system,

wherein the write commands each indicate to store the plurality of data to one of the logical addresses.

16. The memory control circuit unit according to claim 9, wherein the plurality of characteristic parameters corresponding to the plurality of data are a number of times of reading corresponding to the plurality of data, a frequency of reading corresponding to the plurality of data, or a reading time interval corresponding to the plurality of data.

17. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erasing units, each physical erasing unit of the plurality of physical erasing units has a plurality of physical programming units, the plurality of physical programming units are at least divided into a lower physical programming unit, a middle physical programming unit and an upper physical programming unit, and the time for reading data from the lower physical programming unit is shorter than the time for reading data from the upper physical programming unit and the middle physical programming unit; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for recording a plurality of characteristic parameters corresponding to a plurality of data, and identifying first data in the plurality of data as constant read data according to the plurality of characteristic parameters, wherein the constant read data is read more frequently than second data in the plurality of data,

Wherein the memory control circuit unit is further configured to program the first data into a first physical erase unit among the plurality of physical erase units and the second data into the first physical erase unit, wherein the first data is programmed into a physical program unit belonging to the lower physical program unit among the first physical erase unit,

the memory control circuit unit uses a single-layer memory cell mode to program the first data into the physical programming unit and uses a multi-layer memory cell mode to program the second data into the first physical erasing unit.

18. The memory storage device of claim 17, wherein the memory control circuit unit is further configured to sort the plurality of data according to the plurality of characteristic parameters to generate a write sequence corresponding to the plurality of data; and programming the plurality of data into the first physical erase unit of the plurality of physical erase units according to the writing sequence.

19. The memory storage device of claim 18, wherein the memory control circuit unit is further configured to configure a plurality of logical addresses to map at least a portion of the plurality of physical programming units, wherein the plurality of data is stored to one of the plurality of logical addresses separately,

In the operation of recording the plurality of characteristic parameters corresponding to the plurality of data, the memory control circuit unit establishes a read count table in which the number of times of reading of each of the logical addresses is recorded, and separately takes the number of times of reading of the logical addresses storing the plurality of data as the plurality of characteristic parameters corresponding to the plurality of data.

20. The memory storage device according to claim 19, wherein in the operation of sorting the plurality of data according to the plurality of characteristic parameters to generate the write order corresponding to the plurality of data, the memory control circuit unit obtains the number of times of reading of the logical addresses storing the plurality of data from the read count table, and arranges the logical addresses storing the plurality of data according to the number of times of reading of the logical addresses storing the plurality of data to generate the write order.

21. The memory storage device of claim 17, wherein,

22. The memory storage device of claim 18, wherein the memory control circuit unit is further configured to select at least two physical erase units from among the plurality of physical erase units to perform an effective data collection operation, and to read the plurality of data from the at least two physical erase units.

23. The memory storage device of claim 19, wherein the memory control circuit unit is further configured to receive a plurality of write instructions from the host system,

24. The memory storage device of claim 17, wherein the plurality of characteristic parameters corresponding to the plurality of data are a number of reads corresponding to the plurality of data, a frequency of reads corresponding to the plurality of data, or a time interval of reads corresponding to the plurality of data.