CN108694979A

CN108694979A - Method for writing data, memorizer control circuit unit and memory storage apparatus

Info

Publication number: CN108694979A
Application number: CN201710221175.9A
Authority: CN
Inventors: 胡俊洋
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2017-04-06
Filing date: 2017-04-06
Publication date: 2018-10-23
Anticipated expiration: 2037-04-06
Also published as: CN108694979B

Abstract

The present invention provides a kind of method for writing data for reproducible nonvolatile memorizer module comprising:The majority characteristic parameter of the corresponding more data for being intended to sequencing of record;According to these characteristic parameters, these data are arranged, identify the normal reading data among these data;And will be identified as in the Data programming often read to the first instance programmed cell of reproducible nonvolatile memorizer module, wherein the time for reading data from first instance program unit is shorter than the time for reading data from the second instance program unit of reproducible nonvolatile memorizer module.Base this, the read performance of these data can be promoted effectively.

Description

Method for writing data, memorizer control circuit unit and memory storage apparatus

Technical field

The present invention relates to a kind of method for writing data, memories for reproducible nonvolatile memorizer module to control Circuit unit and memory storage apparatus.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years so that demand of the consumer to storage media Also rapidly increase.Since type nonvolatile (rewritable non-volatile memory) has data Non-volatile, power saving, it is small, without the characteristics such as mechanical structure, read or write speed be fast, be most suitable for portable electronic product, such as pen Note type computer.Solid state disk is exactly a kind of memory storage apparatus using flash memory module as storage media.Therefore, closely Year, flash memory industry was as a ring quite popular in electronic industry.

In anti-and (NAND) type flash memory module, entity program unit is by being arranged on same word-line Several storage units formed.According to the storable bit number of each storage unit, NAND type flash memory module can area It is divided into single-order storage unit (Single Level Cell, SLC) NAND type flash memory module, multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module and three rank storage units (Trinary Level Cell, TLC each storage unit of) NAND type flash memory module, wherein SLC NAND type flash memories module can store 1 The data (that is, " 1 " with " 0 ") of bit, each storage units of MLC NAND type flash memory modules can store 2 bits Each storage unit of data and TLC NAND type flash memory modules can store the data of 3 bits.

Since each storage unit of SLC NAND type flash memory modules can store the data of 1 bit, In SLC NAND type flash memory modules, the several storage units being arranged on same word-line are a corresponding entity journeys Sequence unit.

For SLC NAND type flash memory modules, each storage of MLC NAND type flash memory modules The floating gate accumulation layer of unit can store the data of 2 bits, wherein each storage state (that is, " 11 ", " 10 ", " 01 " with " 00 ") include least significant bit (Least Significant Bit, LSB) and most significant bit member (Most Significant Bit,MSB).For example, the value for the 1st bit counted from left side in storage state is LSB, and calculated from left side The value of the 2nd bit risen is MSB.Therefore, the several storage units being arranged on same word-line constitute 2 entity journeys Sequence unit, wherein the entity program unit that thus LSB of a little storage units is formed is known as lower entity program unit (low physical programming unit), and the entity program unit that thus MSB of a little storage units is formed Referred to as upper entity program unit (upper physical programming unit).In particular, when entity journey in sequencing When mistake occurs for sequence unit, therefore the data that lower entity program unit is stored may also be lost.

Similarly, the data of 3 bits can be stored in TLC NAND type flash memory moulds each storage unit in the block, Wherein each storage state (that is, " 111 ", " 110 ", " 101 ", " 100 ", " 011 ", " 010 ", " 001 " and " 000 ") includes a left side Centre effective bit (Center Significant of the LSB for the 1st bit that side is counted, the 2nd bit counted from left side Bit, CSB) and the MSB of the 3rd bit counted from left side.Therefore, the several storage lists being arranged on same word-line Member constitutes 3 entity program units, wherein under the entity program unit that thus LSB of a little storage units is formed is known as Entity program unit, entity program unit during the entity program unit that thus CSB of a little storage units is formed is known as, And the entity program unit that thus MSB of a little storage units is formed is known as upper entity program unit.In particular, In TLC NAND type flash memory modules, stored to what the data ensured on a word-line can be stablized, it is necessary to this Word-line completes sequencing three times.For example, after to the sequencing of the storage unit progress first time on first word-line, first Storage unit on word-line can be in first state (first state).And to the storage list on Article 2 word-line Storage unit while member carries out sequencing on first word-line can be programmed again.At this point, on first word-line Storage unit can be in fringe (foggy state).Then, to the storage unit on Article 3 word-line into stroke Storage unit while sequence on first, second word-line can be programmed again, at this point, depositing on first word-line Storage unit can be in shape (fine state).Furthermore sequencing is being carried out to the storage unit on Article 4 word-line While second, third word-line on storage unit can be programmed again.At this point, the storage list on Article 2 word-line Member can be in shape, and it is stable storage that thus the data in the storage unit on first word-line, which can be just ensured that,.

As the storable bit of each storage unit increases, while but also identifying the storage state of each storage unit Time be consequently increased.Therefore, the efficiency for executing and reading instruction how is effectively promoted, shortens the time for reading data, is This field technology personnel project of interest.

Invention content

A kind of method for writing data of present invention offer, memorizer control circuit unit and memory storage apparatus, effectively Improve the read performance of reproducible nonvolatile memorizer module in ground.

One example of the present invention embodiment proposes that a kind of data for reproducible nonvolatile memorizer module are written Method, wherein reproducible nonvolatile memorizer module have a most entity erased cells, among entity erased cell There are each entity erased cell most entity program units, these entity program units to be at least divided into first Entity program unit and second instance programmed cell, and the time of reading data is short from first instance programmed cell In the time for reading data from second instance programmed cell.Notebook data wiring method includes:The corresponding more data of record Most characteristic parameters;According to these characteristic parameters, identify that the first data among above-mentioned more data are often to read data;With And by the first instance journey of the first instance erased cell among the first Data programming to above-mentioned most entity erased cells Sequence unit.

In one example of the present invention embodiment, above-mentioned method for writing data further includes being arranged according to features described above parameter Above-mentioned more data, to generate the write sequence of corresponding above-mentioned more data;And according to this write sequence, by above-mentioned more stroke counts According in sequencing to first instance erased cell.

In one example of the present invention embodiment, above-mentioned method for writing data further includes most logical addresses of configuration to reflect The least a portion of most entity program units are incident upon, wherein the more data are respectively stored to described most One of logical address logical address.Also, above-mentioned record corresponds to the step of characteristic parameter of these data and includes:It establishes Count table is read, and records the reading times of each logical address in reading count table;And these data will be stored Logical address the reading times respectively characteristic parameter as these corresponding data.

It is above-mentioned that above-mentioned data are arranged according to characteristic parameter in one example of the present invention embodiment, correspond to these to generate The step of write sequence of data includes:From the reading times for reading the logical address of these data of acquisition storage in count table; And the reading times according to the logical address for storing these data, the logical address that arrangement stores these data are above-mentioned to generate Write sequence.

In one example of the present invention embodiment, above-mentioned method for writing data further includes:By the second Data programming to In the second instance program unit of one entity erased cell, deposited wherein the reading times for storing the logical address of the first data are more than Store up the reading times of the logical address of the second data.

It is above-mentioned according to write sequence in one example of the present invention embodiment, by above-mentioned first Data programming to first Step in the first instance programmed cell of entity erased cell includes:Using single-layer memory cell pattern, by the first data In sequencing to first instance erased cell;And it is real by the second of above-mentioned second Data programming to first instance erased cell Step in body programmed cell includes:Using multilayered memory unit mode, the second Data programming to first instance is erased In unit.

In one example of the present invention embodiment, above-mentioned method for writing data further includes:From above-mentioned entity erased cell it At least two entity erased cells of middle selection collect operation to execute valid data;And from this at least two entities erased cell It is middle to read above-mentioned data.

In one example of the present invention embodiment, above-mentioned method for writing data further includes:More are received from host system Write instruction, wherein these write instructions indicate respectively the above-mentioned data of storage one of to above-mentioned logical address.

In one example of the present invention embodiment, the characteristic parameter of above-mentioned corresponding data be corresponding data reading times, The reading frequency of corresponding data or the read access time interval of corresponding data.

One example of the present invention embodiment proposes memorizer control circuit unit comprising host interface, memory interface With memory management circuitry.Host interface is being connected to host system.Memory interface is non-easily to be connected to duplicative There are most entity erased cells, entity to erase for the property lost memory module, wherein reproducible nonvolatile memorizer module Each entity erased cell among unit has a most entity program units, these entity program units at least by First instance programmed cell and second instance programmed cell are divided into, and number is read from first instance programmed cell According to time be shorter than from second instance programmed cell read data time.Memory management circuitry is connected to the host and connects Mouth and the memory interface, and to record the majority characteristic parameters of corresponding more data, and according to these features ginseng Number identifies that the first data among above-mentioned more data are often to read data.In addition, above-mentioned memory management circuitry is also with following Up to instruction sequence with by the first instance erased cell among the first Data programming to above-mentioned most entity erased cells First instance programmed cell.

In one example of the present invention embodiment, above-mentioned memory management circuitry is whole also to according to features described above parameter Above-mentioned more data are managed, to generate the write sequence of corresponding above-mentioned more data, and according to this write sequence, by above-mentioned more In Data programming to first instance erased cell.

In one example of the present invention embodiment, above-mentioned memory management circuitry also to configure most logical addresses with At least part of most entity program units are mapped, wherein the more data are respectively stored to the majority One of a logical address logical address.Also, it is above-mentioned to deposit in the running of the characteristic parameter in these corresponding data of record Reservoir manages circuit and establishes reading count table, and the reading times of each logical address are recorded in reading count table and will be deposited The reading times of the logical address of these data are stored up respectively as the characteristic parameter for corresponding to these data.

In one example of the present invention embodiment, according to characteristic parameter, above-mentioned data are arranged, to generate these corresponding numbers According to write sequence running in, above-mentioned memory management circuitry from read count table in obtain store these data logically The reading times of location, and according to the reading times for the logical address for storing these data, arrangement stores these data logically Location is to generate above-mentioned write sequence.

In one example of the present invention embodiment, above-mentioned memory management circuitry is also to by the second Data programming to In the second instance program unit of one entity erased cell, deposited wherein the reading times for storing the logical address of the first data are more than Store up the reading times of the logical address of the second data.

In one example of the present invention embodiment, above-mentioned memory management circuitry is to use single-layer memory cell pattern, will In first Data programming to first instance erased cell, and multilayered memory unit mode is used, by above-mentioned second data journey In sequence to first instance erased cell.

In one example of the present invention embodiment, above-mentioned memory management circuitry also to from above-mentioned entity erased cell it At least two entity erased cells of middle selection collect operation and from this at least two entities erased cell to execute valid data It is middle to read above-mentioned data.

In one example of the present invention embodiment, above-mentioned memory management circuitry from host system also receiving more Write instruction, wherein these write instructions indicate respectively the above-mentioned data of storage one of to above-mentioned logical address.

One example of the present invention embodiment proposes a kind of memory storage apparatus comprising connecting interface unit can be made carbon copies Formula non-volatile memory module and memorizer control circuit unit.Connecting interface unit is being connected to host system.It can answer Writing formula non-volatile memory module, there are most entity erased cells, each entity among entity erased cell to erase There are unit most entity program units, these entity program units to be at least divided into first instance programmed cell With second instance programmed cell, and the time of data is read shorter than from second instance journey from first instance programmed cell The time of data is read in sequence unit.It is non-volatile with duplicative that memorizer control circuit unit is connected to connecting interface unit Property memory module, and to record the majority characteristic parameters of corresponding more data, and according to these characteristic parameters, know The first data among not above-mentioned more data are often to read data.In addition, above-mentioned memory management circuitry is also to by first The first instance programmed cell of first instance erased cell among Data programming to above-mentioned most entity erased cells.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit according to features described above also joining Number arranges above-mentioned more data, will be upper to generate the write sequence of corresponding above-mentioned more data, and according to this write sequence It states in more Data programmings to first instance erased cell.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is also a logically to configure majority Location to map at least part of most entity program units, wherein the more data be respectively stored to it is described One of most logical addresses logical address.Also, in the running of the characteristic parameter in these corresponding data of record, on It states memorizer control circuit unit and establishes reading count table, the reading times of each logical address are recorded in reading count table And the reading times of the logical address of these data will be stored respectively as the characteristic parameter for corresponding to these data.

In one example of the present invention embodiment, according to characteristic parameter, above-mentioned data are arranged, to generate these corresponding numbers According to write sequence running in, above-mentioned memorizer control circuit unit stores these data and patrols from reading to obtain in count table The reading times of address are collected, and according to the reading times for the logical address for storing these data, arrangement stores patrolling for these data Address is collected to generate above-mentioned write sequence.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is also to by the second Data programming Into the second instance program unit of first instance erased cell, wherein the reading times for storing the logical address of the first data are big In the reading times for the logical address for storing the second data.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is to use single-layer memory cell mould Formula by the first Data programming to first instance erased cell, and uses multilayered memory unit mode, above-mentioned second is counted According in sequencing to first instance erased cell.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit from above-mentioned entity also erasing list At least two entity erased cells are chosen among member to execute valid data collection operation and erase from this at least two entity Above-mentioned data are read in unit.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit from host system also receiving More write instructions, wherein these write instructions indicate respectively the above-mentioned data of storage one of to above-mentioned logical address.

Based on above-mentioned, the method for writing data, memorizer control circuit unit and memory storage dress of this exemplary embodiment Set is, according to the feature of data, to arrange the sequence of write-in data, the Data programming that will often read when executing write operation Into the faster entity program unit of reading speed, read performance is thus effectively improved.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to coordinate attached drawing to make Carefully it is described as follows.

Description of the drawings

Fig. 1 is the host system and memory storage apparatus according to an exemplary embodiment;

Fig. 2 is the signal of the computer, input/output device and memory storage apparatus according to an exemplary embodiment Figure;

Fig. 3 is the schematic diagram of the host system and memory storage apparatus according to an exemplary embodiment;

Fig. 4 is the schematic block diagram of the memory storage apparatus according to an exemplary embodiment;

Fig. 5 A and Fig. 5 B are the storage unit storage architecture and entity erased cell according to an exemplary embodiment Schematic diagram;

Fig. 6 is the schematic block diagram of the memorizer control circuit unit according to an exemplary embodiment;

Fig. 7 and Fig. 8 is the example schematic of the management entity block according to the first exemplary embodiment;

Fig. 9 is the example of the reading count table according to an exemplary embodiment of the invention;

Figure 10 is the example of the execution write instruction according to an exemplary embodiment of the invention;

Figure 11 is the example that the valid data shown according to an exemplary embodiment of the invention collect operation;

Figure 12 is the flow chart of the method for writing data according to an exemplary embodiment of the invention.

Reference sign:

10:Memory storage apparatus

11:Host system

12:Input/output (I/O) device

110:System bus

111:Processor

112:Random access memory (RAM)

113:Read-only memory (ROM)

114:Data transmission interface

20:Motherboard

201:Portable disk

202:Memory card

203:Solid state disk

204:Radio memory storage device

205:GPS module

206:Network interface card

207:Radio transmitting device

208:Keyboard

209:Screen

210:Loudspeaker

30:Memory storage apparatus

31:Host system

32:SD card

33:CF cards

34:Embedded storage device

341:Embedded multi-media card

342:Embedded type multi-core piece sealed storage device

402:Connecting interface unit

404:Memorizer control circuit unit

406:Reproducible nonvolatile memorizer module

410 (0)~410 (N):Entity erased cell

502:Memory management circuitry

504:Host interface

506:Memory interface

508:Buffer storage

510:Electric power management circuit

512:Error checking and correcting circuit

602:Data field

604:Idle area

606:System area

608:Replace area

LBA (0)~LBA (H):Logical block addresses

LZ (0)~LZ (M):Logic region

D0~D5:Data

900:Read count table

901:Logical address field

902:Reading times field

S1201:The step of characteristic parameter of these corresponding data of record

S1203:According to the characteristic parameter of these corresponding data, the step of identifying the normal reading data among these data

S1205:It will be identified as the step in the Data programming often read to lower entity program unit

Specific implementation mode

In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module and controller (also referred to as, control circuit unit).Be commonly stored device storage device be used together with host system so that Host system can write data into memory storage apparatus or be read from memory storage apparatus data.

Fig. 1 is host system, memory storage apparatus and the input/output (I/O) according to an exemplary embodiment The schematic diagram of device, and Fig. 2 is host system according to another exemplary embodiment, memory storage apparatus and defeated Enter/export the schematic diagram of (I/O) device.

Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, RAM) 112, read-only memory (read only memory, ROM) 113 and data transmission interface 114.Place Reason device 111, random access memory 112, read-only memory 113 and data transmission interface 114 are all connected to system bus (system bus)110。

In this exemplary embodiment, host system 11 is connected by data transmission interface 114 and memory storage apparatus 10 It connects.For example, host system 11 can write data into memory storage apparatus 10 via data transmission interface 114 or from memory Data are read in storage device 10.In addition, host system 11 is connect with I/O devices 12 by system bus 110.For example, main Output signal can be sent to I/O devices 12 via system bus 110 or receive input signal from I/O devices 12 by machine system 11.

In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 is on the motherboard 20 for may be provided at host system 11.The number of data transmission interface 114 can be one or more. By data transmission interface 114, motherboard 20 can be connected to memory storage apparatus 10 via wired or wireless way.Storage Device storage device 10 can be for example portable disk 201, memory card 202, solid state disk (Solid State Drive, SSD) 203 or Radio memory storage device 204.Radio memory storage device 204 can be for example close range wireless communication (Near Field Communication Storage, NFC) memory storage apparatus, radio facsimile (WiFi) memory storage apparatus, bluetooth (Bluetooth) memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. are with various wireless Memory storage apparatus based on mechanics of communication.Determine in addition, motherboard 20 can also be connected to the whole world by system bus 110 Position system (Global Positioning System, GPS) module 205, network interface card 206, radio transmitting device 207, key The various I/O devices such as disk 208, screen 209, loudspeaker 210.For example, in an exemplary embodiment, motherboard 20 can be by wirelessly passing 207 access wireless memory storage apparatus 204 of defeated device.

In an exemplary embodiment, mentioned host system is substantially to coordinate to store with memory storage apparatus The arbitrary system of data.Although in above-mentioned exemplary embodiment, host system is explained with computer system, however, Fig. 3 is The schematic diagram of host system and memory storage apparatus according to another exemplary embodiment.Fig. 3 is please referred to, in another model Example embodiment in, host system 31 can also be digital camera, video camera, communication device, audio player, video player or The systems such as tablet computer, and memory storage apparatus 30 can be its used SD card 32, CF cards 33 or embedded storage device The various non-volatile memory storage devices such as 34.Embedded storage device 34 includes embedded multi-media card (embedded MMC, eMMC) 341 and/or embedded type multi-core piece sealed storage device (embedded Multi Chip Package, eMCP) The all types of embedded storage devices being directly connected in memory module on the substrate of host system such as 342.

Fig. 4 is the schematic block diagram of the host system and memory storage apparatus according to an exemplary embodiment.

Please refer to Fig. 4, memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.

In this exemplary embodiment, connecting interface unit 402 is to be compatible to the advanced attachment of sequence (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, connecting interface unit 402 can also be to meet advanced attachment (Parallel Advanced Technology Attachment, PATA) mark side by side Accurate, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, peace Full digital code (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, insertion Formula multimedia storage card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, embedded type multi-core piece encapsulate (embedded Multi Chip Package, eMCP) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.In this exemplary embodiment, connection Interface unit 402 can be encapsulated in memorizer control circuit unit 404 in a chip or connecting interface unit 402 is cloth Outside a chip comprising memorizer control circuit unit.

Memorizer control circuit unit 404 is executing multiple logic gates or control with hardware pattern or firmware pattern implementation System instruction, and writing for data is carried out in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The runnings such as enter, read and erase.

Reproducible nonvolatile memorizer module 406 is to be connected to memorizer control circuit unit 404, and to deposit The data that storage host system 11 is written.Reproducible nonvolatile memorizer module 406 has entity erased cell 410 (0) ~410 (N).For example, entity erased cell 410 (0)~410 (N) can belong to the same memory crystal grain (die) or belong to not Same memory crystal grain.Each entity erased cell is respectively provided with most entity program units, wherein belonging to the same reality The entity program unit of body erased cell can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, this hair It is bright without being limited thereto, each entity erased cell be can by 64 entity program units, 256 entity program units or other An arbitrary entity program unit is formed.

In more detail, entity erased cell is the least unit erased.That is, each entity erased cell contains minimum The storage unit of number being erased together.Entity program unit is the minimum unit of sequencing.That is, entity program unit For the minimum unit of data is written.Each entity program unit generally includes data bit element area and redundancy bit area.Data bit First area includes multiple entity access addresses to store the data of user, and redundancy bit area is to the data of storage system (for example, control information and error correcting code).In this exemplary embodiment, the data bit element area of each entity program unit Middle can include 8 entity access addresses, and the size of an entity access address is 512 bit groups (byte).However, at other Also it may include that the more or fewer entity access addresses of number, the present invention are not intended to limit in exemplary embodiment, in data bit element area The size and number of entity access address.For example, in an exemplary embodiment, entity erased cell is physical blocks, and Entity program unit is physical page or entity sector, but invention is not limited thereto.

In this exemplary embodiment, reproducible nonvolatile memorizer module 406 is three rank storage unit (Trinary Level Cell, TLC) NAND type flash memory module be (that is, can store the quick flashing of 3 data bit elements in a storage unit Memory module).However, the invention is not limited thereto, it is single that reproducible nonvolatile memorizer module 406 can also be multistage storage First (Multi Level Cell, MLC) NAND type flash memory module is (that is, can store 2 data bit in a storage unit The flash memory module of member) or other memory modules with the same characteristics.

Fig. 5 A and Fig. 5 B are the storage unit storage architecture and entity erased cell according to this exemplary embodiment Example schematic.

Fig. 5 A are please referred to, the storage state of each storage unit of reproducible nonvolatile memorizer module 406 can quilt It is identified as " 111 ", " 110 ", " 101 ", " 100 ", " 011 ", " 010 ", " 001 " or " 000 " (as shown in Figure 5A), wherein left side is calculated The 3rd bit that the 1st bit risen is LSB, the 2nd bit being counted from left side is CSB and is counted from left side is MSB. In addition, the several storage units being arranged on same word-line constitute 3 entity program units, wherein thus a little storages The entity program unit that the LSB of unit is formed is known as first instance programmed cell and (hereinafter also referred to descends entity program Unit), the entity program unit that thus MSB of a little storage units is formed is known as second instance programmed cell (below Referred to as upper entity program unit), and the entity program unit that thus CSB of a little storage units is formed is known as third reality Body programmed cell (entity program unit in hereinafter also referred to).

Fig. 5 B are please referred to, an entity erased cell is made of multiple entity program unit groups, wherein each real Body programmed cell group includes the lower entity program list being made of the several storage units being arranged on same word-line First, middle entity program unit and upper entity program unit.For example, in entity erased cell, belong to lower entity program 0th entity program unit of unit, the 1st entity program unit for belonging to middle entity program unit and belong to reality 2nd entity program unit of body programmed cell can be considered as an entity program unit group.Similarly, the 3rd, 4,5 A entity program unit can be considered as an entity program unit group, and and so on other entity program units It is to be divided into multiple entity program unit groups according to this mode.That is, in the exemplary embodiment of Fig. 5 B, entity is smeared Except a total of 258 entity program units of unit, and several storage unit institutes group by being arranged on same word-line At lower entity program unit, middle entity program unit and upper entity program unit can form an entity program list Tuple, therefore the entity erased cell of Fig. 5 B is segmented into 86 entity program unit groups in total.It is to be noted that this hair The bright number for being not used to limit entity program unit or entity program unit group in entity erased cell.

It is noted that in this exemplary embodiment, the speed of data is read from above-mentioned lower entity program unit Therefrom entity program unit and the speed that data are read in upper entity program unit can be faster than.

Fig. 6 is the schematic block diagram of the memorizer control circuit unit according to an exemplary embodiment.

Fig. 6 is please referred to, memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504 and deposits Memory interface 506, buffer storage 508, electric power management circuit 510 and error checking and correcting circuit 512.

Memory management circuitry 502 to control memory control circuit unit 404 overall operation.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the runnings such as to carry out the write-in of data, read and erase.

In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with firmware pattern.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the runnings such as to carry out the write-in of data, read and erase.

Fig. 7 and Fig. 8 is the example schematic of the management entity erased cell according to an exemplary embodiment.

It will be appreciated that being described herein the fortune of the entity erased cell of reproducible nonvolatile memorizer module 406 When making, it is concept in logic to carry out application entity erased cell with the words such as " extraction ", " grouping ", " division ", " association ".Namely It says, the physical location of the entity erased cell of reproducible nonvolatile memorizer module is not changed, but in logic pair can The entity erased cell of manifolding formula non-volatile memory module is operated.

Fig. 7 is please referred to, memorizer control circuit unit 404 (or memory management circuitry 502) can be by entity erased cell 410 (0)~410 (N) are logically grouped into data field 602, idle area 604, system area 606 and substitution area 608.

It is to store to come from host system to logically belong to data field 602 and the entity erased cell in idle area 604 11 data.Specifically, the entity erased cell of data field 602 is regarded as having stored the entity erased cell of data, and The entity erased cell in idle area 604 is the entity erased cell to replacement data area 602.That is, working as from host system When system 11 receives write instruction with the data to be written, memorizer control circuit unit 404 (or memory management circuitry 502) It can use and extract entity erased cell from idle area 604 data are written, with the entity erased cell in replacement data area 602.

The entity erased cell for logically belonging to system area 606 is to record system data.For example, system data includes The entity of manufacturer and model, reproducible nonvolatile memorizer module about reproducible nonvolatile memorizer module The entity program unit number etc. of erased cell number, each entity erased cell.

It is to replace program for bad entity erased cell to logically belong to the entity erased cell in substitution area 608, to take The entity erased cell of generation damage.Specifically, if still having normal entity erased cell and data in substitution area 608 When the entity erased cell damage in area 602, memorizer control circuit unit 404 (or memory management circuitry 502) can be from substitution Normal entity erased cell is extracted in area 608 to replace the entity erased cell of damage.

In particular, the quantity meeting of data field 602, idle area 604, system area 606 and the entity erased cell in substitution area 608 It is different according to different memory specifications.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 10, The grouping relationship that entity erased cell is associated with to data field 602, idle area 604, system area 606 and substitution area 608 can be dynamically It changes.For example, when the entity erased cell damage in idle area 604 is substituted the entity erased cell substitution in area 608, then The entity erased cell in the area 608 of substitution originally can be associated to idle area 604.

Fig. 8 is please referred to, memorizer control circuit unit 404 (or memory management circuitry 502) is with can configuring logical blocks Location LBA (0)~LBA (H) is to map the entity erased cell of data field 602, wherein each logical block addresses have most Logical address is to map the entity program unit of corresponding entity erased cell.Also, work as 11 data to be written of host system When to logical address or updating storage the data in logical address, memorizer control circuit unit 404 (or memory management electricity Road 502) data can be written as start entity erased cell by one entity erased cell of extraction from idle area 604, with wheel For the entity erased cell of data field 602.Also, when this is fully written as the entity erased cell of start entity erased cell When, memorizer control circuit unit 404 (or memory management circuitry 502) can extract empty entity from idle area 604 and smear again Except unit is as start entity erased cell, to continue to write to the update number of the corresponding write instruction for coming from host system 11 According to.In addition, when the number of available entity erased cell in idle area 604 is less than preset value, memorizer control circuit unit 404 (or memory management circuitries 502) can execute collecting garbage (garbage collection) operation (also referred to as, significant figure Operated according to collecting) arrange the valid data in data field 602, the entity without storage valid data in data field 602 is smeared Except unit is associated with again to idle area 604.

In order to identify which entity program unit is the data of each logical address be stored in, in this exemplary embodiment In, memorizer control circuit unit 404 (or memory management circuitry 502) can record logical address and entity program unit it Between mapping relations.For example, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) Logic-entity mapping can be stored in reproducible nonvolatile memorizer module 406 to be reflected to record each logical address The entity program unit penetrated.Memorizer control circuit unit 404 (or memory management circuitry 502) meeting when data to be accessed Logic-entity mapping is loaded into buffer storage 508 to safeguard, and be written or read according to logic-entity mapping Access evidence.

Reflecting for all logical addresses is recorded it is noted that can not be stored since the capacity of buffer storage 508 is limited The mapping table of relationship is penetrated, therefore, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) logical block addresses LBA (0)~LBA (H) can be grouped into multiple logic region LZ (0)~LZ (M), and is patrolled to be each It collects region and configures a logic-entity mapping.In particular, when (or the memory management circuitry of memorizer control circuit unit 404 502) when being intended to update the mapping of some logical block addresses, logic-reality of the logic region belonging to this corresponding logical block addresses Body mapping table can be loaded on buffer storage 508 to be updated.Specifically, if patrolling belonging to this corresponding logical block addresses Logic-the entity mapping for collecting region is not temporarily stored in buffer storage 508 (that is, that is kept in buffer storage 508 patrols Volume-entity mapping is not when recording the mapping for being intended to newer logical block addresses, memorizer control circuit unit 404 (or storage Device manages circuit 502) mapping table swap operation (mapping table swapping operation) can be executed with will be current It is temporarily stored in logic-entity mapping in buffer storage 508 and restores to reproducible nonvolatile memorizer module 406, and Record is intended to newer logical block addresses mapped logic-entity mapping to be loaded into buffer storage 508.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 502 can also procedure code pattern The specific region of reproducible nonvolatile memorizer module 406 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 502 has microprocessor unit (not shown), read-only memory (not Display) and random access memory (not shown).In particular, this read-only memory has driving code, and when memory controls When circuit unit 404 is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in memory module 406 is loaded into the random access memory of memory management circuitry 502.Later, micro- place Reason device unit such as can operate these control instructions to carry out the write-in of data, read and erase at the runnings.

In addition, in another exemplary embodiment of the present invention, the control instruction of memory management circuitry 502 can also a hardware Pattern carrys out implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is to be connected to microcontroller.Wherein, storage unit Circuit is managed to manage the entity erased cell of reproducible nonvolatile memorizer module 406;Memory write circuit is used It is deposited with assigning write instruction to reproducible nonvolatile memorizer module 406 with writing data into duplicative is non-volatile In memory modules 406;Memory reading circuitry to reproducible nonvolatile memorizer module 406 assign reading instruction with Data are read from reproducible nonvolatile memorizer module 406;Memory erases circuit to non-volatile to duplicative Property memory module 406 assign erase instruction data to be erased from reproducible nonvolatile memorizer module 406;And it counts According to processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 406 and from duplicative it is non- The data read in volatile 406.

Referring again to Fig. 6, host interface 504 is to be connected to memory management circuitry 502 and connect to be connected to connection Mouthful unit 402, to receive and identify instruction and data that host system 11 is transmitted.That is, host system 11 is transmitted Instruction and data can be sent to memory management circuitry 502 by host interface 504.In this exemplary embodiment, host Interface 504 is to be compatible to SATA standard.However, it is necessary to be appreciated that the invention is not limited thereto, host interface 504 can also be phase It is dissolved in PATA standards, 1394 standards of IEEE, PCI Express standards, USB standard, UHS-I interface standards, UHS-II interface marks Standard, SD standards, MS standards, MMC standards, CF standards, IDE standards or other suitable data transmission standards.

Memory interface 506 is to be connected to memory management circuitry 502 and duplicative is non-volatile to be deposited to access Memory modules 406.It can be via memory to the data of reproducible nonvolatile memorizer module 406 that is, being intended to be written Interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.

Buffer storage 508, which is connected to memory management circuitry 502 and is configured to temporarily store, comes from host system 11 Temporal data and the data for instructing or coming from reproducible nonvolatile memorizer module 406.

Electric power management circuit 510 is to be connected to memory management circuitry 502 and to control memory storage device 10 Power supply.

Error checking and correcting circuit 512 be connected to memory management circuitry 502 and to execute error checking with Correction program is to ensure the correctness of data.For example, referring to when memory management circuitry 502 receives write-in from host system 11 When enabling, error checking generates corresponding error checking and correcting code with the data that correcting circuit 512 can be this corresponding write instruction (Error Checking and Correcting Code, ECC Code), and memory management circuitry 502 can will correspond to this The data of write instruction are written with corresponding error checking and correcting code into reproducible nonvolatile memorizer module 406. Later, it can be read simultaneously when reading data from reproducible nonvolatile memorizer module 406 when memory management circuitry 502 The corresponding error checking of this data and correcting code, and error checking can be according to this error checking and correction with correcting circuit 512 Code executes error checking and correction program to read data.

Memory management circuitry 502, host interface 504, memory interface 506, buffer storage 508, electricity is described below Power management circuits 510 and error checking and the operation performed by correcting circuit 512, also can refer to as by memorizer control circuit list Performed by member 404.

In this exemplary embodiment, when execution comes from the write instruction of host system 11, memory management circuitry 502 The data (hereinafter also referred to often reading data) often read can be identified according to the characteristic parameter of the corresponding data to be written, and It will often read in Data programming to lower entity program unit.Here, it refers to reflecting ratio according to characteristic parameter often to read data The data that other data (hereinafter also referred to reading very much data) are more frequently read.For example, memory management circuitry 502 can basis The characteristic parameter of the corresponding data to be written, to arrange data and generate the write sequence of these corresponding data, and then according to This write sequence assigns instruction sequence by the Data programming arranged to reproducible nonvolatile memorizer module 406 In.

For example, in this exemplary embodiment, memory management circuitry 502, which can be established, reads count table to record each logic The reading times of address, and using store data logical address reading times as this data characteristic parameter.Namely It says, memory management circuitry 502 can arrange the number to be stored according to the reading times for each logical address for storing these data Generate corresponding write sequence according to this, and according to this write sequence by Data programming to type nonvolatile In module 406.

Fig. 9 is the example of the reading count table according to an exemplary embodiment of the invention.

Fig. 9 is please referred to, it includes logical address field 901 and reading times field 902 to read count table 900.Logical address Field 901 records the number of each logical address, and reading times field 902 records the reading times of counterlogic address. For example, when host system 11 assigns reading instruction to logical address, the reading times of this corresponding logical address add 1.At this In exemplary embodiment, memory storage apparatus 10 after the power is turned on, memory management circuitry 502 can deposit from duplicative is non-volatile The reading instruction update reading count table for reading count table 900 and being assigned according to host system 11 is loaded into memory modules 406 900;And before the power-off of memory storage apparatus 10, memory management circuitry 502 can will read count table 900 and restore to and can answer It writes in formula non-volatile memory module 406.For example, reading count table 900 can be stored in system area 606.

It is using the reading times of logical address as corresponding data it will be appreciated that although in this exemplary embodiment Characteristic parameter, however the invention is not limited thereto, in another exemplary embodiment, can also logical address reading frequency, read Take characteristic parameter of the time interval as corresponding data.

In this exemplary embodiment, when memory storage apparatus 10 receives write instruction and be intended to store from host system 11 Data when, memory management circuitry 502 can keep in these data to buffer storage 508.Then, memory storage apparatus Logical address of 10 meetings indicated by write instruction obtains corresponding reading times from count table 900 is read, and according to institute The reading times of acquisition arrange the data to be stored.In particular, being put in order according to this, stores to reading times are higher and patrol The data of volume address can be programmed into lower entity program unit, thus execute read instruction when, can be substantially improved from The speed of data is read in the logical address being often read, and shortens the time for executing and reading instruction.

Figure 10 is the example of the execution write instruction according to an exemplary embodiment of the invention.

Please refer to Figure 10, it is assumed that note body storage device 10 received from host system 11 one or more write instructions and this Data D0 is stored to logical address LA0, data D1 is stored to logical address LA1, by data by write instruction instruction in order D2 is stored to logical address LA2, data D3 is stored to logical address LA3, data D4 is stored to logical address LA4 and will be counted It is stored to logical address LA5 according to D5.

In this example, data D0~D5 can be first temporarily stored in buffer storage 508 by memory management circuitry 502, and And the reading times of logical address LA0~LA5 are obtained from reading count table 900 according to write instruction.As shown in figure 9, logic The reading times of address LA0 are 0, and the reading times of logical address LA1 are 5, and the reading times of logical address LA2 are 300, logic The reading times of address LA3 are 10, and the reading times of logical address LA4 are 20 and the reading times of logical address LA5 are 10. Base this, original can be received the sequence of write instruction (that is, logical address LA0, logical address LA1, patrolling by memory management circuitry 502 Volume address LA2, logical address LA3, logical address LA4, logical address LA5) new write sequence is adjusted to (that is, logical address LA2, logical address LA3, logical address LA0, logical address LA4, logical address LA5, logical address LA1).Then, memory Entity erased cell can be extracted (for example, entity erased cell 410 (F), below from idle area 604 by managing circuit 502 Can refer to as first instance erased cell), and will store that (also can refer to below is to the data D2 of logical address in order One data) sequencing to the 0th entity program unit of entity erased cell 410 (F), will store to the data of logical address D3 sequencing and will be stored to the data D0 of logical address to the 1st entity program unit of entity erased cell 410 (F) (also being can refer to below as the second data) sequencing to entity erased cell 410 (F) the 2nd entity program unit.Here, 0th~2 entity program unit also can refer to as first instance programmed cell group.Then, memory management circuitry 502 Meeting will store the 3rd entity program unit to the data D4 sequencing of logical address to entity erased cell 410 (F), will The 4th entity program unit to the data D5 sequencing of logical address to entity erased cell 410 (F) is stored, and will Store the 5th entity program unit to the data D1 sequencing of logical address to entity erased cell 410 (F).Here, the 3~5 entity program units also can refer to as first instance programmed cell group.That is, in this example, according to patrolling The reading times of address are collected, it is descending, it is stored in the data D2 and data D4 of two logical addresses of the maximum reading times of tool It can be programmed into lower entity program unit, be stored in the data D3 and data of two logical addresses of the big reading times of tool time D5 can be programmed into middle entity program unit and be stored in the data D0 for two logical addresses for having smaller reading times It can be programmed supreme entity program unit with data D1.

The example of Figure 10 be according to will be identified that the data often read together with other data sequencing in the same entity In programmed cell group, however, the invention is not limited thereto.In another exemplary embodiment, memory management circuitry 502 can also make With single-layer memory cell pattern (SLC mode), lower entity program unit program pattern (lower physical Programming unit programming mode) or combination process pattern (mixture programming mode) By in data D2 and data D4 sequencing to entity program unit group, and using multilayered memory unit mode come by data In D3, data D5, data D0 and data D1 sequencing to entity program unit group.If here, with single-layer memory cell mould Formula uses reproducible nonvolatile memorizer module 406, then each storage unit only stores a bit Data.If Following entity program pattern uses reproducible nonvolatile memorizer module 406, then duplicative non-volatile memories Only belonging to the entity program unit of lower entity program unit in device module 406 can be programmed, and lower entity program Upper entity program unit corresponding to unit can not be programmed.If using duplicative with combination process pattern Non-volatile memory module 406, then valid data (or truthful data), which can be programmed into, belongs to lower entity program unit Entity program unit in, without being programmed into the entity program unit for belonging to upper entity program unit.This Outside, if using reproducible nonvolatile memorizer module 406 with combination process pattern, then correspond to valid data The invalid data (or virtual data) of (or truthful data) can be programmed into the entity program for belonging to entity program unit Change in unit.

The example of Figure 10 is the write sequence of data to be stored to be rearranged, however, of the invention when executing write instruction It is without being limited thereto, when executing valid data and collecting operation, can also this mode by the Data programming more often read to lower entity In programmed cell.

Figure 11 is the example that the valid data shown according to an exemplary embodiment of the invention collect operation.

Please refer to Figure 11, it is assumed that entity erased cell 410 (0), entity erased cell 410 (1) and entity erased cell 410 (2) it is selected to carry out valid data collection operation, and entity erased cell 410 (0) is stored with and belongs to logical address LA0's The valid data D0 and valid data D1 for belonging to logical address LA1, entity erased cell 410 (1), which is stored with, belongs to logical address The valid data D2 of LA2, and entity erased cell 410 (2) is stored with the valid data D for belonging to logical address LA5, wherein dotted line Part indicates invalid data.

In this example, memory management circuitry 502 can be respectively from entity erased cell 410 (0), entity erased cell 410 (1) and reading data D0, D1, D2 and D5 in entity erased cell 410 (2), buffering is temporarily stored in by data D0, D1, D2 and D5 In memory 508, and according to logic-entity mapping from read count table 900 in obtain logical address LA0, LA1, LA2 with The reading times of LA5.As shown in figure 9, the reading times of logical address LA0 are 0, the reading times of logical address LA1 are 5, are patrolled The reading times for collecting address LA2 are 300, and the reading times of logical address LA5 are 10.Base this, memory management circuitry 502 The former sequence (that is, logical address LA0, logical address LA1, logical address LA2, logical address LA5) for reading data can be adjusted For new write sequence (that is, logical address LA2, logical address LA1, logical address LA0, logical address LA5).Then, it stores Device manages circuit 502 can extract an entity erased cell (for example, entity erased cell 410 (F+1)) from idle area 604, And the 0th entity program to the data D2 sequencing of logical address to entity erased cell 410 (F) will be stored in order Unit will store the 1st entity program unit to the data D1 sequencing of logical address to entity erased cell 410 (F), The 2nd entity program unit to the data D0 sequencing of logical address to entity erased cell 410 (F) will be stored, and The 3rd entity program unit to the data D5 sequencing of logical address to entity erased cell 410 (F) will be stored.Also It is to say, descending according to the reading times of logical address in this example, be stored in the maximum reading times of tool two patrol The data D2 and data D5 for collecting address can be programmed into lower entity program unit, be stored in the logic of the big reading times of tool time The data D1 of address can be programmed into middle entity program unit and be stored in the logical address for having smaller reading times Data D0 can be programmed supreme entity program unit.

In the example of Figure 10 and Figure 11, by before programming data, according to corresponding data characteristic parameter (for example, The reading times of logical address) adjustment write-in data sequence, by the Data programming often read to reading speed it is faster under In entity program unit, it can effectively shorten the time for executing and reading instruction.

It will be appreciated that example shown in Figure 10 and Figure 11 is to execute write instruction and valid data collection operation, Write sequence is sequentially directly adjusted according to the reading times of logical address, by the Data programming often read to reading speed Faster in lower entity program unit.However, in another exemplary embodiment, memory management circuitry 502 also can be in logic When the reading times of address are more than predetermined threshold value, corresponding data are just identified as the data often read, and it is suitable to adjust write-in Sequence descends this Data programming to reading speed in entity program unit faster.

Furthermore although in the example of Figure 10 and Figure 11, memory management circuitry 502 can be according to the reading time of logical address It counts sequentially to adjust write sequence, however the invention is not limited thereto, in another exemplary embodiment, memory management circuitry 502 Also it can only identify and often read data, and this Data programming to reading speed is descended faster in entity program unit, as Other read data very much then can be not necessarily to the reading times of logically address to be ranked up.That is, being intended to write when identifying The data entered are when reading very much data, and memory management circuitry 502 can be by the supreme entity program list of this Data programming, middle reality Body programmed cell or lower entity program unit.If for example, identifying the entity of the data often read and predetermined programmed When programmed cell is not lower entity program unit, memory management circuitry 502 can will be identified that the data journey often read It is inserted in the neighbouring next lower entity program unit of sequenceization and by the entity program unit of this predetermined programmed virtual Data (dummy data).

Figure 12 is please referred to, when being intended to more data of sequencing, in step S1201, memory management circuitry 502 can record The characteristic parameter of these corresponding data.As previously mentioned, for example, memory management circuitry 502, which can be established, reads count table 900 to remember Record the reading times of logical address, and using store these data logical address reading times as these data of correspondence Characteristic parameter.

In step S1203, according to the characteristic parameter of these corresponding data, the normal reading data among these data are identified, And in step S1205, memory management circuitry 502 can will be identified as the Data programming often read to lower entity program In unit.

In conclusion the method for writing data of exemplary embodiment of the present invention, memorizer control circuit unit and memory are deposited Storage device can rearrange the sequence of write-in data according to the feature of data, by the Data programming more often read to reading In the entity program unit of speed, read performance is thus effectively improved.

Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change with retouching, therefore the present invention protection Subject to range ought be defined depending on appended claims.

Claims

1. a kind of method for writing data, which is characterized in that be used for reproducible nonvolatile memorizer module, the duplicative Non-volatile memory module has most entity erased cells, each reality among the most entity erased cells Body erased cell has most entity program units, and it is real that most entity program units are at least divided into first Body programmed cell and second instance programmed cell, the time that data are read from the first instance programmed cell are shorter than The time of data is read from the second instance programmed cell, the method for writing data includes:

The majority characteristic parameter of the corresponding more data of record;

According to the most characteristic parameters, identify that the first data among the more data are often to read data, wherein institute The second data among often reading the data more data are stated more frequently to be read;And

By first of the first instance erased cell among first Data programming to the most entity erased cells In entity program unit.

2. method for writing data according to claim 1, which is characterized in that further include:According to the most feature ginsengs Number arranges the more data, to generate the write sequence of the corresponding more data;It, will and according to said write sequence In the first instance erased cell among the more Data programmings to the most entity erased cells.

3. method for writing data according to claim 2, which is characterized in that further include:

Most logical addresses of configuration are to map at least part of most entity program units, wherein more stroke counts According to being respectively stored to one of most logical addresses logical address,

Wherein the step of most characteristic parameters of the corresponding more data of record, includes:

Establish read count table, and it is described reading count table in record the logical address among each logical address Reading times;And

The reading times of the logical address of the more data will be stored respectively as the described more of the corresponding more data Several characteristic parameters.

4. method for writing data according to claim 3, which is characterized in that it is described according to the most characteristic parameters, The more data are arranged, include the step of the said write sequence for corresponding to the more data to generate:

The reading times for the logical address for storing the more data are obtained from the reading count table;And

According to the reading times for the logical address for storing the more data, arrangement stores the described of the more data and patrols Address is collected to generate said write sequence.

5. method for writing data according to claim 1, which is characterized in that further include:

By in the second instance program unit of second Data programming to the first instance erased cell, wherein storing institute The reading times for stating the logical address of the first data are more than the reading times for the logical address for storing second data.

6. method for writing data according to claim 5, which is characterized in that by first Data programming to described The step of first instance program unit of one entity erased cell includes:

It, will be in first Data programming to the first instance erased cell using single-layer memory cell pattern;And

It wherein will be in the second instance program unit of second Data programming to the first instance erased cell Step includes using multilayered memory unit mode, will be in second Data programming to the first instance erased cell.

7. method for writing data according to claim 2, which is characterized in that further include:

At least two entity erased cells, which are chosen, among the most entity erased cells collects behaviour to execute valid data Make;And

The more data are read from at least two entities erased cell.

8. method for writing data according to claim 2, further includes:

More write instructions are received from host system, wherein the more write instructions indicate respectively the storage more data Extremely one of described logical address.

9. method for writing data according to claim 1, which is characterized in that described most of the corresponding more data Characteristic parameter is the reading frequency or described more corresponding of the reading times of the corresponding more data, the corresponding more data The read access time interval of data.

10. a kind of memorizer control circuit unit, which is characterized in that including:

Host interface, to be connected to host system;

Memory interface, to be connected to reproducible nonvolatile memorizer module, wherein the duplicative is non-volatile Memory module has a most entity erased cells, each entity among the most entity erased cells is erased list There are member most entity program units, most entity program units to be at least divided into first instance sequencing Unit and second instance programmed cell, and the time of data is read shorter than from institute from the first instance programmed cell State the time that data are read in second instance programmed cell;And

Memory management circuitry is connected to the host interface and the memory interface,

The wherein described memory management circuitry corresponds to the majority characteristic parameters of more data and according to the majority to record A characteristic parameter identifies that the first data among the more data are often to read data, wherein the normal reading data are compared with institute The second data among more data are stated more frequently to be read,

The wherein described memory management circuitry is also assigning an at least instruction sequence with by first Data programming to institute In the first instance programmed cell for stating the first instance erased cell among most entity erased cells.

11. memorizer control circuit unit according to claim 10, which is characterized in that the memory management circuitry is also According to the most characteristic parameters, to arrange the more data, to generate the write sequence of the corresponding more data; And according to said write sequence, by described the among the more Data programmings to the most entity erased cells In one entity erased cell.

12. memorizer control circuit unit according to claim 11, which is characterized in that the memory management circuitry is also To configure most logical addresses to map at least part of most entity program units, wherein more stroke counts According to being respectively stored to one of most logical addresses logical address,

Wherein in the running of the most characteristic parameters of the corresponding more data of record, the memory management circuitry It establishes and reads count table, the reading time of each logical address among the logical address is recorded in the reading count table Number, and will store the more data logical address reading times respectively as described in the correspondence more data Most characteristic parameters.

13. memorizer control circuit unit according to claim 12, which is characterized in that described according to described most Characteristic parameter arranges the more data, described to deposit in the running to generate the said write sequence of the corresponding more data Reservoir manages the reading times that circuit obtains the logical address for storing the more data from the reading count table, and root According to the reading times for the logical address for storing the more data, arrangement stores the logical address of the more data to produce Raw said write sequence.

14. memorizer control circuit unit according to claim 10, which is characterized in that the memory management circuitry is also To by the second instance program unit of second Data programming to the first instance erased cell,

The reading times for wherein storing the logical address of first data are more than the logical address for storing second data Reading times.

15. memorizer control circuit unit according to claim 14, which is characterized in that the memory management circuitry is Using single-layer memory cell pattern, will be deposited in first Data programming to the first instance erased cell and using multilayer Storage unit pattern, will be in second Data programming to the first instance erased cell.

16. memorizer control circuit unit according to claim 11, which is characterized in that the memory management circuitry is also To choose at least two entity erased cells among the most entity erased cells behaviour is collected to execute valid data Make, and reads the more data from at least two entities erased cell.

17. memorizer control circuit unit according to claim 11, which is characterized in that the memory management circuitry is also To receive more write instructions from the host system,

The wherein described more write instructions indicate respectively the storage more data one of to the logical address.

18. memorizer control circuit unit according to claim 10, which is characterized in that the institute of the corresponding more data State the reading frequency or correspondence that most characteristic parameters are the reading times of the corresponding more data, the corresponding more data The read access time interval of the more data.

19. a kind of memory storage apparatus, which is characterized in that including:

Connecting interface unit, to be connected to host system;

Reproducible nonvolatile memorizer module, wherein the reproducible nonvolatile memorizer module has majority real Body erased cell, each entity erased cell among the most entity erased cells have most entity programs Unit, most entity program units are at least divided into first instance programmed cell and second instance sequencing list Member, and be shorter than from the second instance programmed cell from the time for reading data in the first instance programmed cell Read the time of data;And

Memorizer control circuit unit is connected to the connecting interface unit and the reproducible nonvolatile memorizer module,

The wherein described memorizer control circuit unit corresponds to the majority characteristic parameters of more data and according to described to record Most characteristic parameters identify that the first data among the more data are often to read data, wherein the normal reading data The second data among the more data are more frequently read,

The wherein described memorizer control circuit unit is also erasing first Data programming to the most entities The first instance programmed cell of first instance erased cell among unit.

20. memory storage apparatus according to claim 19, which is characterized in that the memorizer control circuit unit is also According to the most characteristic parameters, to arrange the more data, to generate the write sequence of the corresponding more data; And according to said write sequence, by described the among the more Data programmings to the most entity erased cells In one entity erased cell.

21. memory storage apparatus according to claim 20, which is characterized in that the memorizer control circuit unit is also To configure most logical addresses to map at least part of most entity program units, wherein more stroke counts According to being respectively stored to one of most logical addresses logical address,

Wherein in the running of the most characteristic parameters of the corresponding more data of record, the memorizer control circuit Unit, which is established, reads count table, and the reading of each logical address among the logical address is recorded in the reading count table Take number, and will store the more data logical address reading times respectively as the corresponding more data The most characteristic parameters.

22. memory storage apparatus according to claim 21, which is characterized in that described according to the most features Parameter arranges the more data, in the running to generate the said write sequence of the corresponding more data, the memory Control circuit unit obtains the reading times for the logical address for storing the more data, and root from the reading count table According to the reading times for the logical address for storing the more data, arrangement stores the logical address of the more data to produce Raw said write sequence.

23. memory storage apparatus according to claim 19, which is characterized in that the memorizer control circuit unit is more To by the second instance program unit of second Data programming to the first instance erased cell,

24. memory storage apparatus according to claim 23, which is characterized in that the memorizer control circuit unit makes With single-layer memory cell pattern, in first Data programming to the first instance erased cell and multilayered memory will be used Unit mode, will be in second Data programming to the first instance erased cell.

25. memory storage apparatus according to claim 20, which is characterized in that the memorizer control circuit unit is also To choose at least two entity erased cells among the most entity erased cells behaviour is collected to execute valid data Make, and reads the more data from at least two entities erased cell.

26. memory storage apparatus according to claim 20, which is characterized in that the memorizer control circuit unit is also To receive more write instructions from the host system,

27. memory storage apparatus according to claim 19, which is characterized in that correspond to the described more of the more data Several characteristic parameters are described in the reading times of the correspondence more data, the reading frequency of the corresponding more data or correspondence The read access time interval of more data.