WO2003105155A1

WO2003105155A1 - Method and apparatus for improving the read access time in a non-volatile memory system

Info

Publication number: WO2003105155A1
Application number: PCT/US2003/005354
Authority: WO
Inventors: Alexander K. Mak; Long C. Pham; Stephen J. Gross; Edward P. Tuers; Khandker N. Quader
Original assignee: Sandisk Corporation
Priority date: 2002-06-06
Filing date: 2003-02-20
Publication date: 2003-12-18
Also published as: AU2003230560A1

Abstract

Methods and apparatus for reducing read access times associated with obtaining stored data from a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for providing data to a bus within a memory system that includes a storage area involves providing a first signal (REM) within the memory system and enabling an output buffer in response to the first signal. The first signal indicates that the data is to be provided to the bus from the storage area, and is of a first level which has a first duration. The output buffer provides the data from the storage area to the bus, and remains substantially enabled while the first signal is of the first level. In one embodiment, the method also includes providing a second signal (OE) as an input to the output buffer to enable the output buffer.

Description

METHOD AND APPARATUS FOR IMPROVING THE READ ACCESS TIME IN A NON-VOLATILE MEMORY SYSTEM

BACKGROUND OF THE INVENTION Field of Invention The present invention relates generally to mass digital data storage systems.

More particularly, the present invention relates to systems and methods for reducing the read access time associated with reading data out of a memory core within a nonvolatile memory system.

Description of the Related Art The use of non- volatile memory systems such as flash memory storage systems is increasing due to the compact physical size of such memory systems, and the ability for non-volatile memory to be repetitively reprogrammed. The compact physical size of flash memory storage systems facilitates the use of such storage systems in devices which are becoming increasingly prevalent. Devices which use flash memory storage systems include, but are not limited to, digital cameras, digital camcorders, digital music players, handheld personal computers, and global positioning devices. The ability to repetitively reprogram non-volatile memory included in flash memory storage systems enables flash memory storage systems to be used and reused. Data that is stored in a flash memory storage system or device, once programmed, may be read out of or retrieved from the device. Non-volatile memory, or core memory, in the flash memory storage device may be associated with components which are configured to read data from the core memory, and to provide the data to a bus that is accessible by external devices which use the flash memory device. Fig. la is a diagrammatic block diagram representation of system within a flash memory device which allows bits to be read out of the memory core of the flash memory core. A system 5 includes a memory core 10 that is generally arranged to store bits, and includes multiple storage elements. When a command is issued to read or obtain bits from core 10, core 10 is read and stored into latches 12. Latches 12, or data latches, generally serve to buffer data read from core 10. Typically, there is one latch for every bit that is read from core 10, e.g., there may be 535 latches included in latches 12. The bits are outputted from latches 12 onto a shared sensing amplifier bus 13, on a bit-by-bit basis. That is, only one bit may be located on sensing amplifier bus 13 at any given time.

A sensing amplifier (S/A) 14 senses the data on sensing amplifier bus 13, e.g., sensing amplifier 14 senses whether sensing amplifier bus 13 holds a value of "1" or a value of "0". Sensing amplifier bus 13 may generally include a DLO line and a

DLOn line. Sensing amplifier 14 obtains the data from sensing amplifier bus 13, and provides the data across a link 23 to transfer gates 16. As will be understood by those skilled in the art, transfer gates 16 may enable the data to be toggled out through an output buffer 20. Transfer gates 16, which will be discussed below in more detail with respect to Fig. lb, provide the data through a link 24 to internal buffers 18 which, in turn, pass the data through link 26 to an output buffer 20. Internal buffers 18 and output buffer 20 will be described below with respect to Fig. lc. Output buffer 20 drives the output, e.g., I/O 22, of the overall flash memory device. That is, output buffer 20 provides the data read from core 10 to input/output (I/O) bus 22. With reference to Fig. lb, transfer gates 16 of Fig. la will be described.

Transfer gates 16 include a pmos transfer gate 28a and an nmos transfer gate 28b. Gate 28a is arranged to enable data to pass through from link 23 to gate 28b when an input signal 27a into gate 28a is low, while gate 28b is arranged to enable data to pass through to link 24 when an input signal 27b into gate 28b is high. Although gates 28 generally toggle data such that a bit may be substantially held within either gate 28a or gate 28b for a duration, i.e., a bit may be delayed, it should be appreciated that in some instances, a bit may pass through gates 28 with substantially no delay.

As shown in Fig. lc, internal buffers 18 may include substantially any number of buffers. Internal buffers 18 effectively drive an input signal to output buffer 20. Output buffer 20 includes an inverter 29 which is enabled by an output enable (OE) 32. In effect, output buffer 20 drives an I/O pad.

Fig. 2 is a timing diagram which illustrates the signals associated with system 5 of Fig. la. Timing diagram 50 is arranged to show signals 52 which generally transition between high states and low states. In general, when a read command is issued to read data from a core, e.g., core 10 of Fig. 1, a read busy (R B) signal 52b is pulled low. Then, core 10 of Fig. 1 may be read into latches 12. When a read enable (RE) signal 52e goes high, RE signal 52e causes the inverse of the read enable signal, i.e., read enable inverse (REn) signal 52b, to go low. When REn signal 52b goes low, REn signal 52 may toggle OE signal 52f. Toggling OE signal 52f such that OE signal 52f is effectively pulled high allows OE signal 52f to drive output buffer 20 of Fig. la to output I/O signal 52g on I/O bus 22. As such, when REn signal 52b goes low, REn signal 52b essentially allows output buffer 20 to begin driving I/O bus 22.

Within system 5 of Fig. la, a read access time (tREA) is generally defined to be substantially equal to a time delay from the time REn signal 52b goes low and OE signal 52f going high, i.e., to turn on output buffer 20, summed with a time delay between output buffer 20 being turned on and output buffer 20 driving I/O bus 22. In other words, the read access time associated with system 5 is dependent upon a time delay associated with OE signal 52f going high and output buffer 20 beginning to drive I/O bus 22. It should be understood that once output buffer 20 is turned on, there is generally a lag before output buffer 20 drives I/O bus 22. As shown, tREA 60, which effectively remains constant throughout the operation of system 5 of Fig. la, is shown with respect to reading data bit N+2 from core 10. A start time 62 for measuring tREA 60 is associated with when REn signal 52b goes low, while an end time 62 for measuring tREA60 is associated with when OE signal 52f successfully causes output buffer 20 of Fig. la to drive I/O bus 22. tREA 60 may be measured substantially each time there is a drop in REn signal 52b, i.e., -REA60 may be measured starting each time REn signal 52b exhibits a falling edge. By way of example, an alternate read access time 64, which typically has substantially the same value as tREA 60, may be measured with respect to the read access time associated with reading data bit N+1. Each time RE signal 52e goes high and REn signal 52d goes low, a read command is generally being processed. The processing of a read command results in OE signal 52f going high then, once a bit is read, OE signal 52f goes low. As such, each time a read command is processed, tREA 60 is made up of delays associated with REn signal 52b going low and OE signal 52f turning on output buffer 20 of Fig. la.

A second read enable inverse (REndl) signal 52d is arranged as an input signal for transfer gate 28b of Fig. lb, while a REndO signal 52c, which is associated with signals 52h-j that open latches 12 of Fig. la to sensing amplifier 14, is arranged as an input signal for transfer gate 28a. REndl signal 52d and REndO signal 52c cooperate to allow data to pass from sensing amplifier 14 of Fig. la to buffers 18. The value of tREA 60 is generally relatively high, e.g., on the order of approximately 35 nanoseconds (ns). A significant portion of tREA 60 is attributable to the time required to drive I/O bus 22 of Fig. la once output buffer 20 or, more specifically, inverter 29 of output buffer 20, is turned on. When tREA 60 is relatively high, the performance of an overall memory system may be affected. For example, reading commands may be executed less efficiently than desired, thereby causing the overall memory system of operate less efficiently.

Since tREA 60 is on the order of approximately 35 ns, the low time associated with REn signal 52b has a duration of approximately 35 ns. A low time for REn signal 52b is indicated at 66. Typically, a high time for REn signal 52b, which is indicated at 68, as well as a high time for other signals, is expected to be less than approximately 15 ns for performance reasons. As such, since output is only driven onto I/O bus 22 of Fig. la when REn signal 52b is low, and the delay to drive I/O bus 22 may be substantial, the duty cycle of REn signal 52b is not fifty percent, when a high time of approximately 15 ns or less is expected. To create a fifty percent duty cycle for REn signal 53b, high time as indicated at 68 may be increased to approximately 35 ns, thereby significantly increasing the duration of an overall read process. Increasing the duration of an overall read process and, hence, increasing an overall stream read time, generally results in a compromise in performance levels. A fifty percent duty cycle clock is generally easier for a system to create than a non-fifty percent duty cycle clock. In other words, if a fifty percent duty cycle is created, the system does not need to be concerned with making a low time longer than a high time. Some systems may use delay elements such as RC delays to make a non- fifty percent duty cycle. However, these delay elements are relatively susceptible to noise, power supply, and temperature variations. As a result, the high and low times of the clock may vary and are hard to control. Alternatively, a relatively simple ring oscillator may achieve a fifty percent duty cycle clock relatively easily. There are systems that are unable to create a non-fifty percent duty cycle clock and, therefore, use the worst case cycle time which may be approximately 70 nanoseconds (ns), e.g., 35ns high and 35ns(low), in length as compared to a cycle time of approximately 50 ns, e.g., 15 ns high and 35 ns low. As such, there is a relatively significant performance impact.

Therefore, what is desired is a system which increases the speed at which data may be read from a memory core of a non-volatile memory system. Specifically, what is needed is a system and a method which reduces delays associated with read access times while allowing duty cycles associated with read enable signals to be improved. SUMMARY OF THE INVENTION The present invention relates to a system and a method for reducing read access times associated with obtaining stored data from a non-volatile memory system. According to one aspect of the present invention, a method for providing data to a bus within a memory system that includes a storage area involves providing a first signal within the memory system and enabling an output buffer in response to the first signal. The first signal indicates that the data is to be provided to the bus from the storage area, and is of a first level which has a first duration. The output buffer being provides the data from the storage area to the bus, and remains substantially enabled while the first signal is of the first level. In one embodiment, the method also includes providing a second signal as an input to the output buffer to enable the output buffer. The second signal substantially maintains a second level while the first signal is of the first level, thereby causing the output buffer to remain enabled.

In another embodiment, the data includes a first bit and a second bit, and the method further includes obtaining a request to provide the first bit and the second bit to the bus. The first signal is provided in response to the request. In such an embodiment, a read access time associated with providing the first bit to the bus is greater than a read access time associated with providing the second bit to the bus. By enabling an output buffer associated with a read system of a non- volatile memory device to remain on once it is effectively turned on, delays associated with turning on the output buffer in response to processing each bit that is being read may be substantially eliminated. Hence, the time required to read the data or, more specifically, the read access time associated with the read system may be reduced. As a result, the read process may occur more efficiently, and the performance of the overall memory device may be enhanced.

According to another aspect of the present invention, a memory device for storing information includes a memory core, a latch mechanism, and an output buffer. The memory core stores a first bit and a second bit, and the latch mechanism retrieves the first bit and the second bit in response to a first signal which has a first value and a first duration. The output buffer is enabled in response to the first signal, and receives the first bit and the second bit sequentially from the latch mechanism when enabled. In general, the output buffer remains substantially enabled for approximately the first duration.

In one embodiment, the first duration substantially encompasses a time associated with the output buffer receiving the first bit and the second bit. In another embodiment, the memory device includes a master/slave latch. The master/slave latch receives the first bit and the second bit from the latch mechanism, and pipelines the first bit and the second bit into the output buffer.

According to still another aspect of the present invention, a memory system, includes a core that stores a first bit and a second bit, and a plurality of latches that load the first bit from the core and the second bit from the core. The memory system also includes a sensing amplifier that retrieves the first bit and the second bit, as well as a toggling mechanism that retrieves the first bit and the second bit from the sensing amplifier and passes the first bit and the second bit through the toggling mechanism. A buffer arrangement of the memory system retrieves the first bit and the second bit from the toggling mechanism, and an output buffer retrieves the first bit and the second bit from the toggling mechanism. The output buffer process the first bit and the second bit, and also provides the first bit and the second bit as an output. The output buffer is further enabled in response to a command to read the first bit and the second bit, and remains enabled while the first bit and the second bit are processed. In one embodiment, the memory system may include a pipelining mechanism that pipelines the first bit and the second bit from the buffer arrangement to the output buffer.

These and other advantages of the present invention will become apparent upon reading the following detailed descriptions and studying the various figures of the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The invention may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which: Fig. 1 a is a diagrammatic block diagram representation of system within a flash memory device which allows bits to be read out of the memory core of the flash memory core.

Fig. lb is a diagrammatic representation of transfer gates, i.e., transfer gates 16 of Fig. la, which are a part of a flash memory device. Fig. lc is a diagrammatic representation of internal buffers and an output buffer, i.e., internal buffers 18 and output buffer 20 of Fig. la, which are a part of a flash memory device.

Fig. 2 is a timing diagram which illustrates the signals associated with a reading system associated with a memory device, i.e., reading system 5 of Fig. la. Fig. 3a is a diagrammatic representation of a general host system which includes a non- volatile memory device in accordance with an embodiment of the present invention.

Fig. 3b is a diagrammatic representation of a non-volatile memory device, i.e., non- volatile memory device 120 of Fig. 3a, in accordance with an embodiment of the present invention.

Fig. 4 is a timing diagram which illustrates the signals associated with a reading system associated with a memory device, i.e., reading system 5 of Fig. la, in accordance with an embodiment of the present invention. Fig. 5 is a diagrammatic representation of a reading system which includes pipelining capabilities in a non- volatile memory device in accordance with an embodiment of the present invention.

Fig. 6 is a diagrammatic representation of a master/slave latch, i.e., master/slave latch 530 of Fig. 5, in accordance with an embodiment of the present invention.

Fig. 7 is a timing diagram which illustrates the signals associated with a reading system that is associated with a memory device and included pipelining functionality , i.e., reading system 502 of Fig. 5, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Within a non-volatile memory device such as a flash memory system, when data is to be read out of the device, the efficiency with which the data is read is dependent upon a read access time (tREA). Improving the efficiency with which the data is read from the device generally serves to improve the overall performance of the device.

The tREA may be generally defined to be the difference between delays associated with logic associated with the device, e.g., delays associated with initiating an output buffer to drive an input/output (I/O) bus, and the amount of time an inverse read enable (REn) signal associated with the device remains high. Typically, the value of the tREA is on the order of approximately 35 nanoseconds (ns). A substantial percentage of the tREA is associated with the time required for an output buffer to drive an I/O bus once the output buffer is enabled. That is, the process of "warming up" an output buffer accounts for a significant percentage of the tREA. By substantially eliminating the time required for an output buffer to drive an I/O bus once the output buffer is enable, tREA may be reduced and, as a result, the efficiency with which data is read from a memory device may be improved. That is, by substantially eliminating the need to enable the output buffer each time a bit is to be read, tREA may be reduced. In one embodiment, the output buffer may be enabled in response to a first bit being read, and remain enabled such that the output buffer is effectively already enabled while subsequent bits are read. As such, the first instance of tREA which corresponds to the read access time for the first bit may be higher than substantially all subsequent instances of tREA. Reducing substantially all instances of tREA allows an overall read process to be more efficient and, as a result enables the duty cycle for REn to be closer to approximately fifty percent.

Typically, data is read out of a core of a non-volatile memory device in response to a command from a host system which wishes to obtain the data. Referring to Fig. 3a, a general host system which includes a non-volatile memory device, e.g., a CompactFlash memory card, will be described. A host or computer system 100 generally includes a system bus 104 which allows a microprocessor 108, a random access memory (RAM) 112, and input/output circuits 116 to communicate. It should be appreciated that host system 100 may generally include other components, e.g., display devices and networking device, which are not shown for purposes of illustration.

In general, host system 100 may be capable of capturing information including, but not limited to, still image information, audio information, and video image information. Such information may be captured in real-time, and may be transmitted to host system 100 in a wireless manner. While host system 100 may be substantially any system, host system 100 is typically a system such as a digital camera, a video camera, a cellular communications device, an audio player, or a video player. It should be appreciated, however, that host system 100 may generally be substantially any system which stores data or information, and retrieves data or information. Host system 100 may also be a system which either only captures data, or only retrieves data. That is, host system 100 may be a dedicated system which stores data, or host system 100 may be a dedicated system which reads data. By way of example, host system 100 may be a memory writer which is arranged only to write or store data. Alternatively, host system 100 may be a device such as an MP3 player which is typically arranged to read or retrieve data, and not to capture data. A non- volatile memory device 120 which, in one embodiment, is a removable non- volatile memory device, is arranged to interface with bus 104 to store information. An optional input/output circuit block 130 may allow non- volatile memory device 120 to interface with indirectly with bus 104. When present, such an input/output circuit block interface 130 serves to reduce loading on bus 104, as will be understood by those skilled in the art. Non-volatile memory device 120 includes nonvolatile memory 124 and a memory control system 128. In one embodiment, nonvolatile memory device 120 may be implemented on a single chip or a die. Alternatively, non-volatile memory device 120 may be implemented on a multi-chip module, or on multiple discrete components which may be used together as nonvolatile memory device 120.

Non-volatile memory 124, or core, is arranged to store data such that data may be accessed and read as needed. Data stored in non- volatile memory 124 may also be erased as appropriate, although it should be understood that some data in non-volatile memory 124 may not be erased. The processes of storing data, reading data, and erasing data are generally controlled by memory control system 128. In one embodiment, memory control system 128 manages the operation of non-volatile memory 124 such that the lifetime of non- volatile memory 124 is substantially maximized by essentially causing sections of non-volatile memory 124 to be worn out substantially equally.

While non- volatile memory device 120 has generally been described as including a memory control system 128, t.e., a controller, it should be understood that not all non- volatile memory devices include a controller. By way of example, while non-volatile memory devices including, but not limited to, PC cards, CompactFlash cards, MultiMedia cards, and secure digital cards include controllers, other nonvolatile memory devices including, but not limited to, Smart Media cards and Memory Stick cards may not include controllers. In an embodiment in which nonvolatile memory device 124 does not include a controller, the functions associated with the controller may be integrated into a single chip, as will be appreciated by those skilled in the art. It should be understood that non- volatile memory device 120 may generally be implemented as either a single-chip device or a multi-chip module.

Sensing components 132 are included in non- volatile memory device 120 may be used to read data from non- volatile memory 124. Sensing components 132 may generally include, but are not limited to, latches, transfer gates, buffers, and sensing amplifiers such as those described previously with respect to Fig. la. In one embodiment, memory control system 128 may provide signals, e.g., a read enable (RE) signal or an output enable (OE) signal, which may be used to cause sensing components 132 to perform various actions.

With reference to Fig. 3b, non-volatile memory device 120 will be described in more detail in accordance with an embodiment of the present invention. As described above, non-volatile memory device 120 includes non- volatile memory 124 and memory control system 128. Memory 124 and control system 128, or controller, are primary components of non- volatile memory device 120. Memory 124 may be an array of memory cells formed on a semiconductor substrate, wherein one or more bits of data are stored in the individual memory cells by storing one of two or more levels of charge on individual storage elements of the memory cells. A non- volatile flash electrically erasable programmable read only memory (EEPROM) is an example of a common type of memory for such systems.

Control system 128 communicates over a bus 15 to a host computer or other system that is using the memory system to store data. Bus 15 is generally a part of bus 104 of Fig. 3a. Control system 128 also controls operation of memory 124, which may include a memory cell array 11 , to write data provided by the host, read data requested by the host and perform various housekeeping functions in operating memory 124. Control system 128 generally includes a general-purpose microprocessor which has associated non-volatile software memory, various logic circuits, and the like. One or more state machines are often also included for controlling the performance of specific routines.

Memory cell array 11 is typically addressed by control system 128 through address decoders 17, which may be included in sensing components 132 of Fig. 3a. Decoders 17 apply the correct voltages to gate and bit lines of array 11 in order to program data to, read data from, or erase a group of memory cells being addressed by the control system 128. Additional circuits 19, which may also be included in sensing components 132, include programming drivers that control voltages applied to elements of the array that depend upon the data being programmed into an addressed group of cells. Circuits 19 also include sense amplifiers and other circuits necessary to read data from an addressed group of memory cells. Data to be programmed into array 11, or data recently read from array 11, are typically stored in a buffer memory 21 within control system 128. Control system 128 also usually contains various registers for temporarily storing command and status data, and the like. Array 11 is divided into a large number of BLOCKS 0 - N of memory cells. As is common for flash EEPROM systems, the block is the unit of erase. That is, each block contains the minimum number of memory cells that are erased together. Each block is typically divided into a number of pages, as also illustrated in Fig. 3a. A page is the unit of programming. That is, a basic programming operation writes data into a minimum of one page of cells. One or more sectors of data are typically stored within each page. As shown in Fig. 3b, one sector includes user data and overhead data. Overhead data typically includes an error correction code (ECC) that has been calculated from the user data of the sector. A portion 71 of the control system 128 calculates the ECC when data is being programmed into array 11, and also checks the ECC when data is being read from array 11. Alternatively, the ECCs are stored in different pages, or different blocks, than the user data to which they pertain.

A sector of user data is typically 512 bytes, corresponding to the size of a sector in magnetic disk drives. Overhead data is typically an additional 28 bytes. One sector of data is most commonly included in each page but two or more sectors may instead form a page. A large number of pages form a block, anywhere from eight pages, for example, up to 512, 1024 or more pages. The number of blocks is chosen to provide a desired data storage capacity for the memory system. Array 11 is typically divided into a few sub-arrays (not shown), each of which contains a proportion of the blocks, which operate somewhat independently of each other in order to increase the degree of parallelism in the execution of various memory operations. An example of the use of multiple sub-arrays is described in U.S. Patent No. 5,890,192, which is incorporated herein by reference in its entirety. Reducing the time associated with retrieving bits from non-volatile memory core 124 enables the efficiency with which data may be obtained from non-volatile memory device 120 to be increased. As mentioned above, enabling an output buffer, e.g., output buffer 20 of Fig. la, in response to reading a first bit and allowing the output buffer to remain enabled when subsequent bits are read typically reduces the tREA associated with non- volatile memory device 120. Specifically, aside from the tREA associated with reading the first bit, the tREA associated with reading each subsequent bit is reduced.

Fig. 4 is a timing diagram which illustrates the signals associated with a reading system associated with a memory device, i.e., reading system 5 of Fig. la, in accordance with an embodiment of the present invention. A timing diagram 404 includes representations of signals associated with the operation of a reading system. A tREA 406 that is associated with reading a first bit is generally defined to be substantially equal to a time delay from the time a REn signal 408 goes low and a OE signal 412 goes high, i.e., to turn on output buffer 20 of Fig. la, added to a time delay between output buffer 20 being turned on and output buffer 20 driving I/O bus 22 with respect to a first bit. As shown, tREA 406 is shown with respect to reading data bit N from core 10 of Fig. la.

In general, the tREA associated with system 5 of Fig. la may affect an overall cycle time. A low time associated with REn (tREL), which may affected by the tREA associated with system 5, and a high time associated with REn (tREH) generally make up the overall cycle time. To provide a performance improvement, the tREA may be reduced such that system 5, in one embodiment, may operate at a cycle time of approximately 40 ns, e.g., 20 ns high and 20 ns low, or better. In one embodiment, a tREA may generally be based upon a difference between tREH 414, tREL 415, and a substantially component-dictated delay.

To reduce the tREA associated with reading substantially all bits with the exception of bit N, OE signal 412 remains high once OE signal 412 transitions from low to high in response to a command to read the first bit. In other words, OE signal 412 is generally independent of REn signal 408 after the first bit is read. Allowing OE signal 412 to remain high enables output buffer 20, as shown in Fig. lc, to remain enabled and, hence, ready to drive input/output (I/O) bus 22. As such, the tREA associated with reading bits other than bit N, as for example a tREA 416, essentially does not depend on a delay between enabling output buffer 20 and driving I/O bus 22. In the described embodiment, i.e., an embodiment in which OE signal 412 remains high once OE signal 412 is enabled and a read busy (R/B) signal 418 remains high, tREA 416 and subsequent tREAs are dependent upon time delays associated with components of system 5 of Fig. la, as previously mentioned. Specifically, tREA 416 is partially dependent upon the delay (tdl) measured from when REn signal 408 goes high, i.e., a rising edge of REn signal 408, and data being sensed on sensing amplifier bus 13 of Fig. la. Such a delay is indicated, for example, at 417. -REA 416 is also dependent upon a delay (td2) associated with data passing through internal buffers 18 of Fig. la and a delay (td3) associated with data passing through output buffer 20. In other words, tREA 416 may be expressed as follows:

tREA = tdl + td2 + td3 - tREL - tREH Of the delays which essentially make up tREA 416, the most significant "sub- delay" is associated with output buffer 20 of Fig. la. That is, the delay through output buffer 20 of Fig. la is generally more time consuming than both the delay measured from when REn signal 408 goes high until data is sensed on sensing amplifier bus 13, and the delay associated with the data passing through internal buffers 18.

It should be appreciated that the delay measured from when REn signal 408 goes high until data is sensed on sensing amplifier bus 13 of Fig. la may increase as a falling edge of REn signal 408 moves closer to a rising edge of REn signal 408. Specifically, if tREL is considered to be too short, the delay to output bits onto sensing amplifier bus 13 of Fig. la may increase since the falling edge of REn signal 408 generally toggles latches by causing latch toggling (DL) signals 420 to go high. By way of example, falling edge 424 of REn signal 408 causes DL signal 420b that is associated with a latch that reads in bit N+1 (DL N+1) to be toggled out of the latch, or otherwise opened to sensing amplifier 14 of Fig. la. When tREL for bit N+1 is short and tREH remains relatively high, then the sense output time relative to the falling edge of REn signal 408 that is associated with bit N+2 may increase. As a result, tREA 416 may increase.

Reducing tREA 416 and subsequent tREAs, in addition to increasing the efficiency of a read operation, also allows the duty cycle of REn signal 416 to be set at closer to approximately fifty percent. That is, the low time of REn signal 416 may be shortened after a first bit is read such that the low time of REn signal 416 is closer to the high time of REn signal 416, i.e., so that there is less of a difference between the amount of time REn signal 416 spends at a low value and the amount of time REn signal 416 spends at a high value. In order to further reduce tREA 416 and subsequent tREAs, a master/slave latch may be added to a system such as system 5 of Fig. la to pipeline bits that are being provided to an output buffer. Pipelining the bits allows the delay associated with data passing through the output buffer to be reduced, as when a one bit is being passed through the output buffer, a subsequent bit is held within the master-slave latch. With reference to Fig. 5, a reading system in a non-volatile memory device which includes pipelining capabilities will be described in accordance with an embodiment of the present invention. A reading system 506 includes a core 506 in which bits of data may be stored. Core 506, which may be a non-volatile memory storage area, may include storage elements which store bits of data. When a read command is received by the non- volatile memory device with which reading system 506 is associated, bits are loaded into latches 510. Latches then, in response to DL signals such as DL signals 420 of Fig. 4, load bits on a bit-by-bit basis onto a sensing amplifier bus 514.

A sense or sensing amplifier 518 receives bits through sensing amplifier bus 514, and provides them to transfer gates 522. Transfer gates 522, like transfer gates 16 of Figs, la-b, generally include an nmos transfer gate in series with a pmos transfer gate. Transfer gates 522 toggle bits, and provide the bits to internal buffers 526. In one embodiment, internal buffers 526 may be tristate buffers. Internal buffers 528 provide the bits to a master/slave latch 530 through a link 528. Master/slave latch 530, which will be discussed below with respect to Fig. 6, pipelines bits acquired through link 528, and outputs the bits onto a link 532 to an output buffer 534 which drives an I/O bus 536.

Master/slave latch 530 is effectively a pipelining latch in the read path of system 502. As shown in Fig. 6, master/slave latch 530 may include two transfer gates 604 which are each enabled by the same signal, e.g., a "REndl" signal which is effectively a shifted version of an REn signal. Master/slave latch 530 function such that when the REndl signal goes low, data passed from link 528 through transfer gate 604a to a link 608. Then, when the REndl signal transitions from low to high, the data passes from link 608 through transfer gate 604b to link 532. Unlike transfer gates 522 of Fig. 5, a bit may not pass directly through master/slave latch 530, since both transfer gates 604 included in master/slave latch 530 operate using the same enabling signal, as will be understood by those skilled in the art.

Pipelining is accomplished by master/slave latch 530 when one bit is being clocked out of master/slave latch 530 while a subsequent bit is being clocked in. Specifically, when a first bit is being clocked out through transfer gate 604b, a subsequent bit may be loaded on link 528 waiting to be clocked into transfer gate 604a. As such, the bits are pipelined such that while output buffer 534 of Fig. 5 is processing the first bit, the subsequent bit may be held in master/slave latch 530 such that as soon as the first bit is provided to I/O bus 536, the subsequent bit may be provided to output buffer 534. Such pipelining enables the delay time associated with data passing through output buffer 534 to be reduced, thereby reducing the tREA associated with system 502 after the first bit is read.

Within system 502, when a first bit is to be read out of a latch included in latches 510, an OE signal which enables output buffer 534 to drive I/O bus 536 transitions from a low value to a high value. Once output buffer 534 is enabled, output buffer 534 remains enabled, i.e., the OE signal remains high until all bits are obtained from latches 510. Hence, bits may pass from master/slave latch 530 through buffer 534 and onto I/O bus 536 without being delayed while output buffer 534 is in the process of being enabled. Fig. 7 is a timing diagram which illustrates the signals associated with a reading system that is associated with a memory device and included pipelining functionality, i.e., reading system 502 of Fig. 5, in accordance with an embodiment of the present invention. A timing diagram 702 includes an OE signal 706 which transitions from a low value to a high value in response to reading a first bit. More specifically, OE signal 706 goes high when an R B signal 710 goes high to initiate reading bits using reading system 502 of Fig. 5. R/B signal 710 remains high until substantially all bits are read. Hence, OE signal 706 also remains high until substantially all bits are read. An REndl signal 722 is arranged to toggle master/slave latch 530 of Figs. 5 and 6 to pipeline bits into output buffer 534. The tREAs associated with system 502 of Fig. 5 which includes pipelining capabilities and an output buffer that is substantially always enabled are generally lower than the tREAs associated with a system in which the output buffer is substantially always enabled but does not include pipelining capabilities. For example, when a read path is pipelined, tREAs generally are not affected by a delay that occurs between the time when an REn signal has a rising edge and the time when data is sensed on a sensing amplifier bus, as will be appreciated by those skilled in the art. That is, the delay between reading data out of latches 510 of Fig. 5 and the data being provided to link 528 may be substantially masked. More specifically, delays for tREAs, that may be attributed to tdl, td2, tREL, and td3, which were described above with respect to Fig. 4, may effectively be absorbed by previous cycles associated with REn signal 726.

Once OE signal 706 is high, the overall tREA associated with system 502 of Fig. 5 is dependent substantially only upon the amount of time REn signal 726 stays high, or tREH 730, a delay (td4) associated with data passing through output buffer 534, and a delay (td5) from a rising edge of REn signal 726 to REndl signal 722 going high. That is, the overall tREA for system 502 of Fig. 5 may be expressed as follows:

tREA = td4 + td5 - tREH More generally, as discussed above, tREA is the difference between the time delays associated with components of a read system such as system 502 of Fig. 5 and tREH. The overall tREA is shown at 734. It should be understood that the tREA associated with reading a first bit is substantially higher than overall tREA 734, as the tREA associated with reading the first bit includes a delay associated with OE signal 706 initially transitioning from a low value to a high value and output buffer 534 of Fig. 5 driving I/O bus 536.

The delay from a rising edge of REn signal 726 to RENdl signal 722 going high may be considered to be the delay associated with providing a bit from second transfer gate 604b of Fig. 6 to output buffer 534 of Fig. 5. Hence, in terms of time delays that may be attributed to components of system 502 of Fig. 5, the overall tREA of system 502 may be considered to be dependent upon substantially only the delay associated with second transfer gate 604b of Fig. 6 and the delay associated with data passing through output buffer 534. Since the overall tREA of a pipelined read system is reduced, the duty cycle associated with the pipelined system may be set to be approximately a fifty percent duty cycle. In general, reducing the overall tREA improves the read process and, hence, improves the overall efficiency associated with a non-volatile memory system which includes a pipelined read system. Although only a few embodiments of the present invention have been described, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit or the scope of the present invention. By way of example, while the use of an output buffer that remains enabled after it is initially enabled may improve read systems associated with non-volatile memory systems, an output buffer that remains enabled while an R/B signal remains high may be implemented with respect to a substantially any suitable memory system. Such suitable memory systems may include, but are not limited to, volatile memory systems and mass storage devices.

An output buffer has generally been described as being enabled and remaining enabled when an OE signal, e.g., OE signal 412 of Fig. 4, has a high value, it should be appreciated that in some embodiment, an output buffer may be arranged to be enabled when the OE signal has a low value. In addition, while an OE signal is shown as transitioning from a low value to a high value substantially in response to an R B signal, e.g., R B signal 418 of Fig. 4, transitioning from a low value to a high value, the OE signal may be arranged to be substantially always enabled. That is, OE signal may always have a high value, even when an associated R B signal has a low value without departing from the spirit or the scope of the present invention.

While a latch that pipelines data that is being read out of a core has been described as being composed of transfer gates, it should be appreciated that such a latch may be substantially any suitable latch. Further, in lieu of using latches, any components which are suitable for enabling data to be pipelined may be used instead of a latch.

In general, the configuration of read systems may vary. For instance, the number of latches associated with a read system may vary, and the number of tristate buffers and transfer gates may also vary without departing from the spirit or the scope of the present invention. Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method for providing data to a bus within a memory system, the memory system including a storage area, the method comprising: providing a first signal within the memory system, the first signal being arranged to indicate that the data is to be provided to the bus from the storage area, wherein the first signal is of a first level which has a first duration; and enabling an output buffer in response to the first signal, the output buffer being arranged to provide the data from the storage area to the bus, wherein the output buffer remains substantially enabled while the first signal is of the first level.

2. The method of claim 1 further including: providing a second signal as an input to the output buffer to enable the output buffer, the second signal being arranged to substantially maintain a second level while the first signal is of the first level.

3. The method of claim 2 wherein the first level and the second level are a high level.

4. The method of claim 2 wherein the first signal is a read-busy signal and the second signal is an output-enable signal.

5. The method of claim 1 wherein the data includes a first bit and a second bit and the method further includes: obtaining a request to provide the first bit and the second bit to the bus, wherein the first signal is provided in response to the request.

6. The method of claim 5 wherein a read access time associated with providing the first bit to the bus is greater than a read access time associated with providing the second bit to the bus.

7. The method of claim 6 wherein the read access time associated with providing the first bit to the bus includes a delay associated with enabling the output buffer.

8. The method of claim 7 wherein the read access time associated with providing the second bit to the bus does not includes the delay associated with enabling the output buffer.

9. The method of claim 5 wherein the memory system includes a pipelining enabler, the method further including: pipelining the first bit and the second bit through the pipelining enabler to the output buffer.

10. The method of claim 1 wherein the memory system is a non- volatile memory system.

11. A memory system comprising: a storage area, the storage area being arranged to store data; an output buffer, the output buffer being arranged to receive data from the storage area; a bus, the bus being arranged to be driven by the output buffer; means for providing a first signal within the memory system, the first signal being arranged to indicate that the data is to be provided to the bus from the storage area, wherein the first signal is of a first level which has a first duration; and means for enabling the output buffer in response to the first signal, the output buffer being arranged to provide the data from the storage area to the bus, wherein the output buffer remains substantially enabled while the first signal is of the first value.

12. The memory system of claim 11 further including: means for providing a second signal as an input to the output buffer to enable the output buffer, the second signal being arranged to substantially maintain a second level while the first signal is of the first level.

13. The memory system of claim 12 wherein the first level and the second level are a high level.

14. The memory system of claim 11 wherein the data includes a first bit and a second bit, the memory system further including: means for obtaining a request to provide the first bit and the second bit to the bus, wherein the means for providing the first signal are arranged to provide the first signal in response to the request.

15. The memory system of claim 14 wherein a read access time associated with providing the first bit to the bus is greater than a read access time associated with providing the second bit to the bus.

16. The memory system of claim 15 further includes: means for pipelining the first bit and the second bit from the storage area to the output buffer.

17. The memory system of claim 11 wherein the memory system is a non- volatile memory system.

18. The memory system of claim 17 wherein the memory system is a card selected from the group consisting of a PC card, a CompactFlash card, a MultiMedia card, a secure digital card, a Memory Stick card, and a Smart Media card.

19. A memory device for storing information, the memory device comprising: a memory core, the memory core being arranged to store a first bit and a second bit; a latch mechanism, the latch mechanism being arranged to retrieve the first bit and the second bit in response to a first signal, the first signal having a first value and a first duration; and an output buffer, the output buffer being arranged to be enabled in response to the first signal, the output buffer being arranged to receive the first bit and the second bit sequentially from the latch mechanism when enabled, wherein the output buffer remains substantially enabled for approximately the first duration.

20. The memory device of claim 19 wherein the first duration substantially encompasses a time associated with the output buffer receiving the first bit and the second bit.

21. The memory device of claim 19 further including: a bus, the bus being arranged to be driven by the output buffer.

22. The memory device of claim 19 further including a master/slave latch, the master/slave latch being arranged to receive the first bit and the second bit from the latch mechanism, the master/slave latch further being arranged to pipeline the first bit and the second bit into the output buffer.

23. The memory device of claim 19 further including a master/slave latch, the master/slave latch being arranged to pipeline the first bit and the second bit into the output buffer.

24. The memory device of claim 19 further including: a controller, the controller being arranged to provide the first signal.

25. The memory device of claim 19 wherein the memory core includes non-volatile storage elements.

26. The memory device of claim 25 wherein the memory device is a nonvolatile memory system.

27. The memory device of claim 26 wherein the memory device is one selected from the group consisting of a single chip device, a multi-chip device, a PC card, a CompactFlash card, a MultiMedia card, a secure digital card, a Memory Stick card, and a Smart Media card.

28. A computing system, comprising: a host; and a memory device, the memory device being in communication with the host, the memory device being arranged to receive a command from the host, the memory device including a memory core, the memory core being arranged to store a first bit and a second bit, a latch mechanism, the latch mechanism being arranged to retrieve the first bit and the second bit in response to a first signal, the first signal having a first value and a first duration, the first signal being arranged to be generated in response to the command, and an output buffer, the output buffer being arranged to be enabled in response to the first signal, the output buffer being arranged to receive the first bit and the second bit sequentially from the latch mechanism when enabled, wherein the output buffer remains substantially enabled for approximately the first duration.

29. The computing system of claim 28 wherein the first duration substantially encompasses a time associated with the output buffer receiving the first bit and the second bit.

30. The computing system of claim 28 wherein the memory device further includes a bus, the bus being arranged to be driven by the output buffer, the bus being further arranged to enable the host to communicate with the memory device.

31. The computing system of claim 28 wherein the memory device further includes a master/slave latch, the master/slave latch being arranged to receive the first bit and the second bit from the latch mechanism, the master/slave latch further being arranged to pipeline the first bit and the second bit into the output buffer.

32. The computing system of claim 28 wherein the memory core includes non-volatile storage elements.

33. The computing system of claim 32 wherein the memory device is a non- volatile memory system.

34. The computing system of claim 33 wherein the memory device is a card selected from the group consisting of a PC card, a CompactFlash card, a MultiMedia card, a secure digital card, a Memory Stick card, and a Smart Media card.

35. The computing system of claim 28 wherein the host is arranged to capture the information and to provide the information to the memory device.

36. The computing system of claim 35 wherein the host is one selected from the group consisting of a digital camera, a video camera, a cellular telephone, a communications device, an audio player, and a video player.

37. The computing system of claim 28 wherein the memory device is removably coupled to the host.

38. A memory system, comprising: a core, the core being arranged to store a first bit and a second bit; a plurality of latches, the plurality of latches including a first latch and a second latch, wherein the first latch is arranged to load the first bit from the core and the second latch is arranged to load the second bit from the core; a bus; an output buffer, the first latch being arranged to provide the first bit to the output buffer, the second latch being arranged to provide the second bit to the output buffer, the output buffer being arranged to drive the bus when the output buffer is on to provide the first bit and the second bit on the bus, wherein the output buffer is turned on in response to a command to provide the first bit on the bus and the output buffer remains on after the command to provide the first bit; and a signal, the signal having a transition between a low value and a high value, wherein the second bit is provided as an input to the output buffer before the transition.

39. The memory system of claim 38 wherein the output buffer remains on between the first bit being provided to the output buffer and the second bit being provided to the output buffer.

40. The memory system of claim 39 wherein the output buffer remains on while the output buffer provides the second bit on the bus.

41. The memory system of claim 38 wherein the signal is a read enable signal.

42. The memory system of claim 38 wherein the signal is an inverse read enable signal.

43. A memory system, comprising: a core, the core being arranged to store a first bit and a second bit; a plurality of latches, the plurality of latches being arranged to load the first bit from the core and the second bit from the core; a sensing amplifier, the sensing amplifier being arranged to retrieve the first bit and the second bit, the sensing amplifier further being arranged to process the first bit and the second bit; a toggling mechanism, the toggling mechanism being arranged to retrieve the first bit and the second bit from the sensing amplifier and to toggle the first bit and the second bit through the toggling mechanism; a buffer arrangement, the buffer arrangement being arranged to retrieve the first bit and the second bit from the toggling mechanism; and an output buffer, the output buffer being arranged to retrieve the first bit and the second bit from the toggling mechanism and to process the first bit and the second bit, the output buffer further being arranged to provide the first bit and the second bit as an output of the output buffer, the output buffer being enabled in response to a command to read the first bit and the second bit, wherein the output buffer remains enabled while the first bit and the second bit are processed.

44. The memory system of claim 43 further including: a pipelining mechanism, the pipelining mechanism being arranged to pipeline the first bit and the second bit from the buffer arrangement to the output buffer.

45. A read system, the read system being included in a memory system, the memory system comprising: means for storing a first bit and a second bit; means for retrieving the first bit and the second bit from the means for storing the first bit and the second bit; means for providing the first bit and the second bit as an output of the read system; means for driving the means for providing the first bit and the second bit as the output of the read system; and means for enabling the driving means such that the means for driving are substantially always enabled to drive the means for providing the first bit and the second bit as the output of the read system.

46. The read system of claim 45 further including: means for pipelining the first bit and the second bit, wherein the means for pipelining are arranged to substantially pipeline the first bit and the second bit from the means for retrieving to the means for driving.