JP2013201405A - Nonvolatile memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable nonvolatile memory device.SOLUTION: The nonvolatile memory device of an embodiment includes: a first wiring layer; a second wiring layer intersecting the first wiring layer; and a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect each other. The first memory layer is in contact with the first wiring layer, and the first wiring layer is capable of supplying metal ions to the first memory layer.

Description

  Embodiments described herein relate generally to a nonvolatile memory device.

  Conventionally, a NAND flash memory has been often used as a large-capacity nonvolatile storage device. However, with the miniaturization of elements, the physical limit is approaching, and recently, new memories such as a ferroelectric memory, a magnetoresistive memory, a phase change memory, and a resistance change memory have been developed. In particular, an ion memory, which is a kind of CBRAM (Conductive Bridging Random Access Memory), has attracted attention as one of resistance variable type memories.

  A memory cell of an ion memory usually has a rewritable storage layer (Rewritable layer), a metal ion supply layer for introducing metal atoms into this layer, and a counter electrode layer disposed on the opposite side of the metal ion supply layer Have

  When this ion memory is used as a cell array, word lines and bit lines are provided above and below the memory cells in order to perform writing, erasing, and reading by applying a potential or current from the outside. A so-called cross-point type memory in which bit lines and word lines are arranged so as to cross each other and bit lines and word lines are alternately stacked is considered to have the highest degree of integration. When this memory cell is used as a cell array, it is necessary to have a rectifying function. At this time, in addition to connecting a rectifying element in series with each memory cell, research to give the counter electrode a rectifying function is also underway. .

  In such an ion memory, with the miniaturization of the memory cell, there is a demand for a memory cell having a highly reliable structure in which pattern collapse and pattern distortion hardly occur during the manufacturing process.

JP 2011-165297 A

  An object of the present invention is to provide a highly reliable nonvolatile memory device.

  The nonvolatile memory device according to the embodiment includes a first wiring layer, a second wiring layer that intersects the first wiring layer, and a first wiring layer that is provided at a position where the first wiring layer and the second wiring layer intersect. 1 memory layer, the first memory layer is in contact with the first wiring layer, and the first wiring layer is a layer capable of supplying metal ions to the first memory layer.

1 is a schematic perspective view of a nonvolatile memory device according to a first embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 1st Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 1st Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 1st Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 1st Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 1st Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 1st Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram of the non-volatile memory device which concerns on 2nd Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 2nd Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 2nd Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 2nd Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 2nd Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on 2nd Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram for demonstrating the manufacturing process of the non-volatile memory device which concerns on a reference example. It is a perspective schematic diagram of the non-volatile memory device which concerns on 3rd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic perspective view of the nonvolatile memory device according to the first embodiment.

  The nonvolatile memory device 1 according to the first embodiment is an ion memory (CBRAM) device which is one of resistance variable memories.

  The nonvolatile memory device 1 includes a wiring layer 30 (first wiring layer 30), a wiring layer 50 (second wiring layer 50) that intersects the wiring layer 30, and a position where the wiring layer 30 and the wiring layer 50 intersect. And a provided storage layer 32 (first storage layer 32). In addition, the nonvolatile memory device 1 intersects the wiring layer 30, and the wiring layer 10 (third wiring layer 10) provided on the opposite side of the wiring layer 50 intersects the wiring layer 30 and the wiring layer 10. The memory layer 14 (second memory layer 14) provided at the position, and the metal layer 16 interposed between the wiring layer 30 and the memory layer 14 are provided.

  The wiring layer 10, the wiring layer 30, and the wiring layer 50 are stacked in the Z direction. The wiring layer 30 extends in the X direction. Each of the wiring layer 50 and the wiring layer 10 extends in the Y direction orthogonal to the X direction and the Z direction.

  In addition, the nonvolatile memory device 1 includes a counter electrode layer 34 (first counter electrode layer 34) provided between the memory layer 32 and the wiring layer 50, and a metal layer 36. The nonvolatile memory device 1 includes a counter electrode layer 12 (second counter electrode layer 12) provided between the wiring layer 10 and the memory layer 14. Further, a set including the wiring layer 30, the memory layer 32, and the counter electrode layer 34 is referred to as a memory cell 45 (first memory cell 45). Further, a set of the counter electrode layer 12, the memory layer 14, and the metal layer 16 is defined as a memory cell 25 (second memory cell 25). Further, the nonvolatile memory device 1 includes an interlayer insulating film between the wiring layers and between the memory cells (not shown in FIG. 1). The storage layer may be referred to as an RW (Rewritable) layer.

  The memory layer 32 is in contact with the wiring layer 30. The wiring layer 30 is, for example, a bit line and functions as a metal ion supply layer that can supply metal ions to the memory layer 32. Here, the metal ion supply layer is a layer made of metal before metal ions are ionized or a layer containing metal ions. The metal layer 16 is a metal ion supply layer capable of supplying metal ions to the memory layer 14, and in the manufacturing process of the nonvolatile memory device 1, a stopper layer at the time of CMP (Chemical Mechanical Polishing). Function as described later. The wiring layer 50 and the wiring layer 10 are, for example, word lines.

  With such a structure, information can be written, erased, and read from the upper and lower storage cells 25 and 45 with a single wiring layer 30. For example, for writing to the memory cell 45, a positive electrode is applied to the wiring layer 30 that is a bit line, and a negative electrode is applied to the wiring layer 50 that is a word line. Then, the metal contained in the wiring layer 30 is ionized and attracted to the wiring layer 50 side, and the metal ions are introduced into the memory layer 32. For this reason, the electrical resistance of the memory layer 32 decreases, and the memory layer 32 becomes conductive with the decrease. As a result, a current flows between the wiring layer 30 and the wiring layer 50. This operation is called write (or set operation).

  Conversely, a negative electrode is applied to the wiring layer 30 that is a bit line, and a positive electrode is applied to the wiring layer 50 that is a word line. Then, the metal ions introduced into the memory layer 32 are returned to the wiring layer 30 and reset to a high resistance value before writing. This operation is called erasure (or reset operation).

  The metal contained in the wiring layer 30 and the metal layer 16 is at least one metal selected from the group consisting of Ag, Cu, Ni, Co, and Ti. The metal contained in the wiring layer 30 and the metal layer 16 may be an alloy containing Ag in any of W, Ta, and Mo. The metal ion introduced into the storage layer is at least one metal ion selected from the group of Ag, Cu, Ni, Co, and Ti.

As a material of the memory layer 32 and the memory layer 14, in addition to a-Si (amorphous silicon), an insulating material such as SiO ₂ or Si ₃ N ₄ or a transition metal such as HfO ₂ , TiO ₂ , or WO ₂ An oxide or the like is used. As the material of the counter electrode layers 12 and 34, doped-Poly-Si, metal, and a laminated film thereof are used. The counter electrode layers 12 and 34 can have a rectifying characteristic in combination with the RW layer by selecting a material. The wiring layer 50 and the wiring layer 10 contain at least a metal selected from the group consisting of W, Mo, Al, Ti, and Ta. The material of the metal layer 36 is W, Mo, or the like.

  The nonvolatile memory device 1 includes a base layer (for example, an interlayer insulating film) (not shown) below the wiring layer 10 in addition to the portion shown in FIG. 1, and each memory cell is provided below the base layer. An integrated circuit for driving is provided. The wiring layer 10 and the wiring layer 50 may be bit lines, and the wiring layer 30 may be word lines.

A manufacturing process of the nonvolatile memory device 1 according to the first embodiment will be described.
2 to 6 are schematic perspective views for explaining the manufacturing process of the nonvolatile memory device according to the first embodiment.

  First, as shown in FIG. 2A, the wiring layer 10 before being processed as a word line is formed on a base layer (not shown), and the counter electrode layer 12, The memory layer 14, the metal layer 16 serving as a metal ion supply layer, and the insulating hard mask layer 18 are formed in this order. That is, the laminated film 20 having the wiring layer 10 / counter electrode layer 12 / memory layer 14 / metal layer 16 is formed on the base layer.

The material of the hard mask layer 18 is, for example, Si ₃ N ₄ , SiO ₂ or the like. The metal layer 16 has electrical conductivity and functions as a stopper layer when performing CMP (Chemical Mechanical Polishing) described later.

  Next, as shown in FIG. 2B, the laminated film 20 is divided into a plurality of parts in the X direction by lithography and RIE (Reactive Ion Etching), and the laminated film 20 becomes a line extending in the Y direction. To be processed. At this stage, a wiring layer 10 (for example, a word line) extending in the Y direction is formed.

Next, as shown in FIG. 3A, an interlayer insulating film 22 is deposited between the adjacent laminated films 20. The material of the interlayer insulating film 22 is SiO ₂ , SiOC or the like. The hard mask layer 18 described above is removed by CMP using the surface of the metal layer 16 as a stop position. Thereby, the surface of the laminated film 20 is planarized.

  Next, as shown in FIG. 3B, a wiring layer 30 before being processed as a bit line is deposited on the stacked film 20 and the interlayer insulating film 22. Subsequently, the memory layer 32, the counter electrode layer 34, the metal layer 36, and the insulating hard mask layer 38 are formed in this order on the wiring layer 30 that also serves as the metal ion supply layer. That is, the laminated film 40 having the wiring layer 30 / memory layer 32 / counter electrode layer 34 / metal layer 36 is formed on the laminated film 20 and the interlayer insulating film 22.

The material of the hard mask layer 38 is, for example, Si ₃ N ₄ , SiO ₂ or the like. The metal layer 36 has electrical conductivity and functions as a stopper layer when performing CMP, which will be described later.

  Next, as shown in FIG. 4A, using the lithography method and the RIE method, the laminated film 40 is divided into a plurality of pieces in the Y direction and processed so that the laminated film 40 becomes a line extending in the X direction. To do. Further, the laminated film 20 located under the laminated film 40 is divided in the Y direction. However, the wiring layer 10 is not RIE processed at this stage. That is, the metal layer 36, the counter electrode layer 34, the memory layer 32, the wiring layer 30 that also serves as a metal ion supply layer, the metal layer 16, the memory layer 14, and the counter electrode layer 12 are etched. Further, the interlayer insulating film 22 is also subjected to RIE processing.

  At this stage, since the counter electrode layer 12, the memory layer 14, and the metal layer 16 are divided into the X direction and the Y direction, a rectangular parallelepiped memory cell 25 is formed. In addition, a wiring layer 30 (for example, a bit line) extending in the X direction is formed.

Next, as shown in FIG. 4B, an interlayer insulating film 42 is deposited between the adjacent laminated films 40 and between the memory cells 25. The material of the interlayer insulating film 42 is SiO ₂ , SiOC or the like. The hard mask layer 38 described above is removed by CMP with the surface of the metal layer 16 as a stop position. Thereby, the surface of the laminated film 40 is planarized.

  Next, as shown in FIG. 5A, the wiring layer 50 before being processed as a word line is formed on the laminated film 40 and the interlayer insulating film 42, and Then, a hard mask layer 52 is formed.

  Next, as illustrated in FIG. 5B, the wiring layer 50, the metal layer 36, the counter electrode layer 34, and the memory layer 32 are further divided in the X direction by using a lithography method and an RIE method. Further, the interlayer insulating film 42 is also subjected to RIE processing.

  At this stage, since the counter electrode layer 34 and the memory layer 32 are divided in the X direction and the Y direction, the memory cell 45 is formed. Further, a wiring layer 50 (for example, a word line) extending in the Y direction is formed.

Next, as shown in FIG. 6, an interlayer insulating film 54 is applied between the adjacent wiring layers 50. Further, subsequently, the hard mask layer 52 described above is removed by CMP using the surface of the metal layer 36 as a stop position.
Through such a manufacturing process, a cross-point type nonvolatile memory device 1 having two mats and three wirings is formed.

A manufacturing process of the nonvolatile memory device according to the reference example will be described.
7 to 11 are schematic perspective views for explaining the manufacturing process of the nonvolatile memory device according to the reference example.

  First, as shown in FIG. 7A, the wiring layer 10 is formed on a base layer (not shown), and the counter electrode layer 12, the memory layer 14, and the metal ion supply layer are further formed on the wiring layer 10. 15, a metal layer 17 and an insulating hard mask layer 18 are formed in this order. That is, the laminated film 20 having the wiring layer 10 / counter electrode layer 12 / memory layer 14 / metal ion supply layer 15 / metal layer 17 is formed on the base layer. The metal ion supply layer 15 includes at least one metal selected from the group consisting of Ag, Cu, Ni, Co, and Ti. The metal layer 17 has electrical conductivity and functions as a stopper layer when performing CMP. The material of the metal layer 17 is W, Mo, or the like.

  Next, as shown in FIG. 7B, the laminated film 20 is divided into a plurality of pieces in the X direction by lithography and RIE, and processed so that the laminated film 20 becomes a line extending in the Y direction. At this stage, the wiring layer 10 (word line) extending in the Y direction is formed.

  Next, as shown in FIG. 8A, an interlayer insulating film 22 is deposited between the adjacent laminated films 20. The hard mask layer 18 described above is removed by CMP using the surface of the metal layer 16 as a stop position.

  Next, as shown in FIG. 8B, a wiring layer 31 before being processed as a bit line is deposited on the stacked film 20 and the interlayer insulating film 22. The material of the wiring layer 31 is W, Mo, or the like. Subsequently, a metal ion supply layer 33, a memory layer 32, a counter electrode layer 34, a metal layer 36, and an insulating hard mask layer 38 are formed in this order on the wiring layer 31. That is, the laminated film 40 having the wiring layer 31 / metal ion supply layer 33 / memory layer 32 / counter electrode layer 34 / metal layer 36 is formed on the laminated film 20 and the interlayer insulating film 22. The metal ion layer 33 includes at least one metal selected from the group consisting of Ag, Cu, Ni, Co, and Ti.

  Next, as shown in FIG. 9A, using the lithography method and the RIE method, the laminated film 40 is divided into a plurality of pieces in the Y direction and processed so that the laminated film 40 becomes a line extending in the X direction. To do. Further, the laminated film 20 located under the laminated film 40 is divided in the Y direction. However, the wiring layer 10 is not RIE processed at this stage. That is, the metal layer 36, the counter electrode layer 34, the memory layer 32, the metal ion supply layer 33, the wiring layer 31, the metal layer 17, the metal ion supply layer 15, the memory layer 14, and the counter electrode layer 12 are etched. Further, the interlayer insulating film 22 is subjected to RIE processing.

  At this stage, since the counter electrode layer 12, the memory layer 14, the metal ion supply layer 15, and the metal layer 17 are divided into the X direction and the Y direction, a rectangular parallelepiped memory cell 25 is formed. Further, a wiring layer 31 (bit line) extending in the X direction is formed.

  Next, as shown in FIG. 9B, an interlayer insulating film 42 is deposited between the adjacent laminated films 40 and between the memory cells 25. The hard mask layer 38 described above is removed by CMP with the surface of the metal layer 16 as a stop position.

  Next, as shown in FIG. 10A, the wiring layer 50 before being processed as a word line is formed on the laminated film 40 and the interlayer insulating film 42, and also on the wiring layer 50. Then, a hard mask layer 52 is formed.

  Next, as shown in FIG. 10B, the wiring layer 50, the metal layer 36, the counter electrode layer 34, the memory layer 32, and the metal ion supply layer 33 are further converted into X using a lithography method and an RIE method. Split in direction. Further, the interlayer insulating film 42 is processed by RIE.

  At this stage, the counter electrode layer 34, the memory layer 32, and the metal ion supply layer 33 are divided into the X direction and the Y direction, so that the memory cell 45 is formed. Further, a wiring layer 50 (word line) extending in the Y direction is formed.

  Next, as shown in FIG. 11A, an interlayer insulating film 54 is applied between the adjacent wiring layers 50. Further, subsequently, the hard mask layer 52 described above is removed by CMP using the surface of the metal layer 36 as a stop position.

  Through such a manufacturing process, a cross point type nonvolatile memory device 500 having two mats and three wirings is formed. FIG. 11B shows the state of the nonvolatile memory device 500 when the interlayer insulating film is removed.

  Also in the reference example, each of the memory cells 25 and 45 is processed into a rectangular parallelepiped shape by the RIE method. However, in the reference example, each of the metal ion supply layers 15 and 33 is provided as compared with the first embodiment. Therefore, in the reference example, the thickness of the hard mask layer 38 must be increased by the sum of the thickness of the metal ion supply layer 15 and the thickness of the metal ion supply layer 33 (see FIG. 9A). .

For example, in the RIE process illustrated in FIG. 9A, when both the material of the hard mask layer 38 and the material of the interlayer insulating film 22 are SiO ₂ , the hard mask is etched when the interlayer insulating film 22 is etched. Layer 38 will also be etched. This is because the material of the hard mask layer 38 and the material of the interlayer insulating film 22 are the same. Therefore, in the reference example, in order to achieve a high selection ratio (ratio of etching rate between the hard mask layer and a portion other than the hard mask layer), the hard mask layer 38 is made as thick as possible.

  However, when the thickness of the hard mask layer 38 is increased, there is a problem that the pattern collapses or the pattern is distorted during the manufacturing process due to the stress that the hard mask layer 38 has as a film as the element is miniaturized. This is a barrier to device miniaturization.

  On the other hand, in the nonvolatile memory device 1 according to the first embodiment, the wiring layer 31 according to the reference example is the wiring layer 30 that is a metal ion supply source. That is, in the nonvolatile memory device 1, the wiring layer 30 serves as both the metal ion supply layer and the bit line.

  In the nonvolatile memory device 1 according to the first embodiment, the formation of the metal ion supply layers 15 and 33 according to the reference example is omitted, and the metal layer 17 (CMP stopper layer) according to the reference example is supplied with metal ions. The metal layer 16 is the source.

  That is, in the first embodiment, not only the process of depositing the metal ion supply layers 15 and 33 can be omitted, but the film thickness to be processed in the RIE process is reduced. Therefore, the thickness of the hard mask layer can be reduced accordingly. As a result, in the first embodiment, the above-described barrier against miniaturization is lowered. Thus, a highly reliable nonvolatile memory device is formed even if miniaturization progresses. Further, since the metal ion supply layers 15 and 33 do not need to be deposited, the thickness of the memory cell is reduced, and the nonvolatile memory device can be made thinner and smaller. Further, since the thickness of the memory cell is reduced, the mechanical strength of the memory cell is increased.

(Second Embodiment)
FIG. 12 is a schematic perspective view of the nonvolatile memory device according to the second embodiment.

  The nonvolatile memory device 2 according to the second embodiment is an ion memory device that is one of resistance variable memories.

  The nonvolatile memory device 2 includes a wiring layer 130, a wiring layer 150 that intersects the wiring layer 130, and a storage layer 132 that is provided at a position where the wiring layer 130 and the wiring layer 150 intersect. In addition, the nonvolatile memory device 2 intersects with the wiring layer 130, the wiring layer 110 provided on the opposite side of the wiring layer 150, and the storage layer provided at a position where the wiring layer 130 and the wiring layer 110 intersect with each other. 114.

  The wiring layer 110, the wiring layer 130, and the wiring layer 150 are stacked in the Z direction. The wiring layer 130 extends in the X direction. Each of the wiring layer 150 and the wiring layer 110 extends in the Y direction orthogonal to the X direction and the Z direction.

  In addition, the nonvolatile memory device 2 includes a core member 200 provided between the adjacent wiring layers 150 and an interlayer insulating film 210 provided between the adjacent wiring layers 150. In other words, the wiring layer 150 is sandwiched between the core material 200 and the interlayer insulating film 210.

  The nonvolatile memory device 2 includes a core material 230 provided between adjacent wiring layers 110 and an interlayer insulating film 220 provided between adjacent wiring layers 110. In other words, the wiring layer 110 is sandwiched between the core material 230 and the interlayer insulating film 220.

  In addition, the nonvolatile memory device 2 includes a core member 240 provided between adjacent wiring layers 130 and an interlayer insulating film 250 provided between adjacent wiring layers 130. In other words, the wiring layer 150 is sandwiched between the core material 240 and the interlayer insulating film 250.

  The material of the wiring layer 130 is the same as that of the wiring layer 30. The wiring layer 130 is, for example, a bit line and a metal ion supply layer. The wiring layer 150 and the wiring layer 110 are, for example, word lines. Each of the memory layers 114 and 132 is in contact with the wiring layer 130.

As a material of the memory layer 132 and the memory layer 114, in addition to a-Si (amorphous silicon), an insulating material such as SiO ₂ or Si ₃ N ₄ or a transition metal such as HfO ₂ , TiO ₂ , or WO ₂ An oxide or the like is used. The wiring layer 150 and the wiring layer 110 contain at least a metal selected from the group consisting of W, Mo, Al, Ti, and Ta. Material of the core material 200,230,240 are _{SiO 2, Si 3 N 4,} SiOC _{, or the like.} The material of the interlayer insulating films 210, 220, and 250 is SiO ₂ , SiOC, or the like.

  The nonvolatile memory device 1 includes a base layer (for example, an interlayer insulating film) (not shown) below the wiring layer 110 in addition to the portion shown in FIG. 1, and each memory cell is provided below the base layer. An integrated circuit for driving is provided. The wiring layer 110 and the wiring layer 150 may be bit lines, and the wiring layer 130 may be word lines.

  With such a structure, information can be written to, erased from, and read from the upper and lower storage layers 132 and 114 with a single wiring layer 130.

A manufacturing process of the nonvolatile memory device 2 according to the second embodiment will be described.
13 to 17 are schematic perspective views for explaining the manufacturing process of the nonvolatile memory device according to the second embodiment.

  First, as shown in FIG. 13A, a core material 230 that is divided in the X direction and extends in the Y direction is formed by lithography and RIE. Subsequently, the core material 230 is covered with the wiring layer 110 so that the film thickness of the wiring layer 110 is uniform everywhere.

  Next, as shown in FIG. 13B, the wiring layer 110 is processed by the RIE method so that the wiring layer 110 covers the side wall of the core material 230.

  Next, as illustrated in FIG. 14A, an interlayer insulating film 220 is deposited between the adjacent wiring layers 110. Further, the surfaces of the wiring layer 110, the interlayer insulating film 220, and the core material 230 are planarized by CMP. At this stage, the wiring layer 110 extending in the Y direction is formed.

  Next, as illustrated in FIG. 14B, the memory layer 114 is formed on the wiring layer 110, the interlayer insulating film 220, and the core material 230. Subsequently, a core material 240 is formed on the memory layer 114.

  Next, as shown in FIG. 15A, the core material 240 is divided in the Y direction by the lithography method and the RIE method to form the core material 240 extending in the X direction. At this stage, a core material 240 that intersects the wiring layer 110 is formed.

  Next, as shown in FIG. 15B, the core material 240 is covered with the wiring layer 130 that also serves as the metal ion supply layer so that the film thickness of the wiring layer 130 is uniform everywhere, and then the RIE method is performed. Thus, the wiring layer 130 is processed so that the wiring layer 130 covers the side wall of the core member 240.

  Next, as illustrated in FIG. 16A, an interlayer insulating film 250 is deposited between the adjacent wiring layers 130. Further, the surfaces of the wiring layer 130, the core material 240, and the interlayer insulating film 250 are planarized by CMP. At this stage, the wiring layer 130 extending in the X direction is formed.

  Next, as illustrated in FIG. 16B, the memory layer 132 is formed on the wiring layer 130, the core material 240, and the interlayer insulating film 250. Further, the core material 200 is formed on the memory layer 132.

  Next, as shown in FIG. 17A, the core material 200 is processed so as to intersect the wiring layer 130 by lithography and RIE.

  Next, as shown in FIG. 17B, after the core material 200 is covered with the wiring layer 150 so that the film thickness of the wiring layer 150 is uniform everywhere, the wiring layer 150 is formed by RIE. The wiring layer 150 is processed so as to cover the side wall of the core member 200.

Thereafter, an interlayer insulating film 210 is deposited between adjacent wiring layers 150, and the surfaces of the interlayer insulating film 210, the core member 200, and the wiring layer 150 are planarized by CMP.
Through such a manufacturing process, a cross-point type nonvolatile memory device 2 having two mats and three wirings is formed.

A manufacturing process of the nonvolatile memory device according to the reference example will be described.
18 to 22 are schematic perspective views for explaining the manufacturing process of the nonvolatile memory device according to the reference example.

  First, as shown in FIG. 18A, the same state as in FIG. 14A, that is, the state in which the wiring layer 110, the interlayer insulating film 220, and the core material 230 extend in the Y direction is prepared.

  Next, as shown in FIG. 18B, the counter electrode layer 112, the memory layer 114, and the metal ion supply layer are formed on the wiring layer 110, the interlayer insulating film 220, and the core material 230. 115 is formed. Subsequently, a core material 240 is formed on the metal ion supply layer 115.

  Next, as shown in FIG. 19A, the core material 240 is divided in the Y direction by the lithography method and the RIE method to form the core material 240 extending in the X direction. At this stage, a core material 240 that intersects the wiring layer 110 is formed.

  Next, as shown in FIG. 19B, after the core material 240 is covered with the wiring layer 130 so that the film thickness of the wiring layer 130 is uniform everywhere, the wiring layer 130 is formed by RIE. The wiring layer 130 is processed so as to cover the side wall of the core member 240.

  Next, as shown in FIG. 20A, an interlayer insulating film 250 is deposited between the adjacent wiring layers 130. Further, the surfaces of the wiring layer 130, the core material 240, and the interlayer insulating film 250 are planarized by CMP. At this stage, the wiring layer 130 extending in the X direction is formed.

  Next, as shown in FIG. 20B, the metal ion supply layer 133, the memory layer 132, and the counter electrode layer are formed on the wiring layer 130, the core material 240, and the interlayer insulating film 250. 134 is formed. Further, the core material 200 is formed on the counter electrode layer 134.

  Next, as shown in FIG. 21A, the core material 200 is processed so as to intersect the wiring layer 130 by lithography and RIE.

  Next, as shown in FIG. 21B, after the core material 200 is covered with the wiring layer 150 so that the film thickness of the wiring layer 150 is uniform everywhere, the wiring layer 150 is formed by RIE. The wiring layer 150 is processed so as to cover the side wall of the core member 200.

Next, as shown in FIG. 22, an interlayer insulating film 210 is deposited between adjacent wiring layers 150, and the surfaces of the interlayer insulating film 210, the core material 200, and the wiring layer 150 are planarized by CMP.
Through such a manufacturing process, a cross point type nonvolatile memory device 600 having two mats and three wirings is formed.

  However, in the nonvolatile memory device 600, the metal ion supply layers 115 and 133 and the counter electrode layers 112 and 134 are provided between the memory cells. Since the metal ion supply layers 115 and 133 and the counter electrode layers 112 and 134 have electrical conductivity, in the nonvolatile memory device 600, current leakage may occur between the memory cells. In order to prevent this current leak, a separate prevention means is required.

  In order to avoid this, the core members 240 and 200 are removed before the interlayer insulating films 250 and 210 are deposited, and the metal ion supply layers 115 and 133 and the counter electrode layer are formed using the wiring layers 130 and 150 as mask members. 112 and 134 need to be divided by the RIE method. However, such a dividing process leads to an increase in the number of processes, resulting in an increase in cost. Further, the method using the wiring layers 130 and 150 as a mask member causes the wiring layers 130 and 150 to be thinned by so-called film reduction of the wiring layers 130 and 150 that occurs during RIE. For this reason, there is a problem that the electrical resistance of the wiring layers 130 and 150 increases.

  On the other hand, in the second embodiment, each of the counter electrode layers 112 and 134 according to the reference example is shared by each of the wiring layers 110 and 150. Furthermore, since the wiring layer 130 itself is used as a metal ion supply source, the metal ion supply layers 115 and 133 according to the reference example are not required. In the second embodiment, the RIE technique that achieves a high selection ratio is not used, and the hard mask layer 38 is not used accordingly.

  Thereby, the pattern collapse etc. which were mentioned in the reference example of 1st Embodiment are avoided, and also the highly reliable non-volatile memory device by which the current leak between memory cells was prevented is implement | achieved.

(Third embodiment)
FIG. 23 is a schematic perspective view of the nonvolatile memory device according to the third embodiment.

The basic configuration of the nonvolatile memory device 3 according to the third embodiment is the same as that of the nonvolatile memory device 2 according to the second embodiment. However, in the nonvolatile memory device 3, a diffusion prevention film 300 that suppresses diffusion of metal ions into the memory layer 132 is provided between the wiring layer 150 and the memory layer 132, and the wiring layer 150 is the wiring layer 130. Similarly, it is made of the same material as the metal ion supply layer. Alternatively, a diffusion prevention film 310 that suppresses the diffusion of metal ions into the memory layer 114 is provided between the memory layer 114 and the wiring layer 110, and the wiring layer 110 is a metal ion supply layer similar to the wiring layer 130. It is composed of the same material. The material of the diffusion preventing films 300 and 310 is SiO ₂ , Si ₃ N ₄ or the like. The film thickness of the diffusion preventing films 300 and 310 is set to a thin film that does not inhibit the tunnel current while suppressing the diffusion of metal ions.

  When such a diffusion prevention film is provided, writing and erasing are performed as follows. For example, for writing to the memory layer 132, a positive electrode is applied to the wiring layer 130 that is a bit line, and a negative electrode is applied to the wiring layer 150 that is a word line. Since the film thickness of the diffusion preventing film 300 is set to a thin film that does not inhibit the tunnel current, an electric field gradient is formed in the memory layer 132. Then, the metal contained in the wiring layer 130 is ionized and attracted to the wiring layer 150 side, and the metal ions are introduced into the memory layer 132. For this reason, the electrical resistance of the memory layer 32 decreases, and the memory layer 32 becomes conductive with the decrease.

  On the other hand, when a negative electrode is applied to the wiring layer 130 that is a bit line and a positive electrode is applied to the wiring layer 150 that is a word line, the metal ions that have been introduced into the memory layer 132 are returned to the wiring layer 130, resulting in a high resistance value before writing. Reset. At this time, metal ions are not introduced into the memory layer 132 from the wiring layer 150 due to the presence of the diffusion prevention film 300. Accordingly, the memory layer 132 shifts from a low resistance to a high resistance.

  In the nonvolatile memory device 3, the wiring layer 150 and the wiring layer 110 are metal ion supply layers. That is, in the third embodiment, since the material of the wiring layers 110 and 150 is the same as that of the wiring layer 130, the manufacturing process can be easily advanced without changing the materials of the wiring layers 110 and 150 and the material of the wiring layer 130. be able to.

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In addition, each element included in each of the above-described embodiments can be combined as much as legally possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 2, 3, 500, 600 Non-volatile memory device 10, 30, 31, 50, 110, 130, 150 Wiring layer 12, 34, 112, 134 Counter electrode layer 14, 32, 114, 132 Memory layer 15, 33 115, 133 Metal ion supply layer 16, 17 Metal layer 18, 38, 52 Hard mask layer 20, 40 Laminated film 22, 42, 54, 210, 220, 250 Interlayer insulating film 25, 45 Memory cell 36 Metal layer 200, 230, 240 Core material 300, 310 Diffusion prevention film

Claims (6)

A first wiring layer;
A second wiring layer intersecting the first wiring layer;
A first memory layer provided at a position where the first wiring layer and the second wiring layer intersect;
A third wiring layer that intersects with the first wiring layer and is provided on the opposite side of the second wiring layer;
A second memory layer provided at a position where the first wiring layer and the third wiring layer intersect;
A metal layer interposed between the third wiring layer and the second memory layer;
With
The first memory layer is in contact with the first wiring layer;
The first wiring layer is a layer capable of supplying metal ions to the first memory layer,
The non-volatile memory device, wherein the metal layer is a layer capable of supplying metal ions to the second memory layer. A first wiring layer;
A second wiring layer intersecting the first wiring layer;
A first memory layer provided at a position where the first wiring layer and the second wiring layer intersect;
With
The first memory layer is in contact with the first wiring layer;
The non-volatile memory device, wherein the first wiring layer is a layer capable of supplying metal ions to the first memory layer. A third wiring layer that intersects with the first wiring layer and is provided on the opposite side of the second wiring layer;
A second memory layer provided at a position where the first wiring layer and the third wiring layer intersect;
A metal layer interposed between the first wiring layer and the second memory layer;
Further comprising
The nonvolatile memory device according to claim 2, wherein the metal layer is a layer capable of supplying metal ions to the second memory layer. A third wiring layer that intersects with the first wiring layer and is provided on the opposite side of the second wiring layer;
A second memory layer provided at a position where the first wiring layer and the third wiring layer intersect;
Provided between the second wiring layer and the first memory layer, or between the second memory layer and the third wiring layer, and the metal ions to the first memory layer or the second memory layer An anti-diffusion film that suppresses the diffusion of
The nonvolatile memory device according to claim 2, further comprising:   The nonvolatile memory device according to claim 1, wherein the metal ion is at least one metal ion selected from the group consisting of Ag, Cu, Ni, Co, and Ti.   6. The nonvolatile memory according to claim 3, wherein the second wiring layer and the third wiring layer include at least one metal selected from the group consisting of W, Mo, Al, Ti, and Ta. apparatus.

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