CN112928135B - Magnetic memory and preparation method thereof - Google Patents

Magnetic memory and preparation method thereof Download PDF

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CN112928135B
CN112928135B CN201911237999.0A CN201911237999A CN112928135B CN 112928135 B CN112928135 B CN 112928135B CN 201911237999 A CN201911237999 A CN 201911237999A CN 112928135 B CN112928135 B CN 112928135B
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mram
array
stt
sot
magnetic tunnel
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CN112928135A (en
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孟皓
迟克群
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Hikstor Technology Co Ltd
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Hikstor Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Abstract

The invention provides a magnetic memory and a preparation method thereof, wherein the magnetic memory comprises at least one hybrid memory array, the hybrid memory array comprises an STT-MRAM array and an SOT-MRAM array which are adjacently arranged, the STT-MRAM array comprises STT-MRAM memory cells arranged in an array, the SOT-MRAM array comprises SOT-MRAM memory cells arranged in an array, and the STT-MRAM memory cells and the SOT-MRAM memory cells have the same laminated structure. The magnetic memory of the invention can not only satisfy the long-time storage of a large amount of data, but also satisfy the frequent erasing and writing of a large amount of data.

Description

Magnetic memory and preparation method thereof
Technical Field
The invention relates to the technical field of magnetic memories, in particular to a magnetic memory and a preparation method thereof.
Background
With the development of Memory technology, a new Memory type, MRAM (Magnetic Random Access Memory), appears on the basis of the traditional SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory), and has a longer service life than a solid state disk, better data non-volatility than SRAM and DRAM, higher device density than SRAM, and has application potential to replace the existing Memory.
However, in any type of memory, it is impossible to achieve both long-term storage of a large amount of data and frequent erasure of a large amount of data. Therefore, there is a need to provide a new memory to meet the application requirements of multiple scenarios.
Disclosure of Invention
In view of the above, the present invention provides a magnetic memory and a method for manufacturing the same, which have various storage characteristics, and can satisfy both long-term storage of a large amount of data and frequent erasing of a large amount of data.
In a first aspect, the present invention provides a magnetic memory comprising at least one hybrid memory array comprising an adjacently disposed STT-MRAM array and an SOT-MRAM array, wherein,
the STT-MRAM array comprises STT-MRAM memory cells arranged in an array, the SOT-MRAM array comprises SOT-MRAM memory cells arranged in an array, and the STT-MRAM memory cells and the SOT-MRAM memory cells have the same laminated structure.
Optionally, the STT-MRAM memory cell comprises a first Magnetic Tunnel Junction (MTJ), the SOT-MRAM memory cell comprises a second Magnetic Tunnel Junction (MTJ), and the first magnetic tunnel junction and the second magnetic tunnel junction have the same layer stack structure.
Optionally, the diameter dimensions of the first magnetic tunnel junctions of all STT-MRAM memory cells in the STT-MRAM array are the same; the diameters of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same size.
Optionally, the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of the same column or row in the STT-MRAM array are the same, and the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of each column or row are gradually reduced from the column or row farthest from the SOT-MRAM array to the column or row closest to the SOT-MRAM array;
the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.
Optionally, the STT-MRAM array is divided into a first sub-array of STT-MRAM and a second sub-array of STT-MRAM disposed adjacent to each other, wherein the second sub-array of STT-MRAM is adjacent to the SOT-MRAM array, wherein the diameter dimensions of the first magnetic tunnel junctions of all STT-MRAM memory cells in the first sub-array of STT-MRAM are the same; the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of the same column or row in the STT-MRAM second sub-array are the same, and the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of each column or row are gradually reduced from the column or row farthest from the SOT-MRAM array to the column or row closest to the SOT-MRAM array;
the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.
Optionally, the STT-MRAM memory cell further comprises a first top electrode coupled to the first magnetic tunnel junction, the first top electrode comprising a first pre-fabricated layer and a first functional layer arranged in a stack, the first pre-fabricated layer in contact with the first magnetic tunnel junction;
the SOT-MRAM memory cell further includes a second top electrode coupled to the second magnetic tunnel junction, the second top electrode including a second pre-fabricated layer and a second functional layer arranged in a stack, the second pre-fabricated layer being in contact with the second magnetic tunnel junction.
Optionally, the first pre-fabricated layer has the same cross-sectional shape and dimensions as the first magnetic tunnel junction, and the second pre-fabricated layer has the same cross-sectional shape and dimensions as the second magnetic tunnel junction;
the cross section of the first functional layer is circular, and the diameter of the first functional layer is larger than or equal to that of the first magnetic tunnel junction; the cross section of the second functional layer is rectangular, and the width of the second functional layer is larger than or equal to the diameter of the second magnetic tunnel junction.
Optionally, the first prefabricated layer and the second prefabricated layer are made of the same material and are selected from one of Pt, ta, W, au and Cu;
the first functional layer and the second functional layer are made of the same material and are selected from one of Pt, ta, W, au and Cu.
Optionally, when the magnetic memory includes a plurality of hybrid memory arrays, the hybrid memory arrays are sequentially arranged, the array arrangement of each hybrid memory array is the same, and the sizes of the STT-MRAM array and the SOT-MRAM array in different hybrid memory arrays are different from each other.
In a second aspect, the present invention provides a method for manufacturing a magnetic memory, the method comprising:
depositing a magnetic tunnel junction multilayer film on a substrate and depositing a top electrode prefabricated layer material film on the magnetic tunnel junction multilayer film;
forming at least one prefabricated structure array on a substrate by photoetching and etching, wherein the prefabricated structure array comprises a first prefabricated structure array and a second prefabricated structure array which are adjacently arranged, the first prefabricated structure array is used for forming an STT-MRAM array, the second prefabricated structure array is used for forming an SOT-MRAM array, the first prefabricated structure array comprises first prefabricated units which are arranged according to an array, the first prefabricated units comprise first magnetic tunnel junctions and first prefabricated layers on the first magnetic tunnel junctions, the second prefabricated structure array comprises second prefabricated units which are arranged according to an array, and the second prefabricated units comprise second magnetic tunnel junctions and second prefabricated layers on the second magnetic tunnel junctions;
filling gaps in the prefabricated structure array with an insulating medium, and performing surface planarization treatment to form a flat surface, wherein the flat surface is positioned above the first prefabricated layer and the second prefabricated layer;
forming a hole groove above the first prefabricated layer and the second prefabricated layer through photoetching and etching;
and depositing a top electrode function layer material film to fill the hole groove, and carrying out chemical mechanical polishing or etching on the top electrode function layer material film to form a first function layer above the first prefabricated layer and a second function layer above the second prefabricated layer.
The magnetic memory provided by the invention utilizes different storage characteristics of the STT-MRAM array and the SOT-MRAM array, not only can satisfy long-time storage of a large amount of data, but also can satisfy frequent erasing and writing of the large amount of data. Meanwhile, the STT-MRAM storage unit and the SOT-MRAM storage unit adopt the same laminated structure and have good process compatibility, so that the magnetic memory provided by the embodiment of the invention is convenient to manufacture.
Drawings
FIG. 1 is a schematic diagram of a memory cell of a magnetic memory according to an embodiment of the present invention;
figure 2 is a top view of the array distribution (only magnetic tunnel junctions shown) for a magnetic memory in accordance with one embodiment of the present invention;
FIG. 3 is a top view of the array distribution of a magnetic memory showing the top electrode above the magnetic tunnel junction in accordance with one embodiment of the present invention;
FIG. 4 is a functional view of a storage region of a magnetic memory in accordance with one embodiment of the present invention;
figure 5 is a top view of the array distribution (only magnetic tunnel junctions shown) for a magnetic memory in accordance with one embodiment of the present invention;
FIG. 6 is a top view of the array distribution of the magnetic memory showing the top electrode above the magnetic tunnel junction in accordance with one embodiment of the present invention;
FIG. 7 is a functional view of a storage region of a magnetic memory in accordance with one embodiment of the present invention;
FIG. 8 is a top view of an array distribution (only magnetic tunnel junctions are shown) for a magnetic memory in accordance with one embodiment of the present invention;
figure 9 is a top view of the array distribution (showing the top electrode above the magnetic tunnel junction) for a magnetic memory in accordance with one embodiment of the present invention;
FIG. 10 is a functional view of a storage region of a magnetic memory in accordance with one embodiment of the present invention;
FIG. 11 is a functional view of a storage region of a magnetic memory in accordance with yet another embodiment of the present invention;
fig. 12A to 12E are schematic structural views of steps of a method for manufacturing a magnetic memory according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Example one
One embodiment of the present invention provides a magnetic memory including a hybrid memory array including an adjacent arrangement of an STT-MRAM array and an SOT-MRAM array, wherein,
the STT-MRAM array comprises STT-MRAM memory cells arranged in an array, the SOT-MRAM array comprises SOT-MRAM memory cells arranged in an array, and the STT-MRAM memory cells and the SOT-MRAM memory cells have the same laminated structure.
In the illustrated embodiment, a memory cell is selected from the STT-MRAM array and the SOT-MRAM array, and as shown in fig. 1, the STT-MRAM memory cell includes a first Magnetic Tunnel Junction (MTJ) 10 and a first top electrode 11 coupled to the first magnetic tunnel junction, the first magnetic tunnel junction 10 includes a first reference layer 101, a first barrier layer 102, and a first free layer 103, the first top electrode 11 includes a first pre-fabricated layer 111 and a first functional layer 112, the first pre-fabricated layer 111 is in contact with the first free layer 103, and the first pre-fabricated layer 111 is used to prevent the first free layer 103 from being oxidized during the fabrication process.
The SOT-MRAM memory cell comprises a second Magnetic Tunnel Junction (MTJ) 20 and a second top electrode 21 coupled to the second magnetic tunnel junction, the second magnetic tunnel junction 20 comprising a second reference layer 201, a second barrier layer 202 and a second free layer 203, the second top electrode 21 comprising a second pre-fabricated layer 211 and a second functional layer 212, the second pre-fabricated layer 211 being in contact with the second free layer 203, the second pre-fabricated layer 211 being configured to prevent oxidation of the second free layer 203 during fabrication.
Further, the cross-sectional shape and size of the first pre-fabricated layer 111 are the same as those of the first magnetic tunnel junction 10, and the cross-sectional shape and size of the second pre-fabricated layer 211 are the same as those of the second magnetic tunnel junction 20. The cross-sectional shape of the first functional layer 112 is circular, and the diameter size of the first functional layer 112 is greater than or equal to the diameter size of the first magnetic tunnel junction 10; the cross-sectional shape of the second functional layer 212 is rectangular, and the width of the second functional layer 212 is greater than or equal to the diameter of the second magnetic tunnel junction 20. The first prefabricated layer 111 and the second prefabricated layer 211 are made of the same material and are selected from one of Pt, ta, W, au and Cu; the first functional layer 112 and the second functional layer 212 are made of the same material, and are selected from one of Pt, ta, W, au, and Cu.
The magnetic memory provided by the embodiment of the invention utilizes different storage characteristics of the STT-MRAM array and the SOT-MRAM array, not only can satisfy long-time storage of a large amount of data, but also can satisfy frequent erasing and writing of the large amount of data. Meanwhile, the STT-MRAM storage unit and the SOT-MRAM storage unit adopt the same laminated structure and have good process compatibility, so that the magnetic memory provided by the embodiment of the invention is convenient to manufacture.
Further, since the diameter size of the magnetic tunnel junction in the memory cell directly affects the storage characteristics of the memory cell, in the embodiment of the present invention, referring to fig. 2 and fig. 3, fig. 2 shows a top view of the magnetic memory (only the magnetic tunnel junction is shown) of the present embodiment, and fig. 3 shows a top view of the magnetic memory (only the top electrode above the magnetic tunnel junction is shown) of the present embodiment. The first magnetic tunnel junctions of all STT-MRAM memory cells in the STT-MRAM array are etched to be cylindrical, and the diameter sizes of the first magnetic tunnel junctions of all STT-MRAM memory cells are the same; the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are etched to be cylindrical, and the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells are the same. Generally, the diameter dimension of the first magnetic tunnel junction of the STT-MRAM memory cell will be greater than the diameter dimension of the second magnetic tunnel junction of the SOT-MRAM memory cell.
The magnetic memory provided by the first embodiment of the invention has the advantages that the STT-MRAM array has high density and non-volatility, so that the STT-MRAM array forms a "data storage area" for a storage scenario requiring a large number of read operations and a small number of write operations, such as storing a "program" or a "model", while the SOT-MRAM array has high service life and non-volatility, and can form a "high frequency erasing area" for a storage scenario requiring a large number of write operations, such as storing "calculation data". The magnetic memory is shown in a view of a storage area, as shown in fig. 4, and includes a data storage area and a high frequency erase/write area.
Example two
In another embodiment of the present invention, a magnetic memory includes a hybrid memory array including an adjacently disposed STT-MRAM array and SOT-MRAM array, wherein,
the STT-MRAM array comprises STT-MRAM memory cells arranged in an array, the SOT-MRAM array comprises SOT-MRAM memory cells arranged in an array, and the STT-MRAM memory cells and the SOT-MRAM memory cells have the same laminated structure.
In the embodiment of the invention, the stack structure of the STT-MRAM memory cell and the SOT-MRAM memory cell is the same as that of the first embodiment, and the description thereof is omitted. Referring to fig. 5 and 6, fig. 5 is a top view of the magnetic memory (only the magnetic tunnel junction is shown) of the present embodiment, and fig. 6 is a top view of the magnetic memory (top electrode above the magnetic tunnel junction is shown) of the present embodiment. The diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of the same column in the STT-MRAM array are the same, and the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of the columns are gradually reduced from the column farthest from the SOT-MRAM array to the column nearest to the SOT-MRAM array; the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same. Generally, the diameter size of a column of STT-MRAM memory cells in the STT-MRAM array closest to the SOT-MRAM array is still larger than the diameter size of the SOT-MRAM memory cells.
In fig. 5 and 6, the STT-MRAM array and the SOT-MRAM array are arranged laterally, it can be understood that when the STT-MRAM array and the SOT-MRAM array are arranged vertically, the first magnetic tunnel junctions of the STT-MRAM memory cells of the same row in the STT-MRAM array have the same diameter size, and the diameter size of the first magnetic tunnel junctions of the STT-MRAM memory cells of each row gradually becomes smaller from the row farthest from the SOT-MRAM array to the row closest to the SOT-MRAM array; the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.
In the magnetic memory provided by the second embodiment, the SOT-MRAM array may form a "high frequency erasing region" for storing frequently erased data, and the size of the memory cells of the STT-MRAM array gradually decreases from left to right, so that the non-volatility decreases from left to right, the erasing speed increases, and the service life increases. Namely, the leftmost side has the strongest non-volatility, the slowest erasing speed and the shortest service life, the rightmost side has the worst non-volatility, the fastest erasing speed and the shortest service life. Therefore, the STT-MRAM array forms a multiplexing area with gradually changed performance from left to right, and when data is not frequently erased, the data is stored at the leftmost side of the multiplexing area; when the frequently erased data needs to be stored, the frequently erased data is stored in the high-frequency erasing area and then stored on the right side of the multiplexing area. The magnetic memory is shown in a view of a storage region, as shown in fig. 7, which includes a multiplexing region and a high-frequency erasing region.
EXAMPLE III
In another embodiment of the present invention, a magnetic memory includes a hybrid memory array including an adjacently disposed STT-MRAM array and SOT-MRAM array, wherein,
the STT-MRAM array comprises STT-MRAM memory cells arranged in an array, the SOT-MRAM array comprises SOT-MRAM memory cells arranged in an array, and the STT-MRAM memory cells and the SOT-MRAM memory cells have the same laminated structure.
In the embodiment of the invention, the laminated structure of the STT-MRAM memory cell and the SOT-MRAM memory cell is the same as that of the first embodiment, and the description thereof is omitted. Referring to fig. 8 and 9, fig. 8 shows a top view of the magnetic memory (only the magnetic tunnel junction is shown) of the present embodiment, and fig. 9 shows a top view of the magnetic memory (top electrode above the magnetic tunnel junction is shown) of the present embodiment. The STT-MRAM array is divided into a first STT-MRAM sub-array and a second STT-MRAM sub-array which are adjacently arranged, wherein the second STT-MRAM sub-array is adjacent to the SOT-MRAM array, and the diameter sizes of the first magnetic tunnel junctions of all STT-MRAM storage units in the first STT-MRAM sub-array are the same; the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of the same column in the second STT-MRAM sub-array are the same, and the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of all columns are gradually reduced from the column farthest from the SOT-MRAM array to the column nearest to the SOT-MRAM array; the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same. Generally, the diameter size of a column of STT-MRAM memory cells in the STT-MRAM array closest to the SOT-MRAM array is still larger than the diameter size of the SOT-MRAM memory cells.
In fig. 8 and 9, the STT-MRAM array and the SOT-MRAM array are arranged in a transverse direction, it can be understood that when the STT-MRAM array and the SOT-MRAM array are arranged in a vertical direction, the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM memory cells of the same row in the STT-MRAM second sub-array are the same, and the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM memory cells of each row are gradually smaller from a row farthest from the SOT-MRAM array to a row closest to the SOT-MRAM array; the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.
In the magnetic memory provided in the third embodiment, the SOT-MRAM array may form a "high frequency erase/write region" for storing frequently erased/written data, and has the characteristics of long service life, high erase/write speed, non-volatility, and medium data density; the STT-MRAM first sub-array forms a 'data storage area' for storing data for a long time, and has the characteristics of strong non-volatility, high data density, long service life, moderate erasing speed and the like; the STT-MRAM second sub-array forms a multiplexing area, the function of the multiplexing area is between the high-frequency erasing area and the data storage area, the multiplexing area can be flexibly multiplexed, and when the data storage amount is increased, the multiplexing area can serve as the data storage area; when the requirement of frequent erasing increases, it can be used as "high frequency erasing area". The magnetic memory is shown in a view of a storage region, and as shown in fig. 10, the magnetic memory includes a data storage region, a multiplexing region, and a high-frequency erasing region.
In addition, if it is assumed that the entire memory region of the magnetic memory is implemented by one hybrid memory array, it is conceivable that the array size of the STT-MRAM array and the SOT-MRAM array in the hybrid memory array is definitely very large, and therefore, the magnetic memory employs a distributed design, and the magnetic memory includes a plurality of hybrid memory arrays, each including the STT-MRAM array and the SOT-MRAM array adjacently disposed, wherein the STT-MRAM array includes STT-MRAM memory cells arranged in an array, and the SOT-MRAM array includes SOT-MRAM memory cells arranged in an array, and the STT-MRAM memory cells have the same stack structure as the SOT-MRAM memory cells. For the description of the structure of each hybrid memory array, reference may be made to the above three embodiments, which are not repeated.
Based on the magnetic memory implementing three, when the magnetic memory includes a plurality of hybrid memory arrays, each hybrid memory array may form a memory region as shown in fig. 10, and a view of the memory region of the final magnetic memory is shown in fig. 11.
It is understood that when the magnetic memory includes a plurality of hybrid memory arrays, the entire memory region of the magnetic memory is formed by the plurality of hybrid memory arrays, and the size of each hybrid memory array itself can be made small on the premise that the memory regions of the magnetic memory are the same. Therefore, the distributed design has the advantages that the distance between the high-frequency erasing area and the data storage area and the distance between the high-frequency erasing area and the data multiplexing area are shorter, and when the stored data are changed from a type of frequent erasing to a type of long-time storage, the data can be more conveniently transferred; meanwhile, the distributed design has more layout flexibility, and can be more conveniently optimized aiming at design functions, such as: the proportion and the performance of three functional areas of different hybrid storage arrays can be different, a 'multiplexing area' is added, the data storage method is more suitable for application scenes that the data storage time is short and the stored data can be frequently changed, and a 'data storage area' is added, and the data storage method is more suitable for application scenes that the data storage time is long and the stored data cannot be changed for a long time.
Another embodiment of the present invention provides a method for manufacturing a magnetic memory, the method including:
s1, depositing a magnetic tunnel junction multilayer film on a substrate and depositing a top electrode prefabricated layer material film on the magnetic tunnel junction multilayer film;
in this embodiment, as shown in fig. 12A, a substrate 300 is provided, a necessary bottom electrode may be embedded in the substrate 300, a first magnetic material layer 301 for forming a reference layer, an insulating oxide material layer 302 for forming a barrier layer, a second magnetic material layer 303 for forming a free layer, and a first heavy metal material layer 304 for forming a top electrode pre-fabricated layer are sequentially deposited on the substrate 300, where the deposited heavy metal material layer 304 may prevent the second magnetic material layer 303 from being oxidized and simultaneously serve to connect the top electrode functional layer and the free layer, where the first magnetic material layer 301 may be a single-layer ferromagnetic material or may be composed of multiple-layer ferromagnetic materials or synthetic ferromagnetic materials, the insulating oxide material layer 302 includes an oxide such as MgO and AlO, the second magnetic material layer 303 may be composed of a single-layer ferromagnetic material or multiple-layer ferromagnetic material, or may be formed by growing a layer of a material such as MgO on the top to form a double-barrier structure, and the first heavy metal material layer 304 may be composed of materials such as Pt, ta, W, au, and Cu.
S2, forming at least one prefabricated structure array on a substrate through photoetching and etching, wherein the prefabricated structure array comprises a first prefabricated structure array and a second prefabricated structure array which are adjacently arranged, the first prefabricated structure array is used for forming an STT-MRAM array, the second prefabricated structure array is used for forming an SOT-MRAM array, the first prefabricated structure array comprises first prefabricated units which are arranged according to an array, the first prefabricated units comprise first magnetic tunnel junctions and first prefabricated layers on the first magnetic tunnel junctions, the second prefabricated structure array comprises second prefabricated units which are arranged according to an array, and the second prefabricated units comprise second magnetic tunnel junctions and second prefabricated layers on the second magnetic tunnel junctions;
as shown in fig. 12B, the first magnetic material layer, the insulating oxide material layer, the second magnetic material layer, and the first heavy metal material layer are etched, generally, into a cylindrical shape, so as to obtain a cylindrical magnetic tunnel junction and a top electrode pre-fabricated layer above the cylindrical magnetic tunnel junction, and one magnetic tunnel junction 40 and one magnetic tunnel junction 50 are respectively selected from the first pre-fabricated structure array and the second pre-fabricated structure array for illustration, where the magnetic tunnel junction 40 includes a first reference layer 401, a first barrier layer 402, and a first free layer 403 stacked from bottom to top, the first pre-fabricated layer above the first barrier layer is 411, the magnetic tunnel junction 50 includes a second reference layer 501, a second barrier layer 502, and a second free layer 503 stacked from bottom to top, the second pre-fabricated layer above the second barrier layer is 511, which are all produced in batch, and a plurality of magnetic tunnel junctions are obtained at the same time, and the magnetic tunnel junctions are arranged at intervals, where the magnetic tunnel junction 40 is used to further form an STT-MRAM storage unit, and the magnetic tunnel junction 50 is used to further form an SOT-MRAM storage unit. In this embodiment, the magnetic tunnel junctions 40 and 50 have the same shape and size, are both cylindrical, and the specific shape and size can be adjusted according to the actual needs, and the two can have different shapes and sizes.
In addition, the STT-MRAM memory unit does not need a strip-shaped heavy metal electrode, so that the integration density is higher than that of the SOT-MRAM memory unit, and the distance between MTJ cylinders for manufacturing the STT-MRAM can be smaller than that of the MTJ cylinders for manufacturing the SOT-MRAM in the process of etching the thin film into the MTJ cylinders.
S3, filling gaps in the prefabricated structure array with an insulating medium, and carrying out surface planarization treatment to form a flat surface, wherein the flat surface is positioned above the first prefabricated layer and the second prefabricated layer;
as shown in fig. 12C, the gap between the magnetic tunnel junctions is filled with the insulating medium 200, which generally includes SiN, siO, siON, etc., and the insulating medium above the first pre-fabricated layer 411 and the second pre-fabricated layer 511 is planarized by using a chemical mechanical polishing method, and the insulating medium 200 still remains above the first pre-fabricated layer 411 and the second pre-fabricated layer 511 after the planarization process, so that it is necessary to ensure a sufficient filling height of the insulating medium 200.
S4, forming a hole groove above the first prefabricated layer and the second prefabricated layer through photoetching and etching;
as shown in fig. 12D, by using photolithography and etching processes, an opening is formed in the insulating medium remained above the first prefabricated layer 411, and a trench is formed in the insulating medium remained above the second prefabricated layer 511, and the etching is stopped on the surfaces of the first prefabricated layer 411 and the second prefabricated layer 511, and the etching can be properly over-etched, so that the first prefabricated layer 411 and the second prefabricated layer 511 can be fully exposed. Wherein, the opening hole adopts the same shape as the magnetic tunnel junction 40 for preparing the STT-MRAM memory unit, thus being etched into a round hole, the size of the opening hole is larger than or equal to the size of the magnetic tunnel junction 40 for preparing the STT-MRAM memory unit, and the size of the opening hole is equal to the size of the magnetic tunnel junction in the embodiment; the trenches are etched to form rectangular trenches having a width greater than or equal to the size of the magnetic tunnel junction 50 used to fabricate the SOT-MRAM memory cells, in this embodiment the trench size is equal to the size of the magnetic tunnel junction. During specific etching, the technological processes of etching the round holes and the rectangular grooves can be carried out in different steps, and the required electrodes are manufactured respectively.
And S5, depositing a top electrode function layer material film to fill the hole, and carrying out chemical mechanical polishing or etching on the top electrode function layer material film to form a first function layer above the first prefabricated layer and a second function layer above the second prefabricated layer.
As shown in fig. 12E, a top electrode functional layer material film is deposited, the top electrode functional layer material film and the top electrode prefabricated layer material film may be the same, such as Pt, ta, W, and the heavy metals are filled in the openings and the slots, and the top electrode functional layer material film is subjected to chemical mechanical polishing or etching, which is required to ensure the isolation between adjacent memory cells, a top electrode functional layer 412 of an STT-MRAM memory unit is formed in the openings and a top electrode functional layer 512 of an SOT-MRAM memory unit is formed in the slots, and the top electrode functional layer 512 serves as a spin orbit torque providing layer. Of course, a part of the top electrode of the magnetic tunnel junction can be kept to have certain continuity according to the actual electrode preparation requirement.
The preparation method of the magnetic memory provided by the embodiment of the invention utilizes the characteristic that the STT-MRAM and the SOT-MRAM have similar processes, the reference layer, the barrier layer, the free layer and the top electrode can use the same set of material system and can be prepared by one-time film deposition, and the process complexity is reduced.
In addition, the size of the tunnel junction for preparing the STT-MRAM and the size of the tunnel junction for preparing the SOT-MRAM can be adjusted according to requirements, and the tunnel junction for preparing the STT-MRAM has higher thermal stability when being larger in size; the tunnel junction size used to fabricate the SOT-MRAM is small, thermal stability is small but the switching rate is fast and the switching current density is low. In combination with tunnel junctions of different sizes, the retention time of a storage portion for retaining data for a long time in a magnetic memory can be increased, while the write rate of a frequently written data portion is increased and the write current density is reduced. The specific preparation method is not affected by changing the size, and the details are not repeated herein.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (6)

1. A magnetic memory comprising at least one hybrid memory array comprising an adjacently disposed STT-MRAM array and SOT-MRAM array, wherein,
the STT-MRAM array comprises STT-MRAM memory cells arranged in an array, the SOT-MRAM array comprises SOT-MRAM memory cells arranged in an array, the STT-MRAM memory cells and the SOT-MRAM memory cells have a same laminated structure, wherein the STT-MRAM memory cells comprise a first Magnetic Tunnel Junction (MTJ), the SOT-MRAM memory cells comprise a second Magnetic Tunnel Junction (MTJ), the first magnetic tunnel junction and the second magnetic tunnel junction have a same laminated structure;
the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of the same column or row in the STT-MRAM array are the same, and the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of each column or row are gradually reduced from the column or row farthest from the SOT-MRAM array to the column or row closest to the SOT-MRAM array;
the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.
2. A magnetic memory comprising at least one hybrid memory array comprising an STT-MRAM array and an SOT-MRAM array disposed adjacent to each other, wherein,
the STT-MRAM array comprises STT-MRAM memory cells arranged in an array, the SOT-MRAM array comprises SOT-MRAM memory cells arranged in an array, the STT-MRAM memory cells and the SOT-MRAM memory cells have a same laminated structure, wherein the STT-MRAM memory cells comprise a first Magnetic Tunnel Junction (MTJ), the SOT-MRAM memory cells comprise a second Magnetic Tunnel Junction (MTJ), the first magnetic tunnel junction and the second magnetic tunnel junction have a same laminated structure;
and, the STT-MRAM array is divided into a first and a second sub-array of STT-MRAM arranged adjacently, wherein the second sub-array of STT-MRAM is adjacent to the SOT-MRAM array, the diameter size of the first magnetic tunnel junctions of all STT-MRAM storage units in the first sub-array of STT-MRAM is the same; the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of the same column or row in the STT-MRAM second sub-array are the same, and the diameter sizes of the first magnetic tunnel junctions of the STT-MRAM storage units of each column or row are gradually reduced from the column or row farthest from the SOT-MRAM array to the column or row closest to the SOT-MRAM array;
the diameter dimensions of the second magnetic tunnel junctions of all SOT-MRAM memory cells in the SOT-MRAM array are the same.
3. The magnetic memory according to claim 1 or 2,
the STT-MRAM memory cell further comprises a first top electrode coupled to the first magnetic tunnel junction, the first top electrode comprising a first pre-fabricated layer and a first functional layer arranged in a stack, the first pre-fabricated layer in contact with the first magnetic tunnel junction;
the SOT-MRAM memory cell further comprises a second top electrode coupled to the second magnetic tunnel junction, the second top electrode comprising a second pre-fabricated layer and a second functional layer arranged in a stack, the second pre-fabricated layer being in contact with the second magnetic tunnel junction.
4. The magnetic memory of claim 3, wherein the first pre-fabricated layer has a cross-sectional shape and dimensions that are the same as the first magnetic tunnel junction, and the second pre-fabricated layer has a cross-sectional shape and dimensions that are the same as the second magnetic tunnel junction;
the cross section of the first functional layer is circular, and the diameter of the first functional layer is larger than or equal to that of the first magnetic tunnel junction; the cross section of the second functional layer is rectangular, and the width of the second functional layer is larger than or equal to the diameter of the second magnetic tunnel junction.
5. The magnetic memory of claim 3, wherein the first pre-fabricated layer and the second pre-fabricated layer are the same material, selected from one of Pt, ta, W, au and Cu;
the first functional layer and the second functional layer are made of the same material and are selected from one of Pt, ta, W, au and Cu.
6. The magnetic memory according to claim 1 or 2, wherein when the magnetic memory comprises a plurality of hybrid memory arrays, the hybrid memory arrays are arranged in sequence, each hybrid memory array is arranged in the same manner, and the size of the STT-MRAM array and the size of the SOT-MRAM array in different hybrid memory arrays are different from each other.
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