WO2021103785A1 - 显示基板、显示面板和电子设备 - Google Patents

显示基板、显示面板和电子设备 Download PDF

Info

Publication number
WO2021103785A1
WO2021103785A1 PCT/CN2020/117039 CN2020117039W WO2021103785A1 WO 2021103785 A1 WO2021103785 A1 WO 2021103785A1 CN 2020117039 W CN2020117039 W CN 2020117039W WO 2021103785 A1 WO2021103785 A1 WO 2021103785A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
orthographic projection
base substrate
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/117039
Other languages
English (en)
French (fr)
Chinese (zh)
Inventor
王武
姜美存
王小元
毕瑞琳
冯文龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chongqing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/280,667 priority Critical patent/US11835829B2/en
Priority to JP2021568951A priority patent/JP7612609B2/ja
Priority to EP20873342.8A priority patent/EP4067988B1/en
Publication of WO2021103785A1 publication Critical patent/WO2021103785A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G02F1/136245—Active matrix addressed cells having more than one switching element per pixel having complementary transistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to the field of display, and in particular, to a display substrate, a display panel and an electronic device.
  • TFT-LCD thin film transistor liquid crystal display panels
  • the embodiment of the present disclosure provides a display substrate, including: a base substrate; a display area provided on the base substrate and a peripheral area at the periphery of the display area, in which virtual pixel units and virtual data lines are provided ,
  • the dummy pixel unit includes a thin film transistor, the thin film transistor includes a first electrode and a second electrode, the first electrode is one of a source electrode and a drain electrode, and the second electrode is the source electrode and the second electrode.
  • the first electrode is electrically connected to the dummy data line, and the second electrode has a first part and a second part separated by a first fracture.
  • the dummy pixel unit further includes a pixel electrode, the second portion of the second electrode is electrically connected to the pixel electrode, and the thin film transistor further includes an active layer and a gate electrode.
  • the orthographic projection of the gate on the base substrate and the orthographic projection of the active layer on the base substrate at least partially overlap, and the first part of the second electrode is on the base substrate The orthographic projections overlap at least partially.
  • the orthographic projection of the active layer on the base substrate and the orthographic projection of the first part of the second electrode on the base substrate at least partially overlap with the The orthographic projection of the second part of the second electrode on the base substrate does not overlap, and the orthographic projection of the first fracture on the base substrate does not overlap with the orthographic projection of the active layer on the base substrate.
  • the orthographic projection of the grid on the base substrate also does not overlap.
  • the orthographic projection of the active layer on the base substrate and the orthographic projection of the first part of the second electrode on the base substrate at least partially overlap and overlap with The orthographic projection of the second part of the second electrode on the base substrate at least partially overlaps, and the orthographic projection of the first fracture on the base substrate falls into the orthographic projection of the active layer on the base substrate and The gate is in an orthographic projection on the base substrate.
  • the orthographic projection of the first part of the second electrode near the edge of the first fracture on the base substrate and the orthographic projection of the gate on the base substrate One edge is flush.
  • the orthographic projection of the gate on the base substrate completely covers the orthographic projection of the first part of the second electrode on the base substrate.
  • the orthographic projection of the gate on the base substrate partially overlaps the orthographic projection of the second part of the second electrode on the base substrate.
  • the second electrode further has a third part, the second part and the third part are separated by a second fracture, each of the first fracture and the second fracture is on the base substrate
  • the orthographic projection does not overlap with the orthographic projection of the gate on the base substrate and does not overlap with the orthographic projection of the active layer on the base substrate, and at least one of the first part and the third part of the second electrode is on the base substrate
  • the orthographic projection on the grid at least partially overlaps with the orthographic projection of the gate on the base substrate and at least partially overlaps with the orthographic projection of the active layer on the base substrate.
  • the second part of the second electrode passes through The first via structure is electrically connected to the pixel electrode.
  • the display substrate further includes a common electrode, wherein an electrode extension layer is further provided in the peripheral area, the electrode extension layer is electrically connected to the common electrode, and the electrode extension layer is connected to the common electrode.
  • the first electrode, the second electrode and the dummy data line are arranged in the same layer of the same material, and the electrode extension layer is electrically connected to the dummy data line.
  • both ends of the same dummy data line are electrically connected to the electrode extension layer to form a conductive loop that passes through the same dummy data line and the electrode extension layer.
  • the display substrate further includes a common electrode and a connection layer, wherein an electrode extension layer is also provided in the peripheral area, the electrode extension layer is electrically connected to the common electrode, and the connection layer is The pixel electrodes are made of the same material and arranged in the same layer.
  • the connection layer is electrically connected to the common electrode through the second via structure, and is electrically connected to the electrode extension layer through the third via structure.
  • the common electrode includes a first common electrode extension portion and a second common electrode extension portion that are connected to each other, and the extension direction of the first common electrode extension portion and the extension direction of the second common electrode extension portion are mutually connected.
  • Cross the orthographic projection of the connecting layer on the base substrate and the orthographic projection of the second common electrode extension on the base substrate at least partially overlap, the orthographic projection of the first common electrode extension on the base substrate At least partially overlap with the orthographic projection of the pixel electrode on the base substrate.
  • the display substrate further includes a common electrode and a gate line, wherein an electrode extension layer is further provided in the peripheral area, the electrode extension layer is electrically connected to the common electrode, and the electrode extension
  • the layer and the first electrode, the second electrode and the dummy data line are arranged in the same layer with the same material, the gate line and the gate are arranged in the same layer with the same material, and the gate line is on the base substrate
  • the orthographic projection of and the orthographic projection of the electrode extension layer on the base substrate have an overlapping area.
  • the electrode extension layer includes a hollow area, and the orthographic projection of the hollow area on the base substrate at least partially overlaps the orthographic projection of the gate line on the base substrate.
  • An embodiment of the present disclosure also provides a display panel, including the display substrate as described in any of the above embodiments.
  • the embodiments of the present disclosure also provide an electronic device, including the display substrate or the display panel as described in any of the above embodiments.
  • FIG. 1A shows a schematic diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 1B shows a partial schematic diagram in the dashed frame P in FIG. 1A;
  • FIG. 2 shows a schematic structural diagram of a thin film transistor in a display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic structural diagram of a dummy thin film transistor in a peripheral area of a display substrate according to some embodiments of the present disclosure
  • FIG. 4 shows a schematic structural diagram of a dummy thin film transistor in a peripheral area of a display substrate according to other embodiments of the present disclosure
  • FIG. 5 shows a schematic structural diagram of a dummy thin film transistor in a peripheral area of a display substrate according to still other embodiments of the present disclosure
  • FIG. 6 shows a schematic diagram of a partial structure of a peripheral area in a display substrate according to still other embodiments of the present disclosure
  • FIG. 7 shows a cross-sectional view taken along line AA in FIG. 6;
  • FIG. 8 shows a cross-sectional view taken along line BB in FIG. 6;
  • Figure 9 shows a cross-sectional view taken along line CC in Figure 6;
  • FIG. 10 schematically shows a schematic diagram of an electronic device including a display substrate according to an embodiment of the present disclosure.
  • FIG. 1A shows a schematic plan view of the display substrate 100.
  • the display area 20 and the peripheral area 30 are shown in FIG. 1A.
  • FIG. 1B shows the details of the part in the dashed frame at the bottom right of FIG. 1A.
  • the boundary between the display area 20 and the peripheral area 30 is represented by a dashed line.
  • the display substrate 100 includes: a base substrate 10 (see the cross-sectional views of FIGS. 7 to 9 ), and a display area 20 and a peripheral area 30 provided on the base substrate 10.
  • the peripheral area 30 is provided on the periphery of the display area 20.
  • the display area 20 is used to display images.
  • a plurality of pixel units 21 and structures such as data lines and gate lines may be provided.
  • the peripheral area 30 is not used for displaying images, but can be used for wiring wiring and the like, for example.
  • a dummy pixel unit 31 and a dummy data line 32 may be provided in the peripheral area 30.
  • the virtual pixel unit 31 and the virtual data line 32 are similar in structure to the pixel unit 21 and the data line 22 in the display area 20, which helps to provide the pixel unit 21 in the display area 20 close to the peripheral area 30 and located in the display area 20.
  • the pixel unit 21 far away from the peripheral area 30 is in a similar environment.
  • the dummy pixel unit 31 may include a thin film transistor 40.
  • FIGS. 1A and 1B Due to the limitation of the picture frame, the specific structures of the thin film transistor 40' in the display area 20 and the thin film transistor 40 in the peripheral area 30 are not shown in FIGS. 1A and 1B. Examples of their specific structures can be seen in Figs. 2-6.
  • the thin film transistor 40 may include a first electrode 41 and a second electrode 42, the first electrode 41 is electrically connected to the dummy data line 32, and the second electrode 42 has a break ( In order to distinguish it from the subsequent embodiments, it may be referred to herein as a first fracture 43) a first part 421 and a second part 422 that are spaced apart.
  • a case where the first electrode 41 is the source electrode and the second electrode 42 is the drain electrode is taken as an example.
  • the first electrode 41 may also be a drain electrode and the second electrode 42 may be a source electrode.
  • the thin film transistor 40 may further include an active layer 44 and The gate 45 is electrically connected to the gate line 52.
  • the source or drain of the thin film transistor 40 in the dummy pixel unit 31 is disconnected through a fracture.
  • the thin film transistor 40 cannot connect the dummy data line 32 with the pixel electrode 51. Therefore, the gate line 52 electrically connected to the gate 45 of the thin film transistor 40 can be reduced. load. This can not only reduce the power consumption caused by the virtual pixel unit 31, but also help improve the uniformity of brightness.
  • the dummy pixel unit 31 and the dummy data line 32 are to ensure that the pixel unit 21 in the display area 20 close to the peripheral area 30 has a similar process environment to the pixel unit 21 in the display area 20 far away from the peripheral area 30.
  • the dummy data line 32 is also disconnected from the dummy pixel unit 31, so that the dummy data line 32 can also be disconnected from the dummy pixel unit 31. It is used to realize some independent functions, such as conducting test signals, connecting common electrodes and so on.
  • the gate line 52 may be electrically connected to the gate 45 of the corresponding thin film transistor 40, and the orthographic projection of the gate line 52 on the base substrate 10 may also be in line with the dummy data line 32. The orthographic projections on the base substrate 10 cross each other.
  • the disconnection of the source or drain of the thin film transistor 40 is only achieved through the fracture (such as the first fracture 43), which has little effect on the overall layer structure layout of the virtual pixel unit 31, which can make the virtual pixel unit 31
  • the layer structure has a high degree of similarity with the pixel units 21 in the display area 20, so as to achieve the purpose of providing a similar process environment for each pixel unit 21 in the display area 20. This is beneficial for maintaining the uniformity of the display brightness of the display area 20.
  • FIG. 2 shows an example of the thin film transistor 40' in the pixel unit 21 in the display area 20.
  • the first electrode 41' is electrically connected to the data line 22, and the second electrode 42' is complete and does not include a break.
  • FIGS. 3 to 5 respectively show three examples of the thin film transistor 40 in the dummy pixel unit 31 in the peripheral region 30. In these three examples, the first electrode 41 is electrically connected to the dummy data line 32, but the position of the first break 43 is different.
  • the orthographic projection of the first fracture 43 on the base substrate and the orthographic projection of the gate 45 on the base substrate 10 do not overlap and are in contact with the active layer 44.
  • the orthographic projections on the base substrate 10 do not overlap.
  • a part of the orthographic projection of the first portion 421 of the second electrode 42 on the base substrate 10 falls into the orthographic projection of the gate 45 on the base substrate 10, and the other part extends.
  • the gate 45 is outside the orthographic projection on the base substrate 10.
  • the orthographic projection of the first portion 421 of the second electrode 42 on the base substrate 10 completely falls into the orthographic projection of the gate 45 on the base substrate 10.
  • FIG. 4 the orthographic projection of the first portion 421 of the second electrode 42 on the base substrate 10
  • the orthographic projection of the first fracture 43 on the base substrate 10 falls into the orthographic projection of the gate 45 on the base substrate 10 and the orthographic projection of the active layer 44 on the base substrate 10.
  • the orthographic projection of a part of the second portion 422 of the second electrode 42 on the base substrate 10 falls into the orthographic projection of the gate 45 on the base substrate 10 and the orthographic projection of the active layer 44 on the base substrate 10. Orthographic projection.
  • the gate line 52 may be The load is greater. Therefore, the case where the orthographic projection of the first fracture 43 on the base substrate 10 falls outside the orthographic projection of the gate 45 and the active layer 44 on the base substrate 10 is more advantageous.
  • the width of the first aperture 43 be as narrow as possible, so that the structure of the dummy pixel unit 31 and the structure of the pixel unit 21 in the display area 20 can be as similar as possible. This is helpful for reducing load and improving display uniformity.
  • the orthographic projection of the gate 45 on the base substrate 10 and the orthographic projection of the active layer 44 on the base substrate 10 are at least Partially (partially or fully) overlapped, and at least partly (partially or fully) overlapped with the orthographic projection of the first portion 421 of the second electrode 42 on the base substrate 10.
  • the orthographic projection of the active layer 44 on the base substrate 10 and the first portion 421 of the second electrode 42 are in alignment with each other.
  • the orthographic projection on the base substrate 10 at least partially (partially or fully) overlaps, and does not overlap with the orthographic projection of the second portion 422 of the second electrode 42 on the base substrate 10.
  • the orthographic projection of the active layer 44 on the base substrate 10 and the first portion 421 of the second electrode 42 are on the base substrate 10.
  • the orthographic projection of the gate 45 on the base substrate 10 and the first portion 421 of the second electrode 42 on the base substrate overlap at least partially (partially or fully).
  • the orthographic projection of the gate 45 on the base substrate 10 completely covers the first part 421 of the second electrode 42 on the substrate 10 Orthographic projection on the substrate 10. This can prevent the first portion 421 of the second electrode 42 from being excessively extended.
  • the orthographic projection of the gate 45 on the base substrate 10 and the second portion 422 of the second electrode 42 on the base substrate 10 The orthographic projections on are partially overlapped.
  • the orthographic projection of the gate 45 on the base substrate 10 covers the orthographic projection of the active layer 44 on the base substrate 10.
  • the embodiment of the present disclosure is not limited thereto.
  • FIG. 6 shows a schematic diagram of a partial structure of a peripheral area 30 in a display substrate according to still other embodiments of the present disclosure.
  • Two virtual pixel units 31 and one virtual data line 32 are shown.
  • only one structure of the thin film transistor 40 is shown.
  • the thin film transistor 40" in the dummy pixel unit 31 may also include a gate 45, an active layer 44, a first electrode 41, and a second electrode 42.
  • the first electrode 41 is electrically connected to the dummy data line 32.
  • the second electrode 42 has a first portion 421, a second portion 422, and a third portion 421'.
  • the first part 421 and the second part 422 are separated by a first fracture 43
  • the second part 422 and the third part 421' are separated by a second fracture 43'.
  • the third portion 421' may be, for example, farther away from the dummy data line 32 connected to the first electrode 41 than the first portion 421.
  • the third portion 421' of the second electrode 42 The extension direction of the second electrode 42 may be parallel to the extension direction of the first portion 421 of the second electrode 42.
  • the orthographic projection of the first fracture 43 on the base substrate does not overlap with the orthographic projection of the gate 45 on the base substrate 10 and does not overlap with the orthographic projection of the active layer 44 on the base substrate 10. .
  • the orthographic projection of the second fracture 43' on the base substrate and the orthographic projection of the gate 45 on the base substrate 10 do not overlap, and are on the base substrate 10 with the active layer 44.
  • the orthographic projections do not overlap either.
  • the orthographic projection of at least one of the first portion 421 and the third portion 421' of the second electrode 42 on the base substrate may overlap with the orthographic projection of the gate 45 on the base substrate 10 and overlap with the active layer.
  • the orthographic projection of 44 on the base substrate 10 also has an overlapping portion.
  • the second portion 422 of the second electrode 42 may include a first section 427 adjacent to the first fracture 43 and a second section 428 adjacent to the second fracture 43'.
  • the width of the first section 427 is greater than the width of the second section 428, so that the width of the second electrode 42
  • the projection of the second part 422 on the base substrate 10 is in an "L" shape as a whole.
  • the first section 427 has a relatively large width, which facilitates the provision of a via structure in the first section 427 to electrically connect with other conductive layers (for example, the pixel electrode 51).
  • the first electrode 41 in the thin film transistor 40" may have a first extension 411, a second extension 412, and a third extension 413 that are electrically connected to each other.
  • the extension directions of the first portion 421 or the third portion 421' of the second electrode 42 are parallel.
  • the first extension portion 411 may be located between the first portion 421 and the third portion 421' of the second electrode 42.
  • the second extension portion 412 may be located on the side of the first portion 421 of the second electrode 42 away from the third portion 421' of the second electrode 42
  • the third extension portion 413 may be located on the third portion 421' of the second electrode 42 away from the first portion 421'.
  • the dummy pixel unit 31 may further include a pixel electrode 51, and the second part 422 of the second electrode 42 may be connected to the The pixel electrode 51 is electrically connected.
  • the above-mentioned structure of the thin film transistor 40" can improve the load capacity of the gate line compared with the structure of the thin film transistor shown in FIG.
  • the width of the first fracture 43 and the second fracture 43' may be, for example, 2 micrometers to 5 micrometers.
  • Fig. 7 is a cross-sectional view taken along line AA in Fig. 6.
  • the film structure of the thin film transistor 40" can be seen more clearly from FIG. 7.
  • the display substrate 100 may include a first insulating layer 71 and a second insulating layer 72.
  • the first insulating layer 71 such as a gate
  • the polar insulating layer is located between the gate 45 and the active layer 44.
  • the second insulating layer 72 such as a planarization layer or an interlayer dielectric layer, is located between the layer where the pixel electrode 51 is located and the thin film transistor 40.
  • the first portion 421, the second portion 422, and the third portion 421' of the first electrode 41 and the second electrode 42 may be made of the same material (for example, metal or alloy materials such as titanium and aluminum) and arranged on the same layer.
  • the first fracture 43 Separate the first portion 421 and the second portion 422 of the second electrode 42.
  • the active layer 44 is located between the layer where the first electrode 41 and the second electrode 42 are located and the first insulating layer 71.
  • the pixel electrode 51 may pass through the first insulating layer 71, for example.
  • a via structure 511 is electrically connected to the second portion 422 of the second electrode 42.
  • the first via structure 511 can be formed by forming a through hole in the second insulating layer 72 and then coating the through hole with a conductive layer.
  • the conductive layer (for example, a metal layer) in the first via structure 511 can be made of the same material and arranged in the same layer as the pixel electrode 51.
  • the first via structure 511 can penetrate the second insulating layer 72 and the second insulating layer 72 and the second insulating layer.
  • the second part 422 of the electrode 42 is in contact.
  • the display substrate 100 may also include a common electrode 53.
  • the common electrode 53 and the pixel electrode 51 can apply necessary voltages to the pixel unit to realize the display function.
  • an electrode extension layer 33 is further provided in the peripheral region 30, and the electrode extension layer 33 is electrically connected to the common electrode 53.
  • the electrode extension layer 33 can be used to increase the area of the common electrode 53 to improve signal performance. Stability.
  • the electrode extension layer 33 may be arranged in the form of a large conductive layer, as shown in Figure 6.
  • the electrode extension layer 33 may be in contact with the first electrode 41, the second electrode 42 and The dummy data lines 43 are arranged in the same layer with the same material to simplify the process.
  • a connection layer 34 may also be provided to facilitate electrical connection between the common electrode 53 and the electrode extension layer 33.
  • the connection layer 34 and the pixel electrode 51 may be made of the same material and arranged in the same layer.
  • the connection layer 34 is electrically connected to the common electrode 53 through the second via structure 61 and is electrically connected to the common electrode 53 through the third via structure 62. It is electrically connected to the electrode extension layer 33.
  • the second via structure 61 may be formed by forming a through hole passing through the first insulating layer 71 and the second insulating layer 72 and then coating the through hole with a conductive layer (for example, a metal layer).
  • the third via structure 62 may be formed by forming a through hole through the second insulating layer 72 and then coating the through hole with a conductive layer. It can be clearly seen from FIG. 8 that the conductive layer in the second via structure 61 and the connection layer 34 may be made of the same material and arranged in the same layer. The second via structure 61 may penetrate the first insulating layer 71 and the second insulating layer 72 to be in contact with the common electrode 53. Similarly, the third via structure 62 and the connection layer 34 may be made of the same material and arranged in the same layer. The third via structure 62 may penetrate the second insulating layer 72 to be in contact with the electrode extension layer 33. However, the embodiment of the present disclosure is not limited thereto. For example, the common electrode 53 and the electrode extension layer 33 may also be directly electrically connected without the connection layer 34.
  • the common electrode 53 may include a first common electrode extension 531 and a second common electrode extension 532 that are connected to each other.
  • the second via structure 61 is formed at the second common electrode extension 532 for electrically connecting the second common electrode extension 532 and the connection layer 34.
  • the second common electrode extension 532 may be arranged to extend along the edge of the electrode extension layer 33 to better arrange the second via structure 61, especially when a plurality of second via structures 61 are provided.
  • the first common electrode extension 531 of the common electrode 53 may extend from the second common electrode extension 532 and the gate line 52 substantially side by side. This does not mean that the extension direction of the first common electrode extension 531 of the common electrode 53 and the extension direction of the gate line 52 must be parallel.
  • the first common electrode extension 531 may extend zigzag in order to bypass the transistor and other structures ( As shown in Figure 6).
  • the first common electrode extension 531 may cross the dummy data line 32.
  • the overall extension direction of the first common electrode extension 531 from the second common electrode extension 532 can be defined as the first direction (the x direction in FIG. 6), and the second common electrode extension 532 The extension direction is defined as the second direction (the y direction in Fig. 6).
  • the first direction and the second direction are approximately ninety degrees, and the first common electrode extension 531 and the second common electrode extension 532 of the common electrode 53 form an L-shaped structure.
  • the design of this structure facilitates the electrical connection between the common electrode 53 and the connection layer 34.
  • the embodiment of the present disclosure is not limited thereto, for example, the overall extension direction of the first common electrode extension 531 and the extension direction of the second common electrode extension 532 may not be perpendicular.
  • the orthographic projection of the connection layer 34 on the base substrate 10 and the orthographic projection of the second common electrode extension 532 on the base substrate 10 at least partially overlap, for example, the connection layer
  • the orthographic projection of 34 on the base substrate 10 completely covers the orthographic projection of the second common electrode extension 532 on the base substrate 10. This facilitates the layout of the second via structure 61.
  • the orthographic projection of the first common electrode extension 532 on the base substrate 10 and the orthographic projection of the pixel electrode 51 on the base substrate 10 may at least partially overlap.
  • the orthographic projection of the first common electrode extension 531 on the base substrate 10 and the orthographic projection of the dummy data line 32 on the base substrate 10 cross each other.
  • the electrode extension layer 33 is electrically connected to the dummy data line 32. This allows the dummy data line 32 to also be electrically connected to the common electrode 53, which further increases the actual area of the common electrode 53 and improves the stability of the signal.
  • both ends of the same dummy data line 32 may be electrically connected to the electrode extension layer 33 to form a conductive loop passing through the same dummy data line 32 and the electrode extension layer 33.
  • This structure can make the potential distribution on the common electrode 53 more uniform. For example, if the dummy data line 32 is disconnected and cannot form a conductive loop with the electrode extension layer 33, there may be a relatively large potential difference on both sides of the fracture of the dummy data line 32.
  • the same dummy data line 32 and the electrode extension layer 33 constitute a conductive loop, which helps to reduce this excessive potential difference as much as possible, which is beneficial to realize the brightness uniformity of the display pixels in the display area 20.
  • the first insulating layer 71 may be located on a side of the common electrode 53 away from the base substrate 10 and on a side of the electrode extension layer 33 facing the base substrate 10.
  • the second insulating layer 72 may be located between the electrode extension layer 33 and the connection layer 34 and located on the side of the active layer 44 away from the base substrate 10.
  • a gate line 52 is provided on the display substrate 100, and the electrode extension layer 33 is made of the same material as the first electrode 42, the second electrode 42, and the dummy data line 32.
  • Layer arrangement, the gate line 52 and the gate electrode 45 are arranged in the same layer with the same material.
  • the orthographic projection of the gate line 52 on the base substrate 10 and the orthographic projection of the electrode extension layer 33 on the base substrate 10 have an overlapping area.
  • the electrode extension layer 33 overlaps the gate line 52, which is beneficial to the wiring on the display substrate 100, and the electrode extension layer 33 can also have as large an area as possible to improve signal stability.
  • the electrode extension layer 33 may include a hollow area 35.
  • the orthographic projection of the hollow area 35 on the base substrate 10 and the orthographic projection of the gate line 52 on the base substrate 10 at least partially (partially or fully) overlap.
  • the conductive layer portion of the electrode extension layer 33 is removed.
  • One or more hollow regions 35 are provided where the gate line 52 and the electrode extension layer 33 overlap, which can reduce the electrode extension layer 33 (for example, the layer where the first electrode 41 and the second electrode 42 are located) and the gate line 52
  • the parasitic capacitance between the layers prevents the increase in the area of the conductive layer caused by the electrode extension layer 33 to significantly increase the parasitic capacitance, thereby preventing uneven brightness due to the difference in parasitic capacitance.
  • the embodiments of the present disclosure are not limited thereto, and the display substrate 100 may also include more virtual pixel units.
  • the embodiments of the present disclosure also provide a display panel, which may include the display substrate 100 according to any of the above-mentioned embodiments.
  • the display substrate and the display panel according to the embodiments of the present disclosure can be used not only in thin film transistor type liquid crystal display devices, but also in other types of display devices such as organic light emitting diodes (OLED).
  • the display panel in the embodiment of the present disclosure may be, for example, a thin film transistor type liquid crystal display panel, or may be any other type of display panel known in the art such as an organic light emitting diode (OLED) display panel.
  • the display device in the embodiment of the present disclosure may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, etc.
  • an embodiment of the present disclosure also provides an electronic device 200.
  • the electronic device 200 includes the display substrate 100 according to any one of the foregoing embodiments.
  • the electronic device can be, for example, any display device, such as a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a car monitor, an e-book, and so on.
  • the “same layer arrangement” mentioned in the present disclosure means that the involved layers are formed at the same time in the same process step, but it does not mean that these layers must have the same thickness or height in the cross-sectional view. Using the design of "same layer setting" can simplify the manufacturing process of the display substrate and the display panel as much as possible.
  • Each conductive layer in the embodiment of the present disclosure may be made of conductive metal, or may be made of non-metallic conductive material.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
PCT/CN2020/117039 2019-11-28 2020-09-23 显示基板、显示面板和电子设备 Ceased WO2021103785A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/280,667 US11835829B2 (en) 2019-11-28 2020-09-23 Display substrate having dummy pixel, display panel, and electronic device
JP2021568951A JP7612609B2 (ja) 2019-11-28 2020-09-23 表示基板、表示パネルおよび電子機器
EP20873342.8A EP4067988B1 (en) 2019-11-28 2020-09-23 Display substrate, display panel and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911212220.XA CN112859466B (zh) 2019-11-28 2019-11-28 显示基板和显示面板
CN201911212220.X 2019-11-28

Publications (1)

Publication Number Publication Date
WO2021103785A1 true WO2021103785A1 (zh) 2021-06-03

Family

ID=75996024

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/117039 Ceased WO2021103785A1 (zh) 2019-11-28 2020-09-23 显示基板、显示面板和电子设备

Country Status (5)

Country Link
US (1) US11835829B2 (cg-RX-API-DMAC7.html)
EP (1) EP4067988B1 (cg-RX-API-DMAC7.html)
JP (1) JP7612609B2 (cg-RX-API-DMAC7.html)
CN (1) CN112859466B (cg-RX-API-DMAC7.html)
WO (1) WO2021103785A1 (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113555409A (zh) * 2021-07-21 2021-10-26 京东方科技集团股份有限公司 显示装置、显示面板及其制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116034316B (zh) * 2021-08-27 2025-07-04 京东方科技集团股份有限公司 显示基板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103676381A (zh) * 2013-12-26 2014-03-26 南京中电熊猫液晶显示科技有限公司 一种液晶显示器及其驱动装置
CN108121119A (zh) * 2016-11-29 2018-06-05 乐金显示有限公司 液晶显示器
US20180157114A1 (en) * 2016-12-01 2018-06-07 Samsung Display Co., Ltd. Reflective liquid crystal device
CN109426041A (zh) * 2017-08-21 2019-03-05 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN210573114U (zh) * 2019-11-28 2020-05-19 京东方科技集团股份有限公司 显示基板和显示面板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493129A (en) * 1988-06-29 1996-02-20 Hitachi, Ltd. Thin film transistor structure having increased on-current
JP3205373B2 (ja) * 1992-03-12 2001-09-04 株式会社日立製作所 液晶表示装置
JP4102912B2 (ja) 1999-11-24 2008-06-18 カシオ計算機株式会社 アクティブ型液晶表示パネル
KR100626600B1 (ko) * 2000-08-02 2006-09-22 엘지.필립스 엘시디 주식회사 액정 표시 장치용 어레이 기판 및 그 제조 방법
JP4770103B2 (ja) * 2002-08-06 2011-09-14 ソニー株式会社 半導体装置
JP2006030627A (ja) 2004-07-16 2006-02-02 Sharp Corp 表示装置用基板及びそれを用いた液晶表示装置
KR20080024278A (ko) * 2006-09-13 2008-03-18 삼성전자주식회사 박막 트랜지스터 표시판 및 이를 포함하는 액정 표시 장치
JP2010276665A (ja) * 2009-05-26 2010-12-09 Panasonic Liquid Crystal Display Co Ltd 表示装置
CN103969859B (zh) 2014-04-22 2016-08-24 京东方科技集团股份有限公司 一种显示用基板及显示装置
CN104465675B (zh) * 2014-12-31 2017-08-25 深圳市华星光电技术有限公司 薄膜晶体管阵列基板、液晶面板以及液晶显示器
KR102336419B1 (ko) * 2015-04-30 2021-12-06 엘지디스플레이 주식회사 액정 표시 장치용 어레이 기판
KR102576999B1 (ko) * 2016-07-05 2023-09-12 삼성디스플레이 주식회사 액정표시장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103676381A (zh) * 2013-12-26 2014-03-26 南京中电熊猫液晶显示科技有限公司 一种液晶显示器及其驱动装置
CN108121119A (zh) * 2016-11-29 2018-06-05 乐金显示有限公司 液晶显示器
US20180157114A1 (en) * 2016-12-01 2018-06-07 Samsung Display Co., Ltd. Reflective liquid crystal device
CN109426041A (zh) * 2017-08-21 2019-03-05 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN210573114U (zh) * 2019-11-28 2020-05-19 京东方科技集团股份有限公司 显示基板和显示面板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113555409A (zh) * 2021-07-21 2021-10-26 京东方科技集团股份有限公司 显示装置、显示面板及其制作方法

Also Published As

Publication number Publication date
JP2023503204A (ja) 2023-01-27
CN112859466B (zh) 2025-04-22
EP4067988A4 (en) 2023-01-11
EP4067988A1 (en) 2022-10-05
US20220043315A1 (en) 2022-02-10
CN112859466A (zh) 2021-05-28
JP7612609B2 (ja) 2025-01-14
US11835829B2 (en) 2023-12-05
EP4067988B1 (en) 2025-11-19

Similar Documents

Publication Publication Date Title
US11950464B2 (en) Display panel and electronic device
CN210573114U (zh) 显示基板和显示面板
CN108831302B (zh) 显示面板及显示装置
US20180292693A1 (en) A display panel and an array substrate thereof
US20160372490A1 (en) Array substrate and manufacturing method thereof, and display panel
US11774818B2 (en) Display panel and electronic apparatus
US10199397B2 (en) Electrical connection structure, array substrate and display device
US20180366492A1 (en) Array Substrate, Display Panel, Manufacturing Method, and Display Device
WO2021083298A1 (zh) 一种显示基板及其制作方法、显示装置
US10147744B2 (en) Array substrate, method of manufacturing the same, and display device
US11387310B2 (en) Array substrate with connection portion connecting power bus and power line and display panel
WO2018054098A1 (zh) 阵列基板及其制造方法、显示面板和显示设备
WO2018126676A1 (zh) 像素结构及其制作方法、阵列基板和显示装置
CN116524811A (zh) 一种显示面板及显示装置
US12235556B2 (en) Display substrate, display panel and display device
CN106094373A (zh) Tft基板及其制作方法
WO2013037236A1 (zh) 阵列基板及液晶显示面板
US20180329248A1 (en) Flat display panel and method of manufacturing the same
WO2021103785A1 (zh) 显示基板、显示面板和电子设备
CN117460334A (zh) 阵列基板和显示面板
CN101561609A (zh) 主动阵列基板、液晶显示面板及制造主动阵列基板的方法
WO2018176809A1 (zh) 阵列基板及其制作方法、显示装置
US20250273138A1 (en) Array substrate and display apparatus
US12527182B2 (en) Array substrate, display apparatus, and method of fabricating array substrate
US12501791B2 (en) Array substrate and display apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20873342

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021568951

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020873342

Country of ref document: EP

Effective date: 20220628

ENP Entry into the national phase

Ref document number: 2020873342

Country of ref document: EP

Effective date: 20220628

WWG Wipo information: grant in national office

Ref document number: 2020873342

Country of ref document: EP