WO2021103618A1 - Configuration of operating frequency of chip - Google Patents

Abstract

Embodiments of the present disclosure provide a method and device for configuring the operating frequency of a chip. The method comprises: acquiring multiple subtasks of a target task and task parameters of each subtask, wherein the task parameters comprise a parameter indicating the scale of computation of the subtask; determining, on the basis of the task parameters of each of the multiple subtasks, a target chip frequency of each subtask; and configuring, according to the determined target chip frequencies corresponding to the respective subtasks, operating frequencies of a chip when executing the respective subtasks.

Description

Chip working frequency setting Technical field

The present disclosure relates to smart device technology, in particular to a method and device for setting the operating frequency of a chip.

Background technique

With the development of 5G and artificial intelligence technology, end devices (for example, smart phones, smart cameras, etc.) are given more computing requirements and need to perform more tasks. However, most of the chips used for computing processing included in the end device have power consumption limitations, and cannot fully utilize the computing peak capability of the device. Frequency reduction is one of the main methods of preventing excessive power consumption of the chip. The frequency reduction technology mainly reduces the power consumption of the chip by temporarily reducing the operating frequency of the chip (frequency).

In some technologies, an initial operating frequency can be set before the application program is executed in the terminal device, and the chip runs at the initial operating frequency to perform calculation processing on the application program. In addition, during the operation of the application program, when the power consumption of the chip exceeds the standard, a fixed frequency reduction strategy can be adopted for the chip, for example, the working frequency of the chip is reduced by a fixed ratio, or the working frequency is reduced to A fixed value.

Summary of the invention

The embodiments of the present disclosure provide at least a method and device for setting the operating frequency of a chip.

In a first aspect, a method for setting the operating frequency of a chip is provided. The method includes: acquiring a plurality of subtasks of a target task and task parameters of each subtask, the task parameters including parameters used to indicate the operation scale of the subtasks Based on the task parameters of each subtask in the multiple subtasks, determine the target chip frequency of each subtask; according to the determined target chip frequency of each subtask, set the operating frequency of the chip to execute each subtask.

According to any embodiment of the present disclosure, the method further includes: performing task analysis processing on the target task to obtain the multiple subtasks and the task parameters of each subtask; storing each subtask and each subtask in the multiple subtasks The corresponding relationship of the task parameters of each subtask; the obtaining multiple subtasks of the target task and the task parameters of each subtask includes: searching the task parameters of each subtask from the stored corresponding relationships.

According to any embodiment of the present disclosure, the task parameter includes at least one of the following: a calculation amount of the subtask, and a memory access amount of the subtask.

According to any embodiment of the present disclosure, the determining the target chip frequency of each subtask based on the task parameter of each subtask of the plurality of subtasks includes: acquiring device information of the device where the chip is located, and The device information includes device resource information; the target chip frequency of each subtask is determined based on the device information and the task parameter of each subtask of the multiple subtasks.

According to any embodiment of the present disclosure, the device resource information includes any one or more of the following: the number of computing units, bandwidth, and memory capacity.

According to any one of the embodiments of the present disclosure, the device information further includes: the chip temperature of the chip; the determining each subtask based on the device information and the task parameter of each subtask of the plurality of subtasks The target chip frequency of includes: determining the target of the first subtask based on the task parameters of the first subtask among the plurality of subtasks, the device resource information, and the chip temperature during execution of the first subtask Chip frequency.

According to any embodiment of the present disclosure, the determining the target chip frequency of each subtask based on the device information and the task parameter of each subtask of the plurality of subtasks includes: acquiring a plurality of first data and A preset mapping relationship between a plurality of second data, the first data includes preset task parameters and preset device information, the second data includes a preset chip frequency; according to the preset mapping relationship, the Device information and task parameters of each subtask determine the target chip frequency of each subtask.

According to any embodiment of the present disclosure, the determining the target chip frequency of each subtask according to the preset mapping relationship, the device information, and the task parameters of each subtask includes: determining the third data and the task parameters of each subtask. The distance between each first data in the plurality of first data in the preset mapping relationship, the third data includes task parameters and device information of the first subtask among the plurality of subtasks; It is assumed that the preset chip frequency corresponding to the target first data closest to the third data in the mapping relationship is used as the target chip frequency of the first subtask.

According to any embodiment of the present disclosure, before the obtaining the preset mapping relationship between the plurality of first data and the plurality of second data, the method further includes: obtaining a plurality of sets of optional chip frequencies, and obtaining samples obtained A plurality of discrete first data; for each of the first data in the plurality of first data, a set of chip frequencies is selected from the plurality of sets of optional chip frequencies as the The data corresponds to the second data, and a mapping relationship between each of the first data and the selected second data is established.

According to any embodiment of the present disclosure, the preset chip frequency corresponding to the first data in the preset mapping relationship is based on the second chip frequency under the condition of each group of selectable chip frequencies in the multiple sets of selectable chip frequencies. The performance evaluation parameter corresponding to one data is selected from the multiple sets of optional chip frequencies.

According to any embodiment of the present disclosure, the performance evaluation parameters include task processing performance parameters and chip operating power consumption; the preset chip frequency corresponding to the first data in the preset mapping relationship is: the multiple groups Among the optional chip frequencies, the chip operating power consumption is lower than the preset power consumption and the optional chip frequency with the best task processing performance parameters.

According to any embodiment of the present disclosure, the method further includes: receiving configuration information input by a user for the preset mapping relationship.

According to any embodiment of the present disclosure, the determining the target chip frequency of each subtask based on the task parameter of each subtask in the plurality of subtasks includes: The task parameters are selected from multiple sets of selectable chip frequencies, and the chip frequency that enables the chip to achieve the lowest task running time under the restriction of chip power consumption is selected as the target chip frequency.

According to any embodiment of the present disclosure, the method further includes: receiving frequency setting strategy information input by a user; and determining the target chip of each subtask based on the task parameter corresponding to each subtask in the plurality of subtasks The frequency includes: determining the target chip frequency of each subtask based on the frequency setting strategy information and the task parameter of each subtask of the multiple subtasks.

According to any embodiment of the present disclosure, the frequency setting strategy information includes enabling or disabling the chip frequency dynamic setting function for subtasks.

According to any embodiment of the present disclosure, the operating frequency includes at least one of the following: a core frequency of the chip or a memory frequency.

In a second aspect, a device for setting the operating frequency of a chip is provided. The device includes: an acquisition module for acquiring multiple subtasks of a target task and task parameters of each subtask. The task parameters include A parameter of the calculation scale of the task; a frequency control module for determining the target chip frequency of each subtask based on the task parameters of each of the multiple subtasks; a frequency setting module for determining each subtask according to the task parameters The target chip frequency is to set the working frequency of the chip to execute each subtask.

In a third aspect, an electronic device is provided, including: a memory and a processor, the memory is configured to store machine-readable instructions, and the processor is configured to invoke the machine-readable instructions to implement the first aspect of the present disclosure method.

According to any embodiment of the present disclosure, the device further includes: a chip configured to process each subtask in the target task based on the operating frequency set by the processor.

In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the processor is prompted to implement the method described in the first aspect of the present disclosure.

The method and device for setting the working frequency of a chip provided by the embodiments of the present disclosure determine the target chip frequency of each subtask in the target task based on the task parameters of the subtask, so that the chip can use the subtask when executing each subtask. The target chip frequency runs at the target chip frequency. This refined frequency setting method enables the implementation of each sub-task to achieve the best operating performance as much as possible, thereby increasing the operating speed of the entire task.

Description of the drawings

Fig. 1 shows a flowchart of a method for setting a chip operating frequency provided by some embodiments of the present disclosure.

Fig. 2 shows another flowchart of a method for setting a chip operating frequency provided by some embodiments of the present disclosure.

FIG. 3 shows another flowchart of the process of establishing a preset mapping relationship provided by some embodiments of the present disclosure.

FIG. 4 shows another flowchart of a method for setting the operating frequency of a chip provided by some embodiments of the present disclosure.

Fig. 5 shows a block diagram of a device for setting the operating frequency of a chip provided by some embodiments of the present disclosure.

FIG. 6 shows another block diagram of the device for setting the operating frequency of a chip provided by some embodiments of the present disclosure.

Fig. 7 shows a block diagram of an electronic device with a chip operating frequency provided by some embodiments of the present disclosure.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of the present disclosure, in the following, in conjunction with the drawings in one or more embodiments of the present disclosure, a comparison of the technical solutions in one or more embodiments of the present disclosure The technical solution is described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on one or more embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work shall fall within the protection scope of the present disclosure.

The embodiments of the present disclosure provide a method for setting the operating frequency of a chip in a terminal device. The method aims to make the operating performance of the device better when the chip runs at the set operating frequency, for example, tasks running on the device It can be processed at a faster speed. Among them, the chip can be an artificial intelligence (AI) chip, for example, an AI chip used in a smartphone, an AI chip used in an autonomous vehicle, an AI chip used in edge devices of the Internet of Things, etc. Wait. It may also be other types of chips, such as a CPU (Central Processing Unit) chip, a DSP (Digital Signal Processing), a memory chip, etc., which are not limited in the embodiment of the present disclosure.

Fig. 1 shows a flow chart of a method for setting the operating frequency of a chip provided by some embodiments of the present disclosure. As shown in Fig. 1, the method may include the following processing.

In step 100, a plurality of subtasks of the target task and task parameters of each subtask are acquired, the task parameters including parameters used to indicate the operation scale of the subtasks.

In this step, the target task may be a task to be executed and processed on the device. For example, the task may be a training task of a deep learning model, or an inference task of a neural network model, or running an application program, etc. The execution of the target task requires the use of a chip on the device, and the chip is responsible for part or all of the processing work such as calculations during the execution of the task.

The subtask may be a relatively independent execution unit included in the target task. For example, the target task can include multiple functions, which can be divided according to functions, and each function is used as an independent subtask in the target task. For another example, the task code can also be divided into multiple code blocks and subtasks are divided according to the code blocks, and each piece of code is relatively complete. For example, a relatively complete or independent code block as a subtask. For another example, when the target task is the training or inference task of a neural network model, each layer or layers of the neural network model can be regarded as a subtask; or, it can also be the code segment of the realization process of each layer As a subtask. For another example, one or at least two of the multiple functional modules can also be used as a subtask, and so on.

The embodiments of the present disclosure do not limit the way of dividing subtasks, and there may be multiple ways of dividing subtasks, such as the above-mentioned function as a unit, code block as a unit, network layer or operator as a unit, or function module as a unit. It should be noted that although dividing the target task into multiple sub-tasks can achieve fine-grained frequency settings and improve equipment operating performance, too many sub-tasks may cause more frequent frequency settings. It has a certain impact on the operating performance of the equipment. Therefore, you can balance the settings of the number of subtasks. For example, try not to divide the inside of the loop body included in the target task into subtasks to reduce the number of frequency settings. The specific settings can be based on actual conditions. Needs to proceed, so I won’t go into details here.

In the embodiment of the present disclosure, the task parameter of the subtask may include a parameter used to indicate the calculation scale of the subtask, for example, may include a parameter used to indicate one or more resources that the subtask needs to occupy. As an example, the task parameters may include but are not limited to at least one of the following: calculation amount of the subtask, memory access (memory access is the number of times the chip accesses the memory and/or the total amount of data accessed when the subtask is executed), Or, it may also include other types of task parameters, which are not limited in the embodiment of the present disclosure.

In the embodiments of the present disclosure, the task parameters of the subtasks can be obtained in various ways. For example, obtain task parameters of subtasks from other devices or from other functional modules in the system, or obtain task parameters of subtasks from local storage, or obtain task parameters of each subtask by performing task analysis on the target task. and many more.

In some embodiments, in order to obtain the task parameter more quickly, the correspondence between each subtask and the respective task parameter may be stored in advance. Exemplarily, task analysis processing may be performed on the target task in advance to obtain multiple subtasks included in the target task and task parameters of each subtask, and each subtask and its task parameters are stored. In this way, when the target task needs to be run, the task parameters of each subtask can be quickly found based on the stored information. In some examples, the correspondence between the subtasks and task parameters can be stored in the form of key-value. For example, corresponding task IDs can be set for multiple subtasks, and the task IDs of the subtasks can be stored as keys , And store the task parameters of this subtask as value. The key-value storage method is suitable for querying through the primary key, with fast query speed and large amount of stored data. But the present disclosure is not limited to this.

In some embodiments, in addition to obtaining the task parameters of each subtask, device information of the device where the chip is located can be further obtained, and the target chip frequency of each subtask can be jointly determined based on the device information and task parameters.

Wherein, the aforementioned device information may include device resource information of the device where the chip is located. The device resource information is used to indicate information about the available resources of the device. As an example, the device resource information may include, but is not limited to, any of the following or Multiple device resource information: the number of computing units, bandwidth, memory capacity, etc. In some embodiments, the target chip frequency of each subtask may also depend on the dependency between multiple subtasks or the task execution mode, such as serial, parallel, or serial between partial subtasks and partial subtasks. Parallel and so on. For example, if the execution of each subtask obtained by the division of the target task is in a serial relationship, then the chip can occupy all available device resources on the device when executing each subtask, such as occupying all computing units and all bandwidth on the device. And so on, but the embodiments of the present disclosure are not limited thereto.

In step 102, the target chip frequency of each subtask is determined based on the task parameter of each subtask in the plurality of subtasks.

In this step, the target chip frequency of each subtask can be determined according to the task parameters of the subtask. Alternatively, the target chip frequency of each subtask may be jointly determined based on the device information of the device where the chip is located and the task parameters of each subtask.

In some embodiments, multiple sets of optional chip frequencies may be determined, and a corresponding optional chip frequency may be selected for each subtask from the multiple sets of optional chip frequencies based on a certain strategy. Wherein, the multiple sets of optional chip frequencies are a specific number of discrete frequencies that can be set by the chips in the device. For example, taking setting the core frequency of the chip as an example, the core frequency may include m frequency values such as x1, x2...xm. The aforementioned strategies can be set based on actual needs. Several exemplary strategies will be described below, but the embodiments of the present disclosure are not limited thereto.

In some embodiments, the determination of the target chip frequency can be transformed into an optimization problem. In some alternative implementations, the task running time can be used as the main reference factor for selection. As an example, it can be based on each sub The task parameters of the task, among the multiple sets of optional chip frequencies that can be set, select the chip frequency that enables the chip to achieve the lowest task running time under the restriction of chip power consumption, as the target chip frequency of each subtask . Among them, in some examples, multiple subtasks can be analyzed as a whole to determine the overall task running time of the target task. At this time, under the condition of determining the shortest task running time, each of the multiple subtasks can be obtained at the same time. The target chip frequency of each subtask. Or, in other examples, the task running time of each subtask can be analyzed separately, and the target chip frequency of the subtask can be determined based on the shortest task running time of each subtask as a condition, and so on. In other optional implementation manners, one or any of the system resources consumed by the task, chip operating power consumption, task operating speed, and task execution result accuracy can also be selected as reference factors. This is not limited.

In the following, the target chip frequency is determined according to the task parameters and device information of the subtasks as an example to illustrate the principle of solving an optimization problem. Take one of the subtasks as an example. The task parameter of the subtask is k ⁿ (n represents the n-dimensional space, such as the amount of memory access, the amount of calculation, etc.), and the device information corresponding to the subtask is d ^m (m represents the m-dimensional space, Such as memory capacity, etc.), and assume that the chip frequency is x, where the frequency can be a core frequency, a memory frequency, or a frequency combination of a core frequency and a memory frequency. P(k ⁿ , d ^m , x) represents the operating power consumption of the chip. It can be seen that the operating power consumption of the chip is related to task parameters, device information and chip frequency. Even if the task parameters and device information are fixed and the chip frequency changes, P will Will change accordingly. T(k ⁿ , d ^m , x) represents the task running time. Similarly, even if the task parameters and device information are fixed, T will change when the chip frequency changes. Then you can combine the task parameters and device information of the above subtasks with multiple chip frequencies to obtain the corresponding chip operating power consumption and task operating time, and select from multiple chip frequencies based on the chip operating power consumption and task operating time The optimal chip frequency for each subtask.

For example, the optimal chip frequency can be selected according to the following formula (1):

The above formula (1) indicates that the lowest task running time is achieved under the condition of chip power consumption limit (not exceeding Power _Limited ), which is the optimization goal of the optimization problem. Find the optimal chip frequency with this optimization goal. Among the multiple optional chip frequencies that the chip can set, if a certain chip frequency is used, the subtask can be processed with the shortest task running time under the condition of chip power consumption. , The chip frequency is the target chip frequency of the subtask.

Since at least one parameter in the task parameter and the device information of each subtask may be different, the target chip frequency of each subtask may also be different. In this step, the target chip frequency that best matches each subtask can be found, so that the subtask is completed at the fastest speed and the chip does not exceed the power consumption.

In step 104, according to the determined target chip frequency of each subtask, the operating frequency of the chip when each subtask is executed is set.

In this step, during the running process of the target task, when one of the subtasks is run, the chip frequency can be set as the target chip frequency of the subtask, or it can be based on the target chip frequency and the device or chip executing The current status information of the subtask, for example, the status information of the device or the chip when the chip starts to execute the subtask, such as the chip temperature, is used to set the operating frequency of the chip when the subtask is executed. Among them, in some embodiments, the above process of determining the target chip frequency may be performed uniformly before executing the target task, and the target chip frequency of each of the multiple subtasks is stored, and then, in the process of running each subtask, Set the chip frequency to the target chip frequency of the subtask. In other embodiments, the target chip frequency of each subtask may also be determined before the execution of each subtask. For example, the target chip frequency of the subtask may be determined based on the task parameters of the subtask and the current state information of the device or chip. Frequency. At this time, the determination of the target chip frequency of each subtask may be performed at different times, which is not limited in the embodiment of the present disclosure.

In the embodiment of the present disclosure, the operating frequency of the chip may include at least one of the following: the core frequency of the chip or the memory frequency. For example, the method of the embodiment of the present disclosure can be used only to set the core frequency of the chip, where the memory frequency can be set to a fixed value or set in the unit of the target task, or the method is only used to set the memory frequency, where the core The frequency can be set as a fixed value or set in the unit of the target task, or this method is used to set the core frequency and memory frequency of the chip, for example, the core frequency and the memory frequency are set as a combination of frequencies, and the target chip of each subtask Frequency is the combination of frequencies.

The frequency of the memory may be the frequency of a volatile memory, such as the frequency of SDRAM (Synchronous Dynamic Random Access Memory). For example, DDR SDRAM (Double Data Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, and so on. The frequency of the memory may also be the frequency of a non-volatile memory, such as the frequency of a flash memory.

The method for setting the working frequency of the chip in the embodiment of the present disclosure determines the target chip frequency of each subtask based on the task parameters of each subtask in the target task, so that the chip can use the target chip of the subtask when executing each subtask. Frequency operation. This refined frequency setting method can achieve the optimal operating performance as much as possible when executing each subtask, thereby increasing the operating speed of the entire task.

Figure 2 provides another flow chart of a method for setting chip operating frequency in some embodiments of the present disclosure. The method takes the target chip frequency jointly determined according to the task parameters and device information of the subtasks as an example, and exemplarily shows A way to determine the frequency of the target chip. As shown in FIG. 2, the method may include the following processing, wherein the same steps as those in FIG. 1 will not be described in detail.

In step 200, task analysis is performed on the target task to be run on the device to obtain multiple subtasks and task parameters of each of the subtasks. For example, the task parameter of each subtask may include at least one of the following: the calculation amount and the memory access amount of the subtask.

In step 202, the device information of the device where the chip is located is obtained.

For example, the device information of the device where the chip is located may include device resource information, and the device resource information may include at least one of the following: bandwidth, number of computing units, memory capacity, and so on.

In step 204, a preset mapping relationship between a plurality of first data and a plurality of second data is acquired.

In this step, the device may pre-store a plurality of mapping relationships between a plurality of first data and a plurality of second data, where the first data includes preset task parameters and preset device information of the subtask, and the second data includes preset device information. Set the chip frequency. For example, the preset chip frequency may be the core frequency of the chip. For another example, the preset chip frequency may be a combination of the core frequency of the chip and the memory frequency.

For example, the following Table 1 illustrates the preset mapping relationship between multiple first data and multiple second data:

Table 1 Mapping relationship example

The following example illustrates how to establish the above-mentioned mapping relationship.

Assume that no matter what task is executed on the device, the values of the task parameters and device information will be within a certain range. For example, the value of the task parameter is within the range F1, and the value of the device information is within the range F2. Both F1 and F2 can be referred to as the preset first data value range. Then, you can sample within the value range of the first data to obtain some discrete sampling points, that is, to obtain multiple sets of first data, for example, (k1, d1), (k2, d2), (k3, d3), etc., Among them, k1, k2, and k3 represent task parameters, and d1, d2, and d3 represent device information. In addition, assuming that the chip frequency to be set is the core frequency, it may include multiple sets of optional chip frequencies that the chip may set, for example, x1, x2, x3, and so on.

Specifically, for each group of the first data, a group of chip frequencies can be selected from the above-mentioned multiple groups of optional chip frequencies as the second data corresponding to the first data, and the first data and the second data can be established. The mapping relationship between the data. Among them, in some embodiments, when selecting the second data from multiple sets of optional chip frequencies, the selection may be based on performance evaluation parameters. For example, the performance evaluation parameters of the first data under the condition of each group of optional chip frequencies can be determined separately, for example, a performance evaluation parameter can be obtained according to the first data and one group of optional chip frequencies; according to the first data and Another set of optional chip frequencies obtains another performance evaluation parameter, where the performance evaluation parameter can be obtained through simulation, inference, or mathematical formula operation, which is not limited in the embodiment of the present disclosure.

After obtaining the corresponding performance evaluation parameters of the first data under the conditions of each group of optional chip frequencies, a group of chip frequencies can be selected from the multiple sets of optional chip frequencies as the first data according to the performance evaluation parameters The corresponding second data. For example, the performance evaluation parameters may include task processing performance parameters and chip operating power consumption, and the chip operating power consumption of the above multiple sets of optional chip frequencies may be lower than the preset power consumption and the optional chip frequency with the optimal task processing performance parameters As the second data corresponding to the first data. Exemplarily, the aforementioned task processing performance parameters include but are not limited to task processing time.

As shown in FIG. 3, an example of a process of establishing a preset mapping relationship is illustrated, and in this example description, the task processing performance parameter is the task running time, and the chip frequency is the core frequency as an example.

In step 2041, traverse the multiple sets of optional chip frequencies, and obtain the operating time under the conditions of each set of optional chip frequencies and the first data according to each set of optional chip frequencies and a certain set of first data. The operating power consumption and task running time of the chip.

For example, assuming that the chip has ten sets of optional chip frequencies, for a set of first data, the ten sets of chip frequencies can be combined respectively to obtain ten chip operating power consumption P and ten task operating time T. For example, when the chip frequency is x1, the corresponding chip operating power consumption of the subtask is P1, and the task running time is T1; when the chip frequency is x2, the corresponding chip operating power consumption of the subtask is P2, and the task is running Time is T2.

In some embodiments, P may be determined according to the power consumption model, and T may be determined according to the runtime model. Among them, the model input of the power consumption model is task parameters, device information and chip frequency, and the model output is P. The model inputs of the runtime model are task parameters, device information and chip frequency, and the model outputs T.

The specific structure of the above-mentioned power consumption model and runtime model can be obtained in a variety of ways, for example, a support vector machine, a feedback neural network, a K-means aggregation algorithm, and so on.

In the following, both the power consumption model and the runtime model are neural network models as an example, and the neural network model can be obtained through model training. Among them, the training sample set can be given a fixed task list X={r ₁ , r ₂ ,..., r _p }, and the frequency set of the device is X={x ₁ , x ₂ ,... .., x _q }, these sets are used as the training set of the neural network model. For example, for a certain task r ₁ , the task parameters of the task can be obtained, and the device information of the device can be obtained, and then a frequency x ₁ is selected from the above device frequency set, and the three are used as the input of the power consumption model. After the model is processed, the predicted value of the operating power consumption of the chip is output. There is a difference between the predicted value and the real value of the chip's operating power consumption under the condition of input task parameters, device information, and frequency x ₁ (the result of real device operation). According to the difference, backpropagation is performed to train the function. Consumption model. In the same way, the runtime model can also be trained in the above manner, but the output is changed to the task runtime, which will not be described in detail here.

After obtaining the trained power consumption model and the running time model, input the first data and the chip frequency to the power consumption model to obtain the running power consumption of the chip. For example, by inputting the first data (k1, d1) and the chip frequency xi into the power consumption model, the operating power consumption Pi of the chip can be obtained. Input the first data and chip frequency to the runtime model to get the task runtime. For example, by inputting the first data (k1, d1) and the chip frequency xi into the runtime model, the task runtime Ti can be obtained.

In step 2042, the chip frequency that determines the optimal chip running power consumption and task running time is selected as the second data corresponding to the first data.

In this step, for example, according to the selection condition of the optimal chip frequency in formula (1), among multiple sets of chip frequencies, the chip frequency with the lowest task running time within the limit of chip running power consumption can be selected as the second data. For example, among _{all chip frequencies xi satisfying Pi≤Power Limited} , the chip frequency with the smallest Ti, such as x1, is selected as the second data corresponding to the first data (k1, d1).

In step 2043, a mapping relationship between the first data and the second data is established.

As described above, among the multiple sets of first data corresponding to the discrete sampling points, each set of first data can obtain the second data corresponding to the first data, that is, the optimal chip frequency, according to the process shown in FIG. 3. In this way, the second data corresponding to each first data in the multiple first data can be obtained, and each mapping relationship is established accordingly, thereby obtaining a set of mapping relationships. The set may include multiple sets of mapping relationships, and each set of mapping relationships The relationship includes a first data and a corresponding second data. The set of mapping relationships may be the preset mapping relationships described in step 204, as shown in Table 1 as an example.

In step 206, the chip frequency corresponding to the subtask in the preset mapping relationship is determined as the target chip frequency according to the preset mapping relationship, the device information, and the task parameters of the subtask.

For example, suppose the task parameter of a certain subtask is k1, and the device information corresponding to the subtask is d1. By looking up Table 1, the target chip frequency can be obtained as x1. This subtask can be called the first subtask.

In addition, because the first data in the mapping relationship table is discrete, sometimes the task parameters and device information of the first subtask are not completely consistent with the first data in the mapping relationship. In this case, as an optional implementation In this way, the first data closest to the device information and task parameters of the first task can be found in the mapping relationship table, and the chip frequency corresponding to the closest first data is used as the target chip frequency of the first subtask.

For example, assuming that the task parameters and device information of the first subtask can be referred to as third data, such as (k3, d3), the distance between the third data and each first data in the mapping relationship can be calculated. The distance can be calculated by taking the third data and each first data as a vector, and calculating the distance between the vectors, for example, it can be (Euclidean distance between the vector of the third data and the vector of each first data Or other distances. The chip frequency corresponding to the first data closest to the third data distance can be used as the target chip frequency of the first subtask.

Wherein, in some embodiments, the above-mentioned first data closest to the third data may be the closest downward, and the closest downward refers to taking the first data corresponding to the lower chip frequency as much as possible. For example, suppose that two adjacent first data of the third data are the first data Y1 and the first data Y2, and the distances between the first data Y1 and the first data Y2 and the third data are equal, the first The chip frequency corresponding to the data Y1 is lower than the chip frequency corresponding to the second data Y2, so you can choose to use the chip frequency corresponding to Y1. If the distances between the first data Y1 and the first data Y2 and the third data are not equal, the first data with a relatively close distance can still be selected as the target first data. For another example, as long as the distance between the first data Y1 and the distance between the first data Y2 and the third data is within a preset range, the first data corresponding to the lower chip frequency is preferentially selected. The preset range may be based on the actual The requirement setting is not limited in the embodiment of the present disclosure.

In step 208, according to the determined target chip frequency of each subtask, the operating frequency of the chip to execute each subtask is set.

In this step, in the running process of the target task, when one of the subtasks is run, the frequency of the chip can be set as the target chip frequency of the subtask.

In the method for setting the operating frequency of the device chip in the embodiment of the present disclosure, the task to be executed is decomposed to obtain multiple subtasks, and the target chip frequency of each subtask is obtained respectively. This refined frequency setting method can make each task The sub-task part is as far as possible to achieve the best operating performance, thereby improving the running speed of the entire task. In addition, by pre-establishing the mapping relationship between task parameters, device information and chip frequency, it is possible to speed up the determination of the chip frequency and improve the performance of the device.

FIG. 4 provides another flow chart of the method for setting the working frequency of the chip according to some embodiments of the present disclosure. In this example, setting the combined frequency of the chip is taken as an example for description, and the obtained device information may also include the chip of the chip Temperature, the chip temperature can be collected by the temperature sensor in the device where the chip is located. In addition, it is assumed that the target task to be performed is a three-layer neural network model inference task.

Among them, for different end devices, such as GPU (Graphics Processing Unit, graphics processing unit), CPU, or end device where the DSP chip is located, due to different device information, the power consumption model and runtime model obtained by training may be completely different. The model can be determined by offline training for the specific end device where the target task is running. After the power consumption model and the runtime model are determined, the determined model and the optimization problem solving engine can be stored in the end device. Among them, the processing performed by the optimization problem solving engine can be referred to the process of establishing the preset mapping relationship in the process description shown in Figure 2. The optimization problem solving engine can obtain the result according to the sampled multiple sets of first data and the determined model Each chip frequency corresponds to the chip running power consumption and task running time, and then the optimal chip frequency is selected according to formula (1), thereby establishing the mapping relationship between the first data and the second data. Optionally, the device may execute the establishment of the preset mapping relationship, or another device may execute the process of establishing the preset mapping relationship, and store the pre-established mapping relationship in the device where the target task is running. The device can directly look up the table when running the target task.

In step 400, task analysis is performed on the target task to be run on the device, and multiple subtasks and task parameters of each of the subtasks are obtained.

For example, the target task is an inference task of a three-layer neural network model, each of which can be a subtask. Then, after task analysis in this step, a subtask list can be obtained. The subtask list includes three subtasks: subtask 1, subtask 2, and subtask 3. In addition, this step also analyzes and obtains the task parameters of each subtask, for example, the amount of memory access and the amount of calculation of the subtask. For example, the subtask list may include: <subtask 1, task parameter 1>, <subtask 2, task parameter 2>, <subtask 3, task parameter 3>. The task parameters can be expressed as k ⁿ (n represents n-dimensional space, such as the amount of memory access and the amount of calculation). Subtask 1, subtask 2, and subtask 3 can be regarded as the first subtask, respectively.

In step 402, the device information of the device where the chip is located is obtained.

Among them, the device information may include device resource information. In an example, the subtask 1, the subtask 2 and the subtask 3 are in a serial relationship, and the device resource information occupied by these subtasks during operation may be the same. For example, the bandwidth, the number of computing units, etc. can be the same.

Device information can be expressed as d ^m (m represents m-dimensional space, such as bandwidth, memory capacity, etc.).

In step 404, before it is determined that the execution of subtask 1 is about to start, the chip temperature C1 on the chip is collected, and according to the task parameters of subtask 1, device resource information and chip temperature C1, it is determined that the device of subtask 1 is running. The chip on the corresponding to the set target chip frequency.

In some embodiments of the present disclosure, the device information may also include the chip temperature of the chip, because an excessively high temperature during the execution of the task will also cause the chip to take measures to reduce the frequency. In other words, the device information in the embodiments of the present disclosure not only includes device resource information such as the number of computing units, bandwidth, and memory capacity, but also includes chip temperature. In addition, the chip temperature may be dynamically acquired, that is, before each subtask in the running process of the target task starts to execute, the chip temperature corresponding to the subtask is acquired, and the target chip frequency of the subtask is determined accordingly.

In step 406, the working frequency of the chip is set to the target chip frequency of subtask 1, and the execution of subtask 1 is started.

In step 408, before it is determined that the execution of subtask 2 is about to start, the chip temperature C2 on the chip is collected, and according to the task parameters of subtask 2, device resource information and chip temperature C2, it is determined that the device of subtask 2 is running. The chip on the corresponding to the set target chip frequency.

In the embodiment of the present disclosure, the temperature of the chip changes during the running process of the target task, then the latest chip temperature can be collected and combined with the chip before each subtask is executed during the running process of the target task. The temperature determines the target chip frequency for this subtask.

It should also be noted that the chip frequency in the embodiment of the present disclosure may be a combined frequency or one of the combined frequencies, that is, the core frequency and the memory frequency of the chip are set at the same time. For example, the core frequency is x and the memory frequency is y. For example, when the task parameters and device information of the subtask are (k1, d1) (the device information can include device resource information and chip temperature), the corresponding chip frequency can be (x1, y1); when the subtask is When the task parameters and device information are (k2, d2), the corresponding chip frequency can be (x2, y2).

In addition, when determining the power consumption model and the runtime model, for example, the input of the power consumption model can include: k1, d1, x1, y1, and the output of the model can be the chip's operating power consumption P; the same way, the input of the runtime model It can include: k1, d1, x1, y1, and the output of the model can be the task running time T. Moreover, when training the power consumption model and the runtime model, the device information may include the chip temperature.

In step 410, the working frequency of the chip is set to the target chip frequency of subtask 2, and the execution of subtask 2 is started.

In step 412, before it is determined that subtask 3 will be executed, the chip temperature C3 of the chip on the device is collected, and the task parameters of subtask 3, device resource information, and chip temperature C3 are used to determine where subtask 3 is running. The chip on the device corresponds to the set target chip frequency.

In step 414, the operating frequency of the chip is set to the target chip frequency of subtask 3, and the execution of subtask 3 is started.

When all the subtasks included in the target task are executed, the operating frequency of the device chip can be reset to the default value, and the execution of the target task ends.

In the method for setting the working frequency of the chip in the embodiment of the present disclosure, the task to be executed is decomposed to obtain multiple subtasks, and the target chip frequency of each subtask is obtained respectively. This refined frequency setting method can make each subtask of the task Some parts are as far as possible to achieve the best operating performance, thereby improving the running speed of the entire task. In addition, in the process of task operation, dynamically collecting the chip temperature during the execution of the first subtask, and synthesizing the chip temperature to determine the target chip operating frequency of the first subtask, which can make the determination of the chip operating frequency more comprehensive. Therefore, the frequency setting is more reasonable, and the operation performance of the equipment is further improved.

In addition, the end device may also provide a user interface through which the input configuration information for the preset mapping relationship can be received. For example, the user can calculate or estimate the target chip frequency that each subtask should use offline, and store the preset mapping relationship between each subtask and the corresponding target chip frequency in the device, so that the device runs according to the The configured preset mapping relationship only needs to set the working frequency of the corresponding chip when the subtask is executed.

The aforementioned user interface can also be used to receive frequency setting strategy information. The frequency setting strategy information may include, for example, a model for determining chip operating power consumption and task operating time according to task parameters and device information, or how to select and determine the target chip frequency of a certain subtask according to the power consumption model and task operating time model. According to the frequency setting strategy information, based on the frequency setting strategy information and the task parameters of each of the multiple subtasks, the target chip frequency corresponding to the chip on the device when each subtask is running can be determined.

In addition, the frequency setting strategy information may also include: turning on or turning off the chip frequency dynamic setting function for subtasks. When the frequency setting strategy information includes enabling the chip frequency dynamic setting function for subtasks, the device can determine the target chip frequency for each subtask of the target task according to the method for setting chip operating frequency described in the foregoing embodiment of the present disclosure. For example, you can collect task parameters, chip temperature, and device resource information of subtasks, and select and determine the target chip frequency to be used based on these information, power consumption model and task runtime model. When the frequency setting strategy information includes turning off the chip frequency dynamic setting function for subtasks, the device can directly obtain the target chip frequency that each subtask should use according to the preset mapping relationship configured offline and calculated through the user interface.

Through the above user interface, a more flexible chip frequency setting method can be provided, and the user can update the chip frequency determination method more conveniently, making the chip frequency determination more reasonable and faster.

FIG. 5 is an exemplary structure diagram of a device for setting the operating frequency of a chip provided by an embodiment of the present disclosure. As shown in FIG. 5, the device may include: an acquisition module 51, a frequency control module 52, and a frequency setting module 53.

The obtaining module 51 is configured to obtain multiple subtasks of the target task and task parameters of each subtask, where the task parameters include parameters for representing the operation scale of the subtasks. Exemplarily, the task parameter includes at least one of the following: a calculation amount of the subtask, and a memory access amount of the subtask.

The frequency control module 52 is configured to determine the target chip frequency of each subtask based on the task parameter of each subtask in the multiple subtasks.

The frequency setting module 53 is configured to set the operating frequency of the chip to execute each subtask according to the determined target chip frequency of each subtask.

In an example, as shown in FIG. 6, the device may further include: a task analysis module 54 for performing task analysis processing on the target task to obtain the multiple subtasks and task parameters of each subtask; and storing Correspondence between each subtask and the task parameter of each subtask in the plurality of subtasks. The obtaining module 51, when used to obtain multiple subtasks of the target task and the task parameters of each subtask, includes: searching the task parameters of each subtask from the stored correspondence relationship.

For example, in actual implementation, when starting to run a target task, the task analysis module 54 can first perform task analysis processing on the target task, such as parsed to obtain multiple subtasks, and then analyze each of the multiple subtasks separately Obtain the task parameters of each subtask. The task analysis module 54 can store the corresponding relationship between each subtask obtained by the analysis and its task parameters.

The obtaining module 51 may be responsible for controlling the running process of the target task. For example, the obtaining module 51 may obtain the corresponding relationship parsed and stored by the task analyzing module 54 described above, and control the execution of each subtask therein one by one. Exemplarily, assuming there are three subtasks, when the first subtask is to be executed, the obtaining module 51 can obtain the task parameters of the first subtask from the corresponding relationship, and combine the task parameters and the device of the device where the chip is located. The information is sent to the frequency control module 52, and the frequency control module 52 determines the target chip frequency of the first subtask according to task parameters and device information.

Then, the frequency control module 52 may send the determined target chip frequency to the frequency setting module 53, and the frequency setting module 53 may set the operating frequency of the chip to the target chip frequency. Moreover, the frequency setting module 53 may send a feedback signal to the acquiring module 51 after setting the working frequency of the chip to notify the acquiring module 51 that the frequency setting has been completed. Then, the acquisition module 51 can start to execute the first subtask according to the feedback signal.

When the execution of the first subtask ends, the acquisition module 51 can start to prepare to execute the second subtask. Similarly, before the execution of the second subtask, the acquisition module 51 can obtain the first subtask from the correspondence obtained by the task analysis module 54. The task parameters of the two subtasks are sent to the frequency control module 52 to determine the target chip frequency of the second subtask. After the frequency setting module 53 feedbacks that the chip frequency setting is completed, the acquiring module 51 starts to execute the second subtask. The implementation of the third subtask is similar, and will not be detailed again. After the acquiring module 51 confirms that all the subtasks of the target task have been executed, it can send a frequency reset signal to the frequency control module 52, and the frequency control module 52 then sends a frequency reset signal to the frequency setting module 53, and the frequency setting module 53 The operating frequency of the chip can be set to the default value. At this point, the execution of the target task is over.

In an example, when the frequency control module 52 is used to determine the target chip frequency of each subtask based on the task parameters of each of the multiple subtasks, it includes: acquiring device information of the device where the chip is located, The device information includes device resource information; based on the device information and the task parameter of each subtask of the multiple subtasks, the target chip frequency of each subtask is determined. For example, the device resource information includes any one or more of the following: the number of computing units, bandwidth, and memory capacity.

In an example, the device information further includes: the chip temperature of the chip; the frequency control module 52 is further configured to: based on the task parameters of the first subtask among the plurality of subtasks, the device resource information, and The chip temperature during execution of the first subtask determines the target chip frequency of the first subtask.

In an example, the frequency control module 52 is configured to: obtain a preset mapping relationship between a plurality of first data and a plurality of second data, the first data includes preset task parameters and preset device information, so The second data includes a preset chip frequency; the target chip frequency of each subtask is determined according to the preset mapping relationship, the device information, and the task parameters of each subtask.

In an example, when the frequency control module 52 is used to determine the target chip frequency of each subtask according to the preset mapping relationship, the device information, and the task parameters of each subtask, it includes: determining a third The distance between the data and each first data in the plurality of first data in the preset mapping relationship, the third data includes task parameters and device information of the first subtask among the plurality of subtasks; The preset chip frequency corresponding to the target first data closest to the third data in the preset mapping relationship is used as the target chip frequency of the first subtask.

In an example, the frequency control module 52 is further configured to obtain multiple sets of selectable chip frequencies before obtaining the preset mapping relationship between the multiple first data and the multiple second data, and obtain the discrete discrete data obtained by sampling. A plurality of first data; for each of the first data in the plurality of first data, a set of chip frequencies is selected from the plurality of sets of selectable chip frequencies as the chip frequency corresponding to each of the first data Second data, and establish a mapping relationship between each of the first data and the selected second data.

In one example, the preset chip frequency corresponding to the first data in the preset mapping relationship is preset based on the first data under the condition of each group of selectable chip frequencies in a plurality of sets of selectable chip frequencies The corresponding performance evaluation parameters are selected from the multiple sets of optional chip frequencies.

In an example, the performance evaluation parameters include task processing performance parameters and chip operating power consumption; the preset chip frequency corresponding to the first data in the preset mapping relationship is: the multiple sets of selectable chip frequencies The operating power consumption of the medium chip is lower than the preset power consumption and the optional chip frequency with the best task processing performance parameters.

In an example, as shown in FIG. 6, the device may further include: an interface module 55, configured to receive configuration information of the preset mapping relationship input by the user.

In an example, when the frequency control module 52 is used to determine the target chip frequency of each subtask based on the task parameters of each subtask of the plurality of subtasks, it includes: The task parameters of the task are selected from multiple sets of selectable chip frequencies, and the chip frequency that enables the chip to achieve the lowest task running time under the limitation of chip power consumption is selected as the target chip frequency.

In an example, the interface module 55 is further configured to: receive frequency setting strategy information input by the user; the frequency control module 52 is further configured to: based on the frequency setting strategy information and each of the multiple subtasks The task parameters to determine the target chip frequency of each subtask.

In an example, the frequency setting strategy information includes enabling or disabling the chip frequency dynamic setting function for subtasks.

In an example, the operating frequency includes at least one of the following: a core frequency of the chip or a memory frequency.

In some embodiments, the above-mentioned apparatus may be used to execute any corresponding method described above, and for the sake of brevity, it will not be repeated here.

The embodiment of the present disclosure also provides an electronic device. As shown in FIG. 7, the electronic device 700 includes a memory 710 and a processor 720. The memory 710 is used to store machine-readable instructions 711, and the processor 720 is used to call The machine-readable instruction 711 implements the method for setting the operating frequency of the chip in any embodiment of this specification. The target chip for chip operating frequency setting may be the memory 710 and/or the processor 720. In an example, the electronic device 700 may further include a communication interface 730 and a bus 740. The memory 710, the processor 720, and the communication interface 730 are connected to each other through a bus 740. In an example, the electronic device 700 may further include a chip 750 configured to process each subtask in the target task based on the operating frequency set by the processor 720.

The embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the processor is prompted to implement the chip operating frequency setting method of any embodiment of this specification . In an example, the computer-readable storage medium may be the memory 710 in FIG. 7.

Those skilled in the art should understand that one or more embodiments of the present disclosure may be provided as a method, a system, or a computer program product. Therefore, one or more embodiments of the present disclosure may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, one or more embodiments of the present disclosure may adopt computer programs implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The form of the product.

Among them, "and/or" in the embodiments of the present disclosure means having at least one of the two, for example, "multi and/or B" includes three schemes: multi, B, and "multi and B".

The various embodiments in the present disclosure are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the data processing device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment.

The specific embodiments of the present disclosure have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than in the embodiments and still achieve desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown in order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

The embodiments of the subject and functional operations described in the present disclosure can be implemented in the following: digital electronic circuits, tangible computer software or firmware, computer hardware including the structures disclosed in the present disclosure and structural equivalents thereof, or among them A combination of one or more. The embodiments of the subject matter described in the present disclosure may be implemented as one or more computer programs, that is, one or one of the computer program instructions encoded on a tangible non-transitory program carrier to be executed by a data processing device or to control the operation of the data processing device Multiple modules. Alternatively or additionally, the program instructions may be encoded on artificially generated propagated signals, such as machine-generated electrical, optical, or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiver device for data transmission. The processing device executes. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

The processing and logic flow described in the present disclosure can be executed by one or more programmable computers executing one or more computer programs to perform corresponding functions by operating according to input data and generating output. The processing and logic flow can also be executed by a dedicated logic circuit, such as FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit), and the device can also be implemented as a dedicated logic circuit.

Computers suitable for executing computer programs include, for example, general-purpose and/or special-purpose microprocessors, or any other type of central processing unit. Generally, the central processing unit will receive instructions and data from a read-only memory and/or a random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or the computer will be operatively coupled with this mass storage device to receive data from or send data to it. It transmits data, or both. However, the computer does not have to have such equipment. In addition, the computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or, for example, a universal serial bus (USB ) Flash drives are portable storage devices, just to name a few.

Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (such as EPROM, EEPROM, and flash memory devices), magnetic disks (such as internal hard disks or Removable disks), magneto-optical disks, CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by or incorporated into a dedicated logic circuit.

Although the present disclosure contains many specific implementation details, these should not be construed as limiting the scope of any disclosure or the scope of protection, but are mainly used to describe the features of specific embodiments of the specific disclosure. Certain features described in multiple embodiments within the present disclosure can also be implemented in combination in a single embodiment. On the other hand, various features described in a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although features may function in certain combinations as described above and even initially claimed as such, one or more features from the claimed combination may in some cases be removed from the combination, and the claimed The combination of protection can point to a sub-combination or a variant of the sub-combination.

Similarly, although operations are depicted in a specific order in the drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can usually be integrated together in a single software product. , Or packaged into multiple software products.

Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desired results. In addition, the processes depicted in the drawings are not necessarily in the specific order or sequential order shown in order to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

The foregoing descriptions are only preferred embodiments of one or more embodiments of the present disclosure, and are not intended to limit one or more embodiments of the present disclosure. All within the spirit and principle of one or more embodiments of the present disclosure, Any modification, equivalent replacement, improvement, etc. made should be included in the protection scope of one or more embodiments of the present disclosure.

Claims (35)

1. A method for setting the operating frequency of a chip, characterized in that the method includes:

   Acquiring multiple subtasks of the target task and task parameters of each subtask, where the task parameters include parameters used to indicate the operation scale of the subtasks;

   Determine the target chip frequency of each subtask based on the task parameter of each subtask in the plurality of subtasks;

   According to the determined target chip frequency of each subtask, the working frequency of the chip to execute each subtask is set.
2. The method according to claim 1, wherein the method further comprises:

   Performing task analysis processing on the target task to obtain the multiple subtasks and the task parameters of each subtask;

   Storing the correspondence between each subtask and the task parameter of each subtask among the plurality of subtasks;

   The obtaining the multiple subtasks of the target task and the task parameters of each subtask includes: searching the task parameters of each subtask from the stored correspondence relationship.
3. The method according to claim 1 or 2, wherein the task parameter includes at least one of the following: a calculation amount of the subtask, and a memory access amount of the subtask.
4. The method according to any one of claims 1 to 3, wherein the determining the target chip frequency of each subtask based on the task parameter of each subtask in the plurality of subtasks comprises:

   Acquiring device information of the device where the chip is located, where the device information includes device resource information;

   Determine the target chip frequency of each subtask based on the device information and the task parameter of each subtask of the multiple subtasks.
5. The method according to claim 4, wherein the device resource information includes any one or more of the following: the number of computing units, bandwidth, and memory capacity.
6. The method according to claim 4 or 5, wherein the device information further comprises: the chip temperature of the chip;

   The determining the target chip frequency of each subtask based on the device information and the task parameter of each subtask of the multiple subtasks includes:

   The target chip frequency of the first subtask is determined based on the task parameters of the first subtask among the plurality of subtasks, the device resource information, and the chip temperature when the first subtask is executed.
7. The method according to any one of claims 4 to 6, wherein the determining the target chip frequency of each subtask based on the device information and the task parameters of each subtask of the plurality of subtasks, include:

   Acquiring a preset mapping relationship between a plurality of first data and a plurality of second data, where the first data includes preset task parameters and preset device information, and the second data includes a preset chip frequency;

   Determine the target chip frequency of each subtask according to the preset mapping relationship, the device information, and the task parameters of each subtask.
8. The method according to claim 7, wherein the determining the target chip frequency of each subtask according to the preset mapping relationship, the device information, and the task parameters of each subtask comprises:

   Determine the distance between the third data and each first data in the plurality of first data in the preset mapping relationship, where the third data includes task parameters and equipment of the first subtask among the plurality of subtasks information;

   The preset chip frequency corresponding to the first data closest to the third data in the preset mapping relationship is used as the target chip frequency of the first subtask.
9. The method according to claim 7 or 8, characterized in that, before the obtaining the preset mapping relationship between the plurality of first data and the plurality of second data, the method further comprises:

   Obtain multiple sets of optional chip frequencies, and obtain multiple discrete first data obtained by sampling;

   For each of the plurality of first data, select a set of chip frequencies from the plurality of sets of selectable chip frequencies as the second data corresponding to each of the first data, and establish The mapping relationship between each of the first data and the selected second data.
10. The method according to any one of claims 7 to 9, wherein the preset chip frequency corresponding to the first data in the preset mapping relationship is based on each group of multiple sets of selectable chip frequencies The performance evaluation parameter corresponding to the first data under the condition of the selectable chip frequency is selected from the multiple sets of selectable chip frequencies.
11. The method according to claim 10, wherein the performance evaluation parameters include task processing performance parameters and chip operating power consumption;

    The preset chip frequency corresponding to the first data in the preset mapping relationship is: among the multiple sets of selectable chip frequencies, the operating power consumption of the chip is lower than the preset power consumption and the task processing performance parameter is optimal. Chip frequency.
12. The method according to any one of claims 7 to 11, wherein the method further comprises:

    Receiving configuration information input by the user for the preset mapping relationship.
13. The method according to any one of claims 1 to 12, wherein the determining the target chip frequency of each subtask based on the task parameter of each subtask in the plurality of subtasks comprises:

    Based on the task parameters of each of the multiple subtasks, from multiple sets of optional chip frequencies, select the chip frequency that enables the chip to achieve the lowest task running time under the restriction of chip power consumption, as the target chip frequency.
14. The method according to any one of claims 1 to 13, wherein the method further comprises:

    Receive the frequency setting strategy information input by the user;

    The determining the target chip frequency of each subtask based on the task parameter of each subtask of the plurality of subtasks includes: setting the strategy information based on the frequency and the task parameter of each subtask of the plurality of subtasks, Determine the target chip frequency of each subtask.
15. The method according to claim 14, wherein the frequency setting strategy information comprises turning on or turning off the chip frequency dynamic setting function for subtasks.
16. The method according to any one of claims 1 to 15, wherein the operating frequency includes at least one of the following: a core frequency of the chip or a memory frequency.
17. A device for setting the operating frequency of a chip, characterized in that the device comprises:

    An obtaining module, configured to obtain multiple subtasks of the target task and task parameters of each subtask, the task parameters including parameters used to indicate the operation scale of the subtasks;

    A frequency control module, configured to determine the target chip frequency of each subtask based on the task parameter of each subtask in the plurality of subtasks;

    The frequency setting module is used to set the working frequency of the chip to execute each subtask according to the determined target chip frequency of each subtask.
18. The device according to claim 17, wherein the device further comprises:

    The task analysis module is used to perform task analysis processing on the target task to obtain the multiple subtasks and the task parameters of each subtask; and store the task parameters of each subtask and each subtask in the multiple subtasks Correspondence;

    The acquiring module is further used for searching the task parameters of each subtask from the stored corresponding relationship.
19. The device according to claim 17 or 18, wherein the task parameter includes at least one of the following: a calculation amount of the subtask, and a memory access amount of the subtask.
20. The device according to any one of claims 17 to 19, wherein the frequency control module is further configured to:

    Acquiring device information of the device where the chip is located, where the device information includes device resource information;

    Determine the target chip frequency of each subtask based on the device information and the task parameter of each subtask of the multiple subtasks.
21. The apparatus according to claim 20, wherein the device resource information includes any one or more of the following: the number of computing units, bandwidth, and memory capacity.
22. The apparatus according to claim 20 or 21, wherein the device information further comprises: the chip temperature of the chip;

    The frequency control module is further configured to determine the first subtask based on the task parameters of the first subtask among the plurality of subtasks, the device resource information, and the chip temperature during execution of the first subtask The target chip frequency.
23. The device according to any one of claims 20 to 22, wherein the frequency control module is further configured to:

    Acquiring a preset mapping relationship between a plurality of first data and a plurality of second data, where the first data includes preset task parameters and preset device information, and the second data includes a preset chip frequency;

    Determine the target chip frequency of each subtask according to the preset mapping relationship, the device information, and the task parameters of each subtask.
24. The device according to claim 22, wherein the frequency control module is further configured to:

    Determine the distance between the third data and each first data in the plurality of first data in the preset mapping relationship, where the third data includes task parameters and equipment of the first subtask among the plurality of subtasks information;

    The preset chip frequency corresponding to the first data closest to the third data in the preset mapping relationship is used as the target chip frequency of the first subtask.
25. The device according to claim 23 or 24, wherein the frequency control module is further configured to:

    Before acquiring the preset mapping relationship between the plurality of first data and the plurality of second data, acquiring a plurality of sets of optional chip frequencies, and acquiring a plurality of discrete first data obtained by sampling;

    For each of the first data in the plurality of first data, select a set of chip frequencies from the plurality of selectable chip frequencies as the second data corresponding to each of the first data, and establish The mapping relationship between each of the first data and the selected second data.
26. The device according to any one of claims 23 to 25, wherein the preset chip frequency corresponding to the first data in the preset mapping relationship is based on a plurality of sets of selectable chip frequencies The performance evaluation parameter corresponding to the first data under the condition of each set of selectable chip frequencies is selected from the multiple sets of selectable chip frequencies.
27. The device of claim 26, wherein:

    The performance evaluation parameters include task processing performance parameters and chip operating power consumption;

    The preset chip frequency corresponding to the first data in the preset mapping relationship is: among the multiple sets of selectable chip frequencies, the operating power consumption of the chip is lower than the preset power consumption and the task processing performance parameter is optimal. Chip frequency.
28. The device according to any one of claims 23-27, wherein the device further comprises:

    The interface module is used to receive the configuration information of the preset mapping relationship input by the user.
29. The device according to any one of claims 17 to 28, wherein the frequency control module is further configured to:

    Based on the task parameters of each of the multiple subtasks, from multiple sets of optional chip frequencies, select the chip frequency that enables the chip to achieve the lowest task running time under the restriction of chip power consumption, as the target chip frequency.
30. The device of claim 28, wherein:

    The interface module is further configured to: receive frequency setting strategy information input by the user;

    The frequency control module is further configured to determine the target chip frequency of each subtask based on the frequency setting strategy information and the task parameter of each subtask of the multiple subtasks.
31. The device according to claim 30, wherein the frequency setting strategy information comprises enabling or disabling the chip frequency dynamic setting function for subtasks.
32. The device according to any one of claims 17 to 31, wherein the operating frequency comprises at least one of the following: a core frequency of the chip or a memory frequency.
33. An electronic device, comprising: a memory and a processor, the memory is used to store machine-readable instructions, and the processor is used to call the machine-readable instructions to implement any one of claims 1 to 16 The method described.
34. The device according to claim 33, further comprising:

    The chip is used to process each subtask in the target task based on the operating frequency set by the processor.
35. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the processor is prompted to implement the method according to any one of claims 1 to 16.

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