TW202121116A - Method and apparatus for setting operating frequency of chip, electronic device, and storage medium - Google Patents

Abstract

Examples of the present disclosure provides a method and apparatus for setting an operating frequency of a chip, an electronic device, and a storage medium. The method includes: obtaining a plurality of subtasks of a target task and a task parameter of each subtask, where the task parameter includes a parameter for representing an operational scale of the subtask; determining a target chip frequency for each subtask based on the task parameter of each subtask of the plurality of subtasks; setting an operating frequency of a chip for performing each subtask based on the determined target chip frequency for each subtask.

Description

Method and device for setting chip operating frequency, electronic equipment and recording medium

The present invention relates to smart device technology, in particular to a method and device for setting the operating frequency of a chip.

With the development of 5G and artificial intelligence technologies, terminal devices (for example, smart phones, smart cameras, etc.) are given more computing requirements and need to perform more tasks. However, most of the chips used for computing processing included in the terminal equipment have power consumption limitations, and the computing peak capacity of the equipment cannot be fully utilized. Frequency reduction is one of the main methods to prevent the power consumption of the chip from exceeding the standard. The frequency reduction technology mainly reduces the power consumption of the chip by temporarily reducing the working frequency of the chip (frequency).

In some technologies, an initial operating frequency can be set before the application program is executed in the terminal device, and the chip runs at the initial operating frequency to perform calculation processing on the application program. In addition, during the operation of the application, when the power consumption of the chip exceeds the standard, a fixed frequency reduction strategy can be adopted for the chip. For example, the working frequency of the chip is reduced by a fixed ratio, or the working frequency is reduced to A fixed value.

The embodiments of the present invention provide at least a method and device for setting the operating frequency of a wafer.

In a first aspect, a method for setting a working frequency of a wafer is provided. The method includes: acquiring a plurality of subtasks of a target task and task parameters of each subtask, the task parameters including parameters used to indicate the operation scale of the subtasks; Based on the task parameters of each subtask in the multiple subtasks, the target wafer frequency of each subtask is determined; according to the determined target wafer frequency of each subtask, the operating frequency of the wafer to execute each subtask is set.

According to any embodiment of the present invention, the method further includes: performing task analysis processing on the target task to obtain the multiple subtasks and the task parameters of each subtask; storing each subtask and each subtask in the multiple subtasks The corresponding relationship of the task parameters of each subtask; the obtaining the multiple subtasks of the target task and the task parameters of each subtask includes: searching the task parameters of each subtask from the stored corresponding relationships.

According to any embodiment of the present invention, the task parameter includes at least one of the following: a calculation amount of the subtask, and a memory access amount of the subtask.

According to any embodiment of the present invention, the determining the target chip frequency of each subtask based on the task parameters of each subtask of the plurality of subtasks includes: obtaining device information of the device where the chip is located, and The equipment information includes equipment resource information; the target chip frequency of each subtask is determined based on the equipment information and the task parameters of each of the multiple subtasks.

According to any embodiment of the present invention, the equipment resource information includes any one or more of the following: the number of computing units, bandwidth, and storage device capacity.

According to any embodiment of the present invention, the device information further includes: the wafer temperature of the wafer; the determining each subtask based on the device information and the task parameter of each subtask of the plurality of subtasks The target chip frequency of includes: determining the target of the first subtask based on the task parameters of the first subtask among the plurality of subtasks, the device resource information, and the chip temperature when the first subtask is executed Chip frequency.

According to any embodiment of the present invention, the determining the target chip frequency of each subtask based on the device information and the task parameters of each subtask of the plurality of subtasks includes: acquiring a plurality of first data and A preset mapping relationship between a plurality of second data, the first data includes preset task parameters and preset device information, the second data includes a preset chip frequency; according to the preset mapping relationship, the Equipment information and task parameters of each subtask determine the target chip frequency of each subtask.

According to any embodiment of the present invention, the determining the target chip frequency of each subtask according to the preset mapping relationship, the device information and the task parameters of each subtask includes: determining the third data and the task parameters of each subtask. The distance between each of the plurality of first data in the preset mapping relationship, the third data includes task parameters and equipment information of the first subtask among the plurality of subtasks; Let the preset chip frequency corresponding to the target first data closest to the third data in the mapping relationship be the target chip frequency of the first subtask.

According to any embodiment of the present invention, before the obtaining the preset mapping relationship between the plurality of first data and the plurality of second data, the method further includes: obtaining a plurality of sets of selectable chip frequencies, and obtaining samples obtained A plurality of discrete first data; for each of the first data in the plurality of first data, a set of chip frequencies is selected from the plurality of sets of optional chip frequencies as the The data corresponds to the second data, and a mapping relationship between each of the first data and the selected second data is established.

According to any embodiment of the present invention, the preset chip frequency corresponding to the first data in the preset mapping relationship is based on the second chip frequency under the condition of each group of selectable chip frequencies in the multiple sets of selectable chip frequencies. The performance evaluation parameter corresponding to a data is selected from the multiple sets of optional chip frequencies.

According to any embodiment of the present invention, the performance evaluation parameters include task processing performance parameters and chip operating power consumption; the preset chip frequency corresponding to the first data in the preset mapping relationship is: the multiple groups Among the optional chip frequencies, the chip operating power consumption is lower than the preset power consumption and the optional chip frequency with the best task processing performance parameters.

According to any embodiment of the present invention, the method further includes: receiving configuration information input by a user for the preset mapping relationship.

According to any embodiment of the present invention, the determining the target chip frequency of each subtask based on the task parameters of each subtask in the plurality of subtasks includes: The task parameters are selected from a plurality of groups of selectable chip frequencies, and the chip frequency that enables the chip to achieve the lowest task running time under the limitation of chip power consumption is selected as the target chip frequency.

According to any embodiment of the present invention, the method further includes: receiving frequency setting strategy information input by the user; and determining the target chip of each subtask based on the task parameter corresponding to each subtask in the plurality of subtasks The frequency includes: determining the target chip frequency of each subtask based on the frequency setting strategy information and the task parameters of each subtask of the plurality of subtasks.

According to any embodiment of the present invention, the frequency setting strategy information includes enabling or disabling the chip frequency dynamic setting function for subtasks.

According to any embodiment of the present invention, the operating frequency includes at least one of the following: a core frequency of the chip or a storage device frequency.

In a second aspect, a device for setting the operating frequency of a chip is provided. The device includes: an acquisition module for acquiring multiple subtasks of a target task and task parameters of each subtask. The task parameters include The parameter of the calculation scale of the task; the frequency control module is used to determine the target chip frequency of each subtask based on the task parameter of each of the multiple subtasks; the frequency setting module is used to determine the frequency of each subtask. The target chip frequency of each subtask, and the working frequency of the chip to execute each subtask.

In a third aspect, an electronic device is provided, including: a storage device and a processor, the storage device is used to store computer-readable instructions, and the processor is used to call the computer-readable instructions to implement the first aspect of the present invention Methods.

According to any one of the embodiments of the present invention, the device further includes: a chip for processing each subtask in the target task based on the operating frequency set by the processor.

In a fourth aspect, there is provided a computer-readable recording medium on which a computer program is stored. When the computer program is executed by a processor, the processor is prompted to implement the method described in the first aspect of the present invention.

The method and device for setting the working frequency of a chip provided by the embodiment of the present invention determine the target chip frequency of each subtask in the target task based on the task parameters of the subtask, so that the chip can use the subtask when executing each subtask. The target chip frequency is running. This refined frequency setting method can achieve the best operating performance as much as possible when executing each subtask, thereby increasing the running speed of the entire task.

In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of the present invention, in the following, in conjunction with the drawings in one or more embodiments of the present invention, a comparison of the technical solutions in one or more embodiments of the present invention The technical solution is described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on one or more embodiments of the present invention, all other embodiments obtained by those skilled in the art without making progressive work shall fall within the protection scope of the present invention.

The embodiment of the present invention provides a method for setting the operating frequency of a chip in a terminal device. The method aims to make the operating performance of the device better when the chip runs at the set operating frequency. For example, tasks running on the device can be Processing is completed at a faster speed. Among them, the chip can be an artificial intelligence (AI) chip, for example, an AI chip used in a smart phone, an AI chip used in an autonomous vehicle, an AI chip used in edge devices of the Internet of Things, etc. Wait. It may also be other types of chips, such as a CPU (Central Processing Unit) chip, a DSP (Digital Signal Processing), a memory chip, etc., which are not limited in the embodiment of the present invention.

FIG. 1 shows a flowchart of a method for setting the operating frequency of a wafer according to some embodiments of the present invention. As shown in FIG. 1, the method may include the following processing.

In step 100, a plurality of subtasks of the target task and task parameters of each subtask are acquired, the task parameters including parameters used to indicate the operation scale of the subtasks.

In this step, the target task may be a task to be executed and processed on the device. For example, the task may be a training task of a deep learning model, or an inference task of a neural network model, or running an application program, etc. The execution of the target task requires the use of the chip on the device, and the chip is responsible for part or all of the processing work such as calculations during the execution of the task.

The subtask may be a relatively independent execution unit included in the target task. For example, the target task can include multiple functions, which can be divided according to functions, and each function is used as an independent subtask in the target task. For another example, the task code can also be divided into multiple code blocks and subtasks are divided according to the code blocks, and each piece of code is relatively complete. For example, a relatively complete or independent code block as a subtask. For another example, when the target task is the training or inference task of a neural network model, each layer or layers of the neural network model can be regarded as a subtask; or, it can also be the code segment of the realization process of each layer As a subtask. For another example, one or at least two of the multiple functional modules can also be used as a subtask, and so on.

The embodiment of the present invention does not limit the division of subtasks, and there may be multiple divisions of subtasks, such as the above-mentioned function as a unit, a code block as a unit, a network layer or an operator as a unit, or Take functional modules as the unit, etc. It should be noted that although dividing the target task into multiple sub-tasks can achieve fine-grained frequency settings and improve equipment operating performance, too many sub-tasks may cause more frequent The frequency setting has a certain impact on the performance of the device. Therefore, you can balance the setting of the number of subtasks. For example, try not to divide the inside of the loop body included in the target task into subtasks to reduce the number of frequency settings, etc., specific settings It can be done based on actual needs, so I won’t go into details here.

In the embodiment of the present invention, the task parameter of the subtask may include a parameter used to indicate the calculation scale of the subtask, for example, may include a parameter used to indicate one or more resources that the subtask needs to occupy. As an example, the task parameters may include, but are not limited to, at least one of the following: calculation amount of subtasks, memory access amount (memory access amount is the number of times the chip needs to access the storage device and/or the total amount of data accessed during the execution of the subtask. Quantities), or other types of task parameters may also be included, which is not limited in the embodiment of the present invention.

In the embodiment of the present invention, the task parameters of the subtasks can be obtained in a variety of ways. For example, obtain task parameters of subtasks from other equipment or from other functional modules in the system, or obtain task parameters of subtasks from local storage devices, or obtain the task of each subtask by analyzing the target task. Parameters, etc.

In some embodiments, in order to obtain the task parameter more quickly, the correspondence between each subtask and the respective task parameter may be stored in advance. Exemplarily, task analysis processing may be performed on the target task in advance to obtain multiple subtasks included in the target task and task parameters of each subtask, and each subtask and its task parameters are stored. In this way, when the target task needs to run, the task parameters of each subtask can be quickly found based on the stored information. In some examples, the correspondence between the subtasks and task parameters can be stored in the form of key-value. For example, corresponding task identifiers can be set for multiple subtasks, and the task identifiers of the subtasks can be stored as keys , Save the task parameter of this subtask as value. The key-value storage method is suitable for querying through the primary key, with fast query speed and large amount of stored data. However, the present invention is not limited to this.

In some embodiments, in addition to obtaining the task parameters of each subtask, the device information of the device where the chip is located can be further obtained, and the target chip frequency of each subtask can be jointly determined based on the device information and task parameters.

Among them, the above-mentioned equipment information may include equipment resource information of the equipment where the chip is located. The equipment resource information is used to indicate information about the available resources of the equipment. As an example, the equipment resource information may include, but is not limited to, any of the following or Multiple equipment resource information: the number of computing units, bandwidth, storage capacity, etc. In some embodiments, the target chip frequency of each subtask may also depend on the dependency between multiple subtasks or the task execution mode, such as sequence, parallel, or sequence between partial subtasks and parallel between partial subtasks, etc. . For example, if the execution of each subtask obtained by the division of the target task is in a sequence relationship, then the chip can occupy all available device resources on the device when executing each subtask, such as occupying all computing units and all bandwidth on the device. And so on, but the embodiment of the present invention is not limited thereto.

In step 102, the target wafer frequency of each subtask is determined based on the task parameter of each subtask in the plurality of subtasks.

In this step, the target chip frequency of each subtask can be determined according to the task parameters of the subtask. Alternatively, the target chip frequency of each subtask may be jointly determined based on the device information of the device where the chip is located and the task parameters of each subtask.

In some embodiments, multiple sets of optional chip frequencies may be determined, and a corresponding optional chip frequency can be selected for each subtask from the multiple sets of optional chip frequencies based on a certain strategy. Wherein, the multiple sets of selectable chip frequencies are a specific number of discrete frequencies that can be set for the chips in the device. For example, taking the core frequency of the chip as an example, the core frequency may include m frequency values such as x1, x2...xm. The aforementioned strategies can be set based on actual needs. Several exemplary strategies will be described below, but the embodiments of the present invention are not limited thereto.

In some embodiments, the determination of the target chip frequency can be transformed into an optimization problem. In some alternative implementations, task running time can be used as the main reference factor for selection. As an example, it can be based on each sub The task parameters of the task, among the multiple sets of optional chip frequencies that can be set, select the chip frequency that enables the chip to achieve the lowest task running time under the limit of chip power consumption, as the target chip frequency of each subtask . Among them, in some examples, multiple subtasks can be analyzed as a whole to determine the overall task running time of the target task. At this time, under the condition of determining the shortest task running time, each of the multiple subtasks can be obtained at the same time. The target chip frequency for each subtask. Or, in other examples, the task running time of each subtask can be analyzed separately, and the target chip frequency of the subtask can be determined based on the shortest task running time of each subtask as a condition, and so on. In other optional implementation manners, one or any of the system resources consumed by the task, the power consumption of the chip, the running speed of the task, the accuracy of the task execution result, etc. can also be selected as reference factors. This embodiment of the present invention does not Make a limit.

（n表示n維空間，如訪存量，計算量等），該子任務對應的設備資訊是

（m表示m維空間，比如儲存裝置容量等），並假設晶片頻率是x，其中，該頻率可以為核心頻率、儲存裝置頻率、或是核心頻率與儲存裝置頻率的頻率組合。

表示晶片運行功耗，可以看到，該晶片運行功耗與任務參數、設備資訊和晶片頻率有關，即使固定任務參數和設備資訊，晶片頻率變化時P也會隨之變化。

表示任務運行時間，同理，即使固定任務參數和設備資訊，晶片頻率變化時T也會隨之變化。那麼可將上述子任務的任務參數和設備資訊分別與多種晶片頻率組合，得到對應的晶片運行功耗和任務運行時間，並基於晶片運行功耗和任務運行時間來從多種晶片頻率中選擇每個子任務的最優晶片頻率。The following is an example of determining the target chip frequency based on the task parameters and equipment information of the subtasks to illustrate the principle of solving an optimization problem. Take one of the subtasks as an example, the task parameter of the subtask is

(N represents n-dimensional space, such as the amount of memory access, the amount of calculation, etc.), the device information corresponding to the subtask is

(M represents m-dimensional space, such as storage device capacity, etc.), and assume that the chip frequency is x, where the frequency can be a core frequency, a storage device frequency, or a combination of core frequency and storage device frequency.

Indicates the operating power consumption of the chip. It can be seen that the operating power consumption of the chip is related to task parameters, device information and chip frequency. Even if the task parameters and device information are fixed, P will change when the chip frequency changes.

Represents the task running time. Similarly, even if the task parameters and equipment information are fixed, T will change when the chip frequency changes. Then the task parameters and equipment information of the above subtasks can be combined with multiple chip frequencies to obtain the corresponding chip operating power consumption and task operating time, and based on the chip operating power consumption and task operating time, each sub-task can be selected from multiple chip frequencies. The optimal chip frequency for the task.

…….（1）For example, the optimal chip frequency can be selected according to the following formula (1):

…….(1)

The above formula (1) indicates: the _{lowest task running time is achieved under the condition of chip power consumption (not exceeding Power Limited} ), which is the optimization goal of the optimization problem. Find the optimal chip frequency with this optimization goal. Among the multiple optional chip frequencies that the chip can set, if a certain chip frequency is used, the subtask can be processed with the shortest task running time under the condition of chip power consumption. , The chip frequency is the target chip frequency of the subtask.

Since at least one parameter in the task parameter and the device information of each subtask may be different, the target chip frequency of each subtask may also be different. In this step, the target chip frequency that best matches each subtask can be found, so that the subtask is completed at the fastest speed and the chip does not exceed the power consumption.

In step 104, according to the determined target wafer frequency of each subtask, the operating frequency of the wafer when each subtask is executed is set.

In this step, during the running process of the target task, when one of the subtasks is run, the chip frequency can be set as the target chip frequency of the subtask, or it can be based on the target chip frequency and the device or chip executing The current status information of the subtask, for example, the status information of the device or the chip when the chip starts to execute the subtask, such as the temperature of the chip, is used to set the operating frequency of the chip when the subtask is executed. Among them, in some embodiments, the above process of determining the target chip frequency may be performed uniformly before executing the target task, and the target chip frequency of each of the multiple subtasks is stored, and then, in the process of running each subtask, Set the wafer frequency to the target wafer frequency of this subtask. In other embodiments, before each subtask is executed, the target chip frequency of the subtask may be determined. For example, the target chip of the subtask may be determined based on the task parameters of the subtask and the current state information of the device or chip. Frequency. At this time, the determination of the target chip frequency of each subtask may be performed at different times, which is not limited in the embodiment of the present invention.

In the embodiment of the present invention, the operating frequency of the chip may include at least one of the following: the core frequency of the chip or the frequency of the storage device. For example, the method of the embodiment of the present invention can be used only to set the core frequency of the chip, where the storage device frequency can be set to a fixed value or set in the unit of the target task, or the method is only used to set the storage device frequency, where , The core frequency can be set to a fixed value or set in the unit of the target task, or this method is used to set the core frequency of the chip and the storage device frequency, for example, the core frequency and the storage device frequency are set as a frequency combination. The target chip frequency of the task is this frequency combination.

The frequency of the storage device may be the frequency of a volatile memory, such as the frequency of SDRAM (Synchronous Dynamic Random Access Memory). For example, DDR SDRAM (Double Data Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, and so on. The frequency of the storage device may also be the frequency of a non-volatile memory, such as the frequency of a flash memory.

In the method for setting the working frequency of the chip in the embodiment of the present invention, the target chip frequency of each subtask is determined based on the task parameters of each subtask in the target task, so that the chip can use the target chip of the subtask when executing each subtask. Frequency operation. This refined frequency setting method can achieve the optimal operating performance as much as possible when executing each subtask, thereby increasing the operating speed of the entire task.

Figure 2 shows another flow chart of the method for setting the working frequency of the chip provided by some embodiments of the present invention. The method takes the target chip frequency jointly determined according to the task parameters and device information of the subtasks as an example. A way to determine the frequency of the target wafer is presented. As shown in FIG. 2, the method may include the following processing, wherein the same steps as those in FIG. 1 will not be described in detail.

In step 200, task analysis is performed on the target task to be run on the device to obtain multiple subtasks and task parameters of each of the subtasks. For example, the task parameter of each subtask may include at least one of the following: the calculation amount and the memory access amount of the subtask.

In step 202, the device information of the device where the chip is located is obtained.

For example, the device information of the device where the chip is located may include device resource information, and the device resource information may include at least one of the following: bandwidth, number of computing units, and storage device capacity.

In step 204, a preset mapping relationship between a plurality of first data and a plurality of second data is acquired.

In this step, the device may pre-store the mapping relationship between multiple first data and multiple second data, where the first data includes the preset task parameters of the subtask and the preset device information, and the second data includes the preset information. Set the chip frequency. For example, the predetermined chip frequency may be the core frequency of the chip. For another example, the predetermined chip frequency may be a combination of the core frequency of the chip and the frequency of the storage device.

For example, the following Table 1 illustrates the preset mapping relationship between multiple first data and multiple second data:

Table 1 Example of mapping relationship First data Second data Preset task parameters Default device information Default chip frequency k1 d1 x1 k2 d2 x2 ... ... ...

The following example illustrates how to establish the above-mentioned mapping relationship.

Assume that no matter what task is executed on the device, the values of the task parameters and device information will be within a certain range. For example, the value of the task parameter is within the range F1, and the value of the device information is within the range F2. Both F1 and F2 can be referred to as the preset value range of the first data. Then, you can sample within the value range of the first data to get some discrete sampling points, that is, to get multiple sets of first data, for example, (k1, d1), (k2, d2), (k3, d3), etc., Among them, k1, k2, and k3 represent task parameters, and d1, d2, and d3 represent device information. In addition, assuming that the chip frequency to be set is the core frequency, it may include multiple sets of optional chip frequencies that the chip may set, for example, x1, x2, x3, etc.

Specifically, for each set of the first data, a set of chip frequencies can be selected from the above-mentioned multiple sets of optional chip frequencies as the second data corresponding to the first data, and the first data and the second data can be created. The mapping relationship between the data. Among them, in some embodiments, when selecting the second data from multiple sets of optional chip frequencies, the selection may be based on performance evaluation parameters. For example, the performance evaluation parameters of the first data under the condition of each group of optional chip frequencies can be determined separately, for example, a performance evaluation parameter can be obtained according to the first data and one group of optional chip frequencies; according to the first data and Another set of selectable chip frequencies obtains another performance evaluation parameter, where the performance evaluation parameter can be obtained through simulation, inference, or mathematical formula operation, which is not limited in the embodiment of the present invention.

After obtaining the corresponding performance evaluation parameters of the first data under the conditions of each set of optional chip frequencies, a group of chip frequencies can be selected from the multiple sets of optional chip frequencies as the first data according to the performance evaluation parameters The corresponding second data. For example, the performance evaluation parameters may include task processing performance parameters and chip operating power consumption. Among the multiple sets of optional chip frequencies, the chip operating power consumption can be lower than the preset power consumption and the optional chip frequency with the best task processing performance parameters. As the second data corresponding to the first data. Exemplarily, the aforementioned task processing performance parameters include but are not limited to task processing time.

FIG. 3 shows another flowchart of the process of establishing a preset mapping relationship provided by some embodiments of the present invention. As shown in FIG. 3, an example of a process of establishing a preset mapping relationship is illustrated, and in this example description, the task processing performance parameter is the task running time and the chip frequency is the core frequency as an example.

In step 2041, traverse the multiple sets of optional chip frequencies, and obtain the operating time under the conditions of each set of optional chip frequencies and the first data according to each set of optional chip frequencies and a certain set of first data. The operating power consumption and task running time of the chip.

For example, assuming that the chip has ten sets of optional chip frequencies, for a set of first data, the ten sets of chip frequencies can be combined respectively to obtain ten chip operating power consumption P and ten task operating time T. For example, when the chip frequency is x1, the corresponding chip operating power consumption of the subtask is P1, and the task running time is T1; when the chip frequency is x2, the corresponding chip operating power consumption of the subtask is P2, and the task is running Time is T2.

In some embodiments, P may be determined according to the power consumption model, and T may be determined according to the runtime model. Among them, the model input of the power consumption model is task parameters, equipment information and chip frequency, and the model output is P. The model inputs of the runtime model are task parameters, equipment information, and chip frequency, and the model outputs T.

The specific structure of the above-mentioned power consumption model and runtime model can be obtained in a variety of ways, for example, a support vector machine, a feedback neural network, a K-means aggregation algorithm, and so on.

，設備的頻率集合為

，這些集合作為神經網路模型的訓練集。比如，對於某一任務

，可以得到該任務的任務參數，並獲取該設備的設備資訊，再由上述設備頻率集合中取一個頻率

，三者作為功耗模型的輸入，經過功耗模型的處理後輸出晶片運行功耗的預測值。該預測值與設備在輸入的任務參數、設備資訊和頻率

條件下的晶片運行功耗的真實值（真實設備運行的結果）之間具有差異，根據該差異進行反向傳播，訓練該功耗模型。同理，運行時間模型也可以按照上述方式訓練，只是將輸出改為任務運行時間，在此不再詳述。In the following, both the power consumption model and the runtime model are neural network models as an example for illustration, and the neural network model can be obtained through model training. Among them, the training sample set can be given a fixed task list

, The frequency set of the device is

, These sets are used as the training set of the neural network model. For example, for a task

, The task parameters of the task can be obtained, and the device information of the device can be obtained, and then a frequency can be selected from the above-mentioned device frequency set

, The three are used as the input of the power consumption model, and the predicted value of the operating power consumption of the chip is output after the processing of the power consumption model. The predicted value and the task parameters, equipment information and frequency input by the equipment

There is a difference between the real values of the operating power consumption of the chip under the conditions (the result of the operation of the real device), and back-propagation is performed according to the difference, and the power consumption model is trained. In the same way, the runtime model can also be trained in the above manner, but the output is changed to the task runtime, which will not be described in detail here.

After obtaining the trained power consumption model and the running time model, input the first data and the chip frequency to the power consumption model to obtain the running power consumption of the chip. For example, by inputting the first data (k1, d1) and the chip frequency xi into the power consumption model, the chip's operating power consumption Pi can be obtained. Input the first data and chip frequency to the runtime model to get the task runtime. For example, by inputting the first data (k1, d1) and the chip frequency xi into the runtime model, the task runtime Ti can be obtained.

In step 2042, the chip frequency that determines the optimal chip running power consumption and task running time is selected as the second data corresponding to the first data.

In this step, for example, according to the selection condition of the optimal chip frequency in formula (1), among multiple sets of chip frequencies, the chip frequency with the lowest task running time within the limit of the chip operating power consumption can be selected as the second data. For example, among _{all chip frequencies xi satisfying Pi≤Power Limited} , the chip frequency with the smallest Ti, such as x1, is selected as the second data corresponding to the first data (k1, d1).

In step 2043, a mapping relationship between the first data and the second data is established.

As described above, among the multiple groups of first data corresponding to the discrete sampling points, each group of first data can obtain the second data corresponding to the first data according to the process shown in FIG. 3, that is, the optimal chip frequency. In this way, the second data corresponding to each first data in the multiple first data can be obtained, and each mapping relationship can be established accordingly to obtain a set of mapping relationships. The set can include multiple sets of mapping relationships, and each set of mapping relationships The relationship includes a first data and a corresponding second data. The set of mapping relationships may be the preset mapping relationships described in step 204, as shown in Table 1 as an example.

In step 206, the chip frequency corresponding to the subtask in the preset mapping relationship is determined as the target chip frequency according to the preset mapping relationship, the device information, and the task parameters of the subtask.

通過查表1，可以得到的目標晶片頻率是x1。該子任務可以被稱之為第一子任務。For example, suppose the task parameter of a subtask is k1, and the device information corresponding to the subtask is d1

By looking up Table 1, the target wafer frequency that can be obtained is x1. This subtask can be called the first subtask.

In addition, because the first data in the mapping relationship table is discrete, sometimes the task parameters and device information of the first subtask are not completely consistent with the first data in the mapping relationship. In this case, as an optional implementation In this way, the first data closest to the device information and task parameters of the first task can be found in the mapping relationship table, and the chip frequency corresponding to the closest first data is used as the target chip frequency of the first subtask.

For example, assuming that the task parameters and device information of the first subtask can be called the third data, such as (k3, d3), the distance between the third data and each first data in the mapping relationship can be calculated. The distance can be calculated by taking the third data and each first data as a vector to calculate the distance between the vectors, for example, it can be (Euclidean distance between the vector of the third data and the vector of each first data Or other distances. The chip frequency corresponding to the first data closest to the third data can be used as the target chip frequency of the first subtask.

Among them, in some embodiments, the above-mentioned first data closest to the third data may be the closest downward, and the closest downward refers to taking the first data with a lower frequency corresponding to the chip as much as possible. For example, suppose that the two adjacent first data of the third data are the first data Y1 and the first data Y2, and the distances between the first data Y1 and the first data Y2 and the third data are the same. The chip frequency corresponding to the data Y1 is lower than the chip frequency corresponding to the second data Y2, so you can choose to use the chip frequency corresponding to Y1. If the distance between the first data Y1 and the first data Y2 is not equal to the third data, the first data with a relatively close distance can still be selected as the target first data. For another example, as long as the distance between the first data Y1 and the distance between the first data Y2 and the third data is within a preset range, the first data corresponding to the lower chip frequency is preferentially selected. The preset range can be based on the actual The requirement setting is not limited in the embodiment of the present invention.

In step 208, according to the determined target wafer frequency of each subtask, the operating frequency of the wafer to execute each subtask is set.

In this step, in the running process of the target task, when one of the subtasks is run, the frequency of the wafer can be set as the target wafer frequency of the subtask.

In the method for setting the operating frequency of the device chip in the embodiment of the present invention, the task to be executed is decomposed to obtain multiple subtasks, and the target chip frequency of each subtask is obtained respectively. This refined frequency setting method can make each task The sub-task part is as far as possible to achieve the best operating performance, thereby improving the running speed of the entire task. In addition, by pre-establishing the mapping relationship between task parameters, device information and chip frequency, it is possible to speed up the determination of chip frequency and improve device performance.

FIG. 4 shows another flowchart of a method for setting the working frequency of a chip provided by some embodiments of the present invention. In this example, setting the combined frequency of the chip is taken as an example for description, and the acquired device information may also include the chip The wafer temperature can be collected by the temperature sensor in the device where the wafer is located. In addition, it is assumed that the target task to be performed is a three-layer neural network model inference task.

Among them, for different terminal devices, such as GPU (Graphics Processing Unit, graphics processing unit), CPU or terminal device where the DSP chip is located, due to different device information, the power consumption model and runtime model obtained by training may be completely different. The model can be determined by offline training for the specific terminal device where the target task is running. After the power consumption model and the runtime model are determined, the determined model and the optimization problem solving engine can be stored in the terminal device. Among them, the processing performed by the optimization problem solving engine can be referred to the process of establishing the preset mapping relationship in the process description shown in Figure 2. The optimization problem solving engine can obtain the result based on the sampled multiple sets of first data and the determined model Each chip frequency corresponds to the chip running power consumption and task running time, and then the optimal chip frequency is selected according to formula (1), thereby establishing the mapping relationship between the first data and the second data. Optionally, the device may execute the establishment of the preset mapping relationship, or another device may execute the process of establishing the preset mapping relationship, and store the pre-established mapping relationship in the device where the target task is running. The device can directly look up the table when running the target task.

In step 400, task analysis is performed on the target task to be run on the device, and multiple subtasks and task parameters of each of the subtasks are obtained.

（n表示n維空間，比如訪存量，計算量）。子任務1、子任務2和子任務3可以被分別作為第一子任務。For example, the target task is an inference task of a three-layer neural network model, each of which can be a subtask. Then, after task analysis in this step, a subtask list can be obtained. The subtask list includes three subtasks: subtask 1, subtask 2, and subtask 3. In addition, this step also analyzes and obtains the task parameters of each subtask, for example, the amount of memory access and the amount of calculation of the subtask. For example, the subtask list may include: <subtask 1, task parameter 1>, <subtask 2, task parameter 2>, <subtask 3, task parameter 3>. The task parameters can be expressed as

(N represents n-dimensional space, such as the amount of memory access, the amount of calculation). Subtask 1, subtask 2, and subtask 3 can be regarded as the first subtask, respectively.

In step 402, the device information of the device where the chip is located is obtained.

Among them, the equipment information may include equipment resource information. In an example, the subtask 1, the subtask 2 and the subtask 3 are in a sequence relationship, and the equipment resource information occupied by these subtasks during operation may be the same. For example, the bandwidth, the number of computing units, etc. can be the same.

（m表示m維空間，比如頻寬、儲存裝置容量等）。Equipment information can be expressed as

(M represents m-dimensional space, such as bandwidth, storage device capacity, etc.).

In step 404, before it is determined that the execution of subtask 1 will start, the wafer temperature C1 on the wafer is collected, and according to the task parameters of subtask 1, equipment resource information, and the wafer temperature C1, it is determined that the equipment of subtask 1 is running. The upper chip corresponds to the set target chip frequency.

In some embodiments of the present invention, the device information may also include the wafer temperature of the wafer, because excessively high temperature during the execution of the task will also cause the wafer to take measures to reduce the frequency. That is to say, the device information in the embodiment of the present invention includes not only device resource information such as the number of computing units, bandwidth, storage device capacity, etc., but also chip temperature. In addition, the wafer temperature may be dynamically acquired, that is, before each subtask in the running process of the target task starts to execute, the wafer temperature corresponding to the subtask is acquired, and the target wafer frequency of the subtask is determined accordingly.

In step 406, the operating frequency of the wafer is set to the target wafer frequency of subtask 1, and the execution of subtask 1 is started.

In step 408, before it is determined that subtask 2 will be executed, the wafer temperature C2 on the wafer is collected, and based on the task parameters of subtask 2, equipment resource information and wafer temperature C2, it is determined that the equipment of subtask 2 is running. The upper chip corresponds to the set target chip frequency.

In the embodiment of the present invention, during the operation of the target task, the temperature of the wafer changes, then the latest wafer temperature can be collected and combined with the wafer before each subtask is executed during the operation of the target task. The temperature determines the target wafer frequency for this subtask.

It should also be noted that the chip frequency in the embodiment of the present invention may be a combined frequency or one of the combined frequencies, that is, the core frequency of the chip and the storage device frequency are set at the same time. For example, the core frequency is x, and the storage device frequency is y. For example, when the task parameters and device information of the subtask are (k1, d1) (the device information can include device resource information and chip temperature), the corresponding chip frequency can be (x1, y1); when the subtask is When the task parameters and equipment information are (k2, d2), the corresponding chip frequency can be (x2, y2).

In addition, when determining the power consumption model and the runtime model, for example, the input of the power consumption model can include: k1, d1, x1, y1, and the output of the model can be the chip's operating power consumption P; the same way, the input of the runtime model It can include: k1, d1, x1, y1, and the output of the model can be the task running time T. Moreover, when training the power consumption model and the runtime model, the device information may include the wafer temperature.

In step 410, the operating frequency of the wafer is set to the target wafer frequency of subtask 2, and the execution of subtask 2 is started.

In step 412, before it is determined that subtask 3 will be executed, the wafer temperature C3 of the wafer on the device is collected, and the task parameters of subtask 3, device resource information, and wafer temperature C3 are used to determine where subtask 3 is running. The chip on the device corresponds to the set target chip frequency.

In step 414, the operating frequency of the wafer is set to the target wafer frequency of subtask 3, and the execution of subtask 3 is started.

When all the subtasks included in the target task are executed, the operating frequency of the device chip can be reset to the preset value, and the execution of the target task ends.

In the method for setting the working frequency of the chip in the embodiment of the present invention, the task to be executed is decomposed to obtain multiple subtasks, and the target chip frequency of each subtask is obtained respectively. This refined frequency setting method can make each subtask of the task Some parts are as far as possible to achieve the best operating performance, thereby improving the running speed of the entire task. In addition, in the process of task operation, dynamically collecting the wafer temperature during the execution of the first subtask, and synthesizing the wafer temperature to determine the target wafer operating frequency of the first subtask, which can make the determination of the wafer operating frequency more comprehensive. Therefore, the frequency setting is more reasonable, and the operation performance of the equipment is further improved.

In addition, the terminal device may also provide a user interface through which the input configuration information for the preset mapping relationship can be received. For example, the user can calculate or estimate the target chip frequency that each subtask should use offline, and store the preset mapping relationship between each subtask and the corresponding target chip frequency in the device, so that the device runs according to the The configured preset mapping relationship only needs to set the working frequency of the corresponding chip when the subtask is executed.

The aforementioned user interface can also be used to receive frequency setting strategy information. The frequency setting strategy information may include, for example, a model for determining chip operating power consumption and task operating time based on task parameters and device information, or may also include how to select and determine the target chip frequency of a certain subtask based on the power consumption model and task operating time model. According to the frequency setting strategy information, the target chip frequency corresponding to the chip on the device when each subtask is running can be determined based on the frequency setting strategy information and the task parameters of each of the multiple subtasks.

In addition, the frequency setting strategy information may also include: turning on or off the chip frequency dynamic setting function for subtasks. When the frequency setting strategy information includes turning on the chip frequency dynamic setting function for subtasks, the device can determine the target chip frequency for each subtask of the target task according to the method for setting the chip operating frequency described in the foregoing embodiment of the present invention. For example, you can collect task parameters, chip temperature, equipment resource information of subtasks, and select and determine the target chip frequency to be used based on these information, power consumption model and task runtime model. When the frequency setting strategy information includes turning off the chip frequency dynamic setting function for subtasks, the device can directly obtain the target chip frequency that each subtask should use according to the preset mapping relationship configured offline through the user interface.

Through the above user interface, a more flexible chip frequency setting method can be provided, and the user can update the chip frequency determination method more conveniently, making the chip frequency determination more reasonable and faster.

FIG. 5 shows a block diagram of a device for setting the operating frequency of a chip provided by some embodiments of the present invention. As shown in FIG. 5, the device may include: an acquisition module 51, a frequency control module 52, and a frequency setting module 53.

The obtaining module 51 is configured to obtain multiple subtasks of the target task and task parameters of each subtask, and the task parameters include parameters for representing the calculation scale of the subtasks. Exemplarily, the task parameter includes at least one of the following: a calculation amount of the subtask, and a memory access amount of the subtask.

The frequency control module 52 is configured to determine the target chip frequency of each subtask based on the task parameter of each subtask in the plurality of subtasks.

The frequency setting module 53 is used for setting the working frequency of the chip to execute each subtask according to the determined target chip frequency of each subtask.

FIG. 6 shows another block diagram of the device for setting the operating frequency of a chip provided by some embodiments of the present invention. In an example, as shown in FIG. 6, the device may further include: a task analysis module 54 for performing task analysis processing on the target task to obtain the multiple subtasks and the task parameters of each subtask; and The corresponding relationship between each subtask and the task parameter of each subtask in the plurality of subtasks is stored. The obtaining module 51, when used to obtain multiple subtasks of the target task and the task parameters of each subtask, includes: searching the task parameters of each subtask from the stored correspondence relationship.

For example, in actual implementation, when starting to run a target task, the task analysis module 54 can first perform task analysis processing on the target task, such as analyzing multiple sub-tasks, and then separately perform tasks on each of the multiple sub-tasks. The task parameters of each subtask are obtained by parsing. The task analysis module 54 can store the corresponding relationship between each subtask obtained by the analysis and its task parameters.

The acquisition module 51 may be responsible for controlling the running process of the target task. For example, the acquisition module 51 may acquire the corresponding relationship parsed and stored by the task analysis module 54 described above, and control the execution of each subtask therein one by one. Exemplarily, assuming there are three subtasks, when the first subtask is to be executed, the obtaining module 51 can obtain the task parameters of the first subtask from the corresponding relationship, and combine the task parameters and the device's The equipment information is sent to the frequency control module 52, and the frequency control module 52 determines the target chip frequency of the first subtask according to the task parameters and the equipment information.

Then, the frequency control module 52 can send the determined target chip frequency to the frequency setting module 53, and the frequency setting module 53 can set the working frequency of the chip to the target chip frequency. Moreover, the frequency setting module 53 may send a feedback signal to the acquisition module 51 after setting the working frequency of the chip to notify the acquisition module 51 that the frequency setting has been completed. Then, the acquisition module 51 can start to execute the first subtask according to the feedback signal.

After the execution of the first subtask is finished, the acquisition module 51 can start to prepare to execute the second subtask. Similarly, before the execution of the second subtask, the acquisition module 51 can obtain the corresponding relationship from the task analysis module 54 The task parameters of the second subtask are obtained in the, and sent to the frequency control module 52 to determine the target chip frequency of the second subtask. After the frequency setting module 53 feedbacks that the chip frequency setting is completed, the acquisition module 51 starts to execute the second subtask. The implementation of the third subtask is similar, and will not be detailed again. After the acquisition module 51 confirms that all subtasks of the target task have been executed, it can send a frequency reset signal to the frequency control module 52, and the frequency control module 52 then sends a frequency reset signal to the frequency setting module 53 accordingly. The frequency setting module 53 can set the operating frequency of the chip to a preset value. At this point, the execution of the target task ends.

In one example, when the frequency control module 52 is used to determine the target chip frequency of each subtask based on the task parameters of each of the multiple subtasks, it includes: acquiring device information of the device where the chip is located , The equipment information includes equipment resource information; the target chip frequency of each subtask is determined based on the equipment information and the task parameter of each subtask of the plurality of subtasks. For example, the equipment resource information includes any one or more of the following: the number of computing units, bandwidth, and storage device capacity.

In an example, the device information further includes: the chip temperature of the chip; the frequency control module 52 is further used for: based on the task parameters of the first subtask among the plurality of subtasks, and the device resource information And the wafer temperature during execution of the first subtask to determine the target wafer frequency of the first subtask.

In an example, the frequency control module 52 is configured to obtain a preset mapping relationship between a plurality of first data and a plurality of second data, the first data including preset task parameters and preset device information, The second data includes a preset chip frequency; the target chip frequency of each subtask is determined according to the preset mapping relationship, the device information, and the task parameters of each subtask.

In one example, when the frequency control module 52 is used to determine the target chip frequency of each subtask according to the preset mapping relationship, the device information, and the task parameters of each subtask, it includes: determining the first 3. the distance between the data and each of the plurality of first data in the preset mapping relationship, the third data including task parameters and equipment information of the first subtask among the plurality of subtasks; The preset chip frequency corresponding to the target first data closest to the third data in the preset mapping relationship is used as the target chip frequency of the first subtask.

In one example, the frequency control module 52 is also used to obtain multiple sets of selectable chip frequencies before obtaining the preset mapping relationship between the multiple first data and the multiple second data, and obtain the discrete samples obtained A plurality of first data; for each of the first data in the plurality of first data, a set of chip frequencies is selected from the plurality of sets of selectable chip frequencies as corresponding to each of the first data And establish a mapping relationship between each of the first data and the selected second data.

In an example, the preset chip frequency corresponding to the first data in the preset mapping relationship is based on the first data under the condition of each group of selectable chip frequencies in a plurality of sets of selectable chip frequencies The corresponding performance evaluation parameters are selected from the multiple sets of optional chip frequencies.

In an example, the performance evaluation parameters include task processing performance parameters and chip operating power consumption; the preset chip frequency corresponding to the first data in the preset mapping relationship is: the multiple sets of selectable chip frequencies The operating power consumption of the medium chip is lower than the preset power consumption and the optional chip frequency with the best task processing performance parameters.

In an example, as shown in FIG. 6, the device may further include: an interface module 55 for receiving configuration information input by the user for the preset mapping relationship.

In one example, when the frequency control module 52 is used to determine the target chip frequency of each subtask based on the task parameters of each of the multiple subtasks, it includes: based on each of the multiple subtasks. The task parameters of each subtask are selected from a plurality of groups of selectable chip frequencies, and the chip frequency that enables the chip to achieve the lowest task running time under the limitation of chip power consumption is selected as the target chip frequency.

In an example, the interface module 55 is further used to: receive frequency setting strategy information input by the user; the frequency control module 52 is further used to: based on the frequency setting strategy information and each of the multiple subtasks The task parameters of each subtask determine the target chip frequency of each subtask.

In one example, the frequency setting strategy information includes turning on or off the chip frequency dynamic setting function for the subtask.

In an example, the operating frequency includes at least one of the following: a core frequency of the chip or a storage device frequency.

In some embodiments, the above-mentioned apparatus may be used to execute any corresponding method described above. For the sake of brevity, details are not repeated here.

FIG. 7 illustrates a block diagram of an electronic device with a chip operating frequency provided by some embodiments of the present invention. An embodiment of the present invention also provides an electronic device. As shown in FIG. 7, the electronic device 700 includes a storage device 710 and a processor 720. The storage device 710 is used for storing computer-readable instructions 711, and the processor 720 is used for The computer-readable instruction 711 is invoked to implement the method for setting the operating frequency of the chip in any embodiment of this specification. Wherein, the target chip for setting the chip operating frequency may be the storage device 710 and/or the processor 720. In an example, the electronic device 700 may further include a communication interface 730 and a bus 740. The storage device 710, the processor 720, and the communication interface 730 are connected to each other through a bus 740. In an example, the electronic device 700 may further include a wafer 750 for processing each subtask in the target task based on the operating frequency set by the processor 720.

An embodiment of the present invention also provides a computer-readable recording medium on which a computer program is stored. When the computer program is executed by a processor, it prompts the processor to implement the chip operating frequency setting of any embodiment of this specification. method. In an example, the computer-readable recording medium may be the storage device 710 in FIG. 7.

Those skilled in the art should understand that one or more embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, one or more embodiments of the present invention may adopt the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware. Moreover, one or more embodiments of the present invention may use one or more computer-readable recording media (including but not limited to magnetic disk storage devices, CD-ROMs, optical storage devices, etc.) containing computer-usable program codes therein. The form of a computer program product implemented on it.

Among them, the “and/or” in the embodiment of the present invention means having at least one of the two, for example, “multi and/or B” includes three schemes: multi, B, and “multi and B”.

The various embodiments of the present invention are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the data processing device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment.

The foregoing describes specific embodiments of the present invention. Other embodiments are within the scope of the attached patent application. In some cases, the actions or steps described in the scope of the patent application may be performed in a different order from the embodiment and still achieve desired results. In addition, the processes depicted in the drawings do not necessarily require the specific sequence or sequential sequence depicted in order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

The embodiments of the subject and functional operations described in the present invention can be implemented in the following: digital electronic circuits, tangible computer software or firmware, computer hardware including the structure disclosed in the present invention and structural equivalents thereof, or A combination of one or more of them. Embodiments of the subject matter described in the present invention can be implemented as one or more computer programs, that is, one or one of the computer program instructions encoded on a tangible non-transitory program carrier to be executed by a data processing device or to control the operation of the data processing device Multiple modules. Alternatively or additionally, the program instructions may be encoded on artificially generated propagated signals, such as machine-generated electrical, optical or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiver device for data transmission. The processing device executes. The computer-readable recording medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access storage device, or a combination of one or more of them.

The processing and logic flow described in the present invention can be executed by one or more programmable computers executing one or more computer programs to perform corresponding functions by operating according to input data and generating output. The processing and logic flow can also be executed by a dedicated logic circuit, such as FPGA (Field Programmable Gate Array) or ASIC (Special Application Integrated Circuit), and the device can also be implemented as a dedicated logic circuit.

Computers suitable for executing computer programs include, for example, general-purpose and/or special-purpose microprocessors, or any other types of central processing units. Generally, the central processing unit will receive commands and data from read-only memory and/or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more storage devices for storing instructions and data. Generally, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical discs, or the computer will be operably coupled to this mass storage device to receive data or Send data to it, or both. However, the computer does not have to have such equipment. In addition, the computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a universal serial bus (USB) ) Portable storage devices with flash drives, to name a few.

Computer-readable recording media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and storage devices, including semiconductor storage devices (such as EPROM, EEPROM, and flash memory devices), Disks (such as internal hard disks or mobile hard disks), magneto-optical disks, and CD ROM and DVD-ROM. The processor and storage device can be supplemented by or incorporated into a dedicated logic circuit.

Although the present invention contains many specific implementation details, these should not be construed as limiting any disclosed scope or claimed scope, but are mainly used to describe the features of specific disclosed specific embodiments. Certain features described in multiple embodiments of the present invention can also be implemented in combination in a single embodiment. On the other hand, various features described in a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although features can function in certain combinations as described above and even initially claimed as such, one or more features from the claimed combination can in some cases be removed from the combination, and the claimed The combination of protection can be directed to a sub-combination or a variant of the sub-combination.

Similarly, although operations are depicted in a specific order in the drawings, this should not be construed as requiring these operations to be performed in the specific order shown or performed sequentially, or requiring all illustrated operations to be performed to achieve desired results . In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can usually be integrated together in a single software product. , Or packaged into multiple software products.

Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the attached patent application. In some cases, the actions described in the scope of the patent application can be performed in a different order and still achieve desired results. In addition, the processes depicted in the drawings are not necessarily in the specific order or sequential order shown in order to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

The foregoing descriptions are only preferred embodiments of one or more embodiments of the present invention, and are not intended to limit one or more embodiments of the present invention. All within the spirit and principle of one or more embodiments of the present invention, Any modifications, equivalent replacements, improvements, etc. made should be included in the protection scope of one or more embodiments of the present invention.

100~104, 200~208, 2041~2043, 400~414: steps 51: Obtain modules 52: Frequency control module 53: Frequency setting module 54: Task Analysis Module 55: Interface Module 700: electronic equipment 710: storage device 711: instruction 720: processor 730: Communication interface 740: Bus 750: chip

FIG. 1 shows a flowchart of a method for setting the operating frequency of a wafer according to some embodiments of the present invention. FIG. 2 illustrates another flow chart of a method for setting the operating frequency of a wafer according to some embodiments of the present invention. FIG. 3 shows another flowchart of the process of establishing a preset mapping relationship provided by some embodiments of the present invention. FIG. 4 shows another flowchart of a method for setting the operating frequency of a wafer provided by some embodiments of the present invention. FIG. 5 shows a block diagram of a device for setting the operating frequency of a chip provided by some embodiments of the present invention. FIG. 6 shows another block diagram of the device for setting the operating frequency of a chip provided by some embodiments of the present invention. FIG. 7 illustrates a block diagram of an electronic device with a chip operating frequency provided by some embodiments of the present invention.

100~104: Step

Claims (15)

A method for setting the working frequency of a wafer, the method comprising: Acquiring multiple subtasks of the target task and task parameters of each subtask, where the task parameters include parameters used to indicate the operation scale of the subtasks; Determining the target chip frequency of each subtask based on the task parameter of each subtask in the plurality of subtasks; According to the determined target wafer frequency of each subtask, the operating frequency of the wafer for executing each subtask is set. The method according to claim 1, wherein the method further includes: Performing task analysis processing on the target task to obtain the multiple subtasks and the task parameters of each of the subtasks; Storing the corresponding relationship between each subtask and the task parameter of each subtask among the plurality of subtasks; The step of acquiring the multiple subtasks of the target task and the task parameters of each subtask includes: searching the task parameters of each subtask from the stored correspondence. The method according to claim 1 or 2, wherein the task parameter includes at least one of the following: a calculation amount of the subtask, and a memory access amount of the subtask. The method according to any one of claim items 1 to 3, wherein the step of determining the target chip frequency of each subtask based on the task parameter of each subtask of the plurality of subtasks includes: Acquiring device information of the device where the chip is located, where the device information includes device resource information; The target chip frequency of each subtask is determined based on the equipment information and the task parameter of each subtask of the plurality of subtasks. The method according to claim 4, wherein the device information further includes: the wafer temperature of the wafer; The step of determining the target chip frequency of each subtask based on the equipment information and the task parameters of each of the plurality of subtasks includes: The target chip frequency of the first subtask is determined based on the task parameters of the first subtask among the plurality of subtasks, equipment resource information, and the wafer temperature when the first subtask is executed. The method according to claim 4 or 5, wherein the step of determining the target chip frequency of each subtask based on the equipment information and the task parameter of each of the plurality of subtasks includes : Acquiring a preset mapping relationship between a plurality of first data and a plurality of second data, where the first data includes preset task parameters and preset device information, and the second data includes a preset chip frequency; The target chip frequency of each subtask is determined according to the preset mapping relationship, the equipment information, and the task parameter of each subtask. The method according to claim 6, wherein the step of determining the target chip frequency of each subtask according to the preset mapping relationship, the device information, and the task parameters of each subtask includes: Determine the distance between the third data and each first data in the plurality of first data in the preset mapping relationship, and the third data includes the information of the first subtask among the plurality of subtasks. The task parameters and the equipment information; The predetermined chip frequency corresponding to the first data closest to the third data in the predetermined mapping relationship is used as the target chip frequency of the first subtask. The method according to claim 6 or 7, wherein before the step of obtaining the preset mapping relationship between the plurality of first data and the plurality of second data, the method further includes: Acquiring multiple sets of selectable chip frequencies, and acquiring the plurality of discrete first data obtained by sampling; For each of the first data in the plurality of first data, select a set of chip frequencies from the plurality of selectable chip frequencies as the second data corresponding to each of the first data, and create The mapping relationship between each of the first data and the selected second data. The method according to any one of claim items 6 to 8, wherein the preset chip frequency corresponding to the first data in the preset mapping relationship is based on each group of optional chip frequencies among multiple groups of optional chip frequencies The performance evaluation parameter corresponding to the first data under the condition of frequency is selected from the multiple sets of optional chip frequencies. The method according to any one of claim items 1 to 9, wherein the step of determining the target chip frequency of each subtask based on the task parameter of each subtask in the plurality of subtasks includes: Based on the task parameters of each of the multiple subtasks, from a plurality of sets of optional chip frequencies, select the chip frequency that enables the chip to achieve the lowest task running time under the limit of chip power consumption, as The target chip frequency. The method according to any one of claims 1 to 10, wherein the method further comprises: Receive frequency setting strategy information input by the user; The step of determining the target chip frequency of each subtask based on the task parameters of each of the plurality of subtasks includes: setting strategy information based on the frequency and all of the plurality of subtasks The task parameters of each subtask determine the target wafer frequency of each subtask. The method according to any one of claims 1 to 11, wherein the operating frequency includes at least one of the following: a core frequency of the chip or a storage device frequency. A device for setting the operating frequency of a wafer, wherein the device comprises: An obtaining module for obtaining multiple subtasks of the target task and task parameters of each of the subtasks, where the task parameters include parameters used to indicate the operation scale of the subtasks; A frequency control module, configured to determine the target chip frequency of each subtask based on the task parameter of each of the multiple subtasks; The frequency setting module is used for setting the working frequency of the chip to execute each subtask according to the determined target chip frequency of each subtask. An electronic device comprising: a storage device and a processor, the storage device is used to store computer-readable instructions, and the processor is used to call the computer-readable instructions to implement the method described in any one of claim items 1 to 12 . A computer-readable recording medium has a computer program stored thereon, wherein when the computer program is executed by a processor, the processor implements the method described in any one of request items 1 to 12.

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