JP2022516549A - Chip operating frequency setting - Google Patents

Abstract

An embodiment of the present invention provides a chip operating frequency setting method and an apparatus, wherein the method obtains a plurality of subtasks of a target task and task parameters of each subtask, and each subtask in the plurality of subtasks. To determine the target chip frequency of each of the subtasks based on the task parameters of, and to set the target chip frequency corresponding to each of the established subtasks and the operating frequency when the chip executes each of the subtasks. And, and the task parameter includes a parameter for indicating the calculation scale of the subtask. [Selection diagram] Fig. 1

Description

The present invention relates to smart device technology, specifically, a chip operating frequency setting method, and a device.

With the development of 5G and artificial intelligence technology, end devices (eg smartphones, smart cameras, etc.) are given more computing requirements and need to perform more tasks. However, most of the chips included in the end device used for computing have limited power consumption, and the computing peak capacity of the device cannot be fully utilized. Frequency reduction is currently one of the main methods to prevent excessive power consumption of chips. The frequency reduction technique mainly reduces the power consumption of the chip by temporarily lowering the operating frequency (frequency) of the chip.

In some technologies, one initial operating frequency may be set and the chip may be operated at the initial operating frequency to perform computing processing of the application before executing the application on the end device. In addition, if the power consumption of the chip exceeds the standard during the operation process of the application, a certain frequency reduction strategy can be adopted for the chip. For example, the operating frequency of the chip is reduced in a certain proportion, or which operating frequency is reduced to a certain numerical value.

The embodiments of the present invention provide at least a chip operating frequency setting method and an apparatus.

According to the first aspect, a method for setting a chip operating frequency is provided, in which the method obtains a plurality of subtasks of a target task and task parameters of each subtask, and task parameters of each subtask in the plurality of subtasks. Including determining the target chip frequency of each of the subtasks based on, and setting the operating frequency when the chip executes each of the subtasks based on the determined target chip frequency of each subtask. , The task parameter includes a parameter for indicating the calculation scale of the subtask.

According to any embodiment of the present invention, the method performs a task analysis process on the target task to obtain the plurality of subtasks and task parameters of each subtask, and among the plurality of subtasks. To memorize the correspondence between each subtask and the task parameter of each subtask, and to acquire a plurality of subtasks of the target task and the task parameters of each subtask, each subtask is memorized from the memorized correspondence. Includes searching for task parameters for.

According to any embodiment of the invention, the task parameter comprises at least one of the computational complexity of the subtask and the memory access amount of the subtask.

According to any embodiment of the present invention, determining the target chip frequency of each subtask based on the task parameters of each subtask among the plurality of subtasks is the device information of the device on which the chip is arranged. The device information includes device information and determining the target chip frequency of each subtask based on the device information and the task parameters of each subtask among the plurality of subtasks. including.

According to any embodiment of the invention, the device resource information includes any one or more of the number of compute units, bandwidth, and memory capacity.

According to any embodiment of the invention, the device information further includes the chip temperature of the chip, and the target chip of each subtask is based on the device information and the task parameters of each subtask in the plurality of subtasks. Determining the frequency is based on the task parameters of the first subtask among the plurality of subtasks, the device resource information, and the chip temperature when the first subtask is executed, and the target chip of the first subtask. Includes determining the frequency.

According to any embodiment of the invention, determining the target chip frequency of each subtask based on the device information and the task parameters of each subtask among the plurality of subtasks is a plurality of first data and a plurality. The first data includes a predetermined task parameter and a predetermined device information, and the second data includes a predetermined chip frequency. It includes determining the target chip frequency of each subtask based on the predetermined mapping relationship, the device information, and the task parameters of each subtask.

According to any embodiment of the invention, determining the target chip frequency of each subtask based on the predetermined mapping relationship, the device information, and the task parameters of each subtask is the third data and the predetermined. The third data is to determine the distance between each of the first data in the plurality of first data in the mapping relationship of the third data, the task parameters of the first subtask in the plurality of subtasks, and the task parameters of the first subtask. The predetermined chip frequency corresponding to the target first data including the device information and the closest distance to the third data in the predetermined mapping relationship is determined as the target chip frequency of the first subtask. And, including.

According to any embodiment of the invention, the method obtains a plurality of sets of selectable chip frequencies before obtaining a predetermined mapping relationship between the plurality of first data and the plurality of second data. Then, a plurality of discrete first data obtained by sampling are acquired, and for each of the first data in the plurality of first data, the second data corresponding to each of the first data is obtained. The present invention includes selecting one set of chip frequencies from the plurality of sets of selectable chip frequencies and constructing a mapping relationship between each of the first data and the selected second data. ..

According to any embodiment of the present invention, the predetermined chip frequency corresponding to the first data in the predetermined mapping relationship is the selectable chip frequency of each set among the plurality of selectable chip frequencies. It is selected from the plurality of sets of selectable chip frequencies based on the performance evaluation parameters corresponding to the first data under the condition of.

According to any embodiment of the present invention, the performance evaluation parameters include task processing performance parameters and chip operating power consumption, and the predetermined chip frequencies corresponding to the first data in the predetermined mapping relationship are the plurality. The chip operating power consumption in the set of selectable chip frequencies is less than the predetermined power consumption, and the task processing performance parameter is the best selectable chip frequency.

According to any embodiment of the invention, the method further comprises receiving configuration information for the predetermined mapping relationship entered by the user.

According to any embodiment of the present invention, determining the target chip frequency of each subtask based on the task parameters of each subtask in the plurality of subtasks corresponds to each subtask in the plurality of subtasks. From among a plurality of sets of selectable chip frequencies based on the task parameters to be performed, the operation time for realizing the task under the chip power consumption limiting condition of the chip as the target chip frequency can be shortened to the shortest. Includes selecting possible chip frequencies.

According to any embodiment of the invention, the method further comprises receiving frequency setting strategy information entered by the user, said based on task parameters corresponding to each subtask among the plurality of subtasks. Determining the target chip frequency of each subtask includes determining the target chip frequency of each subtask based on the frequency setting strategy information and the task parameters of each subtask in the plurality of subtasks.

According to any embodiment of the invention, the frequency setting strategy information includes turning on or off the chip frequency dynamic setting function for a subtask.

According to any embodiment of the invention, the operating frequency comprises at least one of the core frequency or the memory frequency of the chip.

According to the second aspect, a chip operating frequency setting device is provided, in which the device includes a acquisition module for acquiring a plurality of subtasks of a target task and task parameters of each subtask, and each subtask in the plurality of subtasks. Based on the task parameters of, the frequency control module for determining the target chip frequency of each of the subtasks, and the operating frequency when the chip executes each of the subtasks based on the determined target chip frequency of each subtask. A frequency setting module for setting is provided, and the task parameter includes a parameter for indicating the calculation scale of the subtask.

According to a third aspect, an electronic device is provided, the electronic device comprising a memory and a processor, wherein the memory stores a machine-readable instruction, and the processor calls the machine-readable instruction. The method described in the first aspect of the present invention is implemented.

According to any embodiment of the invention, the device further comprises a chip that performs processing for each subtask in the target task at an operating frequency set by the processor.

According to a fourth aspect, a computer-readable recording medium on which a computer program is recorded is provided so that when the program is executed by a processor, the processor performs the method according to the first aspect of the present invention. To.

According to the chip operating frequency setting method and apparatus provided by the embodiment of the present invention, the chip executes each subtask by determining the target chip frequency of the subtask based on the task parameter of each subtask in the target task. When doing so, it can be made to operate at the target chip frequency of the subtask. Such a sophisticated frequency setting method can achieve the best possible operating performance when executing each subtask, and can improve the operating speed of the entire task.

It is a flowchart which shows the chip operation frequency setting method provided by some Embodiment of this invention. It is another flowchart which shows the chip operation frequency setting method provided by some examples of this invention. It is another flowchart which shows the construction process of the predetermined mapping relation provided by some examples of this invention. It is another flowchart which shows the chip operation frequency setting method provided by some examples of this invention. It is a block diagram which shows the chip operation frequency setting apparatus provided by some examples of this invention. It is another block diagram which shows the chip operation frequency setting apparatus provided by some examples of this invention. It is a block diagram which shows the electronic device of the chip operating frequency provided by some examples of this invention.

Hereinafter, in order for a person skilled in the art to better understand the technical solution of one or more embodiments of the present invention, the present invention will be referred to in reference to the drawings in one or more embodiments of the present invention. A clear and complete description of the technical solution of one or more embodiments of the invention. Of course, the examples described are only partial examples of the present invention, not all examples. All other examples obtained by one of ordinary skill in the art based on one or more embodiments of the invention without creative work shall be within the scope of the invention.

The embodiments of the present invention provide a method of setting the operating frequency of a chip in an end device. The method aims to improve the operating performance of the device when the chip operates at the set operating frequency. For example, tasks running on a device can be processed and completed faster. Here, the chip can be an Artificial Intelligence (AI) chip, for example used in AI chips used in smartphones, AI chips used in self-driving vehicles, and Internet of Things edge devices. It can be an AI chip or the like. Further, it may be another type of chip such as a CPU (Central Processing Unit) chip, a DSP (Digital Signal Processing), a memory chip, and the like, and the embodiments of the present invention are not limited thereto.

FIG. 1 is a flowchart showing a chip operating frequency setting method provided by some embodiments of the present invention, and as shown in FIG. 1, the method includes the following processing.

In step 100, a plurality of subtasks of the target task and task parameters of each subtask are acquired, and the task parameters include parameters for indicating the calculation scale of the subtasks.

In this step, the target task may be a task to be performed and processed on the device. For example, the task may be a deep learning model training task, a neural network model inference task, or application operation. Execution of the target task needs to use a chip on the device, and the chip is responsible for some or all processing operations such as calculations in the task execution process.

The subtask may be one relatively independent execution unit contained in the target task. For example, a goal task can include multiple functions, the goal task can be divided according to the function, and each function is used as one independent subtask of the goal task. Also, for example, the task code is divided into a plurality of code blocks, the subtasks are divided according to the code blocks, and the code of each segment is relatively complete. For example, use one relatively complete code block or a separate code block as one subtask. Further, for example, when the target task is a training or inference task of the neural network model, each layer or a plurality of layers of the neural network model can be regarded as one subtask. Alternatively, the code segments in the realization process of each layer can be used as one subtask. Also, for example, one or at least two functional modules in a plurality of functional modules can be used as one subtask.

The embodiment of the present invention is not limited to the method of dividing the subtask. There can be multiple subtask division methods, for example, the functions, code blocks, network layers, or operators mentioned above can be divided in units, or functional modules can be divided in units. Dividing the target task into multiple subtasks can provide finer frequency settings and improve device performance, but too many subtasks result in more frequent frequency settings and constant device performance. It should be noted that it can have an impact. Therefore, the setting of the number of subtasks can be balanced, and for example, the inside of the loop body included in the target task can be not further divided into subtasks as much as possible, and the number of frequency settings can be reduced in this way. Specifically, it can be set according to the actual request, and will not be described repeatedly here.

In the embodiment of the present invention, the task parameter of the subtask may include a parameter indicating the operation scale of the subtask, and may include, for example, a parameter of one or a plurality of resources that the subtask needs to occupy. As an example, the task parameter is the calculation amount of the subtask, the memory access amount (the memory access amount is the number of times the chip accelerates the memory when the subtask is executed, and / or the total amount of access data). It may include, but is not limited to, at least one. Alternatively, other types of task parameters may be further included, and the embodiments of the present invention are not limited thereto.

In the embodiment of the present invention, the task parameters of the subtask can be acquired by a plurality of methods. For example, you may get the task parameters of a subtask from another device or another functional module in the system, you may get the task parameters of a subtask from local memory, or you may perform task analysis on the target task. Then, the task parameters of each subtask may be acquired.

In some embodiments, the correspondence between each subtask and each task parameter can be stored in advance in order to acquire the task parameter at a higher speed. Illustratively, it is possible to execute an analysis process on a target task task in advance to obtain a plurality of subtasks included in the target task and task parameters of each subtask, and to store each subtask and its task parameters. can. In this way, when the target task needs to operate in succession, the task parameter of each subtask can be searched at high speed based on the stored information. In some examples, the correspondence between the subtask and the task parameters can be stored in the form of key-value. For example, a corresponding task identifier is set for each of a plurality of subtasks, the task identifier of the subtask is stored as a key, and the task parameter of the subtask is stored as a value. The key-value form storage method is suitable for inquiry via a primary key, the inquiry speed is high, and the amount of data to be stored is large. However, the present invention is not limited to this.

In some embodiments, in addition to the task parameters of each subtask, the device information of the device on which the chip is placed is acquired, and the target chip frequency of each subtask is jointly determined based on the device information and the task parameters. can do.

Here, the device information may include device resource information of the device on which the chip is arranged, and the device resource information is used to indicate information on available resources of the device. As an example, the device resource information may include, but is not limited to, any one or more of the number of compute units, bandwidth, and memory capacity. In some embodiments, the target chip frequency of each subtask can depend on the dependencies between the plurality of subtasks or the way the task is performed, eg, serial, parallel, or serial among some subtasks. You can rely on modes that are parallel between some other subtasks. For example, if the execution of each subtask obtained by dividing the target task is serial, the chip may occupy all available device resources on the device when executing each subtask. It can, for example, occupy all computing units and all bandwidth on the device, but the embodiments of the invention are not limited to this.

In step 102, the target chip frequency of each subtask is determined based on the task parameters of each subtask among the plurality of subtasks.

In this step, the target chip frequency of the subtask can be determined based on the task parameters of each subtask. Alternatively, the target chip frequency of each subtask can be jointly determined based on the device information of the device on which the chip is arranged and the task parameter of each subtask.

In some embodiments, multiple sets of selectable chip frequencies are determined and the corresponding selectable chips for each subtask from among the multiple sets of selectable chip frequencies according to a particular strategy. You can select the frequency. Here, the plurality of sets of selectable chip frequencies may be a specific number of discrete frequencies that can be set for the chip of the device. For example, taking an example of setting the core frequency of a chip, the core frequency may include frequency values of M types such as x1, x2, ..., XM. The strategy can be set according to the actual requirements. Hereinafter, some exemplary strategies will be described, but the embodiments of the present invention are not limited thereto.

In some embodiments, the determination of the target chip frequency can be transformed into an optimization problem, and in some selectable embodiments, it can be determined as the main reference factor for selecting the task run time. .. As an example, a task is realized under the chip power consumption limiting condition of the chip as the target chip frequency of each subtask from a plurality of sets of selectable chip frequencies that can be set based on the task parameters of each subtask. You can select the chip frequency that can minimize the operating time. Here, in some examples, the plurality of subtasks can be analyzed as a whole to determine the overall task operating time of the target task. In this case, after the shortest task operation time is determined, the target chip frequency of each subtask among the plurality of subtasks can be obtained at the same time. Alternatively, in some other examples, the task operating time of each subtask can be analyzed individually and the target chip frequency of the subtask can be determined subject to the shortest task operating time of each subtask. In some other selectable embodiments, it is used as a reference factor to select one or any of the system resources consumed by the task, chip operating power consumption, task operating speed, and accuracy of task execution results. However, the embodiments of the present invention are not limited thereto.

Hereinafter, the principle of solving the optimization problem will be illustrated by taking an example of determining the target chip frequency based on the task parameters and device information of the subtask. Here, taking an example of one subtask, the task parameter of the subtask is kn (n indicates an ⁿ -dimensional space, for example, a memory access amount, a calculation amount, etc.), and corresponds to the subtask. The device information to be used is d ^M (M indicates an M-dimensional space, for example, a memory capacity). It is assumed that the chip frequency is x, where the frequency can be a core frequency, a memory frequency, or a combination of a core frequency and a memory frequency. P (kn, ^{d M} , x) indicates the chip operating power consumption, and it can be seen that the chip operating power consumption is related to the task parameter, the device information, and the chip frequency. Even if the task parameters and device information are fixed, when the chip frequency changes, P also changes accordingly. T (kn, ^{d M} , x) indicates the task operation time. Similarly, even if the task parameters and device information are fixed, when the chip frequency changes, T also changes accordingly. In this case, the task parameters and device information of the subtask are each combined with a plurality of chip frequencies to obtain the corresponding chip operating power consumption and task operating time, and the chip operating power consumption and task operating time are based on the plurality of chip frequencies. The optimum chip frequency for each subtask can be selected from among them.

For example, the best chip frequency can be selected according to the following equation (1).

The above equation (1) shows that the operation time for realizing the task under the chip power consumption limited condition (Power _Limited ) is the shortest, and this is the optimization goal of the optimization problem. Find the best chip frequency for your optimization goal. When a specific chip frequency is adopted from a plurality of selectable chip frequencies that can be set for the chip, and the processing of the subtask can be completed in the shortest task operation time under the chip power consumption limiting condition, The chip frequency is the target chip frequency of the subtask.

Since the task parameters of each subtask and at least one parameter in the device information can be different from each other, the target chip frequency of each subtask can also be different from each other. This step can find the optimum target chip frequency for each subtask, the subtask can be completed at the fastest speed, and the power consumption of the chip does not exceed the standard.

In step 104, the operating frequency at which the chip executes each of the subtasks is set based on the determined target chip frequency of each subtask.

In this step, in the operation process of the target task, when the operation is performed by one of the subtasks, the chip frequency is set to the target chip frequency of the subtask, or the target chip frequency and the device are used. Alternatively, the operating frequency when the chip executes the subtask can be set based on the current state information such as the chip temperature when the chip starts executing the subtask. Here, in some embodiments, the process of determining the target chip frequency can be executed in advance before executing the target task, and the target chip frequency of each subtask among the plurality of subtasks is stored. can do. After that, in the operation process of each subtask, the frequency of the chip can be set to the target chip frequency of the subtask. In some other embodiments, the target chip frequency of each subtask can be determined before performing each subtask. For example, the target chip frequency of the subtask can be determined based on the task parameters of the subtask and the current state information of the device or chip. In this case, the determination of the target chip frequency of each subtask can be performed at different time points from each other, and the embodiments of the present invention are not limited thereto.

In the embodiment of the present invention, the operating frequency of the chip may include at least one of the core frequency or the memory frequency of the chip. For example, the methods of the embodiments of the present invention can only be used to set the core frequency of the chip, where the memory frequency is set to a fixed value or set in units of target tasks. Can be. Alternatively, the method can only be used to set the memory frequency, where the core frequency can be set to a fixed value or set in units of target tasks. Alternatively, the method is used to set the core frequency and memory frequency of the chip, for example, the core frequency and memory frequency can be set as one frequency combination, and the target chip frequency of each subtask is the combination of the frequencies. be.

Here, the frequency of the memory may be the frequency of the volatile memory, for example, the frequency of SDRAM (SynchrOnOus DynaMic RandoM Access memory, synchronous dynamic random access memory). For example, it may be a DDR SDRAM (DOuble Data Rate SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a DDR4 SDRAM, a DDR5 SDRAM, or the like. The frequency of the memory can further be the frequency of the non-volatile memory and can be the frequency of the flash memory.

According to the chip operating frequency setting method of the embodiment of the present invention, the target chip frequency of the subtask is determined based on the task parameter of each subtask in the target task, so that the subtask is executed when the chip executes each subtask. It can be made to operate at the target chip frequency of. Such a sophisticated frequency setting method can achieve the best possible operating performance when executing each subtask, and can improve the operating speed of the entire task.

FIG. 2 is another flowchart showing a chip operating frequency setting method of some embodiments of the present invention, in which the method jointly determines a target chip frequency based on subtask task parameters and device information. As an example, we propose a method to determine the target chip frequency. As shown in FIG. 2, the method may include the following processing, where the same steps as in FIG. 1 will not be repeated.

In step 200, task analysis is performed on the target task to be operated on the device to obtain a plurality of subtasks and task parameters of each said subtask. For example, the task parameter of each subtask may include at least one of the complexity and memory access of the subtask.

In step 202, the device information of the device in which the chip is arranged is acquired.

For example, the device information of the device on which the chip is located may include device resource information, which may include at least one of bandwidth, number of computing units, and memory capacity. ..

In step 204, a predetermined mapping relationship between the plurality of first data and the plurality of second data is acquired.

In this step, the device may store in advance the mapping relationship between the plurality of first data and the plurality of second data, and the first data in the mapping relationship is a predetermined task parameter of the subtask. And the predetermined device information is included, and the second data includes the predetermined chip frequency. For example, the predetermined chip frequency can be the core frequency of the chip. Further, for example, the predetermined chip frequency may be a combination of the core frequency and the memory frequency of the chip.

For example, Table 1 below shows a predetermined mapping relationship between a plurality of first data and a plurality of second data.

How to construct the above-mentioned mapping relationship will be exemplified below.

Regardless of the type of task performed on the device, the values of task parameters and device information are assumed to be within a certain range. For example, the value of the task parameter is in the range F1 and the value of the device information is in the range F2. Both F1 and F2 can be referred to as a predetermined range of first data values. In this case, some discrete sampling points can be obtained by sampling within the range of the first data value, that is, (k1, d1), (k2, d2), (k3, d3) and the like. The first data of a plurality of sets of can be obtained. Among them, k1, k2, and k3 indicate task parameters, and d1, d2, and d3 indicate device information. Assuming that the chip frequency to be set is the core frequency, a plurality of sets of selectable chip frequencies that can be set in the chip may be included, and may include, for example, x1, x2, x3, and the like.

Specifically, for the first data of each set in the set, one set of chip frequencies is selected from the plurality of sets of selectable chip frequencies as the second data corresponding to the first data. Then, a mapping relationship between the first data and the second data can be constructed. Here, in some embodiments, when the second data is selected from a plurality of sets of selectable chip frequencies, it can be selected based on the performance evaluation parameters. For example, the performance evaluation parameters under the condition of the selectable chip frequency of each set of the first data can be determined, for example, based on the first data and one set of selectable chip frequencies in the first data. One performance evaluation parameter can be obtained, and another performance evaluation parameter can be obtained based on the first data and another set of selectable chip frequencies. Here, the performance evaluation parameter can be obtained by a method of simulation, inference, or mathematical calculation, and the embodiment of the present invention is not limited thereto.

After obtaining the corresponding performance evaluation parameters under the conditions of the selectable chip frequencies of each set of the first data, the said one from the plurality of sets of selectable chip frequencies based on the performance evaluation parameters. A set of chip frequencies can be selected as the second data corresponding to the first data. For example, the performance evaluation parameter may include task processing performance parameters and chip operating power consumption, where the chip operating power consumption among the plurality of selectable chip frequencies is less than a predetermined power consumption and the task. The selectable chip frequency with the best processing performance parameter can be used as the second data corresponding to the first data. Illustratively, the task processing performance parameters include, but are not limited to, task processing time.

FIG. 3 below illustrates the process of constructing a predetermined mapping relationship, and in the description of the example, the task processing performance parameter is the task operation time, and the chip frequency is the core frequency.

In step 2041, for each set of selectable chip frequencies, each set of selectable chip frequencies is based on each set of selectable chip frequencies and a specific set of first data. The chip operation power consumption and the task operation time when operating under the condition of the first data are obtained.

For example, a chip has 10 sets of selectable chip frequencies, and for each set of first data, 10 sets of chip frequencies are combined with 10 sets of chip operating power consumption P and 10 task operations. Get time T. For example, when the chip frequency is x1, the chip operating power consumption of the corresponding subtask is P1, the task operating time is T1, and when the chip frequency is x2, the chip operating power consumption of the corresponding subtask is. It is P2, and the task operation time is T2.

In some embodiments, P can be determined based on the power consumption model and T can be determined based on the operating time model. Here, the model input of the power consumption model is the task parameter, the device information, and the chip frequency, and the model output is P. The model input of the operating time model is task parameters, device information, and chip frequency, and the model output is T.

Specific configurations of the power consumption model and the operating time model can be obtained by a plurality of methods, and support, for example, a vector machine, a feedback neural network, a K-means aggregation algorithm, and the like.

Hereinafter, both the power consumption model and the operating time model will be described by taking an example of being a neural network model, and the neural network model can be obtained by a model training method. Here, the training sample set is a fixed task list X = {r _1, r _2, ... r _p }, and the device frequency set is X = {r _1, r _2, ... r. _q }, and these sets are used as training sets for neural network models. For example, for a specific task r ₁ , the task parameters of the task are obtained, the device information of the device is acquired, one frequency x ₁ is obtained from the device frequency set, and these three are used in the power consumption model. It is confirmed as an input, and the predicted value of the chip operating power consumption is output after processing the power consumption model. There is a difference between the predicted value and the task parameter entered by the device, the device information, and the actual value of the chip operation power consumption under the condition of frequency x ₁ (result of the actual device operation). Backpropagation is performed based on the difference to train the power consumption model. Similarly, the operating time model can also be trained by the method described above, but the output may be changed to the task operating time, which will not be repeated here.

After obtaining the trained power consumption model and operating time model, the chip operating power consumption can be obtained by inputting the first data and the chip frequency into the power consumption model. For example, if the first data (k1, d1) and the chip frequency xi are input to the power consumption model, the chip operating power consumption Pi can be obtained. If the first data and the chip frequency are input to the operation time model, the task operation time can be obtained. For example, if the first data (k1, d1) and the chip frequency xi are input to the operation time model, the task operation time Ti can be obtained.

In step 2042, as the second data corresponding to the first data, the chip frequency having the best chip operating power consumption and task operating time is selected.

In this step, for example, according to the optimum chip frequency selection condition of the equation (1), the task operation time is the longest within the limit range of the chip operating power consumption as the second data from a plurality of sets of chip frequencies. Select a short chip frequency. For example, among all the chip frequencies xi satisfying Pi ≦ POWERLiMitted, the chip frequency having the smallest Ti is selected, and x1 is selected as the second data corresponding to the first data (k1, d1), for example.

In step 2043, a mapping relationship between the first data and the second data is established.

As described above, among the first data of the plurality of sets corresponding to the discrete sampling points, each of the first data of each set corresponds to the first data according to the process shown in FIG. The second data can be obtained, that is, the best chip frequency can be obtained. In this way, it is possible to obtain a set of mapping relationships by obtaining the second data corresponding to each of the first data in the plurality of first data and constructing each mapping relationship based on the second data. can. The set includes a plurality of sets of mapping relationships, each set of mapping relationships containing one first data and one corresponding second data. The set of mapping relationships can be the predetermined mapping relationships described in step 204, for example as in Table 1.

In step 206, the corresponding chip frequency in the predetermined mapping relationship of the subtask is determined as the target chip frequency based on the predetermined mapping relationship, device information, and task parameters of the subtask.

For example, it is assumed that the task parameter of a certain subtask is k1, the device information corresponding to the subtask is d1, and the target chip frequency obtained by searching Table 1 is x1. The subtask is called a first subtask.

Since the first data in the mapping relation table is discrete, the task parameters and device information of the first subtask may not completely match the first data in the mapping relation. In such a case, As a selectable embodiment, the device information of the first task and the first data closest to the task parameter can be searched in the mapping relation table, and the chip frequency corresponding to the closest first data is set. 1 Determine as the target chip frequency of the subtask.

For example, the task parameters and device information of the first subtask are called the third data, and if it is (k3, d3), for example, the distance between the third data and each of the first data in the mapping relationship is calculated. can do. In the calculation of the distance, the distance between the vectors can be calculated by using the third data and each of the first data as one vector. For example, it can be an Euclidean distance or other distance between the vector of the third data and the vector of each first data. The chip frequency corresponding to the first data closest to the third data can be determined as the target chip frequency of the first subtask.

Here, in some embodiments, the first data closest to the third data can be downward and closest data, and the downward closest data is the corresponding chip frequency. Can be the lower first data. For example, the two adjacent first data of the third data are the first data Y1 and the first data Y2, respectively, and the distances between the first data Y1 and the first data Y2 and the third data are equal, and the third data is the same. When the chip frequency corresponding to the 1 data Y1 is lower than the chip frequency corresponding to the second data Y2, the chip frequency corresponding to the Y1 is selected. If the distances between the first data Y1 and the first data Y2 and the third data are not equal, the first data having a closer distance is still selected as the target first data. Further, for example, when the difference between the distances between the first data Y1 and the first data Y2 and the third data is within a predetermined range, the first data having a lower corresponding chip frequency is preferentially selected. The predetermined range can be set according to actual requirements, and the embodiments of the present invention are not limited thereto.

In step 208, the operating frequency at which the chip executes each of the subtasks is set based on the target chip frequency of each of the determined subtasks.

In this step, the frequency of the chip can be set as the target chip frequency of the subtask when the target task is operated by one of the subtasks in the operation process.

According to the method of setting the operating frequency of the device chip according to the embodiment of the present invention, a task waiting to be executed is decomposed to obtain a plurality of subtasks, and a target chip frequency of each subtask is obtained. Such a sophisticated frequency setting method can make each subtask of the task realize the best possible operating performance, and can improve the operating speed of the entire task. Further, by constructing a mapping relationship between the task parameter, the device information, and the chip frequency in advance, the fixed speed of the chip frequency can be increased and the device performance can be improved.

FIG. 4 is another flowchart showing a chip operating frequency setting method of some embodiments of the present invention, and will be described by taking an example of setting a combination frequency of chips in the example. Further, the acquired device information may further include the chip temperature of the chip, and the chip temperature is collected by the temperature sensor in the device in which the chip is arranged. Here, the target task to be executed is an inference task of a three-layer neural network model.

Here, in the case of different end devices such as GPU (Graphics Processing Unit), CPU, or end device in which a DSP chip is arranged, the device information is different from each other, so training is obtained. The power consumption model and the operating time model to be used may be completely different from each other. The deterministic model can be trained offline for the specific end device on which the target task is running. After the power consumption model and the operating time model are established, the determined model and the optimization problem solving engine are stored in the end device. Here, the process performed by the optimization problem solving engine may refer to the process of constructing a predetermined mapping relationship in the description of the process shown in FIG. The optimization problem solving engine obtains chip operating power consumption and task operating time corresponding to each chip frequency based on a plurality of sets of first data sampled and a fixed model, and further, equation (1). By selecting the best chip frequency according to the above, the mapping relationship between the first data and the second data can be constructed. Optionally, a device can be used to build a given mapping relationship, or another device can be used to perform a given mapping relationship building process to create a pre-built mapping relationship. The target task can be stored in the operating device. The device can directly search and use the table when running the target task.

In step 400, task analysis is performed on the target task to be operated by the device to obtain a plurality of subtasks and task parameters of each said subtask.

For example, the target task may be an inference task of a three-layer neural network model, in which each layer may be one subtask. In this case, this step can obtain one subtask list through task analysis, and the subtask list includes three subtasks such as subtask 1, subtask 2, and subtask 3. Further, this step is obtained by further analyzing the task parameters of each subtask, such as the memory access amount and the calculation amount of the subtask. For example, the subtask list may include <subtask 1, task parameter 1>, <subtask 2, task parameter 2>, and <subtask 3, task parameter 3>. The task parameters in it can be indicated by kn (n indicates an ⁿ -dimensional space, for example, a memory access amount or a calculation amount). Subtask 1, subtask 2, and subtask 3 can be used as the first subtask, respectively.

In step 402, the device information of the device in which the chip is arranged is acquired.

Here, the device information may include device resource information. In one example, the subtask 1, the subtask 2, and the subtask 3 have a serial relationship, and the device resource information occupied when these subtasks are operated is the same. For example, the bandwidth, the number of computing units, etc. can be the same.

Device information can be represented by d ^M , where M represents an M-dimensional space, eg bandwidth or memory capacity.

In step 404, the device when the chip temperature C1 of the chip is collected before the subtask 1 is started to be executed, and the subtask 1 is operated based on the task parameters of the subtask 1, the device resource information, and the chip temperature C1. Determine the target chip frequency to be set for the chip.

In some embodiments of the invention, the device information may further include the chip temperature of the chip, which will take steps to lower the frequency of the chip if the temperature is too high in the process of performing the task. Because. That is, the device information of the embodiment of the present invention further includes the chip temperature in addition to the device resource information such as the number of calculation units, the bandwidth, and the memory capacity. Further, the chip temperature may be dynamically acquired, that is, the chip temperature corresponding to the subtask is acquired before executing each subtask in the operation process of the target task, and the subtask is acquired based on the chip temperature. The target chip frequency of can be determined.

In step 406, the operating frequency of the chip is set to the target chip frequency of the subtask 1, and the subtask 1 is started to be executed.

In step 408, before starting the execution of the subtask 2, the chip temperature C2 of the chip is collected, and the device when operating the subtask 2 based on the task parameter of the subtask 2, the device resource information, and the chip temperature C2. Determine the target chip frequency to be set for the chip.

In the embodiment of the present invention, when the temperature of the chip is changed in the operation process of the target task, the latest chip temperature is collected every time one subtask is executed in the operation process of the target task. The target chip frequency of the subtask is determined by combining the chip temperatures.

It is necessary to explain that the chip frequency of the embodiment of the present invention can be one combination frequency or one frequency in the combination frequency, that is, the core frequency and the memory frequency of the chip can be set simultaneously. For example, the core frequency is x and the memory frequency is y. For example, if the task parameter and device information of the subtask is (k1, d1) (the device information in it may include the device resource information and the chip temperature), the chip frequency to be adopted may be (x1, y1). If the task parameter and device information of the subtask is (k2, d2), the chip frequency to be adopted can be (x2, y2).

Further, when determining the power consumption model and the operating time model, for example, the input of the power consumption model may include k1, d1, x1, y1 and the output of the model may be the chip operating power consumption P, and so on. In addition, the input of the operating time model may include k1, d1, x1, y1 and the output of the model may be the task operating time T. Also, when training the power consumption model and operating time model, the device information may include chip temperature.

In step 410, the operating frequency of the chip is set to the target chip frequency of the subtask 2, and the subtask 2 is started to be executed.

In step 412, before starting the execution of the subtask 3, the chip temperature C3 of the chip is collected, and the device when operating the subtask 3 based on the task parameter, the device resource information, and the chip temperature C3 of the subtask 3. Determine the target chip frequency to be set for the chip.

In step 414, the operating frequency of the chip is set to the target chip frequency of the subtask 3, and the subtask 3 is started to be executed.

After the execution of all the subtasks included in the target task is completed, the operating frequency of the device chip can be reset to the default value and the execution of the target task can be completed.

According to the chip operating frequency setting method of the embodiment of the present invention, a task waiting to be executed can be decomposed to obtain a plurality of subtasks, and a target chip frequency of each subtask can be obtained. Such a sophisticated frequency setting method can make each subtask of the task realize the best possible operating performance, and can improve the operating speed of the entire task. Further, in the process of operating the task, the chip temperature at the time of executing the first subtask is dynamically collected, and the target chip operating frequency of the first subtask is determined in combination with the chip temperature to determine the chip operating frequency. The factors to be considered for determination can be made more comprehensive, the frequency setting can be more rational, and the device operating performance can be further improved.

It should be noted that the end device can further provide a user interface, and can receive configuration information for a predetermined mapping relationship input via the user interface. For example, the user can calculate or estimate the target chip frequency that needs to be used for each subtask offline and store a predetermined mapping relationship between each subtask and the corresponding target chip frequency in the device. In this way, when the device operates, it is possible to set the operating frequency of the corresponding chip when operating the subtask based on the arranged predetermined mapping relationship.

The user interface can further receive frequency setting strategy information. The frequency setting strategy information may include, for example, a model that determines chip operating power consumption and task operating time based on task parameters and device information, or how specified based on the power consumption model and task operating time model. It may further include whether to select the target chip frequency of the subtask of. Based on the frequency setting strategy information and the task parameters of each subtask among the plurality of subtasks, it is possible to determine the target chip frequency set on the chip of the device when operating each subtask.

It should be noted that the frequency setting strategy information may further include turning on or off the chip frequency dynamic setting function for the subtask. When the frequency setting strategy information includes turning on the chip frequency dynamic setting function for the subtask, the device is set to each subtask of the target task by the chip operating frequency setting method described in the above-described embodiment of the present invention. The target chip frequency can be determined. For example, subtask task parameters, chip temperature, and device resource information can be collected and the target chip frequency to be used can be selected based on this information and the power consumption model and task operating time model. If the frequency setting strategy information includes turning off the chip frequency dynamic setting feature for subtasks, the device must be used by each subtask according to a given offline calculated mapping relationship configured in the user interface. Get the target chip frequency directly.

Through the user interface, a more flexible chip frequency setting method can be provided, and the user can more conveniently update the chip frequency determination method to make the chip frequency determination more rational and quick. can.

FIG. 5 is an exemplary configuration diagram of the chip operating frequency setting device provided by the embodiment of the present invention, and as shown in FIG. 5, the device includes an acquisition module 51 and a frequency control module 52. , The frequency setting module 53, and the like.

The acquisition module 51 acquires a plurality of subtasks of the target task and task parameters of each subtask, where the task parameters include parameters for indicating the calculation scale of the subtasks. Illustratively, the task parameter comprises at least one of the complexity of the subtask and the memory access of the subtask.

The frequency control module 52 determines the target chip frequency of each subtask based on the task parameters of each subtask among the plurality of subtasks.

The frequency setting module 53 sets the operating frequency when the chip executes each of the subtasks based on the determined target chip frequency of each subtask.

In one example, as shown in FIG. 6, the apparatus executes a task analysis process for the target task to obtain the plurality of subtasks and task parameters of each subtask, and among the plurality of subtasks. Further may include a task analysis module 54 for storing the correspondence between each subtask of the above and the task parameter of each of the subtasks. When the acquisition module 51 acquires a plurality of subtasks of the target task and task parameters of each subtask, the acquisition module 51 searches for the task parameters of each subtask from the stored correspondence.

For example, in actual implementation, when trying to operate one target task, first, the task analysis module 54 executes an analysis process for the target task task, and analyzes, for example, a plurality of subtasks. Then, each subtask in each of a plurality of subtasks is analyzed to obtain the task parameters of each subtask. The task analysis module 54 can store the correspondence between each subtask obtained by analysis and the task parameter.

The acquisition module 51 is in charge of controlling the operation process of the target task. For example, the acquisition module 51 acquires the correspondences analyzed and stored by the task analysis module 54, and executes each of the subtasks in the acquisition module 51. Control one by one. Illustratively, there are three subtasks, and when the first subtask is about to start executing, the acquisition module 51 acquires the task parameters of the first subtask from the correspondence, and the task parameters and chips are arranged. The device information of the device is transmitted to the frequency control module 52, and the frequency control module 52 determines the target chip frequency of the first subtask based on the task parameter and the device information.

Next, the frequency control module 52 can transmit the determined target chip frequency to the frequency setting module 53, and the frequency setting module 53 can set the operating frequency of the chip as the target chip frequency. Further, by transmitting a feedback signal to the acquisition module 51 after setting the operating frequency of the chip by the frequency setting module 53, it is possible to notify the acquisition module 51 that the frequency setting has already been completed. Then, the acquisition module 51 can start executing the first subtask based on the feedback signal.

After the execution of the first subtask is finished, the acquisition module 51 tries to start executing the second subtask, and similarly, before the acquisition module 51 starts executing the second subtask, the task analysis module 54 The task parameter of the second subtask is obtained from the correspondence obtained by and transmitted to the frequency control module 52 to determine the target chip frequency of the second subtask. After feeding back the completion of chip frequency setting by the frequency setting module 53, the acquisition module 51 starts executing the second subtask. The execution of the third subtask is similar and will not be repeated. After confirming that all the subtasks of the target task have been executed by the acquisition module 51, the frequency reset signal is transmitted to the frequency control module 52, and the frequency control module 52 sends the frequency reset signal to the frequency setting module 53 accordingly. The frequency reset signal can be transmitted and the operating frequency of the chip can be set to the default value by the frequency setting module 53. At this point, the execution of the target task is finished.

In one example, the frequency control module 52 obtains device information of the device on which the chip is arranged when determining the target chip frequency of each subtask based on the task parameters of each subtask among the plurality of subtasks. Acquired and determining the target chip frequency of each subtask based on the device information and the task parameters of each subtask among the plurality of subtasks, where the device information includes device resource information. For example, the device resource information includes the number of compute units, bandwidth, and any one or more of the memory capacities.

In one example, the device information further includes the chip temperature of the chip, and the frequency control module 52 further includes task parameters of the first subtask among the plurality of subtasks, the device resource information, and the first. The target chip frequency of the first subtask is determined based on the chip temperature when the subtask is executed.

In one example, the frequency control module 52 acquires a predetermined mapping relationship between the plurality of first data and the plurality of second data, the predetermined mapping relationship, the device information, and the task parameter of each subtask. Based on, the target chip frequency of each of the subtasks is determined, where the first data includes predetermined task parameters and predetermined device information, and the second data includes predetermined chip frequencies.

In one example, the frequency control module 52 determines the target chip frequency of each subtask based on the predetermined mapping relationship, the device information, and the task parameters of each subtask, and the third data and the predetermined one. Determines the distance between each first data in the plurality of first data in the mapping relationship of, and corresponds to the target first data having the closest distance to the third data in the predetermined mapping relationship. A predetermined chip frequency is determined as a target chip frequency of the first subtask, and the third data includes task parameters and device information of the first subtask among the plurality of subtasks.

In one example, the frequency control module 52 further acquires a plurality of sets of selectable chip frequencies before acquiring a predetermined mapping relationship between the plurality of first data and the plurality of second data. A plurality of discrete first data obtained by sampling are acquired, and for each of the first data in the plurality of first data, as second data corresponding to each of the first data. A set of chip frequencies is selected from the plurality of sets of selectable chip frequencies, and a mapping relationship between each of the first data and the selected second data is constructed.

In one example, the predetermined chip frequency corresponding to the first data in the predetermined mapping relationship is in the condition of each set of selectable chip frequencies among a plurality of sets of selectable chip frequencies. It is selected from the plurality of sets of selectable chip frequencies based on the performance evaluation parameters corresponding to the first data.

In one example, the performance evaluation parameters include task processing performance parameters and chip operating power consumption, and the predetermined chip frequency corresponding to the first data in the predetermined mapping relationship can be selected from the plurality of sets. The chip operating power consumption in the chip frequency is less than the predetermined power consumption, and the task processing performance parameter is the best selectable chip frequency.

In one example, as shown in FIG. 6, the device may further include an interface module 55 for receiving configuration information for the predetermined mapping relationship entered by the user.

In one example, the frequency control module 52 determines the target chip frequency of each subtask based on the task parameters of each subtask in the plurality of subtasks, and the task of each subtask in the plurality of subtasks. From a plurality of sets of selectable chip frequencies based on the parameters, the chip that can shorten the operating time for realizing the task under the chip power consumption limiting condition of the chip as the target chip frequency. Select a frequency.

In one example, the interface module 55 further receives the frequency setting strategy information input by the user, and the frequency control module 52 further receives the frequency setting strategy information and each subtask in the plurality of subtasks. The target chip frequency of each of the subtasks is determined based on the task parameters.

In one example, the frequency setting strategy information includes turning on or off the chip frequency dynamic setting function for a subtask.

In one example, the operating frequency includes at least one of the core frequency or the memory frequency of the chip.

In some embodiments, the device may perform any of the corresponding methods described above and will not be repeated herein for the sake of brevity.

An embodiment of the present invention further provides an electronic device, the electronic device 700 comprising a memory 710 and a processor 720, wherein the memory 710 stores a machine-readable instruction 711. The processor 720 calls the machine-readable instruction 711 to implement the chip operating frequency setting method of any of the embodiments herein. Here, the target chip for setting the chip operating frequency may be the memory 710 and / or the processor 720. In one example, the electronic device 700 may further include a communication interface 730 and a bus 740. The memory 710, the processor 720, and the communication interface 730 are connected to each other via the bus 740. In one example, the electronic device 700 may further include a chip 750, which performs processing for each subtask in the target task at an operating frequency set by the processor 720.

The embodiments of the present invention further provide a computer-readable recording medium on which a computer program is recorded, wherein the processor is the chip operating frequency of any of the embodiments herein when the program is executed by the processor. Try to implement the setting method. In one example, the computer-readable recording medium may be the memory 710 in FIG.

Those skilled in the art should appreciate that one or more embodiments of the invention may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the invention may use the form of complete hardware embodiments, complete software embodiments, or software-hardware embodiments. Also, one or more embodiments of the present invention include, but include, one or more computer-usable storage media (disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code. You can use the format of the computer program product implemented on (but not limited to).

Here, "and / or" described in the examples of the present invention means having at least one of both companies, for example, "A and / or B" means A, B, and ". Includes three cases such as "A and B".

Each embodiment in the present invention is described using a gradual method, the same or similar parts between the respective embodiments can be referred to each other, and the other embodiments in each embodiment. The explanation focused on the differences from the example. In particular, in the case of the embodiment of the data processing device, since it is basically similar to the embodiment of the method, it is described relatively briefly, but the related parts may be referred to the explanation of the embodiment of the method. ..

Specific embodiments of the invention have been described above. Other examples are within the scope of the attached "Claims". In some cases, the acts or steps described in the claims may be performed in a different order than in the examples, and the expected result may still be achieved. Also, the process depicted in the drawings does not necessarily require the specific order or sequential order shown to achieve the expected result. In some embodiments, multitasking and parallel processing are also possible or advantageous.

Examples of the subject matter and functional operation in the present invention are digital electronic circuits, tangible computer software or firmware, computer hardware including the configurations and structural equivalents thereof disclosed in the present invention, or one or more thereof. It can be realized by combination. The embodiments of the subject in the present invention can be realized as one or more computer programs, i.e., encoded on a tangible non-temporary program carrier and executed by a data processing apparatus. , Can be implemented as one or more modules in a computer program instruction to control the operation of the data processing device. Alternatively or additionally, the program instruction can be encoded on a manually generated propagating signal, for example, on a machine-generated electrical, optical, or electromagnetic signal. can. The signal is generated to encode the information and transmit it to the appropriate receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage board, a random or serial access memory device, or a combination thereof.

The processing and logical flow in the present invention can be performed by one or more programmable computers running one or more computer programs, performing operations based on input data to produce output. By doing so, the corresponding function is executed. The processing and logic flow can be further executed by a dedicated logic circuit such as FPGA (field programmable gate array) or ASIC (dedicated integrated circuit), and the device can also be realized as a dedicated logic circuit. Can be done.

Suitable computers for running computer programs include, for example, general purpose and / or dedicated microprocessors, or any other type of central processing unit. Generally, the central processing unit will receive instructions and data from read-only memory and / or random access memory. The basic components of a computer include a central processing unit for executing or executing instructions, and one or more memory devices for storing instructions and data. In general, a computer further includes or is operable with one or more mass storage devices for storing data, such as magnetic disks, magnetic optical disks, or optical disks. Combined with, receive data, transmit data, or have both. However, computers do not necessarily have such devices. The computer can be embedded in another device, such as a mobile phone, personal digital assistant (PDA), mobile audio or video player, game console, Global Positioning System (GPS) receiver, or general purpose serial bus. It can be embedded in portable storage devices such as (USB) flash drives, and these devices are just a few examples.

Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, intermediaries, and memory devices, such as semiconductor memory devices (eg, EPROMs, EEPROMs, and flash devices). Includes magnetic discs (eg, internal hard disks or mobile discs), magnetic optical discs, and CD ROMs, and DVD-ROM discs. Processors and memory can be complemented by dedicated logic circuits or incorporated into dedicated logic circuits.

The present invention contains many specific implementation details, which should not be construed as limiting the scope of the invention or the scope of which it seeks to protect, primarily of some embodiments of the invention. Used to describe features. Specific features in a plurality of embodiments of the present invention may also be implemented in combination with a single embodiment. On the other hand, the various features in a single embodiment can be implemented separately in multiple embodiments or in any suitable subcombination. It should be noted that the features play a role in a particular combination as described above and are claimed to be protected in this way from the beginning, but one or more features from the combination claimed to be protected may be excluded from the combination in some cases. And the combinations claimed to be protected can be sub-combined or directed to variants of the sub-combination.

Similarly, the drawings depict operations in a specific order, which either requires them to be performed in a specific order that indicates them, or requires them to be performed in sequence, or all the operations illustrated. It should not be understood that it is a requirement that the expected result be achieved by being executed. In some cases, multitasking and parallel processing can be advantageous. It should be noted that the separation of the various system modules and components in the above embodiments should not be understood to be such separation in all embodiments, and the described program components and systems are: In general, it should be understood that they can be integrated together into a single software product or packaged into multiple software products.

Therefore, specific examples of the subject have already been described. Other examples are within the scope of the attached "Claims". In some cases, the actions described in the claims may be performed in different orders and still achieve the expected results. It should be noted that the processes depicted in the drawings do not necessarily require the specific order or sequence shown to achieve the expected results. In some implementations, multitasking and parallel processing may be advantageous.

The above are only a few embodiments of the invention and are not used to limit the invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the invention should be included within the scope of the invention.

Claims (35)

It is a chip operating frequency setting method.
To get multiple subtasks of the target task and task parameters for each subtask,
Determining the target chip frequency of each subtask based on the task parameters of each subtask among the plurality of subtasks.
Including setting the operating frequency when the chip performs each of the subtasks based on the determined target chip frequency of each subtask.
The chip operating frequency setting method, wherein the task parameter includes a parameter for indicating the calculation scale of the subtask. By executing the task analysis process for the target task to obtain the plurality of subtasks and the task parameters of each subtask,
Further including storing the correspondence between each subtask in the plurality of subtasks and the task parameter of each subtask.
Acquiring multiple subtasks of the target task and task parameters of each subtask is
The chip operating frequency setting method according to claim 1, wherein the task parameter of each subtask is searched from the stored correspondence. The chip operating frequency setting method according to claim 1 or 2, wherein the task parameter includes at least one of the calculation amount of the subtask and the memory access amount of the subtask. Determining the target chip frequency of each subtask based on the task parameters of each subtask among the plurality of subtasks
Acquiring device information of the device on which the chip is placed and
Including determining the target chip frequency of each subtask based on the device information and the task parameters of each subtask among the plurality of subtasks.
The chip operating frequency setting method according to any one of claims 1 to 3, wherein the device information includes device resource information. The chip operating frequency setting method according to claim 4, wherein the device resource information includes the number of computing units, bandwidth, and any one or more of the memory capacities. The device information further includes the chip temperature of the chip.
Determining the target chip frequency of each subtask based on the device information and the task parameters of each subtask among the plurality of subtasks is possible.
Includes determining the target chip frequency of the first subtask based on the task parameters of the first subtask among the plurality of subtasks, the device resource information, and the chip temperature when the first subtask is executed. The chip operating frequency setting method according to claim 4 or 5, wherein the chip operating frequency is set. Determining the target chip frequency of each subtask based on the device information and the task parameters of each subtask among the plurality of subtasks is possible.
Acquiring a predetermined mapping relationship between a plurality of first data and a plurality of second data, the first data includes predetermined task parameters and predetermined device information, and the second data is. , Including a given chip frequency,
One of claims 4 to 6, wherein the target chip frequency of each subtask is determined based on the predetermined mapping relationship, the device information, and the task parameter of each subtask. The chip operating frequency setting method described. Determining the target chip frequency of each subtask based on the predetermined mapping relationship, the device information, and the task parameters of each subtask
Determining the distance between the third data and each of the first data in the plurality of first data in the predetermined mapping relationship, the third data being the third of the plurality of subtasks. 1 Includes task parameters and device information for subtasks
It is characterized by including determining a predetermined chip frequency corresponding to the first data having the closest distance to the third data in the predetermined mapping relationship as a target chip frequency of the first subtask. The chip operating frequency setting method according to claim 7. Before acquiring a given mapping relationship between a plurality of first data and a plurality of second data,
How to set the chip operating frequency
Obtaining multiple sets of selectable chip frequencies and obtaining multiple discrete first data obtained by sampling,
For each of the first data in the plurality of first data, as the second data corresponding to each of the first data, one set of chip frequencies from the plurality of sets of selectable chip frequencies is used. The chip operating frequency setting method according to claim 7 or 8, wherein the method comprises selecting and constructing a mapping relationship between each of the first data and the selected second data. The predetermined chip frequency corresponding to the first data in the predetermined mapping relationship corresponds to the first data under the condition of each set of selectable chip frequencies among a plurality of sets of selectable chip frequencies. The chip operating frequency setting method according to any one of claims 7 to 9, wherein the chip frequency is selected from the plurality of sets of selectable chip frequencies based on the performance evaluation parameters. The performance evaluation parameters include task processing performance parameters and chip operating power consumption.
The predetermined chip frequency corresponding to the first data in the predetermined mapping relationship is such that the chip operating power consumption in the plurality of sets of selectable chip frequencies is less than the predetermined power consumption and the task processing is performed. The chip operating frequency setting method according to claim 10, wherein the performance parameter is the best selectable chip frequency. The chip operating frequency setting method according to any one of claims 7 to 11, further comprising receiving configuration information for the predetermined mapping relationship input by the user. Determining the target chip frequency of each subtask based on the task parameters of each subtask among the plurality of subtasks
To realize a task under the chip power consumption limiting condition of the chip as the target chip frequency from a plurality of sets of selectable chip frequencies based on the task parameters of each subtask in the plurality of subtasks. The chip operating frequency setting method according to any one of claims 1 to 12, further comprising selecting a chip frequency capable of minimizing the operating time. Further including receiving the frequency setting strategy information entered by the user,
Determining the target chip frequency of each subtask based on the task parameters of each subtask among the plurality of subtasks
13. Chip operating frequency setting method. The chip operating frequency setting method according to claim 14, wherein the frequency setting strategy information includes turning on or off a chip frequency dynamic setting function for a subtask. The chip operating frequency setting method according to any one of claims 1 to 15, wherein the operating frequency includes at least one of the core frequency and the memory frequency of the chip. It is a chip operating frequency setting device.
An acquisition module for acquiring multiple subtasks of the target task and task parameters for each subtask,
A frequency control module for determining the target chip frequency of each subtask based on the task parameters of each subtask among the plurality of subtasks.
A frequency setting module for setting the operating frequency when the chip performs each of the subtasks based on the determined target chip frequency of each subtask is provided.
The chip operating frequency setting device, wherein the task parameter includes a parameter for indicating the calculation scale of the subtask. The task analysis process is executed for the target task to obtain the task parameters of the plurality of subtasks and each subtask, and the correspondence relationship between each subtask in the plurality of subtasks and the task parameter of each subtask is stored. With a task analysis module for
The chip operating frequency setting device according to claim 17, wherein the acquisition module further searches for task parameters of each subtask from the stored correspondence. The chip operating frequency setting device according to claim 17 or 18, wherein the task parameter includes at least one of the calculation amount of the subtask and the memory access amount of the subtask. The frequency control module further
Acquire the device information of the device in which the chip is placed, and
Based on the device information and the task parameters of each subtask in the plurality of subtasks, the target chip frequency of each subtask is determined.
The chip operating frequency setting device according to any one of claims 17 to 19, wherein the device information includes device resource information. 20. The chip operating frequency setting device according to claim 20, wherein the device resource information includes the number of computing units, bandwidth, and any one or more of the memory capacities. The device information further includes the chip temperature of the chip.
The frequency control module further targets the first subtask based on the task parameters of the first subtask among the plurality of subtasks, the device resource information, and the chip temperature when the first subtask is executed. The chip operating frequency setting device according to claim 20 or 21, wherein the chip frequency is determined. The frequency control module further
A predetermined mapping relationship between a plurality of first data and a plurality of second data is acquired, wherein the first data includes a predetermined task parameter and a predetermined device information, and the second data includes a predetermined task parameter and a predetermined device information. Including the given chip frequency,
The chip according to any one of claims 20 to 22, wherein the target chip frequency of each subtask is determined based on the predetermined mapping relationship, the device information, and the task parameters of each subtask. Operating frequency setting device. The frequency control module further
The distance between the third data and each of the first data in the plurality of first data in the predetermined mapping relationship is determined, where the third data is the first of the plurality of subtasks. Includes task parameters and device information for subtasks
Further, a claim is characterized in that a predetermined chip frequency corresponding to the first data having the closest distance to the third data in the predetermined mapping relationship is determined as a target chip frequency of the first subtask. 22. The chip operating frequency setting device. The frequency control module further includes:
Before acquiring a predetermined mapping relationship between a plurality of first data and a plurality of second data, a plurality of sets of selectable chip frequencies are acquired and a plurality of discrete firsts obtained by sampling. Get the data,
For each of the first data in the plurality of first data, as the second data corresponding to each of the first data, one set of chip frequencies from the plurality of sets of selectable chip frequencies is used. The chip operating frequency setting device according to claim 23 or 24, which is selected and a mapping relationship between each of the first data and the selected second data is established. The predetermined chip frequency corresponding to the first data in the predetermined mapping relationship is the first data under the condition of each set of selectable chip frequencies among a plurality of sets of selectable chip frequencies. The chip operating frequency setting device according to any one of claims 23 to 25, wherein the chip frequency is selected from the plurality of sets of selectable chip frequencies based on the performance evaluation parameters corresponding to the above. The performance evaluation parameters include task processing performance parameters and chip operating power consumption.
The predetermined chip frequency corresponding to the first data in the predetermined mapping relationship is such that the chip operating power consumption in the plurality of sets of selectable chip frequencies is less than the predetermined power consumption and the task processing is performed. 26. The chip operating frequency setting device according to claim 26, wherein the performance parameter is the best selectable chip frequency. The chip operating frequency setting device according to any one of claims 23 to 27, further comprising an interface module for receiving configuration information for the predetermined mapping relationship input by the user. The frequency control module further
To realize a task under the chip power consumption limiting condition of the chip as the target chip frequency from a plurality of sets of selectable chip frequencies based on the task parameters of each subtask in the plurality of subtasks. The chip operating frequency setting device according to any one of claims 17 to 28, wherein the chip frequency having the shortest operating time is selected. The interface module further receives the frequency setting strategy information input by the user.
28. The frequency control module further comprises determining a target chip frequency for each subtask based on the frequency setting strategy information and task parameters for each subtask among the plurality of subtasks. Chip operating frequency setting device. 30. The chip operating frequency setting device according to claim 30, wherein the frequency setting strategy information includes turning on or off a chip frequency dynamic setting function for a subtask. The chip operating frequency setting device according to any one of claims 17 to 31, wherein the operating frequency includes at least one of the core frequency and the memory frequency of the chip. It ’s an electronic device,
Equipped with memory and processor,
The memory stores machine-readable instructions and
The processor is an electronic device that calls the machine-readable instruction to realize the chip operating frequency setting method according to any one of claims 1 to 16. 33. The electronic device of claim 33, further comprising a chip that performs processing for each subtask in the target task at an operating frequency set by the processor. A computer-readable recording medium on which computer programs are recorded.
A computer-readable recording medium comprising the processor to implement the chip operating frequency setting method according to any one of claims 1 to 16 when the program is executed by the processor.

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