CN114785376B

CN114785376B - Frequency-voltage pre-configuration method and related device

Info

Publication number: CN114785376B
Application number: CN202210487405.7A
Authority: CN
Inventors: 黄河
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-05-06
Filing date: 2022-05-06
Publication date: 2023-07-21
Anticipated expiration: 2042-05-06
Also published as: CN114785376A

Abstract

The application provides a frequency voltage pre-configuration method and a related device, wherein the device comprises a baseband chip, a power management chip and a target hardware combination; the baseband chip is used for detecting a first data task adapting to the target hardware combination, switching the hardware state of the target hardware combination from an idle state to a busy state, and acquiring a reference frequency pressure gear; the power management chip is used for sending a frequency voltage pre-configuration instruction to the power management chip; the power management chip is used for receiving and responding to the frequency voltage pre-configuration instruction sent by the baseband chip, and adjusting the working frequency voltage gear of the target hardware combination from the idle state frequency voltage gear to the reference frequency voltage gear; the target hardware combination is used for processing the data task of the target service type. In this way, in the time of calculating the gear adapting to the load requirement of the task by the baseband chip, the influence of waiting frequency voltage calculation and voting on the service time sequence is effectively reduced by pre-configuring the gear for the target hardware combination.

Description

Frequency-voltage pre-configuration method and related device

Technical Field

The application relates to the technical field of chips, in particular to a frequency voltage pre-configuration method and a related device.

Background

At present, with the high-speed development of electronic technology, the integration and complexity of chips in mobile terminals are increasing, and with the increase of the working frequency of chips, the energy consumption generated by the chips is also increasing.

Disclosure of Invention

The application provides a frequency voltage pre-configuration method and a related device, so as to improve the efficiency and real-time performance of data processing of electronic equipment.

In a first aspect, an embodiment of the present application provides an electronic device, including a baseband chip, a power management chip, and a target hardware combination, where the hardware set includes at least one hardware combination divided according to a service type of a data task that needs to be processed by the baseband chip, and a single hardware combination includes at least one core and at least one signal processing circuit, and hardware in any two hardware combinations is different from each other; wherein,,

the baseband chip is connected with the power management chip and is used for detecting a first data task adapting to the target hardware combination, switching the hardware state of the target hardware combination from an idle state to a busy state and acquiring a reference frequency voltage gear; the frequency voltage pre-configuration instruction is used for indicating the reference frequency voltage gear;

The power management chip is connected with the target hardware combination and is used for receiving and responding to the frequency voltage pre-configuration instruction sent by the baseband chip, and adjusting the working frequency voltage gear of the target hardware combination from an idle state frequency voltage gear to the reference frequency voltage gear, wherein the idle state frequency voltage gear is a low-power consumption frequency voltage gear;

the target hardware combination is used for processing the data task of the target service type, and the target service type is the service type preconfigured to the target hardware combination.

In a second aspect, an embodiment of the present application provides a method for frequency voltage pre-configuration, including:

detecting a first data task adapting to a target hardware combination, switching a hardware state of the target hardware combination from an idle state to a busy state, and acquiring a reference frequency pressure gear;

and sending a frequency voltage pre-configuration instruction to a power management chip, wherein the frequency voltage pre-configuration instruction is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination as the reference frequency voltage gear for the power management chip.

In a third aspect, an embodiment of the present application provides an apparatus for frequency voltage pre-configuration, including:

acquiring a gear unit: detecting a first data task adapting to a target hardware combination, switching a hardware state of the target hardware combination from an idle state to a busy state, and acquiring a reference frequency pressure gear;

And a transmission instruction unit: and sending a frequency voltage pre-configuration instruction to a power management chip, wherein the frequency voltage pre-configuration instruction is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination as the reference frequency voltage gear for the power management chip.

In a fourth aspect, embodiments of the present application provide a computer storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform some or all of the steps as described in the first aspect of the present embodiment.

In a fifth aspect, embodiments of the present application provide a computer program product, wherein the computer program product comprises a computer program operable to cause a computer to perform some or all of the steps as described in the first aspect of the embodiments of the present application.

It can be seen that, in the embodiment of the application, after the baseband chip of the electronic device detects the data task, the reference frequency voltage gear is immediately configured for the target hardware combination through the power management chip, so that the frequency voltage gear of the target hardware combination is quickly switched from the low-power consumption gear to the working gear and data processing is performed, compared with the existing scheme that the configuration is performed after the frequency voltage gear calculation result of the current data task is adapted by waiting for real-time dynamic calculation, the configuration time delay of the frequency voltage gear is reduced, and the efficiency and the real-time performance of the electronic device for data processing are improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of an application scenario of DVFS technology provided in an embodiment of the present application;

FIG. 2a is a flow chart of a software voting configuration of a DVFS technique provided in an embodiment of the present application;

FIG. 2b is a flow chart of a hardware detection configuration of a DVFS technique according to an embodiment of the present application;

FIG. 3a is a block diagram of an electronic device according to an embodiment of the present application;

FIG. 3b is a schematic diagram of voltage division according to an embodiment of the present application;

FIG. 3c is a schematic diagram of a hardware clock tree partition according to an embodiment of the present disclosure;

FIG. 3d is a schematic diagram of a timer according to an embodiment of the present application;

fig. 3e is a flow chart of frequency-voltage pre-configuration of DVFS technology according to an embodiment of the present application;

fig. 4 is a schematic process diagram of a frequency voltage pre-configuration method provided in an embodiment of the present application;

Fig. 5 is a functional unit composition block diagram of a frequency voltage pre-configuration device provided in an embodiment of the present application;

fig. 6 is a functional unit composition block diagram of another frequency voltage pre-configuration device provided in an embodiment of the present application.

Detailed Description

In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Currently, with the development of communication technologies, especially the evolution of the fifth generation mobile communication technology (5th Generation Mobile Communication Technology,5G), independent networking (SA) and Non-independent Networking (NSA) have been deployed in large numbers in commercial networks, and in a 5G scenario, higher requirements are put on communication performance such as throughput, delay, mobility management, etc. of a User Equipment (UE), and at the same time, challenges are put on power consumption control of a baseband chip. Aiming at the problem of the control of the power consumption of the baseband chip, a dynamic voltage frequency adjustment (Dynamic Voltage and Frequency Scaling, DVFS) technology can be introduced to solve, the DVFS technology dynamically configures the clock frequency and the voltage for the chip according to the load requirement of the application program actually operated by the chip, so that the power consumption waste caused by the fact that the clock frequency and the voltage of the chip are larger than the actual requirement can be effectively reduced, and the energy consumption management efficiency is improved.

As shown in fig. 1, fig. 1 is a schematic view of an application scenario of a DVFS technology provided in the embodiment of the present application, taking a typical application scenario of the DVFS technology, i.e. a carrier aggregation scenario, where a network side configures different numbers of carriers for a UE by detecting a current uplink and downlink throughput of the UE, so as to meet uplink and downlink throughput requirements, and the different numbers of carriers affect an operational load of hardware, and the DVFS technology sets different frequency-voltage gears by calculating load requirements under the different numbers of carriers, so as to achieve a purpose of low power consumption control. The DVFS technology mainly uses a control policy combined with software and hardware to implement frequency modulation and voltage regulation on hardware, as shown in fig. 2a and fig. 2b, fig. 2a is a software voting configuration flow chart of the DVFS technology provided by the embodiment of the present application, and fig. 2b is a hardware detection configuration flow chart of the DVFS technology provided by the embodiment of the present application. As shown in the software voting configuration flow chart, the base station issues carrier configuration or de-configuration information to the radio resource control (Ratio Resource Control, RCC) layer of the UE, and then the RCC layer of the UE transmits the information to the hardware combination, and the hardware combination issues the current carrier configuration information to the software module of the DVFS; the base station transmits the dynamic scheduling information to the hardware combination, and the hardware combination transmits the dynamic scheduling information to the DVFS software module; finally, the DVFS software module (the specific implementation manner may be that the baseband chip in the embodiment of the present application invokes the corresponding software program) calculates, according to the current configuration information and the dynamic scheduling information, a frequency voltage gear meeting the requirement of the corresponding hardware combination load, and votes the determined frequency voltage gear to the DVFS hardware module (the specific implementation manner may be that the baseband chip in the embodiment of the present application sends a control signal to the power management chip), and after the DVFS hardware module completes the frequency voltage setting, sends a feedback message to the DVFS software module.

And as shown in the hardware detection configuration flow chart, when the target hardware combination is detected to enter the waiting interruption state, starting a timer with preset duration, if the target hardware combination is not detected to exit the waiting interruption state within the timing range of the timer, clearing the timer, determining that the hardware state of the target hardware combination is in an idle state, and reducing the frequency and the voltage of the hardware state of the target hardware combination. If the target hardware combination is detected to exit the waiting interruption state in the timing range of the timer, the waiting DVFS software module calculates the frequency voltage gear adapting to the data task and performs frequency voltage gear voting, and then the frequency voltage gear is set according to the voting. However, in an actual service scenario, after a timer is overtime, a target hardware combination enters an idle state and is subjected to frequency reduction and voltage reduction to a low-power-consumption gear, if a new data task arrives, the target hardware combination is in the low-power-consumption gear and cannot perform any processing at the moment, and the target hardware combination only can passively wait for the frequency voltage gear voting of the baseband chip to wait for the voltage increase and frequency increase, so that the target hardware combination cannot enter the frequency voltage gear capable of working at a later time, the requirement of a service tight time sequence cannot be met, and the use experience of a user is affected.

In order to solve the above problems, embodiments of the present application provide a method for pre-configuring a frequency voltage and a related device, which are described in detail below with reference to the accompanying drawings.

Referring to fig. 3a, fig. 3a is a block diagram of an electronic device according to an embodiment of the present application, where the electronic device 300 includes a baseband chip 310, a power management chip 320, and a target hardware combination 330, where the target hardware combination 330 is any one of a preset hardware set, the hardware set includes at least one hardware combination divided according to a service type of a data task that needs to be processed by the baseband chip 310, and a single hardware combination includes at least one core and at least one signal processing circuit, where hardware in any two hardware combinations is different from each other; wherein,,

the baseband chip 310 is connected to the power management chip 320, and is configured to detect a first data task adapted to the target hardware combination 330, switch a hardware state of the target hardware combination 330 from an idle state to a busy state, and obtain a reference frequency voltage gear; the power management chip 320 is used for sending a frequency voltage pre-configuration instruction to the power management chip;

the frequency voltage pre-configuration instruction is used for indicating the reference frequency voltage gear.

The power management chip 320 is connected to the target hardware combination 330, and is configured to receive and respond to the frequency voltage pre-configuration instruction sent by the baseband chip 310, and adjust the working frequency voltage gear of the target hardware combination 330 from an idle state frequency voltage gear to the reference frequency voltage gear;

the idle state frequency voltage gear is a low-power consumption frequency voltage gear; the frequency voltage shift includes a frequency shift for setting a frequency of at least one core in the hardware combination and a frequency of at least one signal processing circuit, and a voltage shift for setting a voltage of at least one core in the hardware combination and a voltage of at least one signal processing circuit.

Specifically, the idle state frequency voltage gear is a gear adapted to the situation that the target hardware combination is in the idle state, and at the moment, the electronic equipment judges that the target hardware combination is not required to process a data task of a related service type and is not required to keep a high working gear, so that the target hardware combination is subjected to frequency reduction and voltage reduction to the idle state frequency voltage gear. It will be appreciated that the idle state frequency voltage range characterizes a frequency voltage range that is lower than the operating frequency voltage range achieved when the target hardware combination processes any data task. It is also understood that when the hardware state of the target hardware combination is changed from the busy state to the idle state, the shift of the target hardware combination is reduced in frequency and voltage; when the hardware state of the target hardware combination is changed from the idle state to the busy state, the gear of the target hardware combination is up-converted and boosted.

The gear described in the embodiment of the present application may represent a value classification in a discrete value set, or may represent a value segmentation in a linear value set, which is not limited only.

The target hardware combination 330 is configured to process a data task of a target service type, where the target service type is a service type preconfigured to the target hardware combination.

In one possible example, the reference frequency voltage gear is a frequency voltage gear adapted for a task preceding the first data task.

After the baseband chip calculates the gear that is adapted to the load requirement of the data task to be processed at present, the baseband chip may store the gear into a register, which is not limited herein. When the baseband chip does not detect the data task within a period of time, in order to save power consumption, the hardware state of the target hardware combination is switched from a busy state to an idle state, and frequency and voltage are reduced. When the baseband chip detects that a new data task arrives, the frequency voltage gear adapting to the data task is calculated, the gear stored in the register is taken as a reference frequency voltage gear, the power management chip is controlled to pre-configure the frequency voltage gear of the target hardware combination to the stored gear, and then the baseband chip calculates a new working gear and then adjusts the new working gear.

For example, the idle state frequency voltage gear is set to be a voltage gear first gear and a frequency voltage gear first gear, the frequency voltage gear adapted by the previous task is a voltage gear third gear and a frequency gear second gear, and the frequency voltage gear adapted to the first data task is calculated by the baseband chip to be a voltage gear second gear and a frequency gear second gear. In this case, when the baseband chip detects a new data task, a frequency voltage pre-configuration instruction is sent to the power management chip while calculating a new frequency voltage gear, so as to control the power management chip to raise the voltage gear of the target hardware combination from first gear to third gear, and then raise the frequency voltage gear from first gear to second gear. At this point, the current frequency bin of the target hardware combination may already have the task of processing the data. And then, after the gear adapting to the data task is calculated, the power management chip reduces the voltage gear of the target hardware combination from the third gear to the second gear.

In this example, the baseband chip obtains the frequency voltage gear adapted by the previous task as the reference frequency voltage gear, and uses the reference frequency voltage gear as the pre-configuration gear to control the power management chip to perform frequency voltage pre-configuration, so that the target hardware combination can quickly reach the high frequency voltage gear, thereby quickly performing data task processing, and then performing frequency voltage gear update adjustment according to the calculated frequency voltage gear adapted to the current data task, and balancing the power consumption and processing performance of the chip.

In one possible example, the reference frequency voltage gear is any one of a plurality of selectable frequency voltage gears among the operating frequency voltage gears of the target hardware combination 330.

The working frequency voltage gear in the embodiment of the application is higher than the idle state frequency voltage gear, specifically, the working frequency gear is higher than the idle state frequency gear, and the working voltage gear is higher than the idle state voltage gear. The reference frequency voltage gear is used as a pre-configuration gear, so that the power management chip can perform frequency and voltage boosting on the target hardware combination, and the current working frequency voltage gear of the target hardware combination is closer to the frequency voltage gear required by the actual data processing task than the idle state frequency voltage gear.

For example, the frequency shift is divided into "first shift", "second shift", and "third shift" from small to large according to the magnitude of the supplied clock frequency, and the voltage shift is divided into "first shift", "second shift", "third shift", and "fourth shift" from small to large according to the magnitude of the supplied voltage value. The working frequency voltage gear comprises a working frequency gear and a working voltage gear, and the idle state frequency voltage gear is set to be a frequency gear and a voltage gear which are both "first gears". It is to be understood that, on the premise that the operating frequency gear and the operating voltage gear are different and the lowest gear "first gear" is satisfied, the operating frequency gear may be any one of three selectable frequency gears of "first gear", "second gear" and "third gear", and the operating voltage gear may be any one of four selectable voltage gears of "first gear", "second gear", "third gear" and "fourth gear".

In this example, any one of selectable gears in the working frequency voltage gears of the target hardware combination is obtained dynamically and randomly to serve as the reference frequency voltage gear, so that the target hardware combination is increased in frequency or in voltage, the problem that the target hardware combination needs to wait for the frequency voltage gear to vote to start the frequency increasing and the voltage increasing is avoided, and the time delay influence caused by overlong waiting is reduced.

In one possible example, in terms of the acquiring the reference frequency voltage gear, the baseband chip 310 is specifically configured to: acquiring a plurality of frequency gears and a plurality of voltage gears corresponding to the data task of the target service type; determining the reference frequency gear according to the plurality of frequency gears; and determining the reference voltage gear according to the voltage gears.

The reference frequency voltage gear comprises a reference frequency gear and a reference voltage gear. The frequency shift and the voltage shift corresponding to the data task of the target service type may be a frequency shift and a voltage shift in a historical frequency-voltage shift configured by the target hardware combination stored in the baseband chip, or may be a plurality of frequency shifts and a plurality of voltage shifts corresponding to different data tasks stored in the baseband chip in advance, which is not limited at this time. Preferably, the highest gear of the pre-stored gears should be equivalent to the gear of the maximum load demand among the plurality of data tasks adapting to the target traffic type.

For example, the frequency shift ranges are divided into "first gear", "second gear", "third gear" and "fourth gear" according to the magnitude of the supplied clock frequency, and since the frequency shift range corresponding to the maximum load demand of the data task of the target service type is "third gear", the frequency shift ranges corresponding to the different data tasks stored in the baseband chip in advance are "first gear", "second gear" and "third gear", and finally the reference frequency shift range is determined according to the three frequency shift ranges.

For example, the voltage range is divided into "first range", "second range", "third range" and "fourth range" from small to large according to the magnitude of the supplied voltage value. Assuming that the voltage steps in the history of the voltage steps of the frequency and voltage steps of the target hardware combination stored in the baseband chip include a second step and a third step, one of the two voltage steps is selected as a reference voltage step.

Therefore, in this example, the baseband chip obtains the plurality of frequency gears and the plurality of voltage gears of the working frequency voltage gear of the target hardware combination, determines the reference frequency gear according to the frequency gears, determines the reference voltage gear according to the voltage gears, and finally performs frequency up or voltage up on the target hardware combination according to the determined reference frequency voltage gear, so that the problem that the target hardware combination starts frequency up and voltage up only after waiting for the frequency voltage gear to vote is avoided, and the delay influence caused by overlong waiting is reduced.

In one possible example, the plurality of frequency ranges are historical frequency ranges configured by the target hardware combination 330, and any two frequency ranges are different from each other; the plurality of voltage steps are historical voltage steps configured by the target hardware combination 330, and any two voltage steps are different from each other.

The plurality of frequency steps and the plurality of voltage steps acquired by the baseband chip are historical frequency steps configured for the target hardware combination to adapt to the received data task, and the historical frequency steps can be stored by the storage device which can be a register after the baseband chip calculates each time, and the storage device is not limited herein. The frequency gears and the voltage gears are different from each other, so that the reference frequency gears or the reference voltage gears acquired each time can be ensured to be random and have the same probability.

For example, the frequency ranges are divided into "first gear", "second gear", and "third gear" from small to large according to the magnitude of the supplied clock frequency, and it is assumed that the adaptive frequency ranges calculated by the baseband chip for a plurality of data tasks have "second gear", and "third gear", and since any two of the history frequency ranges stored by the baseband chip are different from each other, the history frequency ranges include "second gear" and "third gear". When a new data task is detected, the baseband chip selects one of the two gears and the three gears as a reference frequency gear.

For example, the voltage steps are divided into "first step", "second step", "third step", and "fourth step" according to the magnitude of the supplied voltage values, and it is assumed that the voltage steps previously allocated to the target hardware combination according to the detected data task by the baseband chip have "second step", "third step", "fourth step", "second step", and "fourth step", and since any two voltage steps in the history voltage steps stored by the baseband chip are different from each other, the history voltage steps actually stored by the baseband chip include "second step", "third step", and "fourth step". When a new data task is detected, the baseband chip selects one of the second gear, the third gear and the fourth gear as a reference voltage gear.

In this example, the reference frequency voltage gear is obtained from the historical frequency voltage gear, and the multiple frequency gears and the multiple voltage gears in the historical frequency voltage gear are subjected to redundancy elimination, so that the reference frequency gear or the reference voltage gear obtained each time is random and the probability is the same, the target hardware combination can be used for rapidly processing the current data task from the probability, the working efficiency of the baseband chip is improved, and the user experience is effectively improved.

In one possible example, the reference frequency range is a frequency mean of the plurality of frequency ranges, or a range closest to the frequency mean; the reference voltage gear is a voltage average value of the plurality of voltage gears, or a voltage gear closest to the voltage average value.

The gear may represent the value classification in the discrete value set, and may represent the value segmentation in the dominant value set, so that the frequency average value or the voltage average value obtained by calculating the average value according to the plurality of frequency gears or the voltage gears may correspond to a preset gear value or may not belong to the preset gear value. Therefore, if the reference frequency voltage gear corresponds to the preset gear value, the reference frequency voltage gear is the value; if the reference frequency voltage gear value cannot be corresponding to the preset gear value, the reference frequency voltage gear value is the same as the nearest gear value. If the calculated average value is the same as the difference value between the adjacent gear values, the gear value with the higher value is preferentially selected as the last reference frequency gear or the reference voltage gear. This may result in a higher probability that the reference voltage or reference frequency range will be greater than the voltage or frequency range required by the currently detected data task load.

For example, the frequency shift is divided into "first shift", "second shift", and "third shift" according to the magnitude of the supplied clock frequency, the first shift "corresponding to the clock frequency being 1 hz, the second shift" corresponding to the clock frequency being 2 hz, and the third shift "corresponding to the clock frequency being 3 hz. Assuming that the plurality of frequency gears include "first gear", "third gear" and "third gear", the frequency average value calculated according to the plurality of frequency gears is "7/3 hz", and since there is no gear corresponding to the frequency average value, the difference value corresponding to the frequency average value is calculated according to the frequency values corresponding to the adjacent gears "second gear" and "third gear", the calculated results are "1/3 hz" and "2/3 hz", respectively, and finally the adjacent gear "second gear" with the smallest difference value is selected as the reference frequency gear.

For example, the voltage shift is divided into "first shift", "second shift", and "third shift" according to the magnitude of the supplied voltage value, wherein the voltage value corresponding to "first shift" is "2 volts", "the voltage value corresponding to" second shift "is" 4 volts ", and the voltage value corresponding to" third shift "is" 6 volts ". Assuming that the plurality of voltage gears include a second gear and a third gear, the voltage average value calculated according to the corresponding voltage values of the plurality of voltage gears is 5 v, since no gear corresponding to the frequency average value exists, the difference value corresponding to the voltage average value is calculated according to the voltage values corresponding to the adjacent gear second gear and the third gear, the calculated result is 1 v, and since the difference values are the same, the third gear of the larger gear is finally selected as the reference voltage gear.

It can be seen that, in this example, since the reference frequency gear is a frequency average value of a plurality of frequency gears, or a gear closest to the frequency average value, the reference voltage gear is a voltage average value of a plurality of voltage gears, or a gear closest to the voltage average value is used as a gear that is beneficial to balancing power consumption and performance of data processing by pre-configuring the frequency voltage.

In one possible example, the baseband chip 310 is further configured to, after the detecting of the first data task of adapting to the target hardware combination 330: acquiring semi-static configuration information of the electronic device 300 and dynamic scheduling information corresponding to the first data task; determining a first frequency voltage gear adapting to the load demand of the first data task according to the semi-static configuration information and the dynamic scheduling information, and sending a first frequency voltage gear vote to the power management chip 320, wherein the first frequency voltage gear vote is used for indicating the first frequency voltage gear; the power management chip 320 is further configured to: and updating the working frequency voltage gear of the target hardware combination 330 from the reference frequency voltage gear to the first frequency voltage gear.

The semi-static configuration message includes, but is not limited to, key parameters such as the number of carriers, the number of multiple inputs and outputs of each carrier, bandwidth, subcarrier spacing, etc., which are related parameters of resources allocated to the UE by the base station through interaction with the UE, and the dynamic scheduling information includes related information of the data task scheduling. Because the resource allocation adopts an on-demand allocation mode, each scheduling needs the interaction of scheduling signaling, the control signaling cost is large, the control signaling cost is relatively fixed according to the size of the communication service data packets, and the time intervals among the data packets also meet a certain regularity, so semi-static configuration can be adopted, namely, the transmission or the reception of the service data is carried out on the same time-frequency resource position every fixed period by storing static configuration information. According to the periodically arriving characteristic, one-time authorization period is used, and certain control information is reserved for the dynamically scheduled service for use while PDCCH resources for scheduling indication are saved. The load demand for processing the data task can be calculated by acquiring the semi-static configuration information and the dynamic scheduling information, so that the adaptive frequency and voltage gear can be configured.

In this example, the baseband chip calculates the frequency-voltage gear to which the target hardware combination needs to be adjusted by acquiring the semi-static configuration information of the electronic device and the relevant dynamic scheduling information of the received data task, so that the target hardware combination can be ensured to complete the data task in the adaptive gear, waste of redundant power consumption is avoided, and the efficiency of power consumption saving is improved. Compared with the prior art, the frequency voltage pre-configuration can reduce the span between the current frequency voltage gear and the frequency voltage gear to be adjusted by the target hardware combination, further effectively reduce delay caused by boosting, improve the chip work response speed, and effectively improve the user experience.

In one possible example, in the determining the first frequency-voltage gear that adapts to the load requirement of the first data task according to the semi-static configuration information and the dynamic scheduling information, the baseband chip 310 is specifically configured to: determining at least one first frequency demand gear, at least one second frequency demand gear and at least one voltage demand gear according to the semi-static configuration information and the dynamic scheduling information, wherein the at least one first frequency demand gear is in one-to-one correspondence with at least one core of the target hardware combination, the at least one second frequency demand gear is in one-to-one correspondence with at least one signal processing circuit of the target hardware combination, and the at least one voltage demand gear is in one-to-one correspondence with at least one core of the target hardware combination and at least one signal processing circuit; determining a first frequency demand gear with the largest value in the at least one first frequency demand gear as the first target frequency gear; determining a second frequency demand gear with the largest value in the at least one second frequency demand gear as the second target frequency gear; and determining the first voltage requirement gear with the largest value in at least one first voltage requirement gear as the first voltage gear.

The first frequency voltage gear comprises a first frequency gear and a first voltage gear, the first frequency gear comprises a first target frequency gear and a second target frequency gear, the first target frequency gear is a frequency gear of a clock frequency domain to which at least one kernel of the target hardware combination belongs, the second target frequency gear is a frequency gear of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs, and the first voltage gear is a voltage gear of a voltage domain to which the target hardware combination belongs; the first frequency voltage gear comprises a first frequency gear and a first voltage gear, the first frequency gear comprises a first target frequency gear and a second target frequency gear, the first target frequency gear is a frequency gear of a clock frequency domain to which at least one kernel of the target hardware combination belongs, the second target frequency gear is a frequency gear of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs, and the first voltage gear is a voltage gear of a voltage domain to which the target hardware combination belongs.

The hardware in the target hardware combination is located in different clock frequency domains, at least one core in the target hardware combination belongs to the same clock frequency domain, at least one signal processing circuit in the target hardware combination belongs to the same clock frequency domain, and the hardware in the whole target hardware combination belongs to the same voltage domain. The different domains are mutually independent and share different frequencies or voltages, and the hardware in the same domain shares the same frequency or voltage, so that the frequency gear corresponding to the target hardware combination is characterized by two frequency magnitudes aiming at different clock frequency domains, and the voltage gear corresponding to the target hardware combination is characterized by the voltage magnitude of the hardware in the whole target hardware combination. It is equally understood that the voltage values corresponding to at least one core and at least one signal processing circuit in the target hardware combination are simultaneously the same in magnitude, and they share one voltage gear.

Alternatively, the cores in the hardware combination represent cores in hardware, generally referred to as basic computation units in a central processing unit (central processing unit, CPU) for performing all operations of computing, receiving or storing commands, processing data, etc. A plurality of cores can be arranged in a CPU and are responsible for controlling and managing the whole mobile station, including timing control, digital system control, radio frequency control, power saving control, man-machine interface control and the like. If frequency hopping is employed, control of the frequency hopping should also be included. The signal processing circuits in the hardware combination include, but are not limited to, baseband processing circuits, amplifiers, filters, linearization processing circuits, etc., where the baseband processing circuits are the basic processing operations responsible for wireless mobile signals. The signal processing circuit is capable of performing various processes including, but not limited to, charge/voltage conversion, current/voltage conversion, frequency/voltage conversion, impedance conversion, etc., and amplifying, active filtering, or operating on the converted electrical signal according to different requirements.

The voltage domains are determined by the hardware power supply link division, and all the hardware in each voltage domain share the same voltage value, as shown in fig. 3b, fig. 3b is a schematic diagram of voltage division provided in the embodiment of the present application. In fig. 3b, the hardware combination 1 and the hardware combination 2 use the power supply link 1 to supply power, the hardware combination 3 and the hardware combination 4 use the power supply link 2 to supply power, and under the same power supply link, all the cores and the signal processing circuit share the same voltage value, and the voltage gear is used for representing the voltage value corresponding to the power supply link 1 or 2. It is equally understood that the voltage values corresponding to at least one core and at least one signal processing circuit in the target hardware combination are simultaneously the same in magnitude, and they share one voltage gear.

The clock frequency domain is determined by the division of the hardware clock tree, as shown in fig. 3c, fig. 3c is a schematic diagram of the division of the hardware clock tree according to the embodiment of the present application. In fig. 3c, there are 4 clock frequency inputs with different magnitudes, i.e. there are 4 frequency gears, and the adjustment of the gears can be divided into a first gear, a second gear, a third gear and a fourth gear according to their magnitudes from low to high, and the multiplexer has a clock frequency selection function, the input is clocks with different gear frequencies, the output is clocks after gear selection, and each hardware area continuously connected to the output is a clock frequency domain. In a hardware combination at least one core and at least one signal processing circuit are assigned to different clock frequency domains, each clock frequency domain corresponding to a different or possibly identical frequency range.

In this example, the voltage and the frequency required by all the hardware units are calculated, and the maximum frequency voltage requirement gear in all the hardware units in the same clock frequency domain or voltage domain is selected for configuration, so that the finally determined frequency voltage gear can meet the frequency voltage requirement of all the hardware units in the target hardware combination, normal processing of the data task is ensured, and the working stability of the chip is improved.

In one possible example, the baseband chip 310 is further configured to, prior to the detecting the first data task of adapting the target hardware combination 330: detecting that the target hardware combination 330 enters a wait for interrupt state, and starting a preset timer; if no data task adapting to the target hardware combination 330 is detected within the timing range of the timer, the hardware state of the target hardware combination 330 is switched from the wait for interrupt state to the idle state. The power management chip 320 is further configured to: and adjusting the working frequency voltage gear of the target hardware combination from a second frequency voltage gear to the idle state frequency voltage gear, wherein the second frequency voltage gear is a preset initial gear or a gear which is suitable for the load requirement of the previous data task.

When the target hardware combination processes the data task of the current service type matched with the target hardware combination, the target hardware combination automatically changes into a waiting interrupt (Wait for interrupt, WFI) state, and the frequency-voltage gear of the target hardware combination at the moment is not changed and still keeps the load demand gear of the last task. When the target hardware combination enters the WFI state, the timer is started to judge whether the high-frequency voltage gear adapting to the load requirement of the last task is required to be continuously maintained when the target hardware combination is in an unoperated state, if the data task which is properly matched with the target hardware combination is not detected within a specified duration, the hardware state of the target hardware combination is set to be an idle state, and the idle state frequency voltage gear is a low-power consumption gear.

Optionally, as shown in fig. 3d, fig. 3d is a schematic diagram of a timer provided in an embodiment of the present application, where a period of the timer is determined, where the period of the timer characterizes a length of a timing range. In a specific service scenario, there is a feature in the communication service timing schedule scheduling, that is, the UE needs to de-allocate downlink scheduling grant information issued by the physical downlink control channel (Physical Downlink Control Channel, PDCCH) at the first several symbols of a downlink slot, and when de-allocates downlink grant, de-allocate downlink data issued by the UE by the physical downlink shared channel (Physical Downlink Shared Channel, PDSCH) at the de-allocating side according to the grant information. It will be appreciated that the delivery of the data task is uncertain in this time slot. As shown in fig. 3d, T0 is the starting time of the timeslot, if the target hardware combination enters the WFI state at this time, the timer is started, and when no new data task is detected within a period of time exceeding the timer, the baseband chip switches the hardware state of the target hardware combination to the idle state and controls the power management chip to reduce the frequency and the voltage of the power management chip. It can be understood that, in the figure, T1, T2, and T3 are the moments when the target hardware combination enters the WFI state, and are all random in practical situations.

It can be seen that in this example, the target hardware combination is prevented from maintaining the high-frequency voltage gear for a long time in the event that the data task is not completed by enabling the timer, thereby causing waste of power consumption. Therefore, the target hardware combination can be reduced in frequency and voltage to a low-power-consumption frequency voltage gear when no task arrives, so that power consumption is saved, and the efficiency of chip power consumption management is improved.

It is to be appreciated that the electronic device 300 may include more or fewer structural elements than those described in the above-described block diagrams, including, for example, a power module, physical key, wi-Fi module, speaker, bluetooth module, sensor, etc., without limitation.

It can be seen that, as shown in fig. 3e, fig. 3e is a flow chart of frequency-voltage pre-configuration of DVFS technology provided in the embodiment of the present application, and fig. 3e is an 8 th step compared to the flow chart of configuration of the prior art shown in fig. 3d, that is, the software module sends a pre-configuration instruction to the hardware module. Therefore, after the baseband chip of the electronic equipment detects the data task, the reference frequency voltage gear is immediately configured for the target hardware combination through the power management chip, so that the frequency voltage gear of the target hardware combination is rapidly switched from the low-power consumption gear to the working gear for data processing, compared with the existing scheme that the configuration is performed after the frequency voltage gear calculation result of the current data task is required to be calculated and adapted in real time, the frequency voltage gear configuration time delay is reduced, and the efficiency and the instantaneity of the electronic equipment for data processing are improved.

Referring to fig. 4, fig. 4 is a schematic process diagram of a frequency voltage pre-configuration method applied to a baseband chip of an electronic device, where the frequency voltage pre-configuration method includes:

step 401, detecting a first data task adapting to a target hardware combination, switching a hardware state of the target hardware combination from an idle state to a busy state, and acquiring a reference frequency pressure gear;

In one possible example, the reference frequency voltage gear is any one of a plurality of selectable frequency voltage gears among the operating frequency voltage gears of the target hardware combination.

In one possible example, the acquiring the reference frequency voltage gear includes: acquiring a plurality of frequency gears and a plurality of voltage gears corresponding to the data task of the target service type; determining the reference frequency gear according to the plurality of frequency gears; and determining the reference voltage gear according to the voltage gears.

In one possible example, the plurality of frequency ranges are historical frequency ranges configured by the target hardware combination, and any two frequency ranges are different from each other; the plurality of voltage gears are historical voltage gears configured by the target hardware combination, and any two voltage gears are different from each other.

In one possible example, after the detecting the first data task adapting the target hardware combination, the method further comprises: acquiring semi-static configuration information of the electronic equipment and dynamic scheduling information corresponding to the first data task; and determining a first frequency voltage gear adapting to the load demand of the first data task according to the semi-static configuration information and the dynamic scheduling information, and sending a first frequency voltage gear vote to the power management chip, wherein the first frequency voltage gear vote is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination as the first frequency voltage gear to the power management chip.

In one possible example, the first frequency-voltage gear includes a first target frequency gear and a second target frequency gear, where the first target frequency gear is a frequency gear of a clock frequency domain to which at least one kernel of the target hardware combination belongs, and the second target frequency gear is a frequency gear of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs, and the first voltage gear is a voltage gear of a voltage domain to which the target hardware combination belongs; the determining a first frequency-voltage gear adapted to the load demand of the first data task according to the semi-static configuration information and the dynamic scheduling information includes: determining at least one first frequency demand gear, at least one second frequency demand gear and at least one voltage demand gear according to the semi-static configuration information and the dynamic scheduling information, wherein the at least one first frequency demand gear is in one-to-one correspondence with at least one core of the target hardware combination, the at least one second frequency demand gear is in one-to-one correspondence with at least one signal processing circuit of the target hardware combination, and the at least one voltage demand gear is in one-to-one correspondence with at least one core of the target hardware combination and at least one signal processing circuit; determining a first frequency demand gear with the largest value in the at least one first frequency demand gear as the first target frequency gear; determining a second frequency demand gear with the largest value in the at least one second frequency demand gear as the second target frequency gear; and determining the first voltage requirement gear with the largest value in at least one first voltage requirement gear as the first voltage gear.

In one possible example, before the detecting the first data task adapting the target hardware combination, the method further comprises: detecting that the target hardware combination enters a waiting interruption state, and starting a preset timer; and if the data task adapting to the target hardware combination is not detected within the timing range of the timer, switching the hardware state of the target hardware combination from the waiting interrupt state to the idle state, and sending a frequency-reducing and voltage-reducing instruction to the power management chip, wherein the frequency-reducing and voltage-reducing instruction is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination into the idle state frequency voltage gear for the power management chip.

Step 402, a frequency voltage pre-configuration instruction is sent to a power management chip, where the frequency voltage pre-configuration instruction is used to provide an instruction for configuring the working frequency voltage gear of the target hardware combination to the reference frequency voltage gear for the power management chip.

In the existing frequency-voltage adjusting technology, if the baseband chip detects that a new data task comes in when the target hardware combination is in an idle state, the target hardware combination maintains a low-power-consumption frequency-voltage gear corresponding to the idle state before the baseband chip calculates the frequency-voltage gear adapting to the load requirement of the data task and performs the frequency-voltage gear voting, so that the service module does not have enough high frequency voltage to process any data task corresponding to the hardware, and the gear span is too large when the frequency is increased to the adapting frequency-voltage gear, the step-up delay is caused, and the requirement of the service tight time sequence cannot be met. The frequency voltage gear of the target hardware combination can be quickly increased from the low-power frequency voltage gear to the higher working gear by acquiring the reference frequency voltage gear and sending the frequency voltage pre-configuration instruction to the power management chip to control the power management chip to pre-configure the frequency voltage gear of the target hardware combination while the baseband chip calculates the frequency voltage gear of the new data task, so that the gear span size can be reduced, the influence of the boosting delay can be reduced, and the target hardware combination can directly process the data task on probability. According to the technical scheme, when the target hardware combination waits for the baseband chip frequency voltage gear voting, the frequency voltage gear can be preconfigured for the target hardware combination, the working efficiency of the chip and the response speed of the chip are improved, and therefore the user experience is improved.

All relevant contents of each scenario related to the above method embodiment may be cited to the functional description of the corresponding device, which is not described herein.

The embodiment of the application provides a frequency voltage pre-configuration device, which can be an electronic device. Specifically, the frequency voltage pre-configuration device is used for executing the steps executed by the electronic device in the frequency voltage pre-configuration method. The frequency voltage pre-configuration device provided by the embodiment of the application can comprise modules corresponding to the corresponding steps.

According to the embodiment of the application, the frequency voltage pre-configuration device can be divided into the functional modules according to the method example, for example, each functional module can be divided corresponding to each function, and two or more functions can be integrated into one processing module. The integrated modules may be implemented in hardware or in software functional modules. The division of the modules in the embodiment of the present application is schematic, which is merely a logic function division, and other division manners may be implemented in practice.

In the case of dividing each functional module by adopting a corresponding function, referring to fig. 5, fig. 5 is a functional unit block diagram of a frequency voltage pre-configuration device provided in an embodiment of the present application, as shown in fig. 5, where the frequency voltage pre-configuration device is applied to an electronic device 300 shown in fig. 3a, and the frequency voltage pre-configuration device 500 includes: the acquisition gear unit 510: detecting a first data task adapting to a target hardware combination, switching a hardware state of the target hardware combination from an idle state to a busy state, and acquiring a reference frequency pressure gear; send instruction unit 520: and sending a frequency voltage pre-configuration instruction to a power management chip, wherein the frequency voltage pre-configuration instruction is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination as the reference frequency voltage gear for the power management chip.

In one possible example, the reference frequency voltage gear includes a reference frequency gear and a reference voltage gear, and the obtaining gear unit 510 is specifically configured to: acquiring a plurality of frequency gears and a plurality of voltage gears corresponding to the data task of the target service type; determining the reference frequency gear according to the plurality of frequency gears; and determining the reference voltage gear according to the voltage gears.

In one possible example, the sending instruction unit 520 is further configured to, after the detecting the first data task of adapting to the target hardware combination: acquiring semi-static configuration information of the electronic equipment and dynamic scheduling information corresponding to the first data task; determining a first frequency voltage gear adapting to the load demand of the first data task according to the semi-static configuration information and the dynamic scheduling information, and sending a first frequency voltage gear vote to the power management chip, wherein the first frequency voltage gear vote is used for indicating the first frequency voltage gear; for the following: and updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the first frequency voltage gear.

In one possible example, the first frequency-voltage gear includes a first target frequency gear and a second target frequency gear, where the first target frequency gear is a frequency gear of a clock frequency domain to which at least one kernel of the target hardware combination belongs, and the second target frequency gear is a frequency gear of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs, and the first voltage gear is a voltage gear of a voltage domain to which the target hardware combination belongs; in the aspect of determining the first frequency-voltage gear that adapts to the load requirement of the first data task according to the semi-static configuration information and the dynamic scheduling information, the sending instruction unit 520 is specifically configured to: determining at least one first frequency demand gear, at least one second frequency demand gear and at least one voltage demand gear according to the semi-static configuration information and the dynamic scheduling information, wherein the at least one first frequency demand gear is in one-to-one correspondence with at least one core of the target hardware combination, the at least one second frequency demand gear is in one-to-one correspondence with at least one signal processing circuit of the target hardware combination, and the at least one voltage demand gear is in one-to-one correspondence with at least one core of the target hardware combination and at least one signal processing circuit; determining a first frequency demand gear with the largest value in the at least one first frequency demand gear as the first target frequency gear; determining a second frequency demand gear with the largest value in the at least one second frequency demand gear as the second target frequency gear; and determining the first voltage requirement gear with the largest value in at least one first voltage requirement gear as the first voltage gear.

In one possible example, the gear acquisition unit 510 is specifically configured to: detecting that the target hardware combination enters a waiting interruption state, and starting a preset timer; if the data task adapting to the target hardware combination is not detected within the timing range of the timer, switching the hardware state of the target hardware combination from the interrupt waiting state to the idle state; for the following: and adjusting the working frequency voltage gear of the target hardware combination from a second frequency voltage gear to the idle state frequency voltage gear, wherein the second frequency voltage gear is a preset initial gear or a gear which is suitable for the load requirement of the previous data task.

It can be seen that, according to the frequency voltage pre-configuration device provided by the embodiment of the application, the frequency voltage pre-configuration operation is added while the baseband chip calculates the frequency voltage gear adapting to the new data task, so that the power management chip is controlled to pre-configure the frequency voltage gear of the target hardware combination, the frequency voltage gear of the target hardware combination can be quickly increased from the low-power frequency voltage gear to the higher working gear, the gear span size can be reduced, the influence of the boosting delay is reduced, and the target hardware combination can directly process the data task on probability. According to the technical scheme, when the target hardware combination waits for the baseband chip frequency voltage gear voting, the frequency voltage gear can be preconfigured for the target hardware combination, the working efficiency of the chip and the response speed of the chip are improved, and therefore the user experience is improved.

It can be understood that, since the method embodiment and the apparatus embodiment are in different presentation forms of the same technical concept, the content of the method embodiment portion in the present application should be adapted to the apparatus embodiment portion synchronously, which is not described herein.

In the case of using integrated units, as shown in fig. 6, fig. 6 is a block diagram of functional units of another frequency voltage pre-configuration apparatus provided in the embodiment of the present application. In fig. 6, the frequency-voltage pre-configuration apparatus 600 includes: a processing module 620 and a communication module 610. The processing module 620 is configured to control and manage the actions of the frequency press pre-configuration device, for example, performing the steps of acquiring the gear unit 510 and transmitting the instruction unit 520, and/or performing other processes of the techniques described herein. The communication module 610 is configured to support interaction between the frequency press pre-configuration apparatus and other devices. As shown in fig. 6, the frequency-voltage pre-configuration apparatus may further include a storage module 630, where the storage module 630 is configured to store program codes and data of the frequency-voltage pre-configuration apparatus.

The processing module 620 may be a processor or controller, such as a central processing unit (Central Processing Unit, CPU), a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an ASIC, an FPGA or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The communication module 610 may be a transceiver, an RF circuit, or a communication interface, etc. The storage module 630 may be a memory.

All relevant contents of each scenario related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein. The frequency pre-configuration device 600 may perform the frequency pre-configuration method shown in fig. 4.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present application are all or partially produced. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more sets of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk.

The present application also provides a computer storage medium storing a computer program for electronic data exchange, the computer program causing a computer to execute some or all of the steps of any one of the methods described in the method embodiments above.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any one of the methods described in the method embodiments above.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus, and system may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may be physically included separately, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: u disk, removable hard disk, magnetic disk, optical disk, volatile memory or nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of random access memory (random access memory, RAM) are available, such as Static RAM (SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced Synchronous Dynamic Random Access Memory (ESDRAM), synchronous Link DRAM (SLDRAM), direct memory bus RAM (DR RAM), and the like, various mediums that can store program code.

Although the present invention is disclosed above, the present invention is not limited thereto. Variations and modifications, including combinations of the different functions and implementation steps, as well as embodiments of the software and hardware, may be readily apparent to those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. The electronic equipment is characterized by comprising a baseband chip, a power management chip and a target hardware combination, wherein the target hardware combination is any one of a preset hardware set, the hardware set comprises at least one hardware combination divided according to the service types of data tasks to be processed by the baseband chip, the single hardware combination comprises at least one kernel and at least one signal processing circuit, and the hardware in any two hardware combinations is different from each other; wherein,,

2. The electronic device of claim 1, wherein the reference frequency bin is a frequency bin adapted for a task preceding the first data task.

3. The electronic device of claim 1, wherein the reference frequency voltage range is any one of a plurality of selectable frequency voltage ranges in the operating frequency voltage ranges of the target hardware combination.

4. The electronic device of claim 1, wherein the reference frequency voltage range comprises a reference frequency range and a reference voltage range, and wherein the baseband chip is specifically configured to:

Acquiring a plurality of frequency gears and a plurality of voltage gears corresponding to the data task of the target service type;

determining the reference frequency gear according to the plurality of frequency gears;

and determining the reference voltage gear according to the voltage gears.

5. The electronic device of claim 4, wherein the plurality of frequency ranges are historical frequency ranges configured for the target hardware combination, and any two frequency ranges are different from each other;

the plurality of voltage gears are historical voltage gears configured by the target hardware combination, and any two voltage gears are different from each other.

6. The electronic device of claim 4, wherein the reference frequency range is a frequency average of the plurality of frequency ranges or a range closest to the frequency average;

the reference voltage gear is a voltage average value of the plurality of voltage gears, or a voltage gear closest to the voltage average value.

7. The electronic device of any of claims 1-6, wherein the baseband chip, after the detecting the first data task to adapt the target hardware combination, is further to:

Acquiring semi-static configuration information of the electronic equipment and dynamic scheduling information corresponding to the first data task; determining a first frequency voltage gear adapting to the load demand of the first data task according to the semi-static configuration information and the dynamic scheduling information, and sending a first frequency voltage gear vote to the power management chip, wherein the first frequency voltage gear vote is used for indicating the first frequency voltage gear;

the power management chip is further configured to: and updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the first frequency voltage gear.

8. The electronic device of claim 7, wherein the first frequency voltage range comprises a first frequency range and a first voltage range, the first frequency range comprises a first target frequency range and a second target frequency range, the first target frequency range is a frequency range of a clock frequency domain to which at least one core of the target hardware combination belongs, the second target frequency range is a frequency range of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs, and the first voltage range is a voltage range of a voltage domain to which the target hardware combination belongs; in the aspect of determining the first frequency-voltage gear adapting to the load demand of the first data task according to the semi-static configuration information and the dynamic scheduling information, the baseband chip is specifically configured to:

Determining at least one first frequency demand gear, at least one second frequency demand gear and at least one voltage demand gear according to the semi-static configuration information and the dynamic scheduling information, wherein the at least one first frequency demand gear is in one-to-one correspondence with at least one core of the target hardware combination, the at least one second frequency demand gear is in one-to-one correspondence with at least one signal processing circuit of the target hardware combination, and the at least one voltage demand gear is in one-to-one correspondence with at least one core of the target hardware combination and at least one signal processing circuit;

determining a first frequency demand gear with the largest value in the at least one first frequency demand gear as the first target frequency gear;

determining a second frequency demand gear with the largest value in the at least one second frequency demand gear as the second target frequency gear;

and determining the first voltage requirement gear with the largest value in at least one first voltage requirement gear as the first voltage gear.

9. The electronic device of any of claims 1-6, wherein the baseband chip, prior to the detecting the first data task to adapt the target hardware combination, is further to:

Detecting that the target hardware combination enters a waiting interruption state, and starting a preset timer;

if the data task adapting to the target hardware combination is not detected within the timing range of the timer, switching the hardware state of the target hardware combination from the interrupt waiting state to the idle state;

the power management chip is further configured to: and adjusting the working frequency voltage gear of the target hardware combination from a second frequency voltage gear to the idle state frequency voltage gear, wherein the second frequency voltage gear is a preset initial gear or a gear which is suitable for the load requirement of the previous data task.

10. A method for frequency press pre-configuration, the method comprising:

a frequency voltage pre-configuration instruction is sent to a power management chip, and the frequency voltage pre-configuration instruction is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination as the reference frequency voltage gear for the power management chip;

acquiring semi-static configuration information of the electronic equipment and dynamic scheduling information corresponding to the first data task; the method comprises the steps of,

determining a first frequency demand gear with the largest value in the at least one first frequency demand gear as a first target frequency gear, wherein the first target frequency gear is a frequency gear of a clock frequency domain to which at least one kernel of the target hardware combination belongs;

determining a second frequency demand gear with the largest value in the at least one second frequency demand gear as a second target frequency gear, wherein the second target frequency gear is a frequency gear of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs;

determining a first voltage demand gear with the largest value in at least one first voltage demand gear as a first voltage gear, wherein the first voltage gear is a voltage gear of a voltage domain to which the target hardware combination belongs;

And sending a first frequency voltage gear vote to the power management chip, wherein the first frequency voltage gear vote is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination as the first frequency voltage gear to the power management chip, the first frequency voltage gear comprises a first frequency gear and a first voltage gear, and the first frequency gear comprises a first target frequency gear and a second target frequency gear.

11. The method of claim 10, wherein the reference frequency step is a frequency step for which a task preceding the first data task is adapted.

12. The method of claim 10, wherein the reference frequency voltage range is any one of a plurality of selectable frequency voltage ranges in the operating frequency voltage ranges of the target hardware combination.

13. The method of claim 10, wherein the reference frequency voltage range comprises a reference frequency range and a reference voltage range; the step of obtaining the reference frequency voltage gear comprises the following steps:

acquiring a plurality of frequency gears and a plurality of voltage gears corresponding to a data task of a target service type;

And determining the reference voltage gear according to the voltage gears.

14. The method of claim 13, wherein the plurality of frequency ranges are historical frequency ranges configured for the target hardware combination, and any two frequency ranges are different from each other; the plurality of voltage gears are historical voltage gears configured by the target hardware combination, and any two voltage gears are different from each other.

15. The method of claim 13, wherein the reference frequency range is a frequency average of the plurality of frequency ranges, or a range closest to the frequency average; the reference voltage gear is a voltage average value of the plurality of voltage gears, or a voltage gear closest to the voltage average value.

16. The method according to any of claims 10-15, wherein prior to the detecting the first data task adapting the target hardware combination, the method further comprises:

if the data task adapting to the target hardware combination is not detected within the timing range of the timer, switching the hardware state of the target hardware combination from the waiting interruption state to the idle state, and sending a control instruction to the power management chip, wherein the control instruction is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination into the idle state frequency voltage gear to the power management chip, and the idle state frequency voltage gear is a low-power consumption gear.

17. A frequency voltage pre-configuration apparatus, the apparatus comprising:

and a transmission instruction unit: a frequency voltage pre-configuration instruction is sent to a power management chip, and the frequency voltage pre-configuration instruction is used for providing an instruction for configuring the working frequency voltage gear of the target hardware combination as the reference frequency voltage gear for the power management chip;

the gear acquisition unit is further used for acquiring semi-static configuration information of the electronic equipment and dynamic scheduling information corresponding to the first data task;

the sending instruction unit is further configured to determine at least one first frequency requirement gear, at least one second frequency requirement gear and at least one voltage requirement gear according to the semi-static configuration information and the dynamic scheduling information, where the at least one first frequency requirement gear corresponds to at least one core of the target hardware combination one to one, the at least one second frequency requirement gear corresponds to at least one signal processing circuit of the target hardware combination one to one, and the at least one voltage requirement gear corresponds to at least one core of the target hardware combination one to one and at least one signal processing circuit one to one; determining a first frequency demand gear with the largest value in the at least one first frequency demand gear as a first target frequency gear, wherein the first target frequency gear is a frequency gear of a clock frequency domain to which at least one kernel of the target hardware combination belongs; determining a second frequency demand gear with the largest value in the at least one second frequency demand gear as a second target frequency gear, wherein the second target frequency gear is a frequency gear of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs; determining a first voltage demand gear with the largest value in at least one first voltage demand gear as a first voltage gear, wherein the first voltage gear is a voltage gear of a voltage domain to which the target hardware combination belongs;

The sending instruction unit is further configured to send a first frequency voltage gear vote to the power management chip, where the first frequency voltage gear vote is configured to provide an instruction for configuring the working frequency voltage gear of the target hardware combination to the power management chip as the first frequency voltage gear, the first frequency voltage gear includes a first frequency gear and a first voltage gear, and the first frequency gear includes the first target frequency gear and the second target frequency gear.