CN114779879B

CN114779879B - Frequency-voltage adjusting method and related device

Info

Publication number: CN114779879B
Application number: CN202210485999.8A
Authority: CN
Inventors: 黄河
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-05-06
Filing date: 2022-05-06
Publication date: 2024-04-30
Anticipated expiration: 2042-05-06
Also published as: CN114779879A

Abstract

The embodiment of the application provides a frequency voltage regulating method and a related device, wherein the device comprises a baseband chip, a power management chip and a target hardware combination; wherein the baseband chip is configured to: detecting a hardware state of a target hardware combination; enabling a timer of a task distribution type corresponding to the first signal processing period based on determining that the target hardware combination enters a waiting interrupt state; when the data task is not detected in the timing range, setting the hardware state of the target hardware combination to be an idle state; the power management chip is configured to: and updating the working frequency voltage gear of the target hardware combination into an idle state frequency voltage gear. Therefore, the busyness of the baseband chip processing data in the period of the current system time is dynamically adapted to the timer, so that the target hardware combination can be kept in a low-power-consumption gear for a long time in probability, the hardware power consumption is reduced, and the energy consumption management efficiency is improved.

Description

Frequency-voltage adjusting method and related device

Technical Field

The application relates to the technical field of chips, in particular to a frequency voltage adjusting method and a related device.

Background

At present, with the high-speed development of electronic technology, the integration and complexity of chips in mobile terminals are increasing, and with the increase of the working frequency of chips, the energy consumption generated by the chips is also increasing.

Disclosure of Invention

The application provides a frequency voltage regulating method and a related device, which can probabilistically ensure that a baseband chip can keep the power consumption control of a data task in a low-power-consumption gear for a long time in a signal processing period with low data processing busyness by starting a first timer corresponding to the busyness of the baseband chip in a first signal processing period, thereby improving the energy consumption management efficiency.

In a first aspect, an embodiment of the present application provides an electronic device, including a baseband chip, a power management chip, and a target hardware combination, where the target hardware combination includes at least one core and at least one signal processing circuit;

The baseband chip is configured to: detecting a hardware state of the target hardware combination; enabling a first timer of a task distribution type corresponding to a first signal processing period based on determining that the target hardware combination enters a waiting interrupt state, wherein the task distribution type is used for indicating the busyness of the baseband chip to process data in the corresponding signal processing period; and when the data task adapting to the target hardware combination is not detected within the timing range of the first timer, setting the hardware state of the target hardware combination from the interrupt waiting state to an idle state;

The power management chip is configured to: and based on the fact that the hardware state of the target hardware combination is determined to be an idle state, updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the idle state frequency voltage gear.

In a second aspect, an embodiment of the present application provides a method for adjusting a frequency voltage, which is used in an electronic device including a baseband chip, a power management chip, and a target hardware combination, where the target hardware combination includes at least one core and at least one signal processing circuit, and the method includes:

detecting a hardware state of the target hardware combination;

Enabling a first timer of a task distribution type corresponding to a first signal processing period based on determining that the target hardware combination enters a waiting interrupt state, wherein the task distribution type is used for indicating the busyness of the baseband chip to process data in the corresponding signal processing period; and

Setting a hardware state of the target hardware combination from the wait for interrupt state to an idle state based on determining that no data task adapting to the target hardware combination is detected within a timing range of the first timer;

And based on the fact that the hardware state of the target hardware combination is determined to be an idle state, updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the idle state frequency voltage gear.

In a third aspect, an embodiment of the present application provides a device for adjusting a frequency voltage, including:

And a detection unit: a hardware state for detecting the target hardware combination;

Enabling the timer unit: the first timer is used for starting a task distribution type corresponding to a first signal processing period based on the fact that the target hardware combination is determined to enter a waiting interrupt state, and the task distribution type is used for indicating the busyness of the baseband chip to process data in the corresponding signal processing period;

a state switching unit: setting a hardware state of the target hardware combination from the wait for interrupt state to an idle state based on determining that no data task adapting the target hardware combination is detected within a timing range of the first timer;

Frequency voltage updating unit: and updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the idle state frequency voltage gear based on the fact that the hardware state of the target hardware combination is determined to be the idle state.

In a fourth aspect, embodiments of the present application provide a computer storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform some or all of the steps as described in the first aspect of the present embodiment.

In a fifth aspect, embodiments of the present application provide a computer program product, wherein the computer program product comprises a computer program operable to cause a computer to perform some or all of the steps described in the first aspect of the embodiments of the present application.

In the embodiment of the application, in the system architecture that the baseband chip controls the target hardware combination to process the data task through the power management chip, in a signal processing period with low busyness of the data processed by the baseband chip, the number of the data tasks is small, and the interval time of adjacent data tasks is longer.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of an application scenario of DVFS technology provided in an embodiment of the present application;

FIG. 2a is a flow chart of a software voting configuration of a DVFS technique according to an embodiment of the present application;

FIG. 2b is a flowchart of a hardware detection configuration of a DVFS technology according to an embodiment of the present application;

FIG. 3a is a block diagram of an electronic device according to an embodiment of the present application;

FIG. 3b is a schematic diagram illustrating a timer switching according to an embodiment of the present application;

FIG. 3c is a schematic diagram of voltage division according to an embodiment of the present application;

FIG. 3d is a schematic diagram of a hardware clock tree partition according to an embodiment of the present application;

fig. 4 is a schematic process diagram of a method for adjusting frequency voltage according to an embodiment of the present application;

Fig. 5 is a functional unit composition block diagram of a frequency voltage adjusting device according to an embodiment of the present application;

fig. 6 is a block diagram of functional units of another frequency voltage adjusting device according to an embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Currently, with the development of communication technologies, especially the evolution of the fifth generation mobile communication technology (5th Generation Mobile Communication Technology,5G), independent networking (Standalone, SA) and Non-independent networking (Non-Standalone, NSA) have been deployed in large numbers in commercial networks, and in a 5G scenario, higher requirements are put on communication performance such as throughput, delay, mobility management, etc. of a User Equipment (UE), and at the same time, power consumption control of a modem is also challenged. Therefore, the DVFS technology solves the problem of power consumption to a certain extent, and can match the clock frequency and the voltage which meet the service scene according to the load requirement of the service scene on the premise of meeting the performance requirements of various communication service scenes, thereby completing the dynamic adjustment of the clock frequency and the voltage, achieving the purpose of reducing the power consumption, realizing the low-power consumption control of a modem, improving the power consumption performance competitiveness of the UE and improving the experience of users for using products.

For example, as shown in fig. 1, fig. 1 is a schematic diagram of an application scenario of a DVFS technology provided in an embodiment of the present application, taking a typical application scenario of the DVFS technology, i.e., a carrier aggregation scenario, where a network side configures different numbers of carriers for a UE by detecting a current uplink and downlink throughput of the UE, so as to meet a requirement of the uplink and downlink throughput, and the different numbers of carriers affect an operation load of hardware, and the DVFS technology sets different frequency-voltage gears by calculating the load requirements under the different numbers of carriers, so as to achieve a purpose of low power consumption control. The DVFS technology mainly uses a control strategy of combining software and hardware to realize frequency modulation and voltage regulation of hardware, as shown in fig. 2a and fig. 2b, fig. 2a is a software voting configuration flow chart of the DVFS technology provided by the embodiment of the present application, and fig. 2b is a hardware detection configuration flow chart of the DVFS technology provided by the embodiment of the present application. As shown in the software voting configuration flow chart, the base station issues carrier configuration or de-configuration information to a radio resource control (Ratio Resource Control, RCC) layer of the UE, and then the RCC layer of the UE transmits the information to a hardware combination, and the hardware combination issues the current carrier configuration information to a software module of the DVFS; the base station transmits the dynamic scheduling information to the hardware combination, and the hardware combination transmits the transmitting information to the DVFS software module; and finally, the DVFS software module calculates a frequency voltage gear meeting the requirement of the corresponding hardware combination load according to the current configuration information and the dynamic scheduling information, votes the determined frequency voltage gear to the DVFS hardware module, and sends a feedback message to the DVFS software module after the DVFS hardware module finishes the frequency voltage setting. And when the target hardware combination is detected to enter the waiting interrupt state, starting a timer adapting to the task distribution type corresponding to the first signal processing period where the current system time is located, and if the target hardware combination is not detected to exit the waiting interrupt state within the timing range of the timer, clearing the timer, determining that the hardware state of the target hardware combination is an idle state, and reducing the frequency and the voltage. If the target hardware combination is detected to exit the waiting interruption state in the timing range of the timer, waiting for the frequency-voltage gear voting, and setting the frequency-voltage gear according to the voting. However, in an actual service scenario, since the timing range of the timer is set by software and is fixed, the timing range may be too long, so that the hardware combination cannot be put into a low-power consumption state at a delay, and thus the actual energy-saving effect cannot reach the expected effect, and the use experience of a user is affected.

In order to solve the above problems, an embodiment of the present application provides an electronic device, which controls a power management chip through a baseband chip to perform frequency modulation and voltage regulation on a target hardware combination. According to the method, after a baseband chip detects that a target hardware combination enters a waiting interrupt state, a first timer adapting to a task distribution type corresponding to a first signal processing period where the current system time is located is started, after a data task adapting to the target hardware combination is not detected all the time within the timing range of the first timer, the baseband chip enables a power management chip to regulate a frequency voltage gear of the target hardware combination through an instruction, so that the target hardware combination keeps low power consumption for a time as long as possible when the task is not required to be processed, the energy saving purpose is achieved, and the problem that the prior art cannot timely carry out frequency reduction and voltage reduction according to specific service scenes is solved.

Referring to fig. 3a, fig. 3a is a block diagram of an electronic device according to an embodiment of the present application, where the electronic device 300 includes a baseband chip 310, a power management chip 320, and a target hardware combination 330, where the target hardware combination includes at least one core and at least one signal processing circuit;

The baseband chip 310 is configured to: detecting a hardware state of the target hardware combination 330; based on determining that the target hardware combination 330 enters a wait for interrupt state, enabling a first timer of a task distribution type corresponding to a first signal processing period, wherein the task distribution type is used for indicating the busyness of the baseband chip 310 to process data in the corresponding signal processing period; and when no data task adapting to the target hardware combination 330 is detected within the timing range of the first timer, setting the hardware state of the target hardware combination 330 from the wait for interrupt state to an idle state;

The power management chip 320 is configured to: and updating the working frequency voltage gear of the target hardware combination 330 from the reference frequency voltage gear to the idle state frequency voltage gear based on the determination that the hardware state of the target hardware combination 330 is the idle state.

The target hardware combination 330 is any one of a preset hardware set, where the hardware set includes at least one hardware combination divided according to a service type of a data task to be processed by the baseband chip 310, and the hardware in any two hardware combinations is different from each other; the target hardware combination 330 is configured to process data tasks of a target traffic type, which is a traffic type pre-configured to the target hardware combination.

The idle state frequency voltage gear is a low-power consumption gear, and the reference frequency voltage gear is a preset initial gear or a gear which is suitable for the load requirement of the previous data task. Specifically, the frequency-voltage gear includes a frequency gear for setting a frequency of at least one core in the hardware combination and a frequency of at least one signal processing circuit, and a voltage gear for setting a voltage of at least one core in the hardware combination and a voltage of at least one signal processing circuit.

Optionally, the connection relationship between the components in the electronic device may be: the baseband chip 310 is connected with the power management chip 320, and the power management chip 320 is connected with the target hardware combination 330, that is, the baseband chip realizes the adjustment of the frequency voltage gear of the target hardware combination through the power management chip.

When the target hardware combination processes the data task of the current service type matched with the target hardware combination, the target hardware combination automatically changes into a waiting interrupt (Wait for interrupt, WFI) state, and the frequency-voltage gear of the target hardware combination at the moment is not changed and still keeps the load demand gear of the last task. When the target hardware combination enters the WFI state, the timer is started to judge whether the high-frequency voltage gear adapting to the load requirement of the last task is required to be continuously maintained when the target hardware combination is in an unoperated state, if the data task which is properly matched with the target hardware combination is not detected within a specified duration, the hardware state of the target hardware combination is set to be an idle state, and the idle state frequency voltage gear is a low-power consumption gear. In the signal processing period of low busyness of the baseband chip for processing data, after the hardware state of the target hardware combination is switched to the idle state by adapting the timer, the low-power-consumption gear can be kept for a long time until a new data task is detected to come and then the high-frequency voltage gear is pulled to adapt to the processing requirement of the data task, so that the power consumption of the data task can be controlled to be kept in the low-power-consumption gear for a long time in the signal processing period of low busyness of the processing data by the baseband chip on probability, and the energy consumption management efficiency is improved. Likewise, if a data task matched with the target hardware group is detected within a specified time length, the chip calculates the gear required by the data task and adjusts the gear, so that the quick adjustment between the gears can be realized, thereby being beneficial to timely meeting the service time sequence and the load demand and avoiding influencing the service.

Optionally, as shown in fig. 3b, fig. 3b is a schematic diagram of switching a timer according to an embodiment of the present application, where the timer is divided into a long-period timer and a short-period timer, and the period of the timer characterizes the length of the timing range; the communication service timing schedule has a feature that the UE needs to de-allocate downlink scheduling grant information issued by the UE through a physical downlink control channel (Physical Downlink Control Channel, PDCCH) at the first several symbols of a downlink slot, and when de-allocating downlink grant, de-allocate downlink data issued by the UE through a physical downlink shared channel (Physical Downlink SHARED CHANNEL, PDSCH) at the de-allocating side according to the grant information. By combining the characteristic of time sequence scheduling of communication service and combining a scheduling mechanism of hardware combination in a baseband chip, a long-period timer is used for a time period of busy data processing of the baseband chip, and a short-period timer is used for a time period of idle data processing of the baseband chip, so that the timing range of the timer can be switched according to the requirement of service scenes, and the time sequence or energy saving requirement is met.

Specifically, as shown in fig. 3b, in the period from T1 to T2 in the downlink timeslot N, since the busy level of the corresponding hardware combination processing data in the period is low, the corresponding hardware combination is not required to keep the high power consumption gear for a long time, which results in waste, and the starting of the short period timer in the period enables the hardware combination to enter the idle state as soon as possible with high probability and reduce the gear to the low power consumption gear so as to achieve the energy saving effect, thereby solving the problem that the power consumption cannot be reduced due to the overlong timer setting in the prior art, and ensuring the optimal control of the power consumption. It can be appreciated that the smaller the timing range b corresponding to the short period timer, the more advantageous the power consumption is saved, but a certain timing range is reserved to prevent the data task from being detected in a shorter interval time under an emergency. The timing range a shown in the figure is a timing range corresponding to a long-period timer, and the long-period timer should be set to be adapted to a time period in which the baseband chip is busy in processing data, so that the target hardware combination cannot be switched to an idle state with a high probability.

In one possible example, the baseband chip 310 is further configured to: detecting a first data task adapting to the target hardware combination in the first signal processing period, switching the hardware state of the target hardware combination from the idle state to a busy state, and determining a first frequency voltage gear adapting to the load requirement of the first data task; the power management chip 320 is further configured to: and adjusting the working frequency voltage gear of the target hardware combination from the idle state frequency voltage gear to the first frequency voltage gear.

After the target hardware combination enters an idle state, if a task which is responsible for processing by the target hardware combination is detected, in order to enable the target hardware combination to process the task, a baseband chip calculates a frequency voltage gear which is supposed to be configured by the target hardware combination according to a load requirement actually required by the task, and sends the calculated frequency voltage gear to a power management chip to adjust a working voltage gear and a working frequency gear which correspond to the target hardware combination. Because a certain time is needed for calculating and transmitting the frequency voltage gear, the target hardware combination which keeps the low-power-consumption gear is not processed for a while before the power management chip acquires the frequency voltage gear transmitted by the baseband chip, and the data task is processed after the gear is adjusted.

For example, the service type of the data task to be processed by the target hardware combination is a downlink decoding service type. When the target hardware combination enters the idle state, if the cell capacity measurement task is detected, the target hardware combination does not need to be switched from the idle state to the busy state and the adjustment of the gear. If a downlink decoding task is detected, the baseband chip calculates that the frequency voltage gear adapting to the load requirement of the downlink decoding task is the fifth gear, and switches the target hardware combination from an idle state to a busy state, and the target hardware combination cannot meet the task processing requirement at the moment because the low-power consumption gear, so that the processing of the data task is started after the power management chip receives the frequency voltage gear vote of the fifth gear sent by the baseband chip and adjusts the frequency voltage gear of the target hardware combination.

In this example, when a data task properly matched with the target hardware group is detected, the hardware state of the target hardware group is switched to a busy state, and then the waiting baseband chip calculates a frequency voltage gear adapted to the data task and votes for a power management chip to adjust the working frequency voltage gear corresponding to the target hardware group. Therefore, the target hardware combination can be controlled to work only when the adaptation task is detected, and the working frequency gear is adapted to the data task, so that unnecessary power consumption waste is avoided, and the power consumption saving efficiency is improved.

In one possible example, the idle state frequency voltage gear includes an idle voltage gear and an idle frequency gear, and the first frequency voltage gear includes the first frequency gear and a first voltage gear; in the aspect that the operating frequency voltage gear of the target hardware combination is adjusted from the idle frequency voltage gear to the first frequency voltage gear, the power management chip 320 is specifically configured to: adjusting the operating voltage range of the target hardware combination 330 from the idle state voltage range to the first voltage range; and adjusting the operating frequency range of the target hardware combination 330 from the idle state frequency range to the first frequency range.

The frequency voltage gear comprises a voltage gear and a frequency gear, and the idle state frequency voltage gear and the first frequency voltage gear also comprise two types of gears for representing voltage and frequency. It will be appreciated that when adjusting the gear, the operating voltage gear is adjusted according to the voltage gear and the operating frequency gear is adjusted according to the frequency gear.

For example, the voltage gear in the idle state frequency voltage gear is the first gear, and the frequency gear is also the first gear; the voltage gear in the first frequency voltage gear is the third gear, and the frequency gear is the second gear. When the frequency voltage gear is adjusted for the target hardware combination, the first gear corresponding to the voltage gear is firstly increased to the third gear, and then the first gear corresponding to the frequency voltage gear is increased to the second gear.

In this example, the calculated gear of the load requirement of the adaptive data task includes two types of gears for voltage and frequency, and the two types of gears correspond to the frequency-voltage gear combined by the target hardware, so that after the adaptive frequency-voltage gear is obtained, the frequency gear and the voltage gear can be respectively adjusted, the frequency-voltage adjusting process is simplified, and the frequency-voltage adjusting efficiency is improved.

In one possible example, the operating frequency range includes a first operating frequency range and a second operating frequency range, the first frequency range includes a first target frequency range and a second target frequency range, the first operating frequency range and the first target frequency range are frequency ranges of a clock frequency domain to which at least one core of the target hardware combination belongs, and the second operating frequency range and the second target frequency range are frequency ranges of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs; in the aspect of adjusting the operating frequency range from the idle frequency range to the first frequency range, the power management chip 320 is specifically configured to: the first operating frequency range of the at least one core of the target hardware combination 330 is adjusted from the idle frequency range to the first target frequency range, and the second operating frequency range of the at least one signal processing circuit of the target hardware combination 330 is adjusted from the idle frequency range to the second target frequency range.

The hardware in the target hardware combination is located in different clock frequency domains, at least one core in the target hardware combination belongs to the same clock frequency domain, at least one signal processing circuit in the target hardware combination belongs to the same clock frequency domain, and the hardware in the whole target hardware combination belongs to the same voltage domain. The different domains are mutually independent and share different frequencies or voltages, and the hardware in the same domain shares the same frequency or voltage, so that the frequency gear corresponding to the target hardware combination is characterized by two frequency magnitudes aiming at different clock frequency domains, and the voltage gear corresponding to the target hardware combination is characterized by the voltage magnitude of the hardware in the whole target hardware combination. For all hardware units belonging to the same clock frequency domain and voltage domain, the same clock frequency and voltage value need to be shared, so that the maximum frequency voltage requirement gear in all hardware units in the domain needs to be selected for configuration in the implementation of frequency voltage regulation.

Alternatively, the cores in the hardware combination represent cores in hardware, generally referred to as basic computation units in a central processing unit (central processing unit, CPU) for performing all operations of computing, receiving or storing commands, processing data, and the like. A plurality of cores can be arranged in a CPU and are responsible for controlling and managing the whole mobile station, including timing control, digital system control, radio frequency control, power saving control, man-machine interface control and the like. If frequency hopping is employed, control of the frequency hopping should also be included. The signal processing circuits in the hardware combination include, but are not limited to, baseband processing circuits, amplifiers, filters, linearization processing circuits, etc., where the baseband processing circuits are the basic processing operations responsible for wireless mobile signals. The signal processing circuit is capable of performing various processes including, but not limited to, charge/voltage conversion, current/voltage conversion, frequency/voltage conversion, impedance conversion, etc., and amplifying, active filtering, or operating on the converted electrical signal according to different requirements.

The voltage domains are determined by hardware power supply link division, and all hardware in each voltage domain share the same voltage value, as shown in fig. 3c, fig. 3c is a schematic diagram of voltage division according to an embodiment of the present application. In fig. 3c, the hardware combination 1 and the hardware combination 2 use the power supply link 1 to supply power, the hardware combination 3 and the hardware combination 4 use the power supply link 2 to supply power, and under the same power supply link, all the cores and the signal processing circuit share the same voltage value, and the voltage gear is used for representing the voltage value corresponding to the power supply link 1 or 2. It is equally understood that the voltage values corresponding to at least one core and at least one signal processing circuit in the target hardware combination are simultaneously the same in magnitude, and they share one voltage gear.

The clock frequency domain is determined by the division of the hardware clock tree, as shown in fig. 3d, fig. 3d is a schematic diagram of the division of the hardware clock tree according to the embodiment of the present application. In fig. 3d, there are 4 clock frequency inputs of different magnitudes, i.e. there are 4 frequency gears, and the adjustment of the gears can be divided into first gear, second gear, third gear and fourth gear according to their magnitudes from low to high, depending on the control of the multiplexer, the multiplexer has a clock frequency selection function, the input is clocks of different gear frequencies, the output is clocks output after gear selection, and each continuously connected hardware area of the output is a clock frequency domain. In a hardware combination at least one core and at least one signal processing circuit are assigned to different clock frequency domains, each clock frequency domain corresponding to a different or possibly identical frequency range.

It can be seen that, in this example, since at least one core and at least one signal processing circuit in the target hardware combination belong to different clock frequency domains, two different frequency ranges are included in the operating frequency range to represent the frequency sizes corresponding to the two different clock frequency domains, and similarly, the frequency range calculated by the baseband chip also includes two different frequency ranges to represent the frequency sizes corresponding to the two different clock frequency domains. When the frequency shift is adjusted, the shift of the two clock frequency domains is also adjusted separately. Through such refined control, the frequency of the adaptation can be respectively adjusted for the kernel and the signal processing circuit, which is beneficial to saving the power consumption.

In one possible example, after the enabling of the first timer adapted to the task distribution type corresponding to the first signal processing period in which the current system time is located, the baseband chip 310 is further configured to: if a second data task adapting to the target hardware combination 330 is detected within the timing range of the first timer, switching the hardware state of the target hardware combination 330 from the waiting interrupt state to the busy state, and determining a second frequency voltage gear adapting to the load requirement of the second data task; the power management chip 320 is further configured to: and updating the working frequency voltage gear of the target hardware combination 330 from the reference frequency voltage gear to the second frequency voltage gear.

The target hardware combination is in a state of waiting for interruption, so that the working frequency voltage gear can be an initial gear or a gear of a load requirement adapted by a previous task. Before the baseband chip calculates and sends the next adaptive frequency voltage gear vote to the power management chip for gear adjustment, if the current frequency voltage gear of the target hardware combination is in a high gear, the target hardware combination can perform advanced data processing so as to reduce unnecessary waiting time.

Optionally, when the baseband chip finds that the task distribution type corresponding to the signal processing period where the current system time is located is busy when the baseband chip processes data, which means that the baseband chip needs to process more data tasks in the period, the interval between two adjacent data tasks is shorter, so that a timer with a longer timing range is started, so that the data task adapted to the target hardware set can be detected in the timing range of the timer, and subsequent frequency and voltage adjustment and task processing can be performed.

Specifically, as shown in fig. 3b, fig. 3b is a schematic diagram of switching a timer according to an embodiment of the present application, in two periods of time, T0 to T1 and T2 to T3, in a downlink time slot N, since the corresponding hardware combination is busy in processing data in the period of time, the long period timer is enabled to make the hardware combination not enter an idle state with a high probability in the period of time. Therefore, the hardware combination can keep the high-power-consumption gear continuously working all the time, can quickly adjust the gear to meet the load requirement of the next data task, prevents the hardware combination from being reduced in frequency and voltage after entering an idle state, and can generate larger step-up delay when the next data task comes temporarily and the low-power-consumption gear is increased to the high-power-consumption gear, so that the requirement of the communication service on the tight time sequence cannot be met. The timing range a corresponding to the long-period timer needs to be at least larger than the maximum interval between the data tasks so as to ensure that the arrival of the data tasks can be checked without overtime of the timer.

In this example, in the period of busy processing data by the baseband chip, due to objective constraint of hardware implementation, a certain delay time exists in the boosting process, and a certain delay is caused by a larger gear span, so in the signal processing period of high busy processing data by the baseband chip, because the number of data tasks is more and the interval duration of adjacent data tasks is shorter, in order to avoid that the working gear of the target hardware combination falls back to the low-power-consumption gear, a timer with a longer timing range can be started, so that the baseband chip can be kept in the high-gear in the signal processing period of busy processing data in probability, and the power consumption of the data tasks is controlled for a longer time. Therefore, not only can the requirement of a tight time sequence be met, but also the load requirement of a data task can be met as soon as possible, the working efficiency of the electronic equipment is improved, the stability is improved and the time delay is reduced.

In one possible example, in the aspect that the operating frequency voltage gear of the target hardware combination is updated from the reference frequency voltage gear to the second frequency voltage gear, the power management chip 320 is specifically configured to: detecting whether the reference frequency voltage gear is equal to the second frequency voltage gear: if yes, keeping the current working frequency voltage gear of the target hardware combination unchanged; and if not, adjusting the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the second frequency voltage gear.

The reference frequency voltage gear may be an initial gear or a gear adapted to the load requirement of the previous data task, so that the reference frequency voltage gear may be greater than the second frequency voltage gear or may be less than or equal to the second frequency voltage gear, and then the data task may be directly processed without frequency voltage adjustment according to actual situations.

For example, when the voltage gear and the frequency gear in the reference frequency voltage gear are both the third gear and the voltage gear and the frequency gear in the second frequency voltage gear are the second gear, if the reference frequency voltage gear is detected to be different from the second frequency voltage gear, the working frequency voltage gear of the target hardware combination is adjusted, that is, the third gear is adjusted to the second gear. When the voltage gear and the frequency gear in the reference frequency voltage gear are both the third gear and the voltage gear and the frequency gear in the second frequency voltage gear are also the third gear, the reference frequency voltage gear is detected to be the same as the second frequency voltage gear, the gear is not needed, the current gear is kept unchanged, the current gear is used for data processing, and other additional operations are not needed.

In this example, the next step of frequency voltage adjustment action is determined according to the magnitude relation between the reference frequency voltage gear and the second frequency voltage gear, so that the processing of the data task can be started while the reference frequency voltage gear and the second frequency voltage gear are unchanged, delay caused by the change of the gear is avoided, frequency voltage adjustment efficiency is improved, response speed of the user terminal equipment for processing the data task is improved, and user experience is further improved.

In one possible example, in the aspect that the operating frequency voltage range of the target hardware combination is updated from the reference frequency voltage range to the second frequency voltage range, the baseband chip 310 is specifically configured to: acquiring semi-static configuration information of the electronic device 300 and dynamic scheduling information corresponding to the second data task; and determining the second frequency pressure gear according to the dynamic scheduling information and the semi-static configuration information.

The semi-static configuration message includes, but is not limited to, key parameters such as the number of carriers, the number of multiple inputs and outputs of each carrier, bandwidth, subcarrier spacing, etc., which are related parameters of resources allocated to the UE by the base station through interaction with the UE, and the dynamic scheduling information includes related information of the data task scheduling. Because the resource allocation adopts an on-demand allocation mode, each scheduling needs the interaction of scheduling signaling, the control signaling cost is large, the control signaling cost is relatively fixed according to the size of the communication service data packets, and the time intervals among the data packets also meet a certain regularity, so semi-static configuration can be adopted, namely, the transmission or the reception of the service data is carried out on the same time-frequency resource position every fixed period by storing static configuration information. According to the periodically arriving characteristic, one-time authorization period is used, and certain control information is reserved for the dynamically scheduled service for use while PDCCH resources for scheduling indication are saved. The load demand for processing the data task can be calculated by acquiring the semi-static configuration information and the dynamic scheduling information, so that the adaptive frequency and voltage gear can be configured.

In this example, the baseband chip calculates the frequency voltage gear to which the target hardware combination needs to be adjusted by acquiring the semi-static configuration information of the electronic device and the relevant dynamic scheduling information of the received data task, so that the target hardware combination can be ensured to complete the data task in the adaptive gear, waste of redundant power consumption is avoided, and the efficiency of power consumption saving is improved.

It is to be appreciated that the electronic device 300 may include more or fewer structural elements than those described in the above-described block diagrams, including, for example, a power module, physical key, wi-Fi module, speaker, bluetooth module, sensor, etc., without limitation.

It can be seen that in the existing frequency voltage adjustment technology, because the timing range of the timer in the baseband chip is set well and fixed in advance, if the time setting is too short, the frequency voltage requirement of the service which cannot meet the requirement of the tight time sequence can be caused due to the constraint of the boost delay, and if the time setting is too long, the hardware corresponding to the service module can not enter an idle state to perform frequency reduction and voltage reduction, so that the purpose of reducing the power consumption can not be achieved. The application can dynamically adapt the busyness of the baseband chip processing data corresponding to the signal processing time period of the current system time to start the timer, and when the busyness is low, the timer with a short timing range is started to switch to an idle state as soon as possible so as to keep a low-power-consumption gear for a longer time, thereby saving power consumption; when the busyness is high, a timer with a long timing range is started, so that the problem that the target hardware combination is frequently reduced in frequency and increased in voltage, and therefore the tight timing requirement cannot be met is avoided. After the data task is detected subsequently, the baseband chip calculates the frequency voltage gear which is suitable for the load requirement of the data task to determine the gear of the target hardware combination, so that the problems that the power consumption is wasted due to too high gear setting and the data task processing cannot be supported due to too low gear setting are avoided. Through the technical scheme, the busyness of the baseband chip can be dynamically adapted to reduce the hardware power consumption of the whole processing process of the data task, and the energy consumption management efficiency is improved, so that the user experience is improved.

Referring to fig. 4, fig. 4 is a schematic process diagram of a method for adjusting frequency and voltage, which is applied to an electronic device including a baseband chip, a power management chip and a target hardware combination, wherein the target hardware combination includes at least one core and at least one signal processing circuit, and the method includes:

Step 401, detecting a hardware state of a target hardware combination;

the hardware states of the target hardware combination include an idle state, a busy state and a wait for interrupt state.

Step 402, based on determining that the target hardware combination enters a waiting interrupt state, starting a first timer of a task distribution type corresponding to a first signal processing period;

The task distribution type is used for indicating the busyness of the baseband chip processing data in the corresponding signal processing time period, and the task distribution type can be but is not limited to include high busyness and low busyness of the baseband chip processing data; the target hardware combination is any one of a preset hardware set, the hardware set comprises at least one hardware combination divided according to the service type of a data task to be processed by the baseband chip, and a single hardware combination comprises at least one kernel and at least one signal processing circuit, and the hardware in any two hardware combinations is different from each other; the target hardware combination is configured to process data tasks of a target traffic type, the target traffic type being a traffic type pre-configured to the target hardware combination.

Step 403, setting the hardware state of the target hardware combination from the interrupt waiting state to an idle state based on determining that the data task adapting to the target hardware combination is not detected within the timing range of the first timer;

And step 404, based on determining that the hardware state of the target hardware combination is an idle state, updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the idle state frequency voltage gear.

The idle state frequency voltage gear is a low-power consumption gear, and the reference frequency voltage gear is a preset initial gear or a gear which is suitable for the load requirement of the previous data task. The frequency voltage shift includes a frequency shift for setting a frequency of at least one core in the hardware combination and a frequency of at least one signal processing circuit, and a voltage shift for setting a voltage of at least one core in the hardware combination and a voltage of at least one signal processing circuit.

Specifically, step 401, step 402, and step 403 are performed by the baseband chip, and step 404 is performed by the power management chip. Optionally, the power management chip may perform the frequency-reducing and voltage-reducing operation on the target hardware combination by determining by itself that the hardware state of the target hardware combination is in an idle state, and may also perform the frequency-reducing and voltage-reducing operation on the target hardware combination by responding to an instruction sent by the baseband chip to the power management chip.

In one possible embodiment, the method further comprises: switching a hardware state of the target hardware combination from the idle state to a busy state based on determining that a first data task adapting the target hardware combination is detected within the first signal processing period; and based on the first frequency voltage gear which is determined to be suitable for the load demand of the first data task, adjusting the working frequency voltage gear of the target hardware combination from the idle state frequency voltage gear to the first frequency voltage gear.

In one possible embodiment, after the enabling of the first timer adapted to the task distribution type corresponding to the first signal processing period in which the current system time is located, the method further includes: switching a hardware state of the target hardware combination from the wait interrupt state to the busy state based on determining that a second data task adapting to the target hardware combination is detected within a timing range of the first timer; and updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to a second frequency voltage gear based on determining the second frequency voltage gear adapting to the load demand of the second data task.

In this example, in the period of high busyness of the baseband chip to process data, due to objective constraint of hardware implementation, a certain delay time exists in the boosting process, and a certain delay is caused by a larger gear span, so in the signal processing period of high busyness of the baseband chip to process data, because the number of data tasks is large and the interval duration of adjacent data tasks is short, in order to avoid that the working gear of the target hardware combination falls back to the low-power-consumption gear, a timer with a longer timing range can be started, so that the baseband chip can be kept at the high-grade position in the power consumption control of the data tasks for a longer time in the signal processing period of high busyness of the processing data. Therefore, not only can the requirement of a tight time sequence be met, but also the load requirement of a data task can be met as soon as possible, the working efficiency of the electronic equipment is improved, the stability is improved and the time delay is reduced.

It can be seen that in the existing frequency voltage adjusting technology, because the timing range of the timer is set well and fixed in advance, if the time setting is too short, the frequency voltage requirement of the service which cannot meet the requirement of the tight time sequence can be caused due to the constraint of the boost delay, and if the setting is too long, the hardware corresponding to the service module can not enter an idle state to perform frequency reduction and voltage reduction, so that the purpose of reducing the power consumption can not be achieved. The application can dynamically adapt the busyness of the baseband chip processing data corresponding to the signal processing time period to start the timer, and when the busyness is low, the timer with a short timing range is started to switch to an idle state as soon as possible so as to keep a low-power-consumption gear for a long time, thereby saving power consumption; when the busyness is high, a timer with a long timing range is started, so that the problem that the target hardware combination is frequently reduced in frequency and increased in voltage, and therefore the tight timing requirement cannot be met is avoided. After the data task is detected subsequently, the baseband chip calculates the frequency voltage gear which is suitable for the load requirement of the data task to determine the gear of the target hardware combination, so that the problems that the power consumption is wasted due to excessively high gear setting or the data task processing cannot be supported due to excessively low gear setting are avoided. Through the technical scheme, the busyness of the baseband chip for processing data can be dynamically adapted to reduce the hardware power consumption of the whole processing process of the data task, and the energy consumption management efficiency is improved, so that the user experience is improved.

All relevant contents of each scenario related to the above method embodiment may be cited to the functional description of the corresponding device, which is not described herein.

The embodiment of the application provides a frequency voltage adjusting device which can be electronic equipment. Specifically, the frequency voltage adjustment is used for executing the steps executed by the electronic device in the frequency voltage adjustment method. The frequency voltage adjusting device provided by the embodiment of the application can comprise modules corresponding to the corresponding steps.

The embodiment of the application can divide the functional modules of the frequency voltage regulating device according to the method example, for example, each functional module can be divided corresponding to each function, and two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. The division of the modules in the embodiment of the application is schematic, only one logic function is divided, and other division modes can be adopted in actual implementation.

In the case of dividing each functional module by adopting a corresponding function, referring to fig. 5, fig. 5 is a block diagram of functional units of a frequency voltage adjusting device according to an embodiment of the present application, as shown in fig. 5, the frequency voltage adjusting device is applied to an electronic device 300 shown in fig. 3a, and the frequency voltage adjusting device 500 includes: the detection unit 510: a hardware state for detecting the target hardware combination; an enable timer unit 520: the first timer is used for starting a task distribution type corresponding to a first signal processing period based on the fact that the target hardware combination is determined to enter a waiting interrupt state, and the task distribution type is used for indicating the busyness of the baseband chip to process data in the corresponding signal processing period; state switching unit 530: setting a hardware state of the target hardware combination from the wait for interrupt state to an idle state based on determining that no data task adapting the target hardware combination is detected within a timing range of the first timer; frequency voltage update unit 540: and updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the idle state frequency voltage gear based on the fact that the hardware state of the target hardware combination is determined to be the idle state.

In one possible example, the frequency voltage adjusting device 500 is specifically configured to: detecting a first data task adapting to the target hardware combination in the first signal processing period, switching the hardware state of the target hardware combination from the idle state to a busy state, determining a first frequency voltage gear adapting to the load requirement of the first data task, and adjusting the working frequency voltage gear of the target hardware combination from the idle state frequency voltage gear to the first frequency voltage gear.

In one possible example, the idle state frequency voltage gear includes an idle voltage gear and an idle frequency gear, and the first frequency voltage gear includes the first frequency gear and a first voltage gear; in the aspect that the working frequency voltage gear of the target hardware combination is adjusted from the idle frequency voltage gear to the first frequency voltage gear, the frequency voltage updating unit 540 is specifically configured to: adjusting the working voltage gear of the target hardware combination from the idle state voltage gear to the first voltage gear; and adjusting the working frequency gear of the target hardware combination from the idle state frequency gear to the first frequency gear.

In one possible example, the operating frequency range includes a first operating frequency range and a second operating frequency range, the first frequency range includes a first target frequency range and a second target frequency range, the first operating frequency range and the first target frequency range are frequency ranges of a clock frequency domain to which at least one core of the target hardware combination belongs, and the second operating frequency range and the second target frequency range are frequency ranges of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs; in the aspect of adjusting the operating frequency range from the idle frequency range to the first frequency range, the frequency voltage updating unit 540 is specifically configured to: the first operating frequency range of at least one core of the target hardware combination is adjusted from the idle frequency range to the first target frequency range, and the second operating frequency range of at least one signal processing circuit of the target hardware combination is adjusted from the idle frequency range to the second target frequency range.

In one possible example, after the enabling of the first timer adapted to the task distribution type corresponding to the first signal processing period in which the current system time is located, the frequency-voltage adjusting device 500 is specifically configured to: if a second data task adapting to the target hardware combination is detected in the timing range of the first timer, switching the hardware state of the target hardware combination from the waiting interruption state to the busy state, determining a second frequency voltage gear adapting to the load requirement of the second data task, and updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the second frequency voltage gear.

In one possible example, in the aspect that the operating frequency voltage range of the target hardware combination is updated from the reference frequency voltage range to the second frequency voltage range, the frequency voltage updating unit 540 is specifically configured to: detecting whether the reference frequency voltage gear is equal to the second frequency voltage gear: if yes, keeping the current working frequency voltage gear of the target hardware combination unchanged; and if not, adjusting the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the second frequency voltage gear.

In one possible example, in terms of the determining a second frequency voltage gear that adapts to the load demand of the second data task, the state switching unit 530 is specifically configured to: acquiring semi-static configuration information of the electronic equipment and dynamic scheduling information corresponding to the second data task; and determining the second frequency pressure gear according to the dynamic scheduling information and the semi-static configuration information.

It can be seen that, according to the frequency voltage adjusting device provided by the embodiment of the application, the first timer which is adapted to the busy degree of the baseband chip processing the data task in the actual current actual signal processing time period is started by detecting that the target hardware combination enters the waiting interrupt state, and when the data task which is adapted to the target hardware combination is not detected to enter in a timeout, the frequency voltage gear of the target hardware combination is adjusted to be a low-power-consumption gear, so that the minimum power consumption is maintained when the data task is not required to be processed, and the energy saving effect is achieved. For example, the busy degree of the chip processing data in the current time period is low, which means that the interval between tasks is too long, so that a timer with a short timing range can be started, and the target hardware combination can be quickly and timely brought into an idle state to keep low power consumption.

It can be understood that, since the method embodiment and the apparatus embodiment are different presentation forms of the same technical concept, the content of the method embodiment portion in the present application should be synchronously adapted to the apparatus embodiment portion, which is not described herein.

In the case of using integrated units, as shown in fig. 6, fig. 6 is a block diagram showing functional units of another frequency voltage adjusting device according to an embodiment of the present application. In fig. 6, the frequency-voltage adjusting apparatus 600 includes: a processing module 620 and a communication module 610. The processing module 620 is configured to control and manage the actions of the tone adjustment device, for example, performing the steps of the detection unit 510, the enable timer unit 520, the state switching unit 530, and the tone update unit 540, and/or to perform other processes of the techniques described herein. The communication module 610 is used to support interactions between the frequency voltage regulating device and other devices. As shown in fig. 6, the frequency and voltage adjustment device may further include a storage module 630, where the storage module 630 is configured to store program codes and data of the frequency and voltage adjustment device.

The processing module 620 may be a Processor or controller, such as a central processing unit (Central Processing Unit, CPU), a general purpose Processor, a digital signal Processor (DIGITAL SIGNAL Processor, DSP), an ASIC, FPGA or other programmable logic device, transistor logic device, hardware components, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules and circuits described in connection with this disclosure. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The communication module 610 may be a transceiver, an RF circuit, or a communication interface, etc. The storage module 630 may be a memory.

All relevant contents of each scenario related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein. The frequency voltage adjusting apparatus 600 may perform the frequency voltage adjusting method shown in fig. 4.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more sets of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk.

The embodiment of the present application also provides a computer storage medium storing a computer program for electronic data exchange, where the computer program causes a computer to execute some or all of the steps of any one of the methods described in the above method embodiments.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform part or all of the steps of any one of the methods described in the method embodiments above.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may be physically included separately, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: u disk, removable hard disk, magnetic disk, optical disk, volatile memory or nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as external cache memory. By way of example, and not limitation, many forms of random access memory (random access memory, RAM) are available, such as static random access memory (STATIC RAM, SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA RATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DR RAM), among various media that can store program code.

Although the present invention is disclosed above, the present invention is not limited thereto. Variations and modifications, including combinations of the different functions and implementation steps, as well as embodiments of the software and hardware, may be readily apparent to those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. An electronic device comprising a baseband chip, a power management chip, and a target hardware combination, wherein the target hardware combination comprises at least one core and at least one signal processing circuit;

the baseband chip is configured to:

detecting a hardware state of the target hardware combination;

When the data task adapting to the target hardware combination is not detected in the timing range of the first timer, setting the hardware state of the target hardware combination from the interrupt waiting state to an idle state;

the power management chip is configured to:

2. The electronic device of claim 1, wherein the electronic device comprises a memory device,

The baseband chip is further configured to: detecting a first data task adapting to the target hardware combination in the first signal processing period, switching the hardware state of the target hardware combination from the idle state to a busy state, and determining a first frequency voltage gear adapting to the load requirement of the first data task;

The power management chip is further configured to: and adjusting the working frequency voltage gear of the target hardware combination from the idle state frequency voltage gear to the first frequency voltage gear.

3. The electronic device of claim 2, wherein the idle state frequency voltage gear comprises an idle state voltage gear and an idle state frequency gear, and the first frequency voltage gear comprises a first frequency gear and a first voltage gear; in the aspect that the working frequency voltage gear of the target hardware combination is adjusted from the idle state frequency voltage gear to the first frequency voltage gear, the power management chip is specifically configured to:

Adjusting the working voltage gear of the target hardware combination from the idle state voltage gear to the first voltage gear; and adjusting the working frequency gear of the target hardware combination from the idle state frequency gear to the first frequency gear.

4. The electronic device of claim 3, wherein the operating frequency range comprises a first operating frequency range and a second operating frequency range, the first frequency range comprising a first target frequency range and a second target frequency range, the first operating frequency range and the first target frequency range being frequency ranges of a clock frequency domain to which at least one core of the target hardware combination belongs, the second operating frequency range and the second target frequency range being frequency ranges of a clock frequency domain to which at least one signal processing circuit of the target hardware combination belongs; in the aspect that the working frequency gear of the target hardware combination is adjusted from the idle state frequency gear to the first frequency gear, the power management chip is specifically configured to:

The first operating frequency range of at least one core of the target hardware combination is adjusted from the idle frequency range to the first target frequency range, and the second operating frequency range of at least one signal processing circuit of the target hardware combination is adjusted from the idle frequency range to the second target frequency range.

5. The electronic device of claim 1, wherein, after the first timer of the task profile type corresponding to the enabled first signal processing period,

The baseband chip is further configured to: if a second data task adapting to the target hardware combination is detected in the timing range of the first timer, switching the hardware state of the target hardware combination from the waiting interrupt state to a busy state, and determining a second frequency voltage gear adapting to the load requirement of the second data task;

The power management chip is further configured to: and updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the second frequency voltage gear.

6. The electronic device of claim 5, wherein in the aspect that the operating frequency voltage range of the target hardware combination is updated from the reference frequency voltage range to the second frequency voltage range, the power management chip is specifically configured to:

Detecting whether the reference frequency voltage gear is equal to the second frequency voltage gear:

If yes, keeping the current working frequency voltage gear of the target hardware combination unchanged;

and if not, adjusting the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the second frequency voltage gear.

7. The electronic device of claim 5, wherein in the determining a second frequency voltage range that adapts to a load demand of the second data task, the baseband chip is specifically configured to:

Acquiring semi-static configuration information of the electronic equipment and dynamic scheduling information corresponding to the second data task; and determining the second frequency pressure gear according to the dynamic scheduling information and the semi-static configuration information.

8. A method of frequency voltage regulation for use in an electronic device comprising a baseband chip, a power management chip, and a target hardware combination, the target hardware combination comprising at least one core and at least one signal processing circuit, the method comprising:

detecting a hardware state of the target hardware combination;

9. The method of claim 8, wherein the method further comprises:

Switching a hardware state of the target hardware combination from the idle state to a busy state based on determining that a first data task adapting the target hardware combination is detected within the first signal processing period; and

And based on the first frequency voltage gear which is determined to be suitable for the load requirement of the first data task, adjusting the working frequency voltage gear of the target hardware combination from the idle state frequency voltage gear to the first frequency voltage gear.

10. The method of claim 8, wherein after the enabling the first timer of the task profile type corresponding to the first signal processing period, the method further comprises:

Switching the hardware state of the target hardware combination from the wait interrupt state to a busy state based on determining that a second data task adapting to the target hardware combination is detected within the timing range of the first timer; and

And based on the second frequency voltage gear which is determined to be suitable for the load requirement of the second data task, updating the working frequency voltage gear of the target hardware combination from the reference frequency voltage gear to the second frequency voltage gear.