CN112162710A - Method and device for reducing chip power consumption, computer equipment and storage medium - Google Patents
Method and device for reducing chip power consumption, computer equipment and storage medium Download PDFInfo
- Publication number
- CN112162710A CN112162710A CN202011195980.7A CN202011195980A CN112162710A CN 112162710 A CN112162710 A CN 112162710A CN 202011195980 A CN202011195980 A CN 202011195980A CN 112162710 A CN112162710 A CN 112162710A
- Authority
- CN
- China
- Prior art keywords
- power consumption
- state
- command
- entering
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000007787 solid Substances 0.000 claims abstract description 34
- 238000004590 computer program Methods 0.000 claims description 12
- 230000004044 response Effects 0.000 claims description 6
- WFDDMRRZEHUPCP-UHFFFAOYSA-N Nc1ccc(Sc2ccc(Sc3ccc(N)cc3)s2)cc1 Chemical compound Nc1ccc(Sc2ccc(Sc3ccc(N)cc3)s2)cc1 WFDDMRRZEHUPCP-UHFFFAOYSA-N 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The invention discloses a method and a device for reducing chip power consumption, computer equipment and a storage medium, wherein the method comprises the steps that a solid state disk responds to a starting instruction to enter a working state; judging whether a command needs to be processed; if no command needs to be processed, entering an idle state; judging whether a power supply command needs to be processed in an idle state; and if no power supply command needs to be processed, entering a low power consumption state. The invention greatly reduces the power consumption of the solid state disk, and simultaneously reduces the temperature of the solid state disk, thereby reducing the heat effect, not only reducing the power consumption again, but also being beneficial to improving the performance of the solid state disk.
Description
Technical Field
The invention relates to a solid state disk, in particular to a method and a device for reducing chip power consumption, a computer device and a storage medium.
Background
With the use of solid state disks, the performance capacity is higher and higher, the power consumption of the solid state disk is concerned more and more, and the solid state disk with low power consumption and high performance is more and more important. After the traditional solid state disk is started, when no low power consumption command (SF command) set in a power state or no power state switching of an apst (autonomous power state), the solid state disk is actually in an idle state, and in the idle state, the solid state disk is in a high-speed idle state, for example, a DDR does not enter self-refresh, a CPU runs at full speed and does not enter WFI, and an NFC (nand flash controller) interface is in a full-speed state but does not have data operation; although the state lasts for a short time, the state is frequent, and occupies a large amount of time in the whole time period, thereby consuming a large amount of unnecessary power consumption resources.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method, a device, a computer device and a storage medium for reducing chip power consumption.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, a method of reducing power consumption of a chip, the method comprising:
responding to a starting instruction by the solid state disk to enter a working state;
judging whether a command needs to be processed;
if no command needs to be processed, entering an idle state;
judging whether a power supply command needs to be processed in an idle state;
and if no power supply command needs to be processed, entering a low power consumption state.
The further technical scheme is as follows: in the step of judging whether a power command needs to be processed in the idle state, the power command includes a low power consumption command and an APST command.
The further technical scheme is as follows: and when the controller is in the low power consumption state, the unused module clock is closed, the data handling module closes the working clock, the NFC closes the interface clock, the DDR enters automatic refreshing, and the CPU core of the controller enters WFI to wait for command interrupt and awakening.
The further technical scheme is as follows: before the step of entering the low power consumption state, the method further comprises:
judging whether the time for entering the idle state exceeds preset time or not;
and if the preset time is exceeded, executing the step of entering the low power consumption state.
The further technical scheme is as follows: after the step of entering the low power consumption state, the method further comprises:
judging whether a new command is received in a low power consumption state;
if a new command is received, judging whether the new command is a command for entering a lower power consumption state;
if not, the low power state is exited.
In a second aspect, an apparatus for reducing power consumption of a chip includes a response unit, a first determination unit, a first state setting unit, a second determination unit, and a second state setting unit;
the response unit is used for responding to the starting instruction by the solid state disk so as to enter a working state;
the first judging unit is used for judging whether a command needs to be processed;
the first state setting unit is used for entering an idle state;
the second judging unit is used for judging whether a power supply command needs to be processed in an idle state;
and the second state setting unit is used for entering a low power consumption state.
The further technical scheme is as follows: the device also comprises a third judging unit;
and the third judging unit is used for judging whether the time for entering the idle state exceeds the preset time.
The further technical scheme is as follows: the device also comprises a fourth judging unit, a fifth judging unit and a third state setting unit;
the fourth judging unit is used for judging whether a new command is received in a low power consumption state;
the fifth judging unit is configured to judge whether the new command is a command to enter a lower power consumption state;
and the third state setting unit is used for exiting the low power consumption state.
In a third aspect, a computer device comprises a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method steps for reducing power consumption of a chip as described above when executing the computer program.
In a fourth aspect, a storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method steps of reducing chip power consumption as described above.
Compared with the prior art, the invention has the beneficial effects that: in the invention, when the solid state disk is in an idle state for a certain time and no other power supply command is operated, the controller actively enters a special power supply state (low power consumption state): namely, the working clock is closed, the NFC closes the interface clock, the DDR enters automatic refreshing, and the CPU core of the controller enters WFI to wait for command interrupt wakeup; when a new command is received, the solid state disk is awakened again, the state is exited, meanwhile, special processing is carried out on the exit command, the operation flow is reduced, the speed reduction and the clock closing mode when the solid state disk is idle greatly reduce the power consumption of the solid state disk, and meanwhile, the temperature of the solid state disk is reduced, so that the heat effect is reduced, the power consumption is reduced again, and the performance of the solid state disk is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more apparent, the following detailed description will be given of preferred embodiments.
Drawings
FIG. 1 is a flowchart of a method for reducing power consumption of a chip according to an embodiment of the present invention
FIG. 2 is a schematic diagram of an embodiment of an apparatus for reducing power consumption of a chip;
FIG. 3 is a schematic block diagram of a computer device of the present invention.
Detailed Description
In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
The invention provides a method for reducing chip power consumption, which can be applied to a solid state disk, can greatly reduce the power consumption of the solid state disk, reduce the heat effect and is beneficial to improving the performance of the solid state disk. The invention is described below by means of specific examples.
Referring to fig. 1, a method for reducing power consumption of a chip includes the following steps:
s10, responding to the starting instruction by the solid state disk to enter a working state, and executing S20;
s20, judging whether a command needs to be processed, if so, executing the step S202, otherwise, executing the step S201;
s201, entering an idle state, and executing S30;
s202, processing the command;
s30, judging whether a power command needs to be processed in the idle state, if so, executing the step S302, otherwise, executing the step S301;
s301, judging whether the time for entering the idle state exceeds the preset time, if so, executing a step S40, and if not, executing a step S20;
s302, switching the power supply state;
s40, entering a low power consumption state, and executing S50;
s50, judging whether a new command is received in a low power consumption state, if so, executing the step S501, otherwise, executing the step S40;
s501, judging whether the new command is a command for entering a lower power consumption state, if so, executing a step S502, and if not, executing a step S60;
s502, entering a lower power consumption state;
and S60, exiting the low power consumption state.
Specifically, after the solid state disk is started, a command processing command exists, and the solid state disk is in an idle state if no command exists; when the time in the space state exceeds 8ms, and when a low power consumption command or APST set by the power state is still not received, the solid state disk is set to be in a low power consumption state, which is called PS0.5, and in the state, the solid state disk enables the CPU core to enter WFI to wait for the command interrupt to wake up. The DDR enters self-refresh, the clock which is not needed to be used temporarily is closed, the data handling module closes the working clock, and the NFC closes the interface clock. Therefore, the power consumption of the chip main control in the idle state can be greatly reduced; when the chip is in a PS0.5 state, when a command wake-up exit is received, the command is distinguished and processed by judging the type of the command, when the command is a command for entering a lower power consumption state, if the command is called as a PS4 command, the solid state disk does not need to particularly exit the PS0.5 state and re-enters a PS4 state, the solid state disk can directly enter the PS4 state from the PS0.5 state, the whole wake-up exit re-entry process is reduced, a part of power consumption in the use process can also be reduced, and particularly when the solid state disk is in a state with a less busy task and uses a DC power supply, much power consumption can be reduced, so that the power consumption is saved; simultaneously, because the deceleration in idle time also makes the temperature of chip follow and reduces to reduced the fuel factor, also reduced the consumption once more simultaneously, also helped improving the performance of chip.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Referring to fig. 2, the apparatus includes a response unit 1, a first determining unit 2, a first state setting unit 3, a second determining unit 4, a second state setting unit 5, a third determining unit 6, a fourth determining unit 7, a fifth determining unit 8, and a third state setting unit 9;
the response unit 1 is used for responding to a starting instruction by the solid state disk so as to enter a working state;
a first judging unit 2, configured to judge whether there is a command to be processed;
a first state setting unit 3 for entering an idle state;
the second judging unit 4 is used for judging whether a power supply command needs to be processed in an idle state;
and a second state setting unit 5 for entering a low power consumption state.
And a third judging unit 6, configured to judge whether the time for entering the idle state exceeds a preset time.
A fourth judging unit 7 for judging whether a new command is received in a low power consumption state;
a fifth judgment unit 8 for judging whether the new command is a command to enter a lower power consumption state;
and a third state setting unit 9 for exiting the low power consumption state.
As shown in fig. 3, the present invention also provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the method steps for reducing the power consumption of the chip as described above.
The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720, memory, and a network interface 750, which are connected by a system bus 710, where the memory may include non-volatile storage media 730 and internal memory 740.
The non-volatile storage medium 730 may store an operating system 731 and computer programs 732. The computer programs 732, when executed, may cause the processor 720 to perform any of a number of methods for reducing chip power consumption.
The processor 720 is used to provide computing and control capabilities, supporting the operation of the overall computer device 700.
The internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730, and when the computer program 732 is executed by the processor 720, the processor 720 can be caused to perform any method for reducing the power consumption of the chip.
The network interface 750 is used for network communication such as sending assigned tasks and the like. Those skilled in the art will appreciate that the configuration shown in fig. 3 is a block diagram of only a portion of the configuration relevant to the present teachings and is not intended to limit the computing device 700 to which the present teachings may be applied, and that a particular computing device 700 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components. Wherein the processor 720 is configured to execute the program code stored in the memory to perform the following steps:
responding to a starting instruction by the solid state disk to enter a working state;
judging whether a command needs to be processed;
if no command needs to be processed, entering an idle state;
judging whether a power supply command needs to be processed in an idle state;
and if no power supply command needs to be processed, entering a low power consumption state.
The further technical scheme is as follows: in the step of judging whether a power command needs to be processed in the idle state, the power command includes a low power consumption command and an APST command.
The further technical scheme is as follows: and when the controller is in the low power consumption state, the unused module clock is closed, the data handling module closes the working clock, the NFC closes the interface clock, the DDR enters automatic refreshing, and the CPU core of the controller enters WFI to wait for command interrupt and awakening.
The further technical scheme is as follows: before the step of entering the low power consumption state, the method further comprises:
judging whether the time for entering the idle state exceeds preset time or not;
and if the preset time is exceeded, executing the step of entering the low power consumption state.
The further technical scheme is as follows: after the step of entering the low power consumption state, the method further comprises:
judging whether a new command is received in a low power consumption state;
if a new command is received, judging whether the new command is a command for entering a lower power consumption state;
if not, the low power state is exited.
It should be understood that, in the embodiment of the present Application, the Processor 720 may be a Central Processing Unit (CPU), and the Processor 720 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Those skilled in the art will appreciate that the configuration of computer device 700 depicted in FIG. 3 is not intended to be limiting of computer device 700 and may include more or less components than those shown, or some components in combination, or a different arrangement of components.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present invention may be implemented in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional units is merely illustrated, and in practical applications, the above distribution of functions may be performed by different functional units according to needs, that is, the internal structure of the apparatus may be divided into different functional units to perform all or part of the functions described above. Each functional unit in the embodiments may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the application. The specific working processes of the units and modules in the above-mentioned apparatus may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one type of logical function division, and other division manners may be available in actual implementation, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (10)
1. A method for reducing power consumption of a chip, the method comprising:
responding to a starting instruction by the solid state disk to enter a working state;
judging whether a command needs to be processed;
if no command needs to be processed, entering an idle state;
judging whether a power supply command needs to be processed in an idle state;
and if no power supply command needs to be processed, entering a low power consumption state.
2. The method of claim 1, wherein the step of determining whether there is a power command requiring processing in the idle state comprises a low power command and an APST command.
3. The method for reducing chip power consumption according to claim 1, wherein in the low power consumption state, the unused module clock is turned off, the data handling module turns off the working clock, the NFC turns off the interface clock, the DDR enters auto-refresh, and the controller CPU core enters WFI to wait for command interrupt wakeup.
4. The method for reducing power consumption of a chip according to claim 1, wherein the step of entering the low power consumption state is preceded by the steps of:
judging whether the time for entering the idle state exceeds preset time or not;
and if the preset time is exceeded, executing the step of entering the low power consumption state.
5. The method for reducing power consumption of a chip according to claim 1, wherein the step of entering the low power consumption state is followed by further comprising:
judging whether a new command is received in a low power consumption state;
if a new command is received, judging whether the new command is a command for entering a lower power consumption state;
if not, the low power state is exited.
6. The device for reducing the power consumption of the chip is characterized by comprising a response unit, a first judgment unit, a first state setting unit, a second judgment unit and a second state setting unit;
the response unit is used for responding to the starting instruction by the solid state disk so as to enter a working state;
the first judging unit is used for judging whether a command needs to be processed;
the first state setting unit is used for entering an idle state;
the second judging unit is used for judging whether a power supply command needs to be processed in an idle state;
and the second state setting unit is used for entering a low power consumption state.
7. The apparatus for reducing chip power consumption according to claim 6, wherein the apparatus further comprises a third determining unit;
and the third judging unit is used for judging whether the time for entering the idle state exceeds the preset time.
8. The apparatus for reducing chip power consumption according to claim 6, wherein the apparatus further comprises a fourth judging unit, a fifth judging unit and a third state setting unit;
the fourth judging unit is used for judging whether a new command is received in a low power consumption state;
the fifth judging unit is configured to judge whether the new command is a command to enter a lower power consumption state;
and the third state setting unit is used for exiting the low power consumption state.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method steps of reducing chip power consumption according to any one of claims 1 to 5 when executing the computer program.
10. A storage medium storing a computer program comprising program instructions which, when executed by a processor, cause the processor to carry out the method steps of reducing chip power consumption according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011195980.7A CN112162710A (en) | 2020-10-30 | 2020-10-30 | Method and device for reducing chip power consumption, computer equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011195980.7A CN112162710A (en) | 2020-10-30 | 2020-10-30 | Method and device for reducing chip power consumption, computer equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112162710A true CN112162710A (en) | 2021-01-01 |
Family
ID=73865375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011195980.7A Pending CN112162710A (en) | 2020-10-30 | 2020-10-30 | Method and device for reducing chip power consumption, computer equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112162710A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114527861A (en) * | 2022-02-21 | 2022-05-24 | 山东岱微电子有限公司 | Instruction processing method, device, equipment and storage medium |
| CN114779879A (en) * | 2022-05-06 | 2022-07-22 | Oppo广东移动通信有限公司 | Frequency-voltage adjusting method and related device |
| CN115933464A (en) * | 2022-11-23 | 2023-04-07 | 四川天邑康和通信股份有限公司 | Circuit working power consumption control system and method for multi-interface and multi-system complete machine |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100050007A1 (en) * | 2008-08-20 | 2010-02-25 | Shan Jiang | Solid state disk and method of managing power supply thereof and terminal including the same |
| US20130007488A1 (en) * | 2011-06-28 | 2013-01-03 | Jo Myung-Hyun | Power management of a storage device including multiple processing cores |
| US20170336854A1 (en) * | 2014-12-27 | 2017-11-23 | Intel Corporation | Enabling system low power state when compute elements are active |
| US20180121124A1 (en) * | 2016-11-01 | 2018-05-03 | Samsung Electronics Co., Ltd. | Memory device having a plurality of low power states |
| CN108255423A (en) * | 2017-12-28 | 2018-07-06 | 深圳忆联信息系统有限公司 | A kind of method and solid state disk for reducing RAID solid state disk power consumptions |
| CN109814804A (en) * | 2018-12-21 | 2019-05-28 | 创新科存储技术（深圳）有限公司 | A kind of method and apparatus reducing distributed memory system energy consumption |
| CN110716633A (en) * | 2019-09-30 | 2020-01-21 | 深圳忆联信息系统有限公司 | Device and method for coordinately managing SSD power consumption, computer device and storage medium |
| CN111752367A (en) * | 2020-06-12 | 2020-10-09 | 深圳忆联信息系统有限公司 | Method and device for reducing power consumption of solid state disk, computer equipment and storage medium |
| CN111813455A (en) * | 2020-07-08 | 2020-10-23 | 深圳忆联信息系统有限公司 | Low-power-consumption realization method and device of solid state disk, computer equipment and storage medium |
| CN111832088A (en) * | 2020-07-13 | 2020-10-27 | 深圳忆联信息系统有限公司 | Low-power-consumption mode data protection method and device for solid state disk, computer equipment and storage medium |
-
2020
- 2020-10-30 CN CN202011195980.7A patent/CN112162710A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100050007A1 (en) * | 2008-08-20 | 2010-02-25 | Shan Jiang | Solid state disk and method of managing power supply thereof and terminal including the same |
| US20130007488A1 (en) * | 2011-06-28 | 2013-01-03 | Jo Myung-Hyun | Power management of a storage device including multiple processing cores |
| US20170336854A1 (en) * | 2014-12-27 | 2017-11-23 | Intel Corporation | Enabling system low power state when compute elements are active |
| US20180121124A1 (en) * | 2016-11-01 | 2018-05-03 | Samsung Electronics Co., Ltd. | Memory device having a plurality of low power states |
| CN108255423A (en) * | 2017-12-28 | 2018-07-06 | 深圳忆联信息系统有限公司 | A kind of method and solid state disk for reducing RAID solid state disk power consumptions |
| CN109814804A (en) * | 2018-12-21 | 2019-05-28 | 创新科存储技术（深圳）有限公司 | A kind of method and apparatus reducing distributed memory system energy consumption |
| CN110716633A (en) * | 2019-09-30 | 2020-01-21 | 深圳忆联信息系统有限公司 | Device and method for coordinately managing SSD power consumption, computer device and storage medium |
| CN111752367A (en) * | 2020-06-12 | 2020-10-09 | 深圳忆联信息系统有限公司 | Method and device for reducing power consumption of solid state disk, computer equipment and storage medium |
| CN111813455A (en) * | 2020-07-08 | 2020-10-23 | 深圳忆联信息系统有限公司 | Low-power-consumption realization method and device of solid state disk, computer equipment and storage medium |
| CN111832088A (en) * | 2020-07-13 | 2020-10-27 | 深圳忆联信息系统有限公司 | Low-power-consumption mode data protection method and device for solid state disk, computer equipment and storage medium |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114527861A (en) * | 2022-02-21 | 2022-05-24 | 山东岱微电子有限公司 | Instruction processing method, device, equipment and storage medium |
| CN114779879A (en) * | 2022-05-06 | 2022-07-22 | Oppo广东移动通信有限公司 | Frequency-voltage adjusting method and related device |
| CN114779879B (en) * | 2022-05-06 | 2024-04-30 | Oppo广东移动通信有限公司 | Frequency-voltage adjusting method and related device |
| CN115933464A (en) * | 2022-11-23 | 2023-04-07 | 四川天邑康和通信股份有限公司 | Circuit working power consumption control system and method for multi-interface and multi-system complete machine |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112162710A (en) | Method and device for reducing chip power consumption, computer equipment and storage medium | |
| US9015396B2 (en) | Reducing latency in a peripheral component interconnect express link | |
| US8850236B2 (en) | Power gating of cores by an SoC | |
| CN101320289B (en) | A method, system, and apparatus for improving multi-core processor performance | |
| CN109885343A (en) | A kind of controller low-power consumption starting method, apparatus, computer equipment and storage medium | |
| CN110716633B (en) | Device and method for coordinately managing SSD power consumption, computer device and storage medium | |
| WO2008016791A1 (en) | System and method for controlling processor low power states | |
| US20140013140A1 (en) | Information processing apparatus and computer program product | |
| CN111813455B (en) | Low-power-consumption realization method and device of solid state disk, computer equipment and storage medium | |
| US20040250147A1 (en) | Uninterrupted system operation | |
| CN102736928B (en) | Fast wake-up computer system method and computer system | |
| CN101727160B (en) | Method and device for switching working modes of coprocessor system and processor system | |
| CN112346556A (en) | Method, device, computer equipment and medium for improving low power consumption efficiency of chip | |
| CN113791738A (en) | Normalized low-power-consumption processing method and device based on solid state disk and computer equipment | |
| CN111752367B (en) | Method and device for reducing power consumption of solid state disk, computer equipment and storage medium | |
| US9760145B2 (en) | Saving the architectural state of a computing device using sectors | |
| CN111077975B (en) | Method and device for reducing Power State3 Power consumption of SSD, computer equipment and storage medium | |
| CN108804150B (en) | Terminal standby process processing method and terminal | |
| CN103218031A (en) | Electronic device and sleep method | |
| CN112579005A (en) | Method and device for reducing average power consumption of SSD, computer equipment and storage medium | |
| CN104077156B (en) | The restarting systems and its method of programmable CPU | |
| CN106375387B (en) | A kind of control method and system of Cluster Rendering node | |
| KR101285665B1 (en) | multi core system on chip supporting a sleep mode | |
| US20100058089A1 (en) | Memory device having a memory sleep logic and methods therefor | |
| CN111767153B (en) | Resource access method and device and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210101 |
|
| RJ01 | Rejection of invention patent application after publication |