JP5982588B2 - System and method for controlling central processing unit power with guaranteed transient deadlines - Google Patents

Description

Related Applications This application is a continuation-in-part of US patent application Ser. No. 13 / 669,043, filed Nov. 5, 2012, entitled “System and Method for Controlling Central Processing Unit Power with Guaranteed Transient Deadlines”. The above application is a continuation-in-part of US patent application Ser. No. 12 / 944,467, filed Nov. 11, 2010, entitled “System and Method for Controlling Central Processing Unit Power with Guaranteed Transient Deadlines”. The above application claims the benefit of priority over US Provisional Application No. 61 / 286,991, filed December 16, 2009, entitled “System and Method of Dynamically Controlling Power in a Central Processing Unit”. All of these applications are incorporated by reference in their entirety.

CROSS-REFERENCE APPLICATION This application is filed by Rychlik et al., US patent application Ser. No. 12 / 944,140 entitled “System And Method For Controlling Central Processing Unit Power Based On Inferred Workload Parallelism”, Rychlik et al., “System and Method for Controlling Central. No. 12 / 944,202 entitled “Processing Unit Power in a Virtualized System”, US Patent Application No. 12 entitled “System and Method for Asynchronously and Independently Controlling Core Clocks in a Multicore Central Processing Unit” by Rychlik et al. US Patent Application No. 12 / 944,378 entitled “System and Method for Controlling Central Processing Unit Power with Reduced Frequency Oscillations” by Thomson et al., “System and Method for Controlling Central Processing Unit Power With” by Thomson et al. No. 12 / 944,561 entitled “Guaranteed Steady State Deadlines” and “System and Met” by Sur et al. Related to US patent application Ser. No. 12 / 944,564 entitled “hod for Dynamically Controlling a Plurality of Cores in a Multicore Central Processing Unit based on Temperature”, which is incorporated by reference.

  Portable computing devices (PCDs) are everywhere. These devices may include cell phones, personal digital assistants (PDAs), portable game consoles, palmtop computers, and other portable electronic devices. In addition to the main functions of these devices, many include peripheral functions. For example, mobile phones have the main functions of making mobile phones and peripherals such as still cameras, video cameras, global positioning system (GPS) navigation, web browsing, sending and receiving e-mail, sending and receiving text messages, and push-to-talk functions Can include functionality. As the capabilities of such devices increase, so does the computational power or power required to support such capabilities. Furthermore, as computing power increases, there is a growing need to effectively manage one or more processors that provide computing power.

  Therefore, what is needed is an improved method for controlling power within a multi-core CPU.

  The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention, and together with the general description above and the detailed description below, illustrate the invention. Useful to explain the characteristics of

1 is a front view of a first embodiment of a portable computing device (PCD) in a closed state. FIG. FIG. 3 is a front view of the first aspect of the PCD in an opened state. It is a block diagram of the 2nd mode of PCD. It is a block diagram of a processing system. 3 is a flowchart showing a first aspect of a method for dynamically controlling power in a CPU. 12 is a flowchart showing a first part of a second mode of a method for dynamically controlling power in a CPU. 12 is a flowchart showing a second part of the second mode of the method for dynamically controlling power in the multi-core CPU. 6 is an exemplary graph showing CPU frequency controlled with dynamic clock and voltage scaling (DCVS) plotted over time. 3 is an exemplary graph showing effective transient response time for various performance levels. FIG. 6 is a block diagram illustrating logical components and information flow in a computing device that implements a dynamic clock frequency / voltage scaling (DCVS) method to ensure performance guarantees in accordance with various aspects. FIG. 5 is a process flow diagram illustrating an aspect method of generating a performance guarantee. FIG. 5 is a process flow diagram illustrating an aspect method of generating a performance guarantee. A processing core is busy longer than a predetermined length of time that exceeds the time required to complete the pre-calculated, predicted, and / or actual steady state workload of that processing core. FIG. 6 is a process flow diagram illustrating various aspects of a method for ensuring performance guarantees to ensure that they do not stay in a state. A processing core is busy longer than a predetermined length of time that exceeds the time required to complete the pre-calculated, predicted, and / or actual steady state workload of that processing core. FIG. 6 is a process flow diagram illustrating various aspects of a method for ensuring performance guarantees to ensure that they do not stay in a state. FIG. 3 is a component block diagram of a mobile device suitable for use in an aspect. FIG. 3 is a component block diagram of a server device suitable for use in certain aspects. FIG. 2 is a component block diagram of a laptop computing device suitable for use in certain aspects. FIG. 4 is an example DCVS solution that sets per-core performance guarantees for threads or workloads executed in a multi-core system. FIG. 2 is an illustration of an exemplary DCVS solution that sets group-based performance guarantees for threads or workloads executed in a multi-core system. The processors in the multiprocessor system do not stay busy longer than required to complete the pre-computed workload, the predicted workload, and / or the actual steady state workload FIG. 6 is a process flow diagram illustrating an aspect method of performing performance assurance to ensure compliance.

  Various aspects are described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the invention or the claims.

  The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

  As used herein, the term “application” may also include files with executable content, such as object code, scripts, bytecodes, markup language files, and patches. In addition, an “application” as referred to herein may also include files that are not inherently executable, such as documents that may need to be opened, or other data files that need to be accessed.

  The term “content” may also include files with executable content, such as object code, scripts, bytecodes, markup language files, and patches. In addition, “content” as referred to herein may include files that are not inherently executable, such as documents that may need to be opened or other data files that need to be accessed.

  As used herein, the terms “component”, “database”, “module”, “system”, etc., refer to hardware, firmware, a combination of hardware and software, software, and running software. It is intended to refer to a computer-related entity. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components may reside within a process and / or thread of execution, and one component may be localized on one computer and / or distributed across two or more computers . In addition, these components can execute from various computer readable media having various data structures stored thereon. A component is one or more data packets (e.g., from one component that interacts with another component in the local system, distributed system, and / or across a network such as the Internet, by signal Can be communicated by a local process and / or a remote process, such as according to a signal having data).

  Referring initially to FIGS. 1 and 2, an exemplary portable computing device (PCD) is shown and is generally designated 100. As shown, PCD 100 may include a housing 102. The housing 102 can include an upper housing portion 104 and a lower housing portion 106. FIG. 1 shows that the upper housing portion 104 can include a display 108. In certain aspects, the display 108 may be a touch screen display. Upper housing portion 104 may also include a trackball input device 110. Further, as shown in FIG. 1, the upper housing portion 104 can include a power on button 112 and a power off button 114. As shown in FIG. 1, the upper housing portion 104 of the PCD 100 may include a plurality of indicator lights 116 and speakers 118. Each indicator light 116 may be a light emitting diode (LED).

  In certain aspects, the upper housing portion 104 is movable relative to the lower housing portion 106, as shown in FIG. Specifically, the upper housing portion 104 can be slidable relative to the lower housing portion 106. As shown in FIG. 2, the lower housing portion 106 can include a multi-button keyboard 120. In certain embodiments, the multi-button keyboard 120 may be a standard QWERTY keyboard. Multi-button keyboard 120 may appear when upper housing portion 104 is moved relative to lower housing portion 106. FIG. 2 further illustrates that the PCD 100 may include a reset button 122 on the lower housing portion 106.

  Referring to FIG. 3, an exemplary, non-limiting aspect of a portable computing device (PCD) is shown and designated generally as 320. As shown, PCD 320 includes an on-chip system 322 that includes a multi-core CPU 324. The multi-core CPU 324 may include a zeroth core 325, a first core 326, and an Nth core 327.

  As shown in FIG. 3, a display controller 328 and a touch screen controller 330 are coupled to the multi-core CPU 324. On the other hand, a display / touch screen 332 external to the on-chip system 322 is coupled to the display controller 328 and the touch screen controller 330.

  FIG. 3 shows that a video encoder 334, such as a phase inversion line (PAL) encoder, a sequential color memory (SECAM) encoder, or a National Television System Committee (NTSC) encoder, is coupled to the multi-core CPU 324. Show further. Further, a video amplifier 336 is coupled to the video encoder 334 and the display / touch screen 332. Video port 338 is also coupled to video amplifier 336. As shown in FIG. 3, a universal serial bus (USB) controller 340 is coupled to the multi-core CPU 324. A USB port 342 is coupled to the USB controller 340. A memory 344 and a subscriber identity module (SIM) card 346 may also be coupled to the multi-core CPU 324. Further, as shown in FIG. 3, a digital camera 348 may be coupled to the multi-core CPU 324. In the exemplary embodiment, digital camera 348 is a charge coupled device (CCD) camera or a complementary metal oxide semiconductor (CMOS) camera.

  As further shown in FIG. 3, a stereo audio codec 350 may be coupled to the multi-core CPU 324. Moreover, an audio amplifier 352 can be coupled to the stereo audio codec 350. In the exemplary embodiment, first stereo speaker 354 and second stereo speaker 356 are coupled to audio amplifier 352. FIG. 3 shows that a microphone amplifier 358 can also be coupled to the stereo audio codec 350. In addition, a microphone 360 can be coupled to the microphone amplifier 358. In certain aspects, a frequency modulation (FM) radio tuner 362 may be coupled to the stereo audio codec 350. An FM antenna 364 is coupled to the FM radio tuner 362. Further, stereo headphones 366 may be coupled to stereo audio codec 350.

  FIG. 3 further illustrates that a radio frequency (RF) transceiver 368 can be coupled to the multi-core CPU 324. RF switch 370 may be coupled to RF transceiver 368 and RF antenna 372. As shown in FIG. 3, a keypad 374 may be coupled to the multi-core CPU 324. A mono headset 376 with a microphone can also be coupled to the multi-core CPU 324. Further, vibrator device 378 may be coupled to multi-core CPU 324. FIG. 3 also shows that the power source 380 can be coupled to the on-chip system 322. In certain aspects, power source 380 is a direct current (DC) power source that provides power to the various components of PCD 320 that require power. Further, in certain embodiments, the power source is a rechargeable DC battery or a DC power source obtained from an AC-DC converter connected to an alternating current (AC) power source.

  FIG. 3 further illustrates that the PCD 320 may also include a network card 388 that may be used to access a data network, such as a local area network, a personal area network, or any other network. Network card 388 can be a Bluetooth® network card, a WiFi network card, a personal area network (PAN) card, a personal area network ultra-low power technology (PeANUT) network card, or any well known in the art. It can be another network card. Furthermore, the network card 388 may be integrated into the chip, ie, the network card 388 may be a full solution in the chip and not a separate network card 388.

  As shown in FIG. 3, display / touch screen 332, video port 338, USB port 342, camera 348, first stereo speaker 354, second stereo speaker 356, microphone 360, FM antenna 364, stereo headphones 366, RF switch 370, RF antenna 372, keypad 374, mono headset 376, vibrator 378, and power source 380 are external to on-chip system 322.

  In certain aspects, one or more of the method steps described herein may be stored in memory 344 as computer program instructions. These instructions may be executed by multi-core CPU 324 to perform the methods described herein. Further, the multi-core CPU 324, memory 344, or a combination thereof may perform one or more of the method steps described herein to dynamically control the power of each CPU or core within the multi-core CPU 324. It can function as a means.

  Referring to FIG. 4, a processing system is shown and generally designated 400. In certain aspects, the processing system 400 may be incorporated into the PCD 320 described above with respect to FIG. As shown, the processing system 400 may include a multi-core central processing unit (CPU) 402 and a memory 404 connected to the multi-core CPU 402. The multi-core CPU 402 may include a zeroth core 410, a first core 412 and an Nth core 414. The zeroth core 410 may include a zeroth dynamic clock and voltage scaling (DCVS) algorithm 416 running thereon. The first core 412 may include a first DCVS algorithm 417 that is executed thereon. Further, the Nth core 414 may include an Nth DCVS algorithm 418 executed thereon. In certain aspects, each DCVS algorithm 416, 417, 418 may be executed independently on each core 410, 412, 414.

  Further, as shown, the memory 404 can include an operating system 420 stored thereon. The operating system 420 may include a scheduler 422, which may include a first execution queue 424, a second execution queue 426, and an Nth execution queue 428. The memory 404 may also include a first application 430, a second application 432, and an Nth application 434 stored therein.

  In certain aspects, the applications 430, 432, 434 may send one or more tasks 436 to be processed by the cores 410, 412, 414 in the multi-core CPU 402 to the operating system 420. Task 436 may be processed or executed as a single task, thread, or a combination thereof. Further, the scheduler 422 can schedule tasks, threads, or combinations thereof for execution within the multi-core CPU 402. In addition, the scheduler 422 can place tasks, threads, or combinations thereof in the execution queues 424, 426, 428. The cores 410, 412, 414 execute tasks, threads, or combinations thereof, for example, as instructed by the operating system 420 for processing or execution of those tasks and threads in the cores 410, 412, 414. Can be removed from the queues 424, 426, 428.

  FIG. 4 also illustrates that the memory 404 can include a parallel processing monitor 440 stored therein. The parallel processing monitor 440 can be connected to the operating system 420 and the multi-core CPU 402. Specifically, concurrency monitor 440 may be connected to scheduler 422 within operating system 420.

  Referring to FIG. 5, a first aspect of a method for dynamically controlling the power of a central processing unit is shown and is generally designated 500. The method 500 may begin at block 502 with a DO loop in which the following steps may be performed when the device is powered on.

  At block 504, a power controller, such as a dynamic clock and voltage scaling (DCVS) algorithm, can monitor one or more CPUs. At decision 506, the power controller can determine whether the transient performance deadline for the CPU has expired. If not, method 500 may end. Otherwise, if the transient performance has expired, the method 500 can proceed to block 508 and the power controller may move the CPU to a higher performance level, i.e. the next higher operating frequency. it can. In one aspect, the controller can transition the CPU to the maximum performance level, i.e., the maximum CPU frequency. However, in another aspect, the CPU may not move to the maximum performance level. The CPU may move to an intermediate level and then move again to either the maximum level or another higher performance level. The number of intermediate transitions and the length of time between transitions can be used to determine this transition frequency value.

  In block 510, the CPU may enter an idle condition. Further, at block 512, the transient performance deadline may be reset. At block 514, the CPU can exit the idle condition. Moving to decision 516, the power controller can determine whether the reaching CPU frequency is at the maximum CPU frequency. If so, the method 500 can end. Otherwise, if the CPU frequency is not at the maximum CPU frequency, the method can proceed to block 518 and the timer can be rescheduled. The method 500 can then end.

  Referring to FIG. 6, a second aspect of the method for dynamically controlling the power of the central processing unit is shown and is generally designated 600. Beginning at block 602, the central processing unit (CPU) can enter an idle state. At block 604, a power controller, such as a dynamic clock and voltage scaling (DCVS) algorithm, may set an idle start time (StartIdleTime) equal to the current time (CurrentTime). Further, at block 606, the power controller can determine a busy time (BusyTime) by subtracting an idle state start time (StartIdleTime) from an idle state end time (EndIdleTime).

  At block 608, the CPU may enter a software wait (SWFI) condition for interrupt. In block 610, the CPU can exit the SWFI condition. Moving to block 612, the power controller may set an idle end time (EndIdleTime) equal to the current time (CurrentTime). Further, at block 614, the power controller may determine an idle time (IdleTime) by subtracting an idle state start time (StartIdleTime) from an idle state end time (EndIdleTime). In block 616, the power controller may determine the CPU frequency (CPUFreq) that is being reached from the update steady state filter (UpdateSteadyStateFilter), the busy time (BusyTime), and the idle time (IdleTime). Thereafter, the method 600 may continue to block 702 of FIG.

At block 702, the power controller may determine an Effective Transient Budget (EffectiveTransientBudget) using the following equation:
EffectiveTransientBudget = (TransientResponseDeadline × NextCPUFreq) / (NextCPUFreq-CPUFreq)
here,
TransientResponseDeadline = transient response deadline, ie slack budget,
NextCPUFreq = Next CPU frequency that is one step higher than the reaching CPU frequency, and
CPUFreq = CPU frequency being reached (CPUFreq)
It is.

  In certain aspects, clock scheduling overhead (ClockSchedulingOverhead) and clock switch overhead (ClockSwitchOverhead) may also be added to EffectiveTransientBudget. Further, a voltage change overhead (VoltageChangeOverhead) may be added to the EffectiveTransientBudget. Moving to block 704, the power controller may set a deadline to move to a higher frequency (SetJumpToFrequency) equal to the idle end time (EndIdleTime) plus the effective transient budget (EffectiveTransientBudget). In another aspect, the deadline for moving may be the current time plus the transient budget. Thereafter, the method 600 can end.

  In a particular aspect, the method 600 described in conjunction with FIGS. 6 and 7 calculates the length of time that the CPU can stay at the frequency determined by the DCVS until the transient expires, In the future, it can be used to schedule a transition to a higher CPU frequency. If the idle state is reentered before the transition to a higher frequency, the scheduled transition can be canceled. The method 600 can delay the transition to a higher frequency by the length of time determined as EffectiveTransientBudget.

  It should be understood that the method steps described herein do not necessarily have to be performed in the order described. Furthermore, terms such as “after”, “next”, “next” are not intended to limit the order of the steps. These terms are only used to guide the reader through the description of the method steps. Further, the methods described herein are described as being executable on a portable computing device (PCD). The PCD may be a mobile phone device, a personal digital assistant device, a smart book computing device, a netbook computing device, a laptop computing device, a desktop computing device, or a combination thereof.

  In certain aspects, the DCVS algorithm measures CPU load / idle time and dynamically adjusts the CPU clock frequency to follow the workload in an attempt to still provide satisfactory system performance while reducing power consumption. Mechanism. As the workload changes, CPU throughput changes can follow the workload change, but at the same time can inevitably lag behind it. Unfortunately, this can lead to problems when the workload has quality of service (QoS) requirements, because the DCVS algorithm cannot follow the workload quickly enough. In addition, tasks can fail.

  Many DCVS techniques involve measuring the steady state performance requirements of the CPU and setting the CPU frequency and voltage to the lowest level that can meet the steady state CPU usage. This is usually done by measuring CPU utilization (percent busy) over a period of time and setting the CPU performance level to a level where the average CPU utilization is between the high and low thresholds. The averaging period is optimized to maintain a moderate response while minimizing the frequency of changing the clock frequency. In order to respond to transient workloads and / or onset of new workloads, panic inputs were sometimes used to rapidly increase CPU frequency.

  In order to avoid the problem of DCVS lagging the workload and causing task failure, the systems and methods disclosed herein provide transient performance guarantees. Transient performance guarantees can be defined as the maximum length of time that a continuously busy pulse can be delayed when compared to running at a higher performance level. This can be accomplished by moving to a higher performance level before the transient performance expires, and resetting the deadline whenever idle, which means that if the CPU is idle, the CPU This is because, by definition, it is not overloaded. As disclosed herein, timers can be rescheduled to ensure QoS guarantees whenever the system goes out of idle and the system's CPU is not operating at maximum frequency.

  In order to minimize the power impact of transient performance guarantees, the present system and method minimizes the probability that an incoming pulse may require an increase in frequency to meet a deadline. This delays the change in frequency or performance level until the effective transient budget is exhausted, as shown in Figure 8, then moves directly to a higher performance level and stays there until the pulse is complete Can be accomplished.

  In certain aspects, the effective transient budget is calculated as a transient response deadline scaled to the current performance level. For example, if the CPU is operating at 75% of the maximum clock rate and the transient response deadline is 16 ms, the effective transient budget is 64 ms, ie 16 ms / (1-0.75). The effective transient budget represents how long the CPU can operate at the current performance level before the budget is exhausted. When the CPU is idle, the effective transient budget can be the same as the transient response deadline. When at the maximum performance level, the effective transient budget is infinite as shown in FIG.

  Using the methods described herein, the system can provide a strict limit on the maximum length of time that a task can be performed at some level other than the maximum level, so tasks that require QoS guarantees. Allows for dynamic CPU clock scaling while implicitly providing a computable limit to the completion of This limit may be set based on which task is currently being executed, the overall system nature, the design of the DCVS algorithm, or other nature, and if the system is not performing any task with QoS requirements Or if the CPU is running at the maximum clock, it may be completely disabled.

  In certain aspects, the method sets a shorter internal effective deadline instead of moving to the maximum frequency when it expires and moves to one or more intermediate frequencies while simultaneously maximizing QoS. It can be expanded by still ensuring that the CPU is at maximum frequency before the delay is exhausted. Furthermore, the method may substantially ensure that the overall CPU power is reduced simultaneously while maintaining a well-defined transient QoS.

  The systems and methods described herein may utilize expedient sampling. In other words, the present system and method can periodically check for timer expiration. In another aspect, the present systems and methods may not utilize expedient sampling.

  As discussed above, various aspects provide strict and computable limits (eg, performance guarantees) for calculations for task completion. In various aspects, such performance guarantees may include dynamic clock and voltage / frequency scaling (to increase processor performance and / or reduce power consumption on a portable computing device (PCD)). (DCVS) may be implemented as part of a method, PCD is a mobile phone, smartphone, personal multimedia player or mobile multimedia player, personal digital assistant (PDA), laptop computer, tablet computer, smart book, ultrabook , A palmtop computer, a wireless email receiver, a multimedia internet-enabled mobile phone, a wireless game controller, and a memory, programmable processor, or core (collectively “processing core” herein) Saving way operating under battery power such as beneficial, such as similar personal electronic devices, including mobile devices. Further, although the various aspects are particularly useful for portable computing devices and mobile computing devices that operate on battery power, the aspects generally include any computing device that includes a processor and where reduced power consumption is beneficial. (For example, a general purpose computer, a desktop computer, a server, etc.).

In general, the dynamic power (switching power) consumed by a chip is C × V ² × f, where C is the capacitance switched per clock period, V is the voltage, and f is the switching frequency. is there. Thus, as the frequency changes, the dynamic power changes linearly with frequency. Dynamic power can account for approximately two-thirds of the total power consumed by the processor chip. Since the frequency at which the chip operates can be related to the operating voltage, voltage scaling can be done in conjunction with frequency scaling. Since the efficiency of some electronic components, such as voltage regulators, can decrease with increasing temperature, power consumption increases with temperature. Since increasing power usage can increase temperature, increasing voltage or frequency can further increase system power demand. Accordingly, the battery operation duration of a computing device may be improved by reducing the frequency and / or voltage applied to the processor when the computing device processor is idle or lightly loaded. Such a decrease in frequency and / or voltage may be done in real time or “on the fly” via dynamic clock and voltage / frequency scaling (DCVS) methods.

  In general, the DCVS solution monitors the percentage of time the processor is idle (compared to the time the processor is busy) and determines how much frequency / voltage of the processor should be adjusted. Is based on the percentage of time that is idle and / or busy. Monitoring the percentage of time that a processor is idle is a value that indicates how long the processor is executing an idle process or an idle thread (eg, a system idle process) (eg, length of time, number of CPU cycles, etc.) ) May include calculating and / or measuring.

  When the operating system determines that there are no other threads ready to be scheduled on a processor, the idle software application, process, or thread (generically referred to herein as a “thread”) on that processor. ) Can be performed. An idle thread can perform various tasks (eg, wait for an interrupt task, put a task in a wait state, etc.), and each task can include multiple processor operations. When a processor executes an idle thread, it may be said to be “idle”, “idle”, and / or “idle condition”.

  In a multiprocessor system, the operating system (or scheduler, controller, etc.) may maintain one or more idle threads for each processor. Since idle threads remain ready for execution, each processor always has a thread ready for execution. In this manner, whenever a thread releases a processor (eg, because the thread has completed its scheduled task or workload), the operating system (eg, via idle thread availability) A thread that is ready to run on that processor, even when all other threads are complete, waiting for resources, or otherwise not currently ready to run Have.

  As discussed above, the DCVS solution can adjust the frequency and / or voltage of a processor based on the processor workload that may include a steady state workload. The steady state workload may be determined prior to execution time, i.e., prior to the processing core entering a busy or active state, in order to perform operations for promoting the workload. The steady state workload calculates the number of CPU clock periods, the number of operations, the number of instructions, and / or the length of time required to complete a task scheduled on the processing core. , By estimating, or predicting. Each processor may have more than one workload (for example, steady state workload and transient workload), and each processor will complete until all tasks in all workloads are complete It may be required to remain busy, running or active (generally “busy” herein).

  In some situations, the DCVS solution can reduce the processor frequency and / or voltage (ie, processor speed) to achieve power savings without affecting processor performance. For example, when a processor workload includes a task whose execution time is dominated by memory access time, the decrease in frequency may not significantly affect the performance of the processor or the execution time of the task. More often, however, DCVS solutions perform processor performance (eg, the time required to complete a given set of tasks) and power consumption (eg, a given set of tasks) Trade-offs with the characteristics of the amount of battery power consumed at the time. In general, the faster the task is performed, the more power is consumed by the processor in performing the task.

  The DCVS solution may be configured to balance performance and power consumption based on the steady state workload of the processor and the steady state performance requirements. Steady state performance requirements are calculated or measured by calculating or measuring values that indicate how long the processor is busy and / or idle (eg, length of time, number of CPU cycles, etc.) Can be determined by averaging the results of and determining the amount of time / processing required to complete the steady state workload of the processor. Based on these calculations, the DCVS solution calculates while the processor achieves reduced power consumption and an acceptable level of responsiveness (for example, mobile device users may not notice the difference). An upper frequency threshold and a lower frequency threshold can be calculated that can operate to meet the established steady state requirements.

  Often processors are required to process / execute transient workloads, including “bursts of work”, where DCVS solutions were not known in advance and were not considered in steady state or frequency threshold calculations. . A transient workload is any task of work that is not known in advance by the system, including any unit of work that is dynamic, temporary, or causes an unexpected spike in processor workload Or it can be a unit. By way of example, a transient workload may include any or all of the tasks performed by the processor in response to user input, system events, detected environmental conditions, remote procedure calls, and the like. As a further example, a transient workload may be generated when a user touches a portable computing device (PCD) touch screen to initiate a user action, where the PCD (e.g., via interface updates, It must immediately respond to the user action (such as by starting a new action by displaying a new image).

  As mentioned above, transient workloads are continuously stable that the DCVS solution can properly consider in advance (eg, as part of determining the upper and lower thresholds). It is not a state load. As a result, transient workloads may leave the processor busy longer than expected and / or otherwise introduce uncertainty in processor execution time. . Such uncertainties may cause computing devices to allocate processing and system resources inefficiently or inappropriately, and with respect to the overall performance and / or responsiveness of the computing device, Especially when a computing device includes multiple processing cores, it can have a significant impact.

  Current computing devices are often multiprocessor systems that include a system on chip (SoC) and / or multiple processing cores (eg, a processor, a core, etc.). In a multiprocessor system, it is common for a single thread to be processed by a first processing core, then by a second processing core, and then again by a first processing core. It is also common for the result of one thread in the first processing core to cause an action in another thread that executes the second processing core. For example, one or more processing cores may depend on results generated by the currently active processor, and / or until the currently active processor completes its workload and / or It may be required to remain in an idle state or a standby state until the processing of the task is completed. In these situations, each processing core can alternatively enter an idle / wait state waiting for the result of processing from the currently active processor. While these processing cores wait for results generated by the currently active processor, their respective DCVS solutions may slow down operation (ie, via frequency / voltage reduction) and compute The device appears to be unresponsive or slow. That is, the DCVS solution implemented on a multiprocessor computing device is that some of the processing cores should operate at a lower frequency or voltage than is optimal for executing the currently active thread, It may conclude erroneously and the computing device may appear to be unresponsive or slow.

  Various aspects may be longer than a predetermined amount of time that exceeds the time required for a processing core to complete its pre-calculated actual steady state workload (e.g., transient Overcoming the above-mentioned limitations by calculating and adhering performance guarantees that ensure that they do not stay busy (due to a typical workload). Such performance guarantees can resolve operating system, resource, and DCVS resolutions to better estimate, schedule, and / or plan for future operations, such as allocating resources and scheduling threads for execution. Can be used by the law and / or other processing cores. In this manner, performance assurance allows a computing device to meet its responsiveness requirements, thus improving the user experience.

  Performance guarantees allow the DCVS solution to adjust the processor frequency and / or voltage based on the varying delay, which means that the processing core will be able to match the current or previous operating frequency / voltage of the processor. Regardless, it ensures that only a defined maximum amount of work, which is at most, lags behind the steady state workload.

  FIG. 10 illustrates logical components and information flow in an aspect of a computing device 1000 that implements a dynamic clock frequency / voltage scaling (DCVS) method that enforces performance guarantees. The computing device 1000 may include a hardware unit 1002, a kernel space software unit 1004, and a user space software unit 1006. In an aspect, the kernel space software unit 1004 and the user space software unit 1006 may be included in the operating system or kernel of the computing device 1000. For example, a computing device may include a kernel that is organized in user space (if non-privileged code is executed) and in kernel space (if privileged code is executed). This separation requires code that is part of the kernel space to be licensed under the General Public License (GPL), while code that runs in user space is licensed under the GPL. Especially important in Android and other GPL environments where there is no need.

  Hardware unit 1002 includes several processing cores (eg, CPU_0, CPU_1, 2D-GPU_0, 2D-GPU_1, 3D-GPU_0, etc.) and various hardware resources shared by the processing core (eg, clock, power And a resource module 1020 that includes a management integrated circuit or “PMIC”, a scratchpad memory, or “SPM”.

  The kernel space software unit 1004 is a processor module (CPU_0 Idle stats, CPU_1 idle stats, 2D-GPU_0 driver, 2D-GPU_1 driver, 3D-GPU_0 driver, etc.) corresponding to at least one of the processing cores in the hardware unit 1002 Each of which may be in communication with one or more idle state statistics device modules 1008. The kernel space software unit 1004 may further include a timer driver module 1014, an input event module 1010, and a CPU request statistics module 1012. In an aspect, the timer driver module 1014 can drive (or manage) a timer for each processing core.

  User space software unit 1006 receives input from each of idle state statistics device module 1008, input event module 1010, timer driver module 1014, and CPU request statistics module 1012 and / or outputs to CPU frequency hot plug module 1018 The DCVS control module 416 may be included. The CPU frequency hot plug module 1018 may be configured to send a communication signal to the resource module 1020. The CPU frequency hot plug module 1018 further applies voltage / frequency changes to each core independently (eg, one core at a time, in turn, etc.) or simultaneously (eg, at about the same time) Can be configured to.

  The DCVS control module 1016 is suitable for execution on any or all of the processing cores (eg, CPU_0, CPU_1, 2D-GPU_0, 2D-GPU_1, 3D-GPU_0, etc.) and / or on the computing device 1000 May contain threads suitable for implementing a DCVS solution. In an aspect, the DCVS control module 1016 may cause an event that causes the DCVS control module 1016 to collect information from one or more processing cores and perform a DCVS operation on the processing core (e.g., a data buffer full, a timer It may include threads that monitor ports or sockets for the occurrence of timeouts, state transitions, etc.). In an aspect, the DCVS control module 1016 may include a single thread DCVS solution that monitors two or more processing cores. In an aspect, the DCVS control module 1016 may include a DCVS solution thread for each processing core.

  In certain aspects, the DCVS control module 1016 may be configured to generate a pulse train. The DCVS control module 1016 can generate the pulse train by monitoring or sampling the processing core busy and / or idle states (or transitions between these states). The DCVS control module 1016 can also generate a pulse train based on information obtained by monitoring the depth of one or more processor execution queues. An execute queue has the ability to execute in the processing core with the executing thread, but is not yet possible to do so (for example, due to another active thread currently executing, etc.) It may contain a collection of multiple threads. Each processing core may have its own execution queue, or a single execution queue may be shared by multiple processing cores. A thread can be removed from the run queue when it requests to go to sleep, when it is waiting on a resource to become available, or when it is terminated. Thus, the number of threads in the execute queue (ie, the depth of the execute queue) is the number of active threads (including threads that are currently being processed (running) and threads that are waiting to be processed ( For example, the number of waiting, running) can be identified.

  In an aspect, the DCVS control module 1016 may be configured to calculate a steady state workload, a steady state requirement, and / or upper and lower frequency / voltage thresholds based on the generated pulse train. . The upper and lower frequency / voltage thresholds allow the processing core to operate to meet the steady state performance requirements while at the same time achieving reduced power consumption of the computing device 1000 to meet responsiveness requirements, A frequency / voltage range can be defined. Satisfying the responsiveness requirement may include performing all the tasks of the workload so that the user of the computing device 1000 is unaware of the degradation in computing device performance or speed.

  The DCVS control module 1016 monitors the performance of the overall computing device 1000 and / or operates one or more of the processing cores between the established upper and lower frequency thresholds Can be configured to ensure that. The DCVS control module 1016 can adjust the processing resources and / or operating frequencies of the processing cores so that they are as large as the threshold.

  As discussed above, the DCVS control module 1016 can generate a pulse train. In an aspect, the pulse train generated for two or more of the processing cores includes a correlation that includes information suitable for determining whether the processing core is performing operations that are cooperative and / or dependent on each other. To generate a model, they can be synchronized in time and correlated. In one aspect, the DCVS control module 1016 uses a correlation model to determine the upper and lower frequency thresholds, initial operating frequency, steady state requirements, and processor workload, and these values interact with each other between processing cores. Decisions can be made to take into account dependencies.

  In an aspect, the DCVS control module 1016 may be configured to calculate and / or maintain performance guarantees. As mentioned above, the processing core may be required to handle / execute transient workloads that the DCVS solution cannot properly consider in advance. Thus, a transient workload may cause the DCVS control module 1016 to operate one or more of the processing cores at a sub-optimal frequency level or within a sub-optimal frequency range. For example, the DCVS control module 1016 cannot consider transient workloads in advance, so the DCVS control module 1016 allows the processing core to respond to both the steady state and transient workloads of the computing device 1000. It may be inappropriately concluded that it can operate at a lower frequency level than is required to complete during a time period suitable to meet the requirements.

  The performance guarantee is that the processing core will not stay busy longer than a given length of time (eg due to a transient workload) / the processing core to complete the steady state workload requirement. In order to ensure that more processing cores do not work than is required for the computer, it provides the computing device 1000 with strict and computable limits that can be used by the DCVS control module 1016. Performance assurance ensures that the DCVS control module 1016 completes the processing core for both steady state and transient workloads during a time period suitable to meet the responsiveness requirements of the computing device 1000. Makes it possible to

  In various aspects, the performance guarantee is an optional measurement suitable for measuring processor performance or time length, such as length of time, amount of work, number of tasks, number of instructions, number of CPU cycles, etc. Can be calculated, defined and / or include. In various aspects, the performance guarantee may be associated with frequency and / or may be a function of frequency.

  In certain aspects, the performance guarantee may include one or more performance guarantee values. In various aspects, performance guarantee values (eg, deadline values, budget values, jump-to-max values, etc.), such as length of time, amount of work, number of tasks, number of instructions, number of CPU cycles, etc. It can be expressed in any unit of measurement suitable for measuring processor performance or time length.

  In various aspects, the performance guarantee value may be a budget value (eg, slack budget, transient budget, etc.), a deadline value (eg, transient deadline, transient response deadline, performance deadline, etc.), and / or a jump-to-max value. May be included.

  The deadline value is a value that indicates the relative time before which the processing core should complete the processing of the workload and / or the relative frequency that the processing core frequency should be raised thereafter. It may be a value indicating time.

  The budget value is a value that indicates the length of time remaining before the processing core should complete processing the workload and / or after which the processing core frequency should be increased. It's okay.

  The jump-to-max value is a relative value by which the processing core should complete the workload processing before and / or after that the processing core frequency should be raised to the maximum frequency. It may be a value indicating time.

  Performance guarantee values may be related to, associated with, and / or a function of frequency or voltage. For example, each of the budget, deadline, and / or jump-to-max values may be a time value calculated as a function of the operating frequency of the corresponding processing core. Thus, each of these values may be 10 milliseconds when the processing core operates at a frequency of 100 MHz, 20 milliseconds when it operates at a frequency of 200 MHz, and operates at a frequency of 400 MHz. Sometimes it can be 40 milliseconds, and so on. In this manner, the guaranteed performance value can be used by the DCVS solution to implement a variable delay to increase the frequency of the processing core.

  As mentioned above and shown in FIG. 9, the DCVS solution can implement variable delay. Such variable delays indicate that the processing core will only be delayed relative to the steady state workload by a maximum amount of work, regardless of the actual operating frequency of the processing core. ,to be certain. In one aspect, the DCVS solution is a defined maximum amount of work (i.e., the processing core is at a steady state workload equal to the deadline value multiplied by the maximum frequency / voltage of the processing core). Can be delayed). In this manner, performance guarantees are not affected by the DCVS solution adjusting the processing core frequency / voltage based on steady state requirements, or dynamically or “on the fly”.

  In an aspect, the DCVS control module 1016 may cause the corresponding processing core to transition from idle state to busy state, enter busy state (e.g., initiate workload processing), and / or exit idle state (e.g., Each time an idle thread releases the processing core, etc.) may be configured to set a deadline value equal to the budget value.

  In an aspect, the DCVS control module 1016 may cause the corresponding processing core to transition from busy to idle, enter idle (eg, start execution of an idle thread), and / or exit busy (eg, Each time a workload is completed, etc.) each time it can be configured to set or reset an existing deadline value.

  FIGS. 11A-11B illustrate a predetermined length that exceeds the time required for a processing core to complete its pre-calculated, predicted, and / or actual steady state workload. An aspect of a DCVS solution 1100 is shown that generates / calculates a performance guarantee that ensures that it does not stay busy (eg, due to a transient workload, etc.) longer than In various aspects, the operation of the DCVS solution may be performed by a thread executing in a processing core or another processing core. In certain aspects, one or more of the operations of the DCVS solution may be performed by an idle thread that executes on the processing core.

  At block 1102, the DCVS solution may cause the processing core to transition from the idle state to the busy state. In block 1104, the DCVS solution may set the value of the idle state end time parameter (EndIdleTime) equal to the current time value (CurrentTime). Therefore, the idle state end time parameter (EndIdleTime) can store a value indicating the time at which the processing core last exited the idle state.

  In various aspects, the operations of blocks 1102 and 1104 may be performed sequentially, in parallel, and / or in any order. For example, in one aspect, the DCVS solution may set the value of the idle state end time parameter (EndIdleTime) before transitioning the processing core from the idle state to the busy state. In another aspect, the DCVS solution may set the value of the idle state end time parameter (EndIdleTime) after transitioning the processing core from the idle state to the busy state.

  In block 1106, the DCVS solution can monitor the operating frequency or voltage of the processing core and make adjustments as necessary. In block 1108, the DCVS solution may cause the processing core to transition from the busy state to the idle state. In an aspect, the DCVS solution can transition the processing core to an idle state by initiating execution of an idle thread on the processing core. In certain aspects, the DCVS solution may transition the processing core to an idle state after the processing core has completed all tasks associated with all workloads.

  In optional block 1110, the DCVS solution can set or reset the existing deadline value. As discussed above, the deadline value may be a performance guarantee value that is included in or associated with the performance guarantee. Additional details regarding operations for setting, resetting and / or calculating deadline values are provided further below.

  In block 1112, the DCVS solution may set the value of the idle state start time parameter (StartIdleTime) equal to the current time value (CurrentTime). At block 1114, the DCVS solution determines the time when the processing core last exited the previous idle state (which may be represented by the idle state end time parameter “EndIdleTime”) and the time the processing core entered the current idle state ( The value of the busy time parameter (BusyTime) can be set equal to the difference from the idle state start time parameter “StartIdleTime”. Therefore, the busy time parameter (BusyTime) can store a value indicating the length of time that the processing core has been in the busy state most recently.

  At block 1116, the DCVS solution may cause the processing core to perform various idle state operations, such as sleep operations, deep sleep operations, or software wait operations for interrupts. Accordingly, at block 1116, a DCVS solution (eg, via an idle thread, operating system, etc.) may cause the processing core to enter a sleep state, a deep sleep state, a wait state for interrupts, etc.

  At block 1118, the DCVS solution and / or idle thread may receive an interrupt request and / or otherwise determine that the processing core should be transitioned from the current state to the busy state. it can. This is a notification that a task has been scheduled for execution in the processing core and / or that the scheduled task is ready for execution (eg, from the operating system scheduler, controller, etc. ) DCVS solution can be achieved by receiving.

  In block 1120, the DCVS solution may set the value of the idle state end time parameter (EndIdleTime) equal to the current time value (CurrentTime). In block 1122, the DCVS solution may set the value of the idle time parameter (IdleTime) equal to the difference between the value of the StartIdleTime parameter and the value of the EndIdleTime parameter. Therefore, the idle time parameter (IdleTime) can store a value indicating the length of time that the processing core last remained in the idle state.

  In block 1124, the DCVS solution may calculate the operating frequency, frequency range, and / or frequency threshold within which the processing core should operate. In some aspects, the DCVS solution may be the length of time the processing core last stayed in the busy state (eg, BusyTime) and / or the length of time the processing core lasted in the idle state (eg, IdleTime). Based on the frequency or frequency range can be calculated. In an aspect, the DCVS solution may be based on historical information, such as an average (or moving average) of the length of time (eg, over a given period or time frame) that the processor has previously remained busy and / or idle. Based on the operating frequency, the frequency range, and / or the frequency threshold can be calculated. In certain aspects, the DCVS solution can calculate an operating frequency, a frequency range, and / or a frequency threshold based on the pulse train. As discussed above, the pulse train may be generated based on busy and / or idle sampling, transitions between states, execution queue depth, and the like.

  In block 1126, the DCVS solution may calculate or select a deadline value. The deadline value may be a value that indicates a relative time that should be set so that the frequency of the processing core is then raised to either the higher or maximum frequency of the next stage. In various aspects, the deadline value may be based on configuration settings, driver inputs, scheduled task volume and / or type, predicted steady state workload, and / or computing device responsiveness requirements. Can be calculated. The deadline value may be determined based on a static value and / or a dynamic value. For example, deadline values are determined based on static configuration values, or based on the type of task that is scheduled to run on the processing core (for example, streaming 1080p video versus streaming 720p video, etc.) obtain.

  In certain aspects, the deadline value may be inversely proportional to the responsiveness requirement of the computing device (ie, the higher the responsiveness requirement, the shorter the deadline). In one aspect, the deadline value is a time value that is a function of the current operating frequency of the processing core (eg, 10 milliseconds for a 100 MHz frequency, 20 milliseconds for a 200 MHz frequency, 40 milliseconds for a 400 MHz frequency, etc.) It can be.

  At block 1128, the DCVS solution may calculate or select a budget value. The budget value does not exceed the sum of the deadline value and the time determined to be required for the processing core to complete the steady state workload requirement, and the processing core is active or busy. It can be a value indicating the length of time that can remain. In some aspects, the budget value is a time value that is a function of the current operating frequency of the processing core (eg, 10 milliseconds for a 100 MHz frequency, 20 milliseconds for a 200 MHz frequency, 40 milliseconds for a 400 MHz frequency, etc.) It can be.

  In various aspects, the budget value may be calculated based on a deadline value, multiple frequency levels or steps, a maximum processor frequency, a steady state processor frequency, and the like. In certain aspects, the budget value may be an effective transient budget and / or may be calculated via any of the equations discussed above.

  In optional block 1130, the DCVS solution can calculate a jump to max value. The jump-to-max value may be a value indicating a relative time after which the processing core frequency should be set to the maximum processing frequency. In an aspect, the jump-to-max value may be calculated by adding the value of the EndIdleTime parameter and the budget value.

  In block 1132, the DCVS solution may transition the processing core from the idle state to the busy state. In some aspects, as part of block 1132, the DCVS solution may set a deadline value equal to the budget value. In various aspects, the DCVS solution may cause the processing core to transition from an idle state to a busy state, enter an active state or a busy state (eg, start processing a workload), and / or exit an idle state ( Each time (eg, when an idle thread releases a processing core), it may be configured to set a deadline value equal to the budget value.

  FIG. 12 shows that a certain processing core exceeds a predetermined length of time that exceeds the time required to complete the pre-calculated, predicted, and / or actual steady state workload of that processing core. Some aspects of the DCVS solution 1200 are shown to ensure that performance guarantees are met to ensure that they are not too busy (eg, due to the presence of a transient workload). In block 1202, the DCVS solution may calculate a predicted steady state workload based on the scheduled task. In block 1204, the DCVS solution may calculate various performance requirements for the processing core, such as a frequency threshold to meet computing device power consumption and / or responsiveness requirements. Performance requirements (for example, frequency threshold) are based on steady state workload, historical information (for example, how long it has been busy so far), processor characteristics, responsiveness requirements, etc. Can be determined.

  At block 1206, the DCVS solution may calculate and set an initial operating frequency and / or various performance guarantee values (eg, deadline values, budget values, jump-to-max values, etc.). In block 1208, the DCVS solution is used to process the amount of time or work (e.g., CPU cycles, etc.) required for the processing core to complete all the tasks of the steady state workload while meeting various performance requirements. Command).

  At block 1210, the DCVS solution is performed at the calculated initial operating frequency / voltage (or within the calculated threshold) and / or meets various device or system requirements. The processing core can be shifted from the idle state to the busy state. In block 1212, the DCVS solution may monitor the actual workload and / or operating frequency of the processing core and adjust the frequency / voltage as needed (eg, according to a default clock and voltage scaling algorithm). it can. In optional block 1214, the DCVS solution may update the performance guarantee value based on the current operating frequency / voltage of the processing core.

  At decision block 1216, the DCVS solution is used when the processing core is required for the processing core to complete all tasks of the calculated time / work (ie, expected steady state workload). It can be determined whether or not the user has been busy for a longer time than the determined time / amount of work. If the DCVS solution determines that the processing core has not been busy for longer than the calculated time / work (ie, decision step 1216 = “No”), at block 1212 the DCVS solution determines the actual workload. / Continue to monitor the frequency and make adjustments when needed.

  If the DCVS solution determines that the processing core has been busy for longer than the calculated time / work (ie, decision step 1216 = “Yes”), at decision block 1218, the DCVS solution It can be determined whether it has been used up. The DCVS solution is that the processing core is busy when the budget value is equal to 0 and / or for a period of time (measured in either time or work) that is greater than the deadline value plus the calculated time / work. When remaining in the state, it can be determined that the budget has been exhausted.

  If the DCVS solution determines that the budget has not been exhausted (ie, decision step 1218 = “No”), at block 1212 the DCVS solution continues to monitor the actual workload / frequency and when necessary. Adjustments can be made. If the DCVS solution determines that the budget is exhausted (ie, decision step 1218 = “Yes”), at block 1220, the DCVS solution can increase the operating frequency / voltage of the processing core. In an aspect, at block 1220, the DCVS solution may raise the operating frequency / voltage of the processing core to the maximum processor frequency. In an aspect, at block 1220, the DCVS solution may increase the operating frequency / voltage threshold. In an aspect, at block 1220, the DCVS solution may step up the operating frequency / voltage of the processing core.

  FIG. 13 illustrates another aspect of a DCVS solution 1300 that enforces performance guarantees. In blocks 1302-1314, the DCVS solution may perform the same or similar operations as those discussed above with respect to blocks 1202-1214 in FIG. In decision block 1316, the DCVS solution determines the calculated time (i.e., the amount of time determined to be required for the processing core to complete all tasks in the predicted steady state workload). It is possible to determine whether or not the processing core has a high probability of completing the current workload before the time (calculated time + deadline) obtained by adding the deadline value and the deadline value.

  If the DCVS solution determines that the processing core is likely to complete the current workload before the calculated time plus the deadline value (ie, decision step 1316 = “Yes”), at block 1312 The DCVS solution can continue to monitor the actual workload / frequency and make adjustments to the operating frequency / voltage as needed.

  If the DCVS solution determines that the processing core is not likely to complete the current workload before the calculated time value plus the deadline value (ie, decision step 1316 = “No”) In block 1318, the DCVS solution can increase the operating frequency / voltage of the processing core. The operating frequency / voltage of the processing core may be increased to the maximum processor frequency or may be increased in steps.

  Various aspects include a method for improving performance on a computing device having a processor, the method comprising determining a steady state workload of the processor and a determined steady state workload on the processor. Determining the amount of work required to perform the steps, calculating a performance guarantee value for the processor, transitioning the processor from idle to busy, and dynamic clock and voltage scaling operations. Executing and scaling the processor frequency based on the processor's actual workload; updating the performance guarantee value based on the scaled frequency; and the sum of the determined amount of work and the performance guarantee value Determine if the processor stays busy for these periods Step a, determined amount and the sum over a period of performance guaranteed value of work, when the processor is determined to remain busy, may include the step of increasing the frequency of the processor.

  In one aspect, when it is determined that the processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value, the step of increasing the frequency of the processor increases the processor frequency to the maximum processor. Increasing the frequency may be included. In a further aspect, the step of increasing the processor frequency when the processor is determined to remain busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value, A step of raising. In a further aspect, the method further updates the performance guarantee value based on the scaled frequency to determine whether the processor remains busy for a period greater than or equal to the determined amount of work and the performance guarantee value. The step of repeatedly increasing the frequency of the processor when it is determined that the processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value may be included.

  In a further aspect, calculating a performance guarantee value for the processor may include calculating a deadline value. In a further aspect, calculating a performance guarantee value for the processor may include calculating a budget value. In a further aspect, determining the steady state workload of the processor may include determining a requirement for a task that is scheduled to be executed on the processor. In a further aspect, the method may include generating a pulse train by sampling busy and idle state transitions. In a further aspect, the operations of determining the steady state workload of the processor, determining the amount of work required to execute the steady state workload on the processor, and calculating a performance guarantee value for the processor include: It is executed by a single thread. In a further aspect, a single thread is executed on the processor. In a further aspect, the single thread is executed on the second processor of the computing device.

  Further aspects include means for determining a steady state workload of the processor, means for determining the amount of work required to perform the determined steady state workload on the processor, Means for calculating a performance guarantee value for the processor; means for transitioning the processor from idle to busy; and performing dynamic clock and voltage scaling operations to determine the processor based on the actual workload of the processor The processor remains busy for a period that is greater than or equal to the sum of the determined amount of work and the guaranteed performance value. Means for determining whether or not the processor is in a period equal to or greater than the sum of the determined amount of work and the guaranteed performance value. If it is determined that remains in Gee state, and means for increasing the frequency of the processor includes a computing device.

  In one aspect, the means for increasing the processor frequency when the processor is determined to remain busy for a period equal to or greater than the sum of the determined amount of work and the guaranteed performance value, Means may be included to increase the processor frequency.

  In a further aspect, the means for increasing the processor frequency when the processor is determined to remain busy for a period greater than or equal to the sum of the determined amount of work and the performance guarantee value, Means may be included. In a further aspect, the computing device further updates the performance guarantee value based on the scaled frequency to determine whether the processor remains busy for a period greater than or equal to the determined amount of work and the performance guarantee value. Including means for repeatedly performing an operation of increasing the frequency of the processor when it is determined that the processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value. obtain.

  In a further aspect, the means for calculating a performance guarantee value for the processor may include means for calculating a deadline value. In a further aspect, the means for calculating a performance guarantee value for the processor may include means for calculating a budget value. In a further aspect, the means for determining the steady state workload of the processor may include means for determining the requirements of a task that is scheduled to be executed on the processor. In a further aspect, the computing device may include means for generating a pulse train by sampling busy and idle state transitions.

  In a further aspect, the computing device determines the steady state workload of the processor, determines the amount of work required to execute the steady state workload on the processor, and provides a performance guarantee value for the processor. Means may be included for performing the calculating operation via a single thread. In a further aspect, the computing device may include means for executing a single thread on the processor. In a further aspect, the computing device may include means for executing a single thread on the second processor of the computing device.

  Further aspects include a computing device that can include a processor configured with processor-executable instructions to perform operations, which can include a first processor configured with processor-executable instructions to perform operations, This operation comprises the steps of determining a steady state workload of the second processor and determining the amount of work required to perform the determined steady state workload on the second processor. Calculating a performance guarantee value for the second processor; transitioning the second processor from idle to busy; and performing dynamic clock and voltage scaling operations to Scaling the frequency of the second processor based on the workload of Updating the performance guarantee value based on the determined frequency, determining whether the second processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value; Increasing the frequency of the second processor when it is determined that the second processor remains busy for a period equal to or greater than the sum of the amount of work done and the performance guarantee value.

  In one aspect, the step of increasing the frequency of the second processor when it is determined that the second processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value. The first processor may be configured with processor-executable instructions so as to include increasing the frequency of the two processors to the maximum processor frequency.

  In a further aspect, the step of increasing the frequency of the second processor when it is determined that the second processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value, The first processor may be configured with processor-executable instructions so as to include increasing the frequency of the two processors in stages.

  In a further aspect, the performance guarantee value is updated based on the scaled frequency to determine whether the second processor remains busy for a time period greater than or equal to the determined amount of work and the performance guarantee value; When it is determined that the second processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value, the operation of increasing the frequency of the second processor is repeatedly executed. The first processor may be further configured with processor executable instructions. In a further aspect, the first processor may be configured with processor-executable instructions such that calculating a performance guarantee value for the second processor may include calculating a deadline value.

  In a further aspect, the first processor may be configured with processor-executable instructions such that calculating a performance guarantee value for the second processor may include calculating a budget value. In a further aspect, the first processor such that determining the steady state workload of the second processor may include determining the requirements of a task that is scheduled to execute on the second processor. May be configured with processor-executable instructions. In a further aspect, the first processor may be configured with processor-executable instructions to perform an operation that further includes generating a pulse train by sampling busy and idle state transitions.

  In a further aspect, determining the steady state workload of the second processor, determining the amount of work required to execute the steady state workload on the second processor, and for the second processor The first processor may be configured with processor-executable instructions so that the operation of calculating the performance guarantee value is performed by a single thread. In a further aspect, the first processor can be configured with processor-executable instructions such that a single thread can be executed on the first processor. In a further aspect, determining the steady state workload of the second processor, determining the amount of work required to execute the steady state workload on the second processor, and for the second processor The first processor may be configured with processor-executable instructions such that performing the operation of calculating a performance guarantee value may include executing a single thread on the second processor.

  A further aspect includes a non-transitory server-readable storage medium storing processor-executable instructions configured to cause a computing device to perform an operation, the operation comprising a steady state workload of a second processor Determining the amount of work required to execute the determined steady state workload on the second processor, and calculating a performance guarantee value for the second processor Transitioning the second processor from idle to busy and performing dynamic clock and voltage scaling operations to scale the frequency of the second processor based on the actual workload of the second processor Step, updating the performance guarantee value based on the scaled frequency, and the amount of work determined Determining whether the second processor remains busy for a period equal to or greater than the total guaranteed performance, and the second processor is busy for a period equal to or greater than the determined amount of work and the total guaranteed performance Increasing the frequency of the second processor when it is determined that the second processor remains.

  In one aspect, the step of increasing the frequency of the second processor when it is determined that the second processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value. Stored processor executable software instructions may be configured to cause the processor to perform an operation so as to include raising the frequency of the two processors to the maximum processor frequency.

  In a further aspect, the step of increasing the frequency of the second processor when it is determined that the second processor remains busy for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value, Step up the frequency of the two processors and update the performance guarantee value based on the scaled frequency, and the second processor is busy for a period equal to or greater than the determined amount of work plus the performance guarantee value The frequency of the second processor when it is determined that the second processor remains busy for a period equal to or greater than the sum of the determined amount of work and the guaranteed performance value. Stored processor-executable software instructions are configured to cause the second processor to perform the operations so that the operations can be repeatedly performed. obtain.

  In a further aspect, the stored processor executable software instructions may be configured to cause the processor to perform an operation such that the step of calculating a performance guarantee value for the second processor may include calculating a deadline value. . In a further aspect, stored processor-executable software instructions may be configured to cause the processor to perform an operation such that calculating a performance guarantee value for the second processor may include calculating a budget value. . In a further aspect, operating the processor such that determining the steady state workload of the second processor can include determining the requirements of a task scheduled to execute on the second processor. Stored processor-executable software instructions may be configured to execute. In a further aspect, stored processor-executable software instructions may be configured to cause the processor to perform an operation that further includes generating a pulse train by sampling busy and idle state transitions.

  In a further aspect, determining the steady state workload of the second processor, determining the amount of work required to execute the steady state workload on the second processor, and for the second processor Stored processor-executable software instructions may be configured to cause a processor to perform an operation such that an operation that calculates a performance guarantee value is performed by a single thread. In a further aspect, stored processor-executable software instructions may be configured to cause the processor to perform an operation such that a single thread is executed on the processor. In a further aspect, stored processor-executable software instructions may be configured to cause a processor to perform an operation such that a single thread is executed on a second processor.

  Various aspects provide numerous advantages and may be implemented in laptops and other mobile devices where performance, power consumption, and / or responsiveness are important. Various aspects may be implemented in servers and personal computers to reduce energy and cooling costs for lightly loaded machines. Reducing heat generation allows the cooling fans of the system to be slowed down or stopped, reducing noise levels and further reducing power consumption. Various aspects can also be used to reduce heat in under-cooled systems when the temperature reaches a certain threshold.

  Although various aspects have been described above for purposes of illustration with respect to a processing core, the method, system, and executable instructions of the aspects are implemented in any system that allows the method to recognize and control frequency or voltage. Can be done. Further, the operation of scaling the frequency or voltage can be performed on any single processor system or multiprocessor system.

  Various aspects may be implemented on various portable or mobile computing devices, an example of which is shown in FIG. Portable computing device 1400 may include a processing core 1401 coupled to memory 1402 and transceiver 1405. A transceiver 1405 may be coupled to the antenna 1404 for transmitting and receiving electromagnetic radiation. The portable computing device 1400 may also include a display 1403 (eg, a touch screen display) and menu selection buttons or rocker switches 1406 for receiving user input. In some portable computing devices, multiple processors 1401 may be provided, such as one processor dedicated to wireless communication functions and one processor dedicated to running other applications.

  Various aspects may also be implemented on any of various commercially available server devices, such as server 1500 shown in FIG. Such a server 1500 typically includes a processing core 1501, and may include a plurality of processor systems 1511, 1521, 1531, one or more of the processor systems being a multi-core processor or including a multi-core processor. Sometimes. Processing core 1501 may be coupled to volatile memory 1502 and mass nonvolatile memory such as disk drive 1503. Server 1500 may also include a floppy disk drive, compact disk (CD) or DVD disk drive 1506 coupled to processing core 1501. Server 1500 may also include a network access port 1504 coupled to processing core 1501 for establishing a data connection with network 1505, such as a local area network coupled to other broadcast system computers and servers.

  The aspects described above may also be implemented in various personal computing devices such as the laptop computer 1600 shown in FIG. The laptop computer 1600 may include a processing core 1601 coupled to a volatile memory 1602 and a high-capacity non-volatile memory such as a flash memory disk drive 1604. Computer 1600 may also include a floppy disk drive 1606 and a compact disk (CD) drive 1608 coupled to processing core 1601. The computing device 1600 also provides data connections, such as USB, FireWire®, or Lightning® connector sockets, or other network connection circuitry for coupling the processing core 1601 to a network or computer. It may include several connector ports coupled to the processing core 1601 for establishing or accepting external memory devices. In a notebook configuration, the computer housing includes a touch pad 1616, a keyboard 1618, and a display 1620, all coupled to a processing core 1601. Other configurations of the computing device may include a computer mouse or trackball coupled to the processor (eg, via a USB input), as is well known.

  Processing cores 1401, 1501, 1601 can be any programmable processor, microprocessor that can be configured by software instructions (applications) to perform various functions, including the various aspects of functions and operations described herein. A microcomputer, a multi-core processor, or a multi-processor chip. Typically, software applications can be stored in internal memory 1402, 1502, 1602 before being accessed and loaded into processing cores 1401, 1501, 1601. Each processing core 1401, 1501, 1601 may include internal memory sufficient to store application software instructions. In some computing devices, additional memory chips (eg, Secure Data (SD) cards) may be plugged into the computing device and coupled to the processing cores 1401, 1501, 1601. Internal memory 1402, 1502, 1602 can be volatile memory, or non-volatile memory such as flash memory, or a mixture of both. As used herein, a general reference to memory is any memory accessible by processing cores 1401, 1501, 1601, including internal memory 1402, removable memory plugged into the mobile device, and memory within processing core 1401. Point to.

  Processing cores 1401, 1501, 1610 may include internal memory sufficient to store application software instructions. In many devices, the internal memory can be volatile memory, or non-volatile memory such as flash memory, or a mixture of both. As used herein, general references to memory are accessible by the processors 1401, 1501, 1610, including internal memory or removable memory plugged into the device and memory within the processing cores 1401, 1501, 1610 themselves Points to a good memory.

  Performance guarantees designed for a single processing CPU typically do not consider thread migration across multiple CPUs. Thus, when transitioning threads from one CPU to another CPU in the operating system scheduler, the transient timer may be restarted on the next CPU, which can cause an undesirable degradation in performance. Thus, in a multi-core processor system that implements a DCVS solution with per-core performance guarantees (eg, transition deadlines), this DCVS solution allows the operating system scheduler to move threads from one core to another. May not be considered, in which case the transient deadline value may or may not be reached when intended. This may prevent the system performance level (eg, CPU frequency, frequency threshold, etc.) from being adequately or sufficiently increased, which may cause the system to meet performance requirements (eg, computing device power consumption and / or responsiveness). May not be properly met.

  Various aspects may include systems, devices, and methods that use transient deadlines within a group of cores so that the initiation of the transient deadline is not affected when the scheduler moves threads between cores within the group. . In these aspects, the transition deadline is still exceeded and the performance level of all CPUs in the group is the workload from the first processing core (eg, CPU0) to the second processing core (eg, CPU1). Raised to meet performance requirements when moved. As a result, these aspects help ensure that well-defined transient QoS is maintained in multiprocessor systems, even while the operating system scheduler moves threads between processing cores. .

  FIG. 17 illustrates an exemplary DCVS solution method 1700 for setting per-core performance guarantees (eg, transient deadlines) for threads or workloads 1702 executing in a multi-core system. In the example shown in FIG. 17, the workload 1702 is assigned a 20 ms transient deadline 1704 on the first processing core (CPU0) when execution begins on the first processing core (CPU0). This is accomplished by setting a transient timer associated with the first processing core (CPU0) to expire 20ms after workload 1702 begins execution, or 20ms after the overall execution time. Can be done.

  After 10ms of the overall execution time, the operating system scheduler moves the workload 1702 from the first processing core (CPU0) to the second processing core (CPU1), and the workload 1702 is transferred to the second processing core ( A new 20ms transition deadline 1706 is assigned on CPU1). This is a transient timer associated with the second processing core (CPU1) so that it expires 20ms after the workload 1702 is moved to the second processing core (CPU1) or 30ms after the overall execution time Can be achieved by setting

  The DCVS solution shown in FIG. 17 sets performance guarantees (eg, transient deadlines) for each core individually (ie, this method uses per-core performance guarantees), so workload 1702 is: The transient deadline 20 ms after the overall execution time that may have been originally intended for the workload 1702 is not reached or reached. As a result, this DCVS solution fails to adequately or sufficiently increase the performance level (eg, CPU frequency) of the processing core (eg, CPU1), which will cause the system to meet performance or power consumption requirements. May not be met.

  FIG. 18 shows an aspect DC800 solution method 1800 of setting group-based performance guarantees for threads or workloads 1702 executing in a multi-core system. In the example shown in FIG. 17, the workload 1702 is assigned to a processing group that includes a first processing core and a second processing core (CPU0 and CPU1) when execution begins on the first processing core (CPU0). In contrast, a 20 ms transition deadline 1804 is assigned. This is associated with both the first and second processing cores (CPU0 and CPU1) so that they expire 20ms after workload 1702 begins execution or 20ms after the overall execution time Can be achieved by setting a transient timer to be set. Workload 1702 is moved from the first processing core (CPU0) to the second processing core (CPU1) by the operating system scheduler, and workload 1702 is still being driven by the 20ms transient deadline 1804 set for the group. Be bound.

  FIG. 19 illustrates a method 1900 of one aspect of a DCVS solution that sets and enforces group-based performance guarantees in a multiprocessor system. At block 1902, the DCVS solution may calculate a predicted steady state workload based on the scheduled task. In block 1904, the DCVS solution may calculate various performance requirements for the processing core, such as a frequency threshold to meet computing device power consumption and / or responsiveness requirements. Performance requirements (for example, frequency threshold) are based on steady state workload, historical information (for example, how long it has been busy so far), processor characteristics, responsiveness requirements, etc. Can be determined.

  In block 1906, the DCVS solution calculates a performance guarantee value (eg, deadline value, budget value, jump-to-max value, etc.) for a processing group that includes a first processing core and a second processing core. can do. In an aspect, at block 1906, the DCVS solution calculates a performance guarantee value for the first processing core and calculates the calculated value to a group that includes both the first processing core and the second processing core. Can be assigned. In another aspect, at block 1906, the DCVS solution calculates a performance guarantee value for the combination of the first processing core and the second processing core, and both the first processing core and the second processing core. A calculated value can be assigned to a group containing.

  In block 1908, the DCVS solution resolves the various performance requirements and the amount of time or work required for the first processing core to complete all the tasks of the steady state workload (e.g., CPU cycles, instructions, etc.) can be calculated. In block 1910, the DCVS solution is performed at the initial operating frequency / voltage at which the first processing core is calculated (or within the calculated threshold) and / or meets various device or system requirements. Thus, the first processing core can be shifted from the idle state to the busy state. In block 1912, the DCVS solution monitors the actual workload and / or operating frequency of the first processing core and adjusts the frequency / voltage as needed (eg, according to default clock and voltage scaling algorithms). can do. In optional block 1914, the DCVS solution may update the performance guarantee value for the group based on the current operating frequency / voltage of the first processing core.

  At decision block 1916, the DCVS solution causes the first processor and the second processor to process the determined amount of work (i.e., the predicted steady state workload to complete all tasks). The amount of time / work determined to be required) and the performance guarantee value or more, for a combined period of time, whether the expected steady state workload or thread remains busy Can be determined. If the DCVS solution determines that the processing core has not been busy longer than the calculated time / work (ie, decision block 1916 = “No”), in block 1912 the DCVS solution / Continue to monitor the frequency and make adjustments when needed.

  The first processor and the second processor remain busy (eg, with respect to an expected steady state workload or thread) for a combined period that is greater than or equal to the determined amount of work plus the guaranteed performance value If the DCVS solution determines (ie, decision step 1916 = “Yes”), at block 1918, the DCVS solution increases the operating frequency / voltage of the first processing core or the second processing core. be able to. In various embodiments, the operating frequency / voltage of the first processing core or the second processing core may be increased to the maximum processor frequency or may be increased in stages.

  Various aspects include a method for improving performance on a computing device having a plurality of processors, the method comprising: determining a steady state workload of a first processor; and Determining the amount of work required to execute the determined steady state workload, calculating a performance guarantee value for a processing group including the first processor and the second processor, and idle Transitioning the first processor from state to busy; performing dynamic clock and voltage scaling operations to scale the frequency of the first processor based on the actual workload of the first processor; The combined period, which is equal to or greater than the sum of the determined amount of work and the performance guarantee value, The first processor and the second processor are busy for a combined period that is greater than or equal to the sum of the determined amount of work and the performance guarantee value. Increasing the frequency of one of the first processor and the second processor when it is determined to remain in the state.

  Further aspects may include a computing device having one or more processors configured with processor-executable instructions to perform various operations corresponding to the methods discussed above.

  Further aspects may include a computing device having various means for performing functions corresponding to the method operations discussed above.

  Further aspects may include a non-transitory processor-readable storage medium storing processor-executable instructions configured to cause a processor to perform various operations corresponding to the method operations discussed above.

  The above method descriptions and process flow diagrams are provided merely as illustrative examples and do not require or imply that the steps of the various aspects must be performed in the order presented. . As will be appreciated by those skilled in the art, the order of the steps in the above aspects may be performed in any order. Words such as “after”, “next”, “next” do not limit the order of the steps, and these words are simply used to guide the reader through the description of the method. Further, any reference to a claim element in the singular form using the article “a”, “an” or “the” should not be construed as limiting the element to the singular.

  The various exemplary logic blocks, modules, circuits, and algorithm steps described with respect to aspects disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in a variety of ways for each specific application, but such implementation decisions should be construed as causing deviations from the scope of the invention. is not.

  The hardware used to implement the various exemplary logic, logic blocks, modules, and circuits described with respect to the aspects disclosed herein includes general purpose processors, digital signal processors (DSPs), and specific applications. Designed to perform integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, individual gate or transistor logic, individual hardware components, or the functions described herein Any combination of these may be implemented or implemented. A general purpose processor may be multiple processors, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, eg, a DSP and multiprocessor combination, multiple processors, one or more multiprocessors in conjunction with a DSP core, or any other such configuration. obtain. Alternatively, some steps or methods may be performed by circuitry that is specific to a given function.

  In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more processor-executable instructions or code on a non-transitory computer-readable storage medium. The steps of the method or algorithm disclosed herein may be embodied in a processor-executable software module that may reside on a tangible or non-transitory computer readable storage medium. A non-transitory computer readable storage medium may be any available storage medium that can be accessed by a computer. By way of example, and not limitation, such computer readable media can be in the form of RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage device, or instructions or data structures. Any other medium that can be used to carry or store the desired program code and that can be accessed by the computer can be included. As used herein, a disk and a disc are a compact disc (“CD”), a laser disc (registered trademark), an optical disc, a digital versatile disc. (disc) (“DVD”), floppy disk, and Blu-ray disc, which normally plays data magnetically, and the disc is optically lasered To play data. Combinations of the above may also be included within the scope of non-transitory computer readable media. Further, the operation of the method or algorithm may be incorporated into a computer program product, one or any combination of code and / or instructions on a non-transitory machine-readable medium and / or non-transitory computer-readable medium, or It can exist as that set.

  The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the spirit or scope of the invention. obtain. Accordingly, the present invention is not intended to be limited to the embodiments shown herein but provides the broadest scope consistent with the following claims and the principles and novel features disclosed herein. Should be done.

100 portable computing devices
102 housing
104 Upper housing part
108 display
110 trackball input device
112 Power on button
114 Power off button
116 Indicator light
118 Speaker
120 multi-button keyboard
122 Reset button
320 portable computing devices
322 On-chip system
324 multi-core CPU
325 0th core
326 1st core
327 Nth core
328 display controller
330 touch screen controller
332 Display / Touchscreen
334 video encoder
336 video amplifier
338 video port
340 USB controller
342 USB
344 memory
346 SIM card
348 CCD / CMOS camera
350 stereo audio codec
352 audio amplifier
354 Stereo Speaker
356 Stereo Speaker
358 Microphone Amplifier
360 microphone
362 FM tuner
364 FM antenna
366 stereo headphones
368 RF transceiver
370 RF switch
372 RF antenna
374 keypad
Mono headset with 376 microphone
378 Vibrator
380 power supply
388 Network Card
400 treatment system
402 multi-core CPU
404 memory
410 0th core
412 1st core
414 Nth core
416 0th DCVS
417 1st DCVS
418th N DCVS
420 operating system
422 Scheduler
424 1st execution queue
426 Second execute queue
428th Nth execution queue
430 First application
432 Second application
434 Nth Application
436 tasks / threads
440 parallel processing monitor
500 methods
600 methods
1000 computing devices
1002 hardware
1004 software
1006 software
1008 Idle state statistics device
1010 Input event
1012 CPU request statistics
1014 Timer driver
1016 DCVS control module
1018 CPU frequency hot plug
1020 clock, PMIC, SPM
1100 method
1200 methods
1300 method
1400 portable computing devices
1401 multiple processors
1402 memory
1403 display
1404 Antenna
1405 transceiver
1406 Menu selection button or rocker switch
1500 servers
1501 processing core
1502 volatile memory
1503 disk drive
1504 Network access port
1505 network
1506 CD or DVD disc drive
1511 multiprocessor system
1521 multiprocessor system
1531 multiprocessor system
1600 laptop computer
1601 processing core
1602 volatile memory
1604 disk drive
1606 floppy disk drive
1608 CD drive
1610 processing core
1616 touchpad
1618 keyboard
1620 display
1700 method
1704 20ms transition deadline
1706 20ms transition deadline
1800 method
1804 20ms transition deadline
1900 method

Claims (40)

A method for improving performance on a computing device having multiple processors, comprising:
Determining a steady state workload of the first processor;
Determining the amount of work required to execute the determined steady state workload on the first processor;
Calculating a performance guarantee value for a processing group including the first processor and the second processor;
Transitioning the first processor from an idle state to a busy state;
Performing a dynamic clock and voltage scaling operation to scale the frequency of the first processor based on the actual workload of the first processor;
Determining whether the first processor and the second processor remain in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value;
When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Increasing the frequency of one of the first processor and the second processor. When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Raising the frequency of one of the first processor and the second processor;
The method of claim 1, comprising raising the frequency of the first processor or the second processor to a maximum processor frequency. When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Increasing the frequency of one of the first processor and the second processor includes gradually increasing the frequency of the first processor or the second processor;
Updating the performance guarantee value based on the scaled frequency;
Determining whether the first processor and the second processor remain in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value;
When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, The method of claim 1, further comprising the step of repeatedly performing an operation of increasing the frequency of one of the first processor and the second processor.   The method of claim 1, wherein calculating the performance guarantee value for the processing group that includes the first processor and the second processor comprises calculating a deadline value.   The method of claim 1, wherein calculating the performance guarantee value for the processing group including the first processor and the second processor comprises calculating a budget value.   Calculating the performance guarantee value for the processing group including the first processor and the second processor determining a requirement of a task scheduled to be executed on the first processor; The method of claim 1 comprising:   The method of claim 1, further comprising generating a pulse train by sampling a transition between a busy state and an idle state. Determining the step of determining the workload of the steady state, the amount of the work that is required to run the workload of the stable state on the first processor of the first processor, the first operation of calculating the performance guarantee value for the processing group including first processor and the second processor, is executed by a single thread, the method according to claim 1.   The method of claim 8, wherein the single thread is executed on the first processor.   The method of claim 8, wherein the single thread is executed on the second processor of the computing device. A first processor;
A second processor;
Means for determining a steady state workload of the first processor;
Means for determining the amount of work required to execute the determined steady state workload on the first processor;
Means for calculating a performance guarantee value for a processing group including the first processor and the second processor;
Means for transitioning the first processor from an idle state to a busy state;
Means for performing a dynamic clock and voltage scaling operation to scale the frequency of the first processor based on the actual workload of the first processor;
Means for determining whether the first processor and the second processor remain in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value;
When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Means for increasing the frequency of one of the first processor and the second processor. When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Means for increasing the frequency of one of the first processor and the second processor;
12. The computing device of claim 11, comprising means for raising the frequency of the first processor or the second processor to a maximum processor frequency. When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Means for increasing the frequency of one of the first processor and the second processor comprises means for stepwise increasing the frequency of the first processor or the second processor;
Updating the performance guarantee value based on the scaled frequency;
Determining whether the first processor and the second processor remain in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value;
When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, 12. The computing device of claim 11, further comprising means for repeatedly performing an operation to raise the frequency of one of the first processor and the second processor.   12. The computing device of claim 11, wherein means for calculating the performance guarantee value for the processing group that includes the first processor and the second processor includes means for calculating a deadline value.   12. The computing device of claim 11, wherein the means for calculating the performance guarantee value for the processing group that includes the first processor and the second processor includes means for calculating a budget value.   Means for calculating a performance guarantee value for a processing group including the first processor and the second processor for determining a requirement of a task scheduled to be executed on the first processor; 12. A computing device according to claim 11, comprising means.   The computing device of claim 11, further comprising means for generating a pulse train by sampling a transition between a busy state and an idle state. Determining the workload of the stable state of the first processor, wherein to determine the amount of work that is required to perform the work load of the steady state, the behavior calculate the performance guarantee value The computing device of claim 11, further comprising means for performing via a single thread.   The computing device of claim 18, further comprising means for executing the single thread on the first processor.   The computing device of claim 18, further comprising means for executing the single thread on the second processor of the computing device. A first processor;
A second processor;
A computing device comprising a primary processor configured with processor-executable instructions to perform the operation, the operation comprising:
Determining a steady state workload of the first processor;
Determining the amount of work required to execute the determined steady state workload on the first processor;
Calculating a performance guarantee value for a processing group including the first processor and the second processor;
Transitioning the first processor from an idle state to a busy state;
Performing a dynamic clock and voltage scaling operation to scale the frequency of the first processor based on the actual workload of the first processor;
Determining whether the first processor and the second processor remain in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value;
When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Raising the frequency of one of the first processor and the second processor. When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Raising the frequency of one of the first processor and the second processor;
22. The primary processor is configured with processor-executable instructions to perform operations to include raising the frequency of the first processor or the second processor to a maximum processor frequency. The computing device described. When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Performing the operation such that increasing the frequency of one of the first processor and the second processor includes gradually increasing the frequency of the first processor or the second processor. The primary processor is configured by processor-executable instructions,
The primary processor is
Updating the performance guarantee value based on the scaled frequency;
Determining whether the first processor and the second processor remain in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value;
When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, 24. The computing device of claim 21, wherein the computing device is configured with processor-executable instructions to repeatedly perform an operation to increase the frequency of one of the first processor and the second processor.   The primary processor is processor-executable such that the step of calculating the guaranteed performance value for the processing group including the first processor and the second processor includes an operation of calculating a deadline value. 24. The computing device of claim 21, configured by instructions.   The primary processor is processor executable such that the step of calculating the performance guarantee value for the processing group including the first processor and the second processor includes calculating a budget value. 24. The computing device of claim 21, configured by instructions.   Calculating the performance guarantee value for the processing group including the first processor and the second processor includes determining a requirement of a task scheduled to be executed on the first processor. The computing device of claim 21, wherein the primary processor is configured with processor-executable instructions to perform operations. The primary processor is
The computing device of claim 21, wherein the computing device is configured with processor-executable instructions to perform an operation further comprising generating a pulse train by sampling a transition between a busy state and an idle state.   Determining the steady state workload of the first processor, determining the amount of work required to execute the steady state workload on the first processor, and the first processor And the primary processor is configured with processor-executable instructions such that the operation of calculating the performance guarantee value for the processing group including the second processor is performed by a single thread. 24. The computing device of claim 21, wherein:   30. The computing device of claim 28, wherein the first processor is the primary processor.   30. The computing device of claim 28, wherein the second processor is the primary processor. A non-transitory computer readable storage medium storing processor-executable software instructions configured to cause a primary processor to perform an operation, the operation comprising:
Determining a steady state workload of the first processor;
Determining the amount of work required to execute the determined steady state workload on the first processor;
Calculating a performance guarantee value for a processing group including the first processor and the second processor;
Transitioning the first processor from an idle state to a busy state;
Performing a dynamic clock and voltage scaling operation to scale the frequency of the first processor based on the actual workload of the first processor;
Determining whether the first processor and the second processor remain in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value;
When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Increasing the frequency of one of the first processor and the second processor. When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Raising the frequency of one of the first processor and the second processor;
The stored processor executable software instructions are configured to cause the primary processor to perform an operation to include raising the frequency of the first processor or the second processor to a maximum processor frequency. 32. The non-transitory computer readable storage medium of claim 31. When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, Increasing the frequency of one of the first processor and the second processor includes increasing the frequency of the first processor or the second processor in stages. The stored processor executable software instructions are configured to cause a processor to perform an operation,
The stored processor executable software instructions are:
Updating the performance guarantee value based on the scaled frequency;
Determining whether the first processor and the second processor remain in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value;
When it is determined that the first processor and the second processor remain in the busy state for the combined period of time that is greater than or equal to the sum of the determined amount of work and the performance guarantee value, 32. The non-transitory computer readable storage medium of claim 31, configured to cause the primary processor to repeatedly perform an operation to increase the frequency of one of the first processor and the second processor.   Calculating the performance guarantee value for the processing group including the first processor and the second processor to calculate an expiration value so that the primary processor performs an operation. 32. The non-transitory computer readable storage medium of claim 31, wherein programmed processor executable software instructions are configured.   The storage for causing the primary processor to perform an operation such that calculating the performance guarantee value for the processing group including the first processor and the second processor includes calculating a budget value. 32. The non-transitory computer readable storage medium of claim 31, wherein programmed processor executable software instructions are configured.   Calculating the performance guarantee value for the processing group including the first processor and the second processor includes determining a requirement of a task scheduled to be executed on the first processor. 32. The non-transitory computer readable storage medium of claim 31, wherein the stored processor executable software instructions are configured to cause the primary processor to perform an operation. The stored processor executable software instructions are:
32. The non-transitory computer readable storage of claim 31 configured to cause the primary processor to perform an operation further comprising generating a pulse train by sampling a transition between a busy state and an idle state. Medium.   Determining the steady state workload of the first processor, determining the amount of work required to execute the steady state workload on the first processor, and the first processor And the stored processor executable to cause the primary processor to perform an operation such that the operation of calculating the performance guarantee value for the processing group including the second processor is performed by a single thread. 32. The non-transitory computer readable storage medium of claim 31, wherein software instructions are configured.   40. The non-transitory computer readable storage medium of claim 38, wherein the first processor is the primary processor.   40. The non-transitory computer readable storage medium of claim 38, wherein the second processor is the primary processor.

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