WO2021097765A1 - 一种乘法器及算子电路 - Google Patents

一种乘法器及算子电路 Download PDF

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Publication number
WO2021097765A1
WO2021097765A1 PCT/CN2019/119993 CN2019119993W WO2021097765A1 WO 2021097765 A1 WO2021097765 A1 WO 2021097765A1 CN 2019119993 W CN2019119993 W CN 2019119993W WO 2021097765 A1 WO2021097765 A1 WO 2021097765A1
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Prior art keywords
transistor
coupled
node
bit
input
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PCT/CN2019/119993
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English (en)
French (fr)
Inventor
范团宝
蒋越星
时小山
王荣军
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华为技术有限公司
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Priority to JP2022529732A priority Critical patent/JP7371255B2/ja
Priority to KR1020227015465A priority patent/KR102676098B1/ko
Priority to CN202111075411.3A priority patent/CN113946312A/zh
Priority to CN201980006794.3A priority patent/CN113227963B/zh
Priority to PCT/CN2019/119993 priority patent/WO2021097765A1/zh
Priority to BR112022007427A priority patent/BR112022007427A2/pt
Priority to EP19953180.7A priority patent/EP4030277A4/en
Publication of WO2021097765A1 publication Critical patent/WO2021097765A1/zh
Priority to US17/750,299 priority patent/US11855661B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3066—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction by means of a mask or a bit-map
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/31—Design entry, e.g. editors specifically adapted for circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60—General implementation details not specific to a particular type of compression
    • H03M7/6011—Encoder aspects

Definitions

  • This application relates to the field of electronic technology, in particular to a multiplier and an operator circuit.
  • AI technology has been gradually popularized in communication equipment such as servers and terminals.
  • AI technology is effective in communication equipment such as central processing unit (CPU) and neural network.
  • the processing unit neural-network processing unit, NPU), image processing unit (graphics processing unit, GPU), or digital signal processor (digital signal processor, DSP) and other processors have high requirements for computing power.
  • the multiplier is used as the processor.
  • the core computing unit plays an increasingly important role.
  • the existing multiplier architecture is designed based on standard encoders and standard adders, as shown in Figure 1.
  • the specific design and implementation can be summarized into three steps: (1) Using the Radix-4 Booth algorithm in the Radix-4 Booth encoder The first value and the second value are encoded to obtain a partial product; (2) the partial product is compressed through the Wallace compression tree; (3) the two partial products obtained by the compression are summed to obtain the multiplication result.
  • the first value and the second value are both 16-bit binary numbers, and the multiplication result is 32-bit binary numbers as an example.
  • A[15:0] represents the first value
  • b[15:0] represents the first value.
  • Two values, y[31:0] represents the result of the multiplication operation.
  • This application provides a multiplier and an operator circuit, which are used to reduce the difficulty of implementing the multiplier.
  • this application adopts the following technical solutions:
  • a multiplier for realizing the multiplication of a first value of M bits (bits) and a second value of N bits, where M and N are integers greater than 1, including: P groups of encoders And W-layer inverse compressor, each group of encoders in the P group of encoders includes N encoders, W is a positive integer, and P is an integer greater than 1; each group of encoders is used to adopt a positive phase encoding operator Or the inverse encoding operator encodes part of the bits in the second value, the group selection signal and the symbol control input signal corresponding to each group of encoders to obtain a partial product term, and the group selection signal and the symbol control input signal are based on Part of the bits in the first value are generated, and the P group of encoders encodes to obtain P partial product items; the W-layer inverted compressor is used to compress P partial product items using an inverted compression operator to obtain two accumulated values , The sum of the two accumulated values is the product of the first value and the second
  • the P group encoder that uses the positive phase encoding operator or the inverted encoding operator for encoding and the W layer inverted compressor that uses the inverted compression operator for compression have relatively simple implementation solutions.
  • this solution has the advantages of small area and low power consumption, so the multiplier has a small area and low power consumption.
  • each of the N encoders corresponds to the first bit and the second bit in the second value
  • the group selection signal includes the first signal and the second bit.
  • each of the encoders is specifically used to encode the first bit, the second bit, the group selection signal, and the symbol control input signal using a positive phase coding operator or a reverse phase coding operator to obtain a partial product term An output bit; where the first bit and the second bit can be two adjacent bits in the second value, or the same bit in the second value.
  • the encoder when an encoder adopts a positive-phase encoding operator, the encoder is a positive-phase encoder, and is specifically configured to perform the following encoding operations: if the first signal and the first bit If the bits are both 1, or the second signal and the second bit are both 1, the output bit obtained by the encoder is the inverse of the sign control input signal; if at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, the output bit obtained by the encoder is the sign control input signal.
  • a positive-phase encoder is provided, and the implementation of the positive-phase encoder is relatively simple, such as small area and low power consumption.
  • the encoder when an encoder adopts an inverted encoding operator, the encoder is an inverted encoder, and is specifically configured to perform the following encoding operations: if the first signal and the first signal If the bits are both 1, or the second signal and the second bit are both 1, the output bit obtained by the encoder is the sign control input signal; if at least one of the first signal and the first bit is 0, Moreover, at least one of the second signal and the second bit is 0, and the output bit obtained by the encoder is the inversion of the sign control input signal.
  • an inverted encoder is provided.
  • the implementation of the inverted encoder is relatively simple, such as small area and low power consumption.
  • W is 1, the W-layer inverting compressor includes: a first layer of inverting compressor; a first layer of inverting compressor, used to follow the order from low to high Sequentially, each digit in the array of P partial product items is compressed using an inverse compression operator until the remaining bits corresponding to each digit are less than three, and the first compressed array is obtained.
  • the first compressed array includes two Each row corresponds to an accumulated value; the compression of each digit is performed for every three bits on the digit; each row in the array of P partial product items includes a partial product item, and each column includes The P partial product items correspond to multiple bits of the same digit.
  • the provided inverting compressor has high compression efficiency.
  • W is an integer greater than 1
  • the W-layer inverting compressor includes: the first layer inverting compressor to the W-th layer inverting compressor; the first layer inverting compression The device is used to compress each digit in the array of P partial product items in sequence from the low digit to the high digit using the inverse compression operator until the remaining bits corresponding to each digit are less than three, to obtain The first compression array; the i-th layer inverted compressor, used to sequentially compress each digit in the i-1th compressed array using an inverted compression operator from low digits to high digits, until each digit corresponds to The remaining bits are less than three, and the i-th compressed array is obtained.
  • the value of i ranges from 2 to W in turn; the W-th compressed array includes two rows, and each row corresponds to an accumulated value.
  • each layer of inverting compressor pairs each The compression of a number of digits is performed on the three bits of the digit; each row in the array of P partial product terms includes a partial product term, and each column includes multiple P partial product terms corresponding to the same digit. Bits.
  • the provided W-layer inverting compressor has high compression efficiency.
  • each inverted compressor is specifically used to perform the following compression: if the three bits are all 0, then carry The output bit is 1, and the current summation output bit is 1. If the three bits are all 1, the carry output bit is 0, and the current summation output bit is 0; if there is one of the three bits, it is 1. If the other two bits are 0, the carry output bit is 1, and the current sum output bit is 0; if two of the three bits are 1, the other bit is 0, then the carry The output bit is 0, and the current sum output bit is 1.
  • a simple and effective compression method of the inverting compressor is provided.
  • the phase of the encoding operator adopted by the encoder corresponding to the same digit is related to the phase of the current sum output bit or carry output bit output by the inverting compressor; where the same
  • the encoder corresponding to a digit refers to an encoder that obtains the output bit corresponding to the same digit by encoding
  • the inverting compressor corresponding to the same digit refers to an inverting compressor that compresses three bits of the same digit.
  • the multiplier further includes: one or more inverters, which are used to determine the current output of one or more inverting compressors in the W-layer inverting compressor. Invert the phase of the output bit and the carry output bit, or invert the phase of at least one of the three bits input to one or more inverting compressors.
  • the compression efficiency of the W-layer inverse compressor can be improved while ensuring the accuracy of the compression result.
  • the multiplier further includes: a precoder, configured to receive the first value, and generate a group selection signal and a sign control input signal according to some bits in the first value.
  • the multiplier further includes: an adder, configured to receive two accumulated values and sum the two accumulated values to obtain a product.
  • an operator circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a Tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, fourteenth transistor and fifteenth transistor; wherein the first transistor and the second transistor are coupled in parallel between the power supply terminal and the first node; The third transistor and the fourth transistor are coupled in parallel between the first node and the second node; the fifth transistor and the seventh transistor are coupled in series between the second node and the ground terminal; the sixth transistor and the eighth transistor are coupled in series on the second node.
  • the control terminals of the third transistor and the fifth transistor are used to receive the first input; the control terminals of the first transistor and the sixth transistor are used to receive the second input; the control of the fourth transistor and the seventh transistor The control terminal of the second transistor and the control terminal of the eighth transistor are used to receive the fourth input; the ninth transistor is coupled between the inverting terminal and the output terminal of the fifth input, and the control terminal of the ninth transistor is coupled to The second node; the tenth transistor is coupled between the second node and the output terminal, the control terminal of the tenth transistor is coupled to the inverted phase of the fifth input; the eleventh transistor and the thirteenth transistor are coupled in series at the output terminal and the ground terminal The control terminal of the eleventh transistor is coupled to the second node; the control terminal of the thirteenth transistor is used to receive the inverted phase of the fifth input; the twelfth transistor is coupled between the output terminal and the second node, and the tenth transistor is The control terminals of the two transistors are used to receive the fifth
  • a positive-phase encoding operator circuit is provided.
  • the number of transistors in the positive-phase encoding operator circuit is small, the occupied area is small, and the implementation is simple, so that when the operator circuit is applied to a multiplier, it can be reduced.
  • the area of the small multiplier is provided.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the ninth transistor, the tenth transistor, and the fourteenth transistor are P-type MOS (PMOS) transistors;
  • the fifth, sixth, seventh, eighth, eleventh, twelfth, thirteenth, and fifteenth transistors are N-type MOS (NMOS) transistors.
  • the provided operator circuit has a smaller turnover rate of the transistor when encoding data, so that the power consumption of the multiplier can be reduced when the operator circuit is applied to the multiplier.
  • an operator circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a Tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, fourteenth transistor and fifteenth transistor; wherein the first transistor and the second transistor are coupled in parallel between the power supply terminal and the first node; The third transistor and the fourth transistor are coupled in parallel between the first node and the second node; the fifth transistor and the seventh transistor are coupled in series between the second node and the ground terminal; the sixth transistor and the eighth transistor are coupled in series on the second node.
  • the control terminals of the third transistor and the fifth transistor are used to receive the first input; the control terminals of the first transistor and the sixth transistor are used to receive the second input; the control of the fourth transistor and the seventh transistor
  • the terminal is used to receive the third input; the control terminals of the second transistor and the eighth transistor are used to receive the fourth input; the ninth transistor and the tenth transistor are coupled in series between the power terminal and the output terminal, and the control terminal of the ninth transistor is coupled
  • the control terminal of the tenth transistor is coupled to the second node;
  • the eleventh transistor is coupled between the second node and the output terminal, and the control terminal of the eleventh transistor is coupled to the fifth input;
  • Two transistors are coupled between the output terminal and the inverted phase of the fifth input, the control terminal of the twelfth transistor is coupled to the second node;
  • the thirteenth transistor is coupled between the output terminal and the second node, and the control of the thirteenth transistor is The fourteenth transistor and the fifteenth transistor are coupled in series
  • an inverted encoding operator circuit in which the number of transistors in the inverted encoding operator circuit is small, the occupied area is small, and the implementation is simple, so that when the operator circuit is applied to a multiplier, it can be reduced. The area of the small multiplier.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the fourteenth transistor are PMOS transistors;
  • the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the twelfth transistor, the thirteenth transistor, and the fifteenth transistor are NMOS transistors.
  • the provided operator circuit has a smaller turnover rate of the transistor when encoding data, so that the power consumption of the multiplier can be reduced when the operator circuit is applied to the multiplier.
  • an operator circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a Tenth Transistor, Eleventh Transistor, Twelfth Transistor, Thirteenth Transistor, Fourteenth Transistor, Fifteenth Transistor, Sixteenth Transistor, Seventeenth Transistor, Eighteenth Transistor, Nineteenth Transistor, Second Ten transistors, twenty-first transistors, and twenty-second transistors; wherein the first transistor and the second transistor are coupled in parallel between the power supply terminal and the first node; the third transistor is coupled between the first node and the first output terminal The fourth transistor is coupled between the first output terminal and the second node; the fifth transistor and the sixth transistor are coupled in parallel between the second node and the ground terminal; the seventh transistor is coupled between the power terminal and the third node The eighth transistor is coupled between the third node and the first output
  • the sixth transistor and the seventeenth transistor are coupled in parallel between the power terminal and the fifth node; the eighteenth transistor is coupled between the fifth node and the second output terminal; the nineteenth transistor is coupled between the second output terminal and the sixth node Between; the twentieth transistor, the twenty-first transistor and the twenty-second transistor are coupled in parallel between the sixth node and the ground terminal; the third transistor, the fourth transistor, the twelfth transistor, the thirteenth transistor, and the The control terminals of the fifteenth transistor and the twentieth transistor are used to receive the first input; the control terminals of the first transistor, the fifth transistor, the seventh transistor, the tenth transistor, the sixteenth transistor, and the twenty-first transistor are used to receive Second input; the control terminals of the second transistor, the sixth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the fourteenth transistor, the seventeenth transistor, and the twenty-second transistor are used to receive the third input; The control terminals of the eighteenth transistor and the nineteenth transistor are coupled to the first output terminal.
  • an inverted compression operator circuit in which the number of transistors in the inverted compression operator circuit is small, the occupied area is small, and the implementation is simple, so that when the operator circuit is applied to a multiplier, it can be reduced.
  • the area of the small multiplier is provided, in which the number of transistors in the inverted compression operator circuit is small, the occupied area is small, and the implementation is simple, so that when the operator circuit is applied to a multiplier, it can be reduced. The area of the small multiplier.
  • Sixth, seventeenth, and eighteenth transistors are PMOS transistors; fourth, fifth, sixth, ninth, tenth, thirteenth, fourteenth, and nineteenth transistors
  • the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are NMOS transistors.
  • the provided operator circuit compresses data when the transistor has a low turnover rate, so that when the operator circuit is applied to the multiplier, the power consumption of the multiplier can be reduced.
  • a processor including a multiplier or an operator circuit; wherein, the multiplier is the multiplier provided in the foregoing first aspect or any possible implementation manner of the first aspect, and the operator circuit An operator circuit provided for any possible implementation manner of the second aspect to the fourth aspect, or the second aspect to the fourth aspect.
  • the processor includes a neural network processing unit.
  • a chip including a multiplier or an operator circuit; wherein the multiplier is the multiplier provided in the first aspect or any possible implementation of the first aspect, and the operator circuit is The operator circuit provided by the foregoing second aspect to the fourth aspect, or any possible implementation manner of the second aspect to the fourth aspect.
  • any processor or chip provided above includes the multiplier or operator circuit provided above. Therefore, the beneficial effects it can achieve can refer to the multiplier or operator circuit provided above. The beneficial effects in the process will not be repeated here.
  • Fig. 1 is an architecture diagram of a multiplier provided in the prior art
  • FIG. 2 is a schematic structural diagram of a communication device provided by an embodiment of this application.
  • FIG. 3 is a schematic structural diagram of a multiplier provided by an embodiment of the application.
  • Fig. 4 is a logical block diagram of a positive phase encoder provided by an embodiment of the application.
  • Fig. 5 is a logical block diagram of an inverted encoder provided by an embodiment of the application.
  • FIG. 6 is a diagram of a compression example of a W-layer inverting compressor provided by an embodiment of the application.
  • FIG. 7 is a logic block diagram of an inverting compressor provided by an embodiment of the application.
  • FIG. 8 is an example diagram of a precoder and an encoder provided by an embodiment of this application.
  • FIG. 9 is a compression example diagram of another W-layer inverting compressor provided by an embodiment of the application.
  • FIG. 10 is a circuit diagram of a positive phase encoder provided by an embodiment of the application.
  • FIG. 11 is a circuit diagram of an inverting encoder provided by an embodiment of the application.
  • FIG. 12 is a circuit diagram of an inverting compressor provided by an embodiment of the application.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • And/or describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the following at least one item (a) or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • At least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple .
  • the embodiments of the present application use words such as “first” and “second” to distinguish objects with similar names or functions or functions. Those skilled in the art can understand the words “first”, “second” and the like. There is no limit to the number and execution order.
  • the term “coupling” is used to indicate electrical connection, including direct connection through wires or connecting ends or indirect connection through other devices. Therefore, “coupling” should be regarded as an electronic communication connection in a broad sense.
  • FIG. 2 is a schematic structural diagram of a communication device provided by an embodiment of the application.
  • the communication device may be a terminal, a server, or the like.
  • the communication device may include a memory 201, a processor 202, a communication interface 203, and a bus 204.
  • the memory 201, the processor 202, and the communication interface 203 are connected to each other through a bus 204.
  • the memory 201 can be used to store data, software programs, and modules, and mainly includes a storage program area and a storage data area.
  • the storage program area can store an operating system, at least one application program required by a function, etc., and the storage data area can store the usage time of the device. The created data, etc.
  • the processor 202 is used to control and manage the actions of the communication device, for example, by running or executing software programs and/or modules stored in the memory 201, and calling data stored in the memory 201 to perform various functions of the device And processing data.
  • the communication interface 203 is used to support the device to communicate.
  • the processor 202 includes, but is not limited to, a central processing unit (Central Processing Unit, CPU), a network processing unit (Network Processing Unit, NPU), a graphics processing unit (Graphics Processing Unit, GPU), or a digital signal processor (Digital Signal Processing Unit, GPU). Processor, DSP) or general-purpose processor, etc.
  • the processor 202 includes one or more multipliers, such as an array of multipliers, and the multiplier is a device that implements a multiplication operation in the processor 202.
  • the bus 204 may be a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and so on. For ease of representation, only one thick line is used in FIG. 2, but it does not mean that there is only one bus or one type of bus.
  • FIG. 3 is a schematic structural diagram of a multiplier provided by an embodiment of the application.
  • the multiplier is used to multiply a first value of M bits and a second value of N bits, M and N Is an integer greater than 1.
  • the multiplier includes: P precoders 301, P group encoders 302, W layer inverse compressor 303, and adder 304.
  • Each group of encoders 3021 in P group encoders 302 includes N codes W is a positive integer, and P is an integer greater than 1. This multiplier is simpler to implement than the traditional design, which will be described in detail below.
  • Each precoder 3011 of the P precoders 301 is used to generate a group selection signal and a symbol control input signal according to some bits in the first value, so that the P precoders 301 correspondingly generate P group selection signals And P symbols control the input signal.
  • P group selection signals and P symbol control input signals correspond to the P group of encoders one-to-one, that is, one group selection signal and one symbol control input signal correspond to a group of encoders.
  • the group selection signal can be generated based on two or three adjacent bits in the first value, and the sign control input signal can be one bit in the first value, or it can be based on two adjacent bits in the first value. One or three bits.
  • the first value is a binary number of 4 bits and expressed as a[3:0]
  • P is equal to 2
  • 2 precoders can generate 2 group selection signals and 2 symbol control inputs according to a[3:0] signal.
  • the first group selection signal can be generated based on a[0] and a[1]
  • the second group selection signal can be generated based on a[1] to a[3].
  • the first symbol control input signal can be a[1]
  • the second symbol control input signal can be a[3].
  • the above a[i] represents the i-th bit from right to left in a[3:0], and the value of i ranges from 0 to 3.
  • Each group of encoders 3021 is used to encode the second value, the group selection signal and the sign control input signal corresponding to the group of encoders by adopting the positive phase coding operator or the reverse phase coding operator to obtain a partial product term, P group coding
  • the encoder obtains P partial product terms.
  • each group of encoders 3021 includes N encoders, each of the N encoders corresponds to the first bit and the second bit in the second value, and the group selection signal includes the first signal and the second signal. ; Then each encoder can be specifically used to: use a positive-phase coding operator or a reverse-phase coding operator to encode the first bit, the second bit, the group selection signal, and the symbol control input signal of the encoder to obtain a partial product One output bit of the item.
  • the N encoders in each group of encoders 3021 respectively encode the N output bits of a partial product term, that is, the partial product term is obtained.
  • the first bit and the second bit may be two adjacent bits in the second value, or the same bit in the second value, which will be described in more detail in subsequent embodiments.
  • each group of encoders 3021 includes 3 encoders.
  • the first encoder corresponds to the two adjacent bits in b[2:0], b[0] and b[1]
  • the second encoder corresponds to b[2:0]
  • the first and second bits corresponding to the third encoder are both b[2] in b[2:0], That is, the last third encoder only inputs one bit b[2] as the first bit and the second bit at the same time.
  • the above b[i] represents the i-th bit from right to left in b[2:0].
  • the first encoder in the first group of codes corresponds to the second value b[2:0]
  • the adjacent two bits are b[0] and b[1]
  • the corresponding group selection signal is the first group selection signal (represented as A and B) generated according to a[0] and a[1], corresponding
  • the symbol control input signal is a[1]
  • the first encoder can be specifically used to encode b[0], b[1], A, B, and a using a positive-phase coding operator or a reverse-phase coding operator [1], get 1 output bit in the first partial product term.
  • the encoder when an encoder adopts a positive phase encoding operator, the encoder may be called a positive phase encoder; when an encoder adopts an inverted encoding operator, the encoder may be called an inverted encoder.
  • the positive phase encoder and the reverse phase encoder are a detailed description of the positive phase encoder and the reverse phase encoder.
  • the positive-phase encoder is specifically used to perform the following encoding operations: if the first signal and the first bit are both 1, or the second signal and the second bit are both 1, then the output bit obtained by the positive-phase encoder is The sign controls the inversion of the input signal; if at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, the output bit obtained by the positive phase encoder Bit is the sign control input signal.
  • Fig. 4 is a logical block diagram of a positive phase encoder provided by an embodiment of the application.
  • the logical block diagram includes an encoding gating unit, an inversion unit, and a switch control unit.
  • the function of the code gating unit is: if A and Sel_A are 1 at the same time, or B and Sel_B are 1 at the same time, then output 1, otherwise output 0; the function of the inversion unit is: take the output of the code gating unit On the contrary; the function of the switch control unit is: if the output of the inversion unit is 1, output S, if the output of the inversion unit is 0, output /S.
  • A represents the first signal
  • B represents the second signal
  • Sel_A represents the first bit
  • Sel_B represents the second bit
  • S represents the sign control input signal
  • /S represents the inversion of the sign control input signal
  • the positive phase encoder can be encoded according to the logic table shown in Table 1 below.
  • the x in Table 1 represents any one of "0” or “1”, and A, B, Sel_A, Sel_B, S And OUT are consistent with A, B, Sel_A, Sel_B, S, and OUT in Figure 4.
  • a Sel_A B Sel_B S OUT 1 1 x x 0 1 1 1 x x 1 0 x x 1 1 0 1 x x 1 1 1 0 0 x 0 x 0 0 0 x 0 x 1 1 x 0 x 0 0 0 x 0 x 0 1 1 1
  • the inverted encoder is specifically used to perform the following encoding operations: if the first signal and the first bit are both 1, or the second signal and the second bit are both 1, then the output bit obtained by the inverted encoder Is a sign control input signal; if at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, the output bit obtained by the inverted encoder is The sign controls the inversion of the input signal.
  • FIG. 5 is a logic block diagram of an inverting encoder provided by an embodiment of the application.
  • the logic block diagram includes an encoding gating unit, an inversion unit, and a switch control unit.
  • the function of the code gating unit is: if A and Sel_A are 1 at the same time or B and Sel_B are 1 at the same time, then output 1, otherwise output 0; the function of the inversion unit is: take the output of the code gating unit On the contrary; the function of the switch control unit is: if the output of the inversion unit is 0, output S, if the output of the inversion unit is 1, output /S.
  • A represents the first signal
  • B represents the second signal
  • Sel_A represents the first bit
  • Sel_B represents the second bit
  • S represents the sign control input signal
  • /S represents the inversion of the sign control input signal
  • the inverted encoder can be specifically encoded according to the logic table shown in Table 2 below, where x in Table 2 represents either "0" or "1", A, B, Sel_A, Sel_B, S and OUT is consistent with A, B, Sel_A, Sel_B, S, and OUT in Figure 5.
  • the W-layer inverting compressor 303 is used for compressing P partial product terms using an inverting compression operator to obtain two accumulated values.
  • the W-layer inverting compressor 303 includes: a first-layer inverting compressor for sequentially arranging each digit in the array of P partial product items in order from low digits to high digits
  • the inverse compression operator is used to compress until the remaining bits corresponding to each digit are less than three, and a first compressed array including two rows is obtained, and each row corresponds to an accumulated value.
  • the W-layer inverting compressor 303 includes: the first layer of inverting compressor to the W-th layer of inverting compressor; the first layer of inverting compressor, used to follow the order from low to high In the order of digits, each digit in the array of P partial product items is compressed by an inverse compression operator until the remaining bits corresponding to each digit are less than three to obtain the first compressed array; the i-th layer is inverted Compressor, used to compress each digit in the i-1th compressed array in the order from low digit to high digit using an inverse compression operator until each digit corresponds to less than three remaining bits, and the first digit is obtained.
  • the i compressed array the value of i ranges from 2 to W in turn, the W-th compressed array includes two rows, and each row corresponds to an accumulated value.
  • each row in the array of P partial product items includes a partial product item, and each column includes multiple bits corresponding to the same digit in the P partial product items.
  • the compression of each digit is for the three bits on the digit
  • each row in the array of P partial product items includes a partial product item, and each column includes multiple bits corresponding to the same digit in the P partial product items.
  • the array of these 8 partial product terms can be shown in Figure 6 (a), PP[ 1] to PP[8] respectively represent 8 partial product terms, and 2 0 , 2 1 , 2 1 ,..., 2 32 represent different digits.
  • the digits refer to the output result of the W-layer inverting compressor. Similar to the ones, tens, or hundreds in decimal system, this digit is used to represent a bit in the binary value of the output result.
  • the output result of the W-layer inverting compressor is a 32-bit binary number, and the output result includes 32 Digits.
  • bits correspond to 0 or 1, indicating a binary information. It can be considered that one digit is one bit in the output result of the W-layer inverse compressor.
  • FIG. 6 is converted into (b) in FIG. 6 to illustrate the compression process of each layer of inverting compressor in the W layer inverting compressor 303.
  • the bits corresponding to other digits other than 24 to 22 are also reserved for less than three bits.
  • Each solid rectangular box in (b) in Figure 6 can be used to indicate An inverting compressor in the first layer of inverting compressor.
  • the first compressed array compressed by the first layer of inverting compressor is shown in Figure 6(c).
  • the bits corresponding to each digit in 2 23 and 2 26 are compressed every three bits, and less than three bits are reserved. Except for 2 6 to 2 23 and 2 26 , other digits correspond to Bits less than three bits are also reserved.
  • Each rectangular box in (c) in Figure 6 can be used to indicate an inverting compressor in the second layer of inverting compressor, and the second layer of inverting compressor compressing
  • the obtained second compressed array is shown in (d) in Figure 6, where Indicates the current sum output bit output by the second layer inverting compressor, and ⁇ represents the carry output bit output by the second layer inverting compressor.
  • the subsequent specific compression process from the third layer inverted compressor to the Wth layer inverted compressor is similar to the specific compression process of the first layer inverted compressor and the second layer inverted compressor described above, and the embodiments of the present application will not be described here. Repeat it again.
  • each inverting compressor is specifically used to perform the following compression: if the three bits are all 0, the carry output bit is 1, and the current sum output bit is 1; If the three bits are all 1, the carry output bit is 0, and the current sum output bit is 0; if one of the three bits is 1, the other two are 0, then The carry output bit is 1, and the current sum output bit is 0; if two of the three bits are 1, and the other bit is 0, the carry output bit is 0, and the current sum output bit is 1.
  • the carry output bit refers to the output bit pointing to the next digit of the current compressed digit
  • the current sum output bit refers to the output bit after the current compressed digit is compressed. For example, suppose that the current compressed digit is 2 5 , the next digit of the current compressed digit is 2 6 , and the three bits of 25 are all 0. After compression, 25 corresponds to 1 1 , 2 6 corresponds to a 1.
  • FIG. 7 is a logical block diagram of an inverting compressor provided by an embodiment of the application.
  • the logical block diagram includes an inverted carry output unit and an inverted sum output unit.
  • the function of the inverted carry output unit is: if at least 2 of Ai, Bi and Ci are valid (valid can be 1, or 0), the output is invalid (if valid is 1, invalid is 0, if valid If it is 0, it is invalid as 1), otherwise the output is valid.
  • the function of the inverted summation output unit is: if 2 of Ai, Bi and Ci are valid or all are invalid, the output is valid, otherwise the output is invalid.
  • the nCip1 input to the inverted summation output unit can be used when it is valid.
  • Ai, Bi, and Ci in the above FIG. 7 respectively represent the three input bits, nCip1 represents the carry output bit, and nSi represents the current sum output bit. That is, each layer of inverting compressor can be specifically compressed according to the logic table shown in Table 3 below.
  • Table 3 Ai, Bi, and Ci respectively represent the three input bits, and nCip1 represents the carry output bit. nSi represents the current sum output bit.
  • the multiplier may also include: one or more inverters, which are used to calculate the current sum output bit and carry output bit output by one or more inverted compressors in the W-layer inverted compressor 303 Invert the phase, or invert the phase of at least one of the three bits input to the one or more inverting compressors.
  • the W-layer inverting compressor 303 may include a multilayer inverting compressor, and each layer of the multilayer inverting compressor may include at least one inverting compressor, and the output phase of each inverting compressor can be adjusted according to requirements. Set, and the output phase of each inverting compressor is opposite to the input phase, so that the input phase of each inverting compressor is also set.
  • the output phase of an inverting compressor can refer to the phases of the current sum output bit and carry output bit output by the inverting compressor, and the phases of the current sum output bit and carry output bit are the same , That is, the same is normal phase or reverse phase.
  • the input phase of an inverting compressor may refer to the set phase of the three bits input to the inverting compressor, and the set phases of the three bits are the same, that is, the same is positive. Phase or reverse.
  • the one or more inverters can be used to reverse the one or more inverting compressors.
  • the phase of the current sum output bit and the carry output bit of the compressor output is reversed to make it consistent with the set output phase.
  • the one or more inverters can be used to The phase of at least one of the three bits of the one or more inverting compressors is reversed to make it consistent with the set input phase.
  • the output phase of at least one inverting compressor included in each layer of inverting compressors can be set as follows: the output phase of the inverting compressor of the last layer is set to the positive phase and the reciprocal The output phase of the second layer of inverting compressor is set to reverse, the output phase of the third-to-last layer of inverting compressor is set to normal phase, ..., and so on, until the first layer of inverting compressor is set The output phase.
  • the first layer of inverting compressor here can refer to the top layer of inverting compressor when compressing multiple bits corresponding to each digit in the order from top to bottom, and the second layer of inverting compressor can Refers to the inverting compressor at the next upper level,..., and so on.
  • the W-layer inverting compressor 303 includes a 4-layer inverting compressor, and it can be set as follows: the output phase of the fourth-layer inverting compressor is set to the normal phase, and the output of the third-layer inverting compressor The phase is set to reverse phase, the output phase of the second layer reverse compressor is set to normal phase, and the output phase of the first layer reverse compressor is set to reverse.
  • the inverter can be adjusted locally.
  • the output phase of the phase compressor is set to reduce the number of inverters required. For example, when the output phase set by a certain inverting compressor is positive (the input phase set by the inverting compressor at this time is inverted), if the output phase of the inverting compressor itself is positive , And the phases of the three bits input to the inverting compressor are also positive, then the inverting compressor requires three inverters to invert the phases of the three bits.
  • the inverting compressor only needs two inverters to invert the output phase of the two output bits (that is, the current sum output bit and the carry output bit) to meet the set output phase and input phase requirements.
  • phase of the encoding operator adopted by at least one of the encoders in the P group of encoders 302 is the same as the phase of the current sum output bit or carry output bit output by the at least one layer of inverting compressor in the W layer inverting compressor 303 related.
  • the phase of the encoding operator adopted by each encoder in the at least one encoder is set to be the same as the input phase of the inverting compressor connected to itself.
  • the phase of the encoding operator adopted by each encoder can be normal phase or reverse phase.
  • the encoder When the phase of the encoding operator adopted by an encoder is positive (that is, the positive phase encoding operator is used), the encoder is the above-mentioned positive encoder; when the phase of the encoding operator adopted by an encoder is reversed ( That is, when the inverted coding operator is used, the encoder is the above-mentioned inverted encoder.
  • the adder 304 is configured to receive the above two accumulated values and sum the two accumulated values to obtain the product. After the W-layer inverting compressor 303 compresses the P partial product terms to obtain the two accumulated values, the W-layer inverting compressor 303 can send the two accumulated values to the adder 304, and the adder 304 receives the two accumulated values. When there are two accumulated values, the product of the first value and the second value can be obtained by summing the two accumulated values.
  • the multiplier described in the present application will be illustrated by taking the first value as a[10:0] and the second value as b[12:0] as an example below.
  • the multiplier may include 6 precoders, 6 sets of encoders, and 3 layers of inverting compressors.
  • the first precoder is used to generate group selection signals S0 and S1 and the symbol control input signal a[1] according to a[0] and a[1];
  • the second precoder is used to generate group selection signals S0 and S1 according to a[1] , A[2] and a[3] generate group selection signals S2 and S3, and a symbol control input signal a[3];
  • the third precoder is used according to a[3], a[4] and a[5] Generate group selection signals S4 and S5, and symbol control input signal a[5];
  • the fourth precoder is used to generate group selection signals S6 and S7, and symbols according to a[5], a[6], and a[7] Control input signal a[7];
  • the fifth precoder is used to generate group selection signals S8 and S9 and symbol control input signal a[9] according to a[7], a[8] and a[9];
  • a precoder is
  • the first group of encoders are used to encode b[12:0], S0, S1, and a[1] to obtain the first partial product term PP[1];
  • the second group of encoders are used to encode b[12:0 ], S2, S3 and a[3] to get the second partial product term PP[2];
  • the third group of encoders are used to encode b[12:0], S4, S5 and a[5] to get the third Partial product term PP[3];
  • the fourth group of encoders are used to encode b[12:0], S6, S7 and a[7] to get the fourth partial product term PP[4];
  • the fifth group of encoders are used for encoding b[12:0], S8, S9 and a[9], get the fifth partial product term PP[5];
  • the sixth group of encoders are used to encode b[12:0], S10 and S_11, get the sixth Partial product term PP[
  • each encoder in each group of encoders is used to encode one bit or two bits in b[12:0], as well as the corresponding group selection signal and symbol control input signal.
  • Figure 8 Shown.
  • the arrangement array corresponding to the six partial product terms PP[1] to PP[6] can be shown in Fig. 9.
  • the W-layer inverting compressor 303 in the above multiplier it can be achieved by 3-layer inverting
  • the compressor compresses the arrangement array shown in FIG. 9, and the detailed compression process is similar to the related description in FIG. 6, and details are not repeated in the embodiment of the present application.
  • the P precoders may include precoders with different structures.
  • the first precoder in FIG. 8 includes a NOT gate and an AND gate
  • the second to fifth precoders The encoder includes XOR gate, XOR gate and NOR gate
  • the sixth precoder includes XOR gate and AND gate.
  • the first encoder of the same group of encoders in the embodiment of the present application may have a different structure from other encoders, and the structure of encoders of different groups may also be different, for example, the first to fifth groups of encoders in FIG. 8
  • the first encoder includes AND gates and XOR gates
  • the second to thirteenth encoders are positive-phase encoders or inverted encoders
  • each encoder in the sixth group of encoders includes AND gates and XOR gates. .
  • PP[1]_i in Figure 8 (the value range of i is 1 to 14) represents the i-th bit of the first partial product term PP[1], A represents the first signal, and B Represents the second signal, Sel_A represents the first bit, Sel_B represents the second bit, S represents the sign control input signal, and OUT represents the output bit.
  • FIG. 10 is a schematic structural diagram of a positive phase encoding operator circuit provided by an embodiment of the application.
  • the positive phase encoding operator circuit may also be referred to as a positive phase encoder.
  • the positive phase encoder includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15.
  • the first transistor M1 and the second transistor M2 are coupled in parallel between the power supply terminal and the first node 1; the third transistor M3 and the fourth transistor M4 are coupled in parallel between the first node 1 and the second node 2;
  • the transistor M5 and the seventh transistor M7 are coupled in series between the second node 2 and the ground terminal; the sixth transistor M6 and the eighth transistor M8 are coupled in series between the second node 2 and the ground terminal.
  • the control ends of the third transistor M3 and the fifth transistor M5 are used to receive the first input A; the control ends of the first transistor M1 and the sixth transistor M6 are used to receive the second input Sel_A; the control ends of the fourth transistor M4 and the seventh transistor M7 The control terminal is used to receive the third input B; the control terminals of the second transistor M2 and the eighth transistor M8 are used to receive the fourth input Sel_B.
  • the ninth transistor M9 is coupled between the inverted /S of the fifth input S and the output terminal OUT, the control terminal of the ninth transistor M9 is coupled to the second node 2, the signal of the second node 2 is /Y; the tenth transistor M10 Coupled between the second node 2 and the output terminal OUT, the control terminal of the tenth transistor M10 is coupled to the inverted /S of the fifth input S; the eleventh transistor M11 and the thirteenth transistor M13 are coupled in series at the output terminal OUT and Between ground terminals.
  • the control terminal of the eleventh transistor M11 is coupled to the second node 2; the control terminal of the thirteenth transistor M13 is used to receive the inverted /S of the fifth input S; the twelfth transistor M12 is coupled to the output terminal OUT and the second node During 2, the control terminal of the twelfth transistor M12 is used to receive the fifth input S; the fourteenth transistor M14 and the fifteenth transistor M15 are coupled in series between the power supply terminal and the ground terminal, and the fourteenth transistor M14 and the tenth transistor M15 are connected in series.
  • the series coupling node of the five transistor M15 is coupled to the inverted /S of the fifth input S; the control ends of the fourteenth transistor M14 and the fifteenth transistor M15 are used to receive the fifth input S.
  • the first input A to the fifth input S may be the first signal, the first bit, the second signal, and the first signal in the related description of the positive phase encoder in the multiplier embodiment. Two bits and symbols control the input signal.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, the tenth transistor M10, and the fourteenth transistor M14 are PMOS transistors; the fifth transistor M5 and the sixth transistor M14 are PMOS transistors.
  • the transistor M6, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fifteenth transistor M15 are NMOS transistors.
  • the aforementioned control terminal may specifically refer to the gate of the corresponding PMOS transistor or NMOS transistor.
  • the first transistor M1 to the fifteenth transistor M15 in the above example may be MOS transistors, or may be replaced by bipolar transistors.
  • the types of the transistors shown in FIG. 10 are only exemplary, and It does not limit the embodiments of this application.
  • FIG. 11 is a schematic structural diagram of an inverted encoding operator circuit provided by an embodiment of the application.
  • the inverted encoding operator circuit may also be referred to as an inverted encoder.
  • the inverting encoder includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15.
  • the first transistor M1 and the second transistor M2 are coupled in parallel between the power supply terminal and the first node 1; the third transistor M3 and the fourth transistor M4 are coupled in parallel between the first node 1 and the second node 2;
  • the transistor M5 and the seventh transistor M7 are coupled in series between the second node 2 and the ground terminal; the sixth transistor M6 and the eighth transistor M8 are coupled in series between the second node 2 and the ground terminal; the third transistor M3 and the fifth transistor
  • the control terminal of M5 is used to receive the first input A; the control terminals of the first transistor M1 and the sixth transistor M6 are used to receive the second input Sel_A; the control terminals of the fourth transistor M4 and the seventh transistor M7 are used to receive the third input B;
  • the control terminals of the second transistor M2 and the eighth transistor M8 are used to receive the fourth input Sel_B.
  • the ninth transistor M9 and the tenth transistor M10 are coupled in series between the power terminal and the output terminal OUT, the control terminal of the ninth transistor M9 is coupled to the inverted /S of the fifth input S, and the control terminal of the tenth transistor M10 is coupled to the first
  • the signal of the second node 2, the second node 2 is /Y
  • the eleventh transistor M11 is coupled between the second node 2 and the output terminal OUT, and the control terminal of the eleventh transistor M11 is coupled to the fifth input S
  • the transistor M12 is coupled between the output terminal OUT and the inverted /S of the fifth input S, the control terminal of the twelfth transistor M12 is coupled to the second node 2
  • the thirteenth transistor M13 is coupled between the output terminal OUT and the second node 2 In between, the control terminal of the thirteenth transistor M13 is coupled to the inverted /S of the fifth input S
  • the fourteenth transistor M14 and the fifteenth transistor M15 are coupled in series between the power terminal and the ground terminal,
  • the first input A to the fifth input S may be the first signal, the first bit, the second signal, and the first signal in the related description of the inverted encoder in the above multiplier embodiment. Two bits and symbols control the input signal.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the fourteenth transistor M14 are PMOS transistors;
  • the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, the thirteenth transistor M13, and the fifteenth transistor M15 are NMOS transistors.
  • the aforementioned control terminal may specifically refer to the gate of the corresponding PMOS transistor or NMOS transistor.
  • the first transistor M1 to the fifteenth transistor M15 in the above example can be MOS transistors, or can be replaced by bipolar transistors.
  • the types of the transistors shown in FIG. 11 are only exemplary, and It does not limit the embodiments of this application.
  • FIG. 12 is a schematic structural diagram of an inverting compression operator circuit provided by an embodiment of the application.
  • the inverting compression operator circuit may also be referred to as an inverting compressor.
  • the inverting compressor includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, tenth transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, fifteenth transistor M15, sixteenth transistor M16, seventeenth transistor M17, An eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, and a twenty-second transistor M22.
  • the first transistor M1 and the second transistor M2 are coupled in parallel between the power supply terminal and the first node 1; the third transistor M3 is coupled between the first node 1 and the first output terminal nCip1; the fourth transistor M4 is coupled between the first node 1 and the first output terminal nCip1.
  • the eleventh transistor M11 and the twelfth transistor M12 are coupled in series between the third node 3 and the second output terminal nSi; the thirteenth transistor M13 and the fourteenth transistor M14 are coupled in series at the second output terminal nSi And the fourth node 4; the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are coupled in parallel between the power terminal and the fifth node 5; the eighteenth transistor M18 is coupled between the fifth node 5 and Between the second output
  • the control terminals of the third transistor M3, the fourth transistor M4, the twelfth transistor M12, the thirteenth transistor M13, the fifteenth transistor M15, and the twentieth transistor M20 are used to receive the first input Ai;
  • the control terminals of the five transistor M5, the seventh transistor M7, the tenth transistor M10, the sixteenth transistor M16, and the twenty-first transistor M21 are used to receive the second input Bi;
  • the control terminals of M8, the ninth transistor M9, the eleventh transistor M11, the fourteenth transistor M14, the seventeenth transistor M17, and the twenty-second transistor M22 are used to receive the third input Ci;
  • the control terminal of the nine transistor M19 is coupled to the first output terminal nCip1.
  • the first input Ai, the second input Bi, and the third input Ci may be the three bits in the related description of the inverting compressor in the above multiplier embodiment, and the first output The terminal nCip1 may be used to output the carry output bit of the inverting compressor, and the second output terminal nSi may be used to output the current sum output bit of the inverting compressor.
  • the transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 are PMOS transistors;
  • the fourteenth transistor M14, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, and the twenty-second transistor M22 are NMOS transistors.
  • the aforementioned control terminal may specifically refer to the gate of the corresponding PMOS transistor or NMOS transistor.
  • the first transistor M1 to the twenty-second transistor M22 in the above examples can be MOS transistors, or bipolar transistors can be used instead.
  • the types of the transistors shown in FIG. 12 are only exemplary, and It does not limit the embodiments of this application.
  • the embodiment of this application compares the multipliers using the positive phase encoder, the inverted encoder and the inverted compressor provided above with the existing multipliers based on the standard encoder and the standard adder, as shown in Table 4 below. As shown in Table 5, as an embodiment of the present application, it is not limited to the following specific parameter values.
  • the number of transistors used by each standard encoder is 22, the occupied area is 0.2736, and the area gain is 1.18.
  • the number of transistors used by each positive-phase encoder or inverted encoder is 15, and the occupied area is Is 0.23256, the area gain is 1, the number of transistors used by each standard adder is 28, the occupied area is 0.2736, the area gain is 1.10, the number of transistors used by each inverting compressor is 24, the occupied area is 0.24816, the area gain Is 1. Therefore, the area of the multiplier provided by the embodiment of the present application is small.
  • the standard encoder has 4 flips per bit of data encoded, the static power consumption is 0.44522, the gain from static power consumption is 1.18, the gain from dynamic power consumption is 1.09, the positive phase encoder or the reverse phase encoder
  • Each encoded 1bit data is flipped 3 times, the static power consumption is 0.4084, the static power consumption and the dynamic power consumption are both 1, and the standard adder is flipped 4 times for each compressed 1bit data, the static power consumption is 0.57685, and the static power consumption gains are 1.10.
  • the gain of dynamic power consumption is 1.80.
  • the inverting compressor flips twice for each bit of data compressed, the static power consumption is 0.32122, and the gains of static power consumption and dynamic power consumption are both 1. Therefore, the power consumption of the multiplier provided in the embodiment of the present application is small.
  • the encoder in the multiplier provided by the embodiment of the application is encoded by using a positive phase encoding operator or an inverted encoding operator, that is, the multiplier uses a positive phase encoder or an inverted encoder for encoding, and the compressor uses
  • the inverting compressor performs compression, and its implementation is relatively simple. For example, it can reduce the number of MOS transistors in the multiplier, thereby reducing the area of the multiplier.
  • the corresponding encoder or compressor has a small number of flips, so that the power consumption of the multiplier is small.

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Abstract

一种乘法器及算子电路，乘法器用于实现M比特位的第一数值与N比特位的第二数值的相乘，包括P组编码器和W层反相压缩器，P组编码器中的每组编码器包括N个编码器；每组编码器用于采用正相编码算子或者反相编码算子编码第二数值中的部分比特位、对应于每组编码器的组选择信号和符号控制输入信号以得到一个部分积项，组选择信号和符号控制输入信号是根据第一数值中的部分比特位产生的，P组编码器编码得到P个部分积项；W层反相压缩器用于采用反相压缩算子压缩P个部分积项，得到两个累加值，两个累加值之和为第一数值与第二数值的乘积。

Description

一种乘法器及算子电路 技术领域
本申请涉及电子技术领域，尤其涉及一种乘法器及算子电路。
背景技术
随着人工智能(artificial intelligence，AI)技术的不断发展和成熟，服务器、终端等通信设备中已逐步普及AI技术，AI技术对通信设备中诸如中央处理单元(central processing unit，CPU)、神经网络处理单元(neural-network processing unit，NPU)、图像处理单元(graphics processing unit，GPU)或者数字信号处理器(digital signal processor，DSP)等处理器的计算能力要求较高，乘法器作为处理器的核心计算单元，扮演着越来越重要的角色。
现有乘法器架构是基于标准编码器和标准加法器来设计，如图1所示，具体的设计实现可归纳为三个步骤：(1)在Radix-4Booth编码器中采用Radix-4Booth算法对第一数值和第二数值进行编码得到部分积；(2)通过Wallace压缩树压缩部分积；(3)将压缩得到的两个部分积求和，即得到乘法运算结果。图1中以第一数值和第二数值均为16位二进制数、乘法运算结果为32位二进制数为例进行说明，a[15:0]表示第一数值，b[15:0]表示第二数值，y[31:0]表示乘法运算结果。但是，上述基于Radix-4Booth算法和Wallace压缩树实现的乘法器中，使用了大量的标准编码器和标准加法器，而标准编码器和标准加法器中金属-氧化物-半导体(metal–oxide–semiconductor，MOS)晶体管的数量多、面积大，从而导致乘法器的面积很大。也即是说，现有的乘法器的设计实现比较复杂。因此，如何设计更易于实现的乘法器就成为一个问题。
发明内容
本申请提供一种乘法器及算子电路，用于降低乘法器的实现难度。为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种乘法器，用于实现M比特位(bits)的第一数值与N比特位的第二数值的相乘，M和N是大于1的整数，包括：P组编码器和W层反相压缩器，P组编码器中的每组编码器包括N个编码器，W是正整数，P是大于1的整数；所述每组编码器，用于采用正相编码算子或者反相编码算子编码第二数值中的部分比特位、对应于所述每组编码器的组选择信号和符号控制输入信号以得到一个部分积项，组选择信号和符号控制输入信号是根据第一数值中的部分比特位产生的，P组编码器编码得到P个部分积项；W层反相压缩器，用于采用反相压缩算子压缩P个部分积项，得到两个累加值，两个累加值之和为第一数值与第二数值的乘积。上述技术方案中，采用正相编码算子或者反相编码算子进行编码的P组编码器以及采用反相压缩算子进行压缩的W层反相压缩器，其实现方案比较简单。例如，该方案具有面积小、功耗小的优点，从而该乘法器的面积小、功耗小。
在第一方面的一种可能的实现方式中，所述N个编码器中每个编码器对应第二数值中的第一比特位和第二比特位，组选择信号包括第一信号和第二信号；所述每个编 码器，具体用于：采用正相编码算子或者反相编码算子编码第一比特位、第二比特位、组选择信号和符号控制输入信号得到一个部分积项的一个输出比特位；其中，第一比特位和第二比特位可以是第二数值中相邻的两个比特位，或者是第二数值中的同一个比特位。上述可能的实现方式中，提供了一种编码器的编码方式，且其实现方案比较简单，例如能够减小编码器的面积。
在第一方面的一种可能的实现方式中，当一个编码器采用正相编码算子时，该编码器是正相编码器，且具体用于执行如下编码操作：若第一信号和第一比特位均为1、或者第二信号和第二比特位均为1，则该编码器得到的输出比特位为符号控制输入信号的反相；若第一信号和第一比特位中的至少一个为0、而且第二信号和第二比特位中的至少一个为0，则该编码器得到的输出比特位为符号控制输入信号。上述可能的实现方式中，提供了一种正相编码器，该正相编码器的实现方案比较简单，例如面积小、功耗低。
在第一方面的一种可能的实现方式中，当一个编码器采用反相编码算子时，该编码器是反相编码器，且具体用于执行如下编码操作：若第一信号和第一比特位均为1、或者第二信号和第二比特位均为1，则该编码器得到的输出比特位为符号控制输入信号；若第一信号和第一比特位中的至少一个为0、而且第二信号和第二比特位中的至少一个为0，则该编码器得到的输出比特位为符号控制输入信号的反相。上述可能的实现方式中，提供了一种反相编码器，该反相编码器的实现方案比较简单，例如面积小、功耗低。
在第一方面的一种可能的实现方式中，W为1，W层反相压缩器包括：第一层反相压缩器；第一层反相压缩器，用于按照从低数位到高数位顺序依次对P个部分积项的排列阵列中每个数位采用反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到第一压缩阵列，第一压缩阵列包括两行，每行对应一个累加值；对每个数位的压缩是针对该数位上的每三个比特位进行的；P个部分积项的排列阵列中的每行包括一个部分积项，每列包括P个部分积项中对应同一数位的多个比特位。上述可能的实现方式中，提供的反相压缩器的压缩效率高。
在第一方面的一种可能的实现方式中，W是大于1的整数，W层反相压缩器包括：第一层反相压缩器至第W层反相压缩器；第一层反相压缩器，用于按照从低数位到高数位顺序依次对P个部分积项的排列阵列中每个数位采用反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到第一压缩阵列；第i层反相压缩器，用于按照从低数位到高数位顺序依次对第i-1压缩阵列中每个数位采用反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到第i压缩阵列，i的取值范围依次从2至W；第W压缩阵列包括两行，每行对应一个累加值；其中，每层反相压缩器对每个数位的压缩是针对该数位上的三个比特位进行的；P个部分积项的排列阵列中的每行包括一个部分积项，每列包括P个部分积项中对应同一数位的多个比特位。上述可能的实现方式中，提供的W层反相压缩器的压缩效率高。
在第一方面的一种可能的实现方式中，对每个数位的每三个比特位，每个反相压缩器具体用于进行以下压缩：若所述三个比特位均为0，则进位输出位为1，当前求和输出位为1；若三个比特位均为1，则进位输出位为0，当前求和输出位为0；若所述 三个比特位中存在一个比特位为1、另外两个比特位为0，则进位输出位为1，当前求和输出位为0；若所述三个比特位中存在两个比特位为1、另外一个比特位为0，则进位输出位为0，当前求和输出位为1。上述可能的实现方式中，提供了一种简单有效的反相压缩器的压缩方式。
在第一方面的一种可能的实现方式中，同一数位对应的编码器采用的编码算子的相位与反相压缩器输出的当前求和输出位或进位输出位的相位有关；其中，该同一数位对应的编码器是指编码得到该同一数位对应的输出比特位的编码器，该同一数位对应的反相压缩器是指压缩该同一数位的三个比特位的反相压缩器。上述可能的实现方式中，提供了一种快速有效的确定编码器采用的编码算子的相位的方式。
在第一方面的一种可能的实现方式中，该乘法器还包括：一个或多个反相器，用于对W层反相压缩器中的一个或多个反相压缩器输出的当前求和输出位和进位输出位的相位取反、或对输入一个或多个反相压缩器的三个比特位中至少一个比特位的相位取反。上述可能的实现方式中，能够在保证压缩结果准确的情况下，提高该W层反相压缩器的压缩效率。
在第一方面的一种可能的实现方式中，该乘法器还包括：预编码器，用于接收第一数值，并根据第一数值中的部分比特位产生组选择信号和符号控制输入信号。
在第一方面的一种可能的实现方式中，该乘法器还包括：加法器，用于接收两个累加值，并对两个累加值求和以得到乘积。
第二方面，提供一种算子电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管和第十五晶体管；其中，第一晶体管和第二晶体管并联耦合在电源端和第一节点之间；第三晶体管和第四晶体管并联耦合在第一节点和第二节点之间；第五晶体管和第七晶体管串联耦合在第二节点和接地端之间；第六晶体管和第八晶体管串联耦合在第二节点和接地端之间；第三晶体管和第五晶体管的控制端用于接收第一输入；第一晶体管和第六晶体管的控制端用于接收第二输入；第四晶体管和第七晶体管的控制端用于接收第三输入；第二晶体管和第八晶体管的控制端用于接收第四输入；第九晶体管耦合在第五输入的反相和输出端之间，第九晶体管的控制端耦合于第二节点；第十晶体管耦合在第二节点和输出端之间，第十晶体管的控制端耦合于第五输入的反相；第十一晶体管和第十三晶体管串联耦合在输出端和接地端之间；第十一晶体管的控制端耦合于第二节点；第十三晶体管的控制端用于接收第五输入的反相；第十二晶体管耦合在输出端和第二节点之间，第十二晶体管的控制端用于接收第五输入；第十四晶体管和第十五晶体管串联耦合在电源端和接地端之间，第十四晶体管和第十五晶体管的串联耦合节点耦合于第五输入的反相；第十四晶体管和第十五晶体管的控制端用于接收第五输入。上述技术方案中，提供了一种正相编码算子电路，该正相编码算子电路中晶体管的数量少、占用面积小，实现简单，从而将该算子电路应用于乘法器中时可以减小乘法器的面积。
在第二方面的一种可能的实现方式中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第九晶体管、第十晶体管和第十四晶体管是P型MOS(PMOS)晶体管； 第五晶体管、第六晶体管、第七晶体管、第八晶体管、第十一晶体管、第十二晶体管、第十三晶体管和第十五晶体管是N型MOS(NMOS)晶体管。上述可能的实现方式中，提供的算子电路编码数据时晶体管的翻转率较小，从而将该算子电路应用于乘法器中时可以减小乘法器的功耗。
第三方面，提供一种算子电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管和第十五晶体管；其中，第一晶体管和第二晶体管并联耦合在电源端和第一节点之间；第三晶体管和第四晶体管并联耦合在第一节点和第二节点之间；第五晶体管和第七晶体管串联耦合在第二节点和接地端之间；第六晶体管和第八晶体管串联耦合在第二节点和接地端之间；第三晶体管和第五晶体管的控制端用于接收第一输入；第一晶体管和第六晶体管的控制端用于接收第二输入；第四晶体管和第七晶体管的控制端用于接收第三输入；第二晶体管和第八晶体管的控制端用于接收第四输入；第九晶体管和第十晶体管串联耦合在电源端和输出端之间，第九晶体管的控制端耦合于第五输入的反相，第十晶体管的控制端耦合于第二节点；第十一晶体管耦合在第二节点与输出端之间，第十一晶体管的控制端耦合于第五输入；第十二晶体管耦合在输出端和第五输入的反相之间，第十二晶体管的控制端耦合于第二节点；第十三晶体管耦合在输出端和第二节点之间，第十三晶体管的控制端耦合于第五输入的反相；第十四晶体管和第十五晶体管串联耦合在电源端和接地端之间，第十四晶体管和第十五晶体管的串联耦合节点耦合于第五输入的反相；第十四晶体管和第十五晶体管的控制端用于接收第五输入。上述技术方案中，提供了一种反相编码算子电路，该反相编码算子电路中晶体管的数量少、占用面积小，实现简单，从而将该算子电路应用于乘法器中时可以减小乘法器的面积。
在第三方面的一种可能的实现方式中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第九晶体管、第十晶体管、第十一晶体管和第十四晶体管是PMOS晶体管；第五晶体管、第六晶体管、第七晶体管、第八晶体管、第十二晶体管、第十三晶体管和第十五晶体管是NMOS晶体管。上述可能的实现方式中，提供的算子电路编码数据时晶体管的翻转率较小，从而将该算子电路应用于乘法器中时可以减小乘法器的功耗。
第四方面，提供一种算子电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管、第二十晶体管、第二十一晶体管和第二十二晶体管；其中，第一晶体管和第二晶体管并联耦合在电源端和第一节点之间；第三晶体管耦合在第一节点和第一输出端之间；第四晶体管耦合在第一输出端和第二节点之间；第五晶体管和第六晶体管并联耦合在第二节点和接地端之间；第七晶体管耦合在电源端和第三节点之间；第八晶体管耦合在第三节点和第一输出端之间；第九晶体管耦合在第一输出端和第四节点之间；第十晶体管耦合在第四节点和接地端之间；第十一晶体管和第十二晶体管串联耦合在第三节点和第二输出端之间；第十三晶体管和第十四晶体管串联耦合在第二输出端和第四节点之间；第十 五晶体管、第十六晶体管和第十七晶体管并联耦合在电源端和第五节点之间；第十八晶体管耦合在第五节点与第二输出端之间；第十九晶体管耦合在第二输出端与第六节点之间；第二十晶体管、第二十一晶体管和第二十二晶体管并联耦合在第六节点与接地端之间；第三晶体管、第四晶体管、第十二晶体管、第十三晶体管、第十五晶体管和第二十晶体管的控制端用于接收第一输入；第一晶体管、第五晶体管、第七晶体管、第十晶体管、第十六晶体管和第二十一晶体管的控制端用于接收第二输入；第二晶体管、第六晶体管、第八晶体管、第九晶体管、第十一晶体管、第十四晶体管、第十七晶体管和第二十二晶体管的控制端用于接收第三输入；第十八晶体管和第十九晶体管的控制端耦合于第一输出端。上述技术方案中，提供了一种反相压缩算子电路，该反相压缩算子电路中晶体管的数量少、占用面积小，实现简单，从而将该算子电路应用于乘法器中时可以减小乘法器的面积。
在第四方面的一种可能的实现方式中，第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十一晶体管、第十二晶体管、第十五晶体管、第十六晶体管、第十七晶体管和第十八晶体管是PMOS晶体管；第四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十三晶体管、第十四晶体管、第十九晶体管、第二十晶体管、第二十一晶体管和第二十二晶体管是NMOS晶体管。上述可能的实现方式中，提供的算子电路压缩数据时晶体管的翻转率较小，从而将该算子电路应用于乘法器中时可以减小乘法器的功耗。
第五方面，提供一种处理器，包括乘法器或算子电路；其中，该乘法器为上述第一方面或者第一方面的任一种可能的实现方式所提供的乘法器，该算子电路为上述第二方面至第四方面、或者第二方面至第四方面的任一种可能的实现方式所提供的算子电路。可选地，所述处理器包括神经网络处理单元。
第六方面，提供一种芯片，包括乘法器或算子电路；其中，该乘法器为上述第一方面或者第一方面的任一种可能的实现方式所提供的乘法器，该算子电路为上述第二方面至第四方面、或者第二方面至第四方面的任一种可能的实现方式所提供的算子电路。
可以理解地，上述提供的任一种处理器或芯片均包括上文所提供的乘法器或算子电路，因此，其所能达到的有益效果可参考上文所提供的乘法器或算子电路中的有益效果，此处不再赘述。
附图说明
图1为现有技术提供的一种乘法器的架构图；
图2为本申请实施例提供的一种通信设备的结构示意图；
图3为本申请实施例提供的一种乘法器的结构示意图；
图4为本申请实施例提供的一种正相编码器的逻辑框图；
图5为本申请实施例提供的一种反相编码器的逻辑框图；
图6为本申请实施例提供的一种W层反相压缩器的压缩示例图；
图7为本申请实施例提供的一种反相压缩器的逻辑框图；
图8为本申请实施例提供的一种预编码器和编码器的示例图；
图9为本申请实施例提供的另一种W层反相压缩器的压缩示例图；
图10为本申请实施例提供的一种正相编码器的电路图；
图11为本申请实施例提供的一种反相编码器的电路图；
图12为本申请实施例提供的一种反相压缩器的电路图。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。另外，本申请的实施例采用了“第一”、“第二”等字样对名称或功能或作用类似的对象进行区分，本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。“耦合”一词用于表示电性连接，包括通过导线或连接端直接相连或通过其他器件间接相连。因此“耦合”应被视为是一种广义上的电子通信连接。
图2为本申请实施例提供的一种通信设备的结构示意图，该通信设备可以是终端、或者服务器等。参见图2，该通信设备可以包括存储器201、处理器202、通信接口203和总线204。其中，存储器201、处理器202以及通信接口203通过总线204相互连接。存储器201可用于存储数据、软件程序以及模块，主要包括存储程序区和存储数据区，存储程序区可存储操作系统、至少一个功能所需的应用程序等，存储数据区可存储该设备的使用时所创建的数据等。处理器202用于对该通信设备的动作进行控制管理，比如通过运行或执行存储在存储器201内的软件程序和/或模块，以及调用存储在存储器201内的数据，执行该设备的各种功能和处理数据。通信接口203用于支持该设备进行通信。
其中，处理器202包括但不限于中央处理单元(Central Processing Unit，CPU)、网络处理单元(Network Processing Unit，NPU)、图形处理器(Graphics Processing Unit，GPU)、或数字信号处理器(Digital Signal Processor，DSP)或者通用处理器等。处理器202中包括一个或多个乘法器，例如包括乘法器阵列，该乘法器是在处理器202中实现乘法运算的器件。
总线204可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线，或者扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图2中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
为了进一步描述技术方案，图3为本申请实施例提供的一种乘法器的结构示意图，该乘法器用于实现M比特位的第一数值与N比特位的第二数值的相乘，M和N是大于1的整数。参见图3，该乘法器包括：P个预编码器301、P组编码器302、W层反相压缩器303和加法器304，P组编码器302中的每组编码器3021包括N个编码器，W是正整数，P是大于1的整数。该乘法器相对于传统设计实现简单，下面将具体介绍。
P个预编码器301中的每个预编码器3011，用于根据第一数值中的部分比特位产 生组选择信号和符号控制输入信号，从而P个预编码器301对应产生P个组选择信号和P个符号控制输入信号。其中，P个组选择信号和P个符号控制输入信号与P组编码器一一对应，即一个组选择信号和一个符号控制输入信号与一组编码器对应。组选择信号可以是根据第一数值中相邻的两个或者三个比特位产生的，符号控制输入信号可以是第一数值中的一个比特位，也可以是根据第一数值中相邻的两个或者三个比特位产生的。
比如，第一数值为4bits的二进制数且表示为a[3:0]、P等于2，则2个预编码器可以根据a[3:0]产生2个组选择信号和2个符号控制输入信号。这2个组选择信号中，第1组选择信号可以根据a[0]和a[1]产生，第2个组选择信号可以根据a[1]至a[3]产生。这2个符号控制输入信号中，第1个符号控制输入信号可以是a[1]，第2个符号控制输入信号可以是a[3]。上述a[i]表示a[3:0]中从右向左的第i个比特位，i取值从0至3。
每组编码器3021，用于采用正相编码算子或者反相编码算子编码第二数值、对应于该组编码器的组选择信号和符号控制输入信号以得到一个部分积项，P组编码器编码得到P个部分积项。
其中，每组编码器3021包括N个编码器，N个编码器中的每个编码器对应第二数值中的第一比特位和第二比特位，组选择信号包括第一信号和第二信号；则每个编码器具体可用于：采用正相编码算子或者反相编码算子编码与该编码器第一比特位、第二比特位、组选择信号和符号控制输入信号，得到一个部分积项的一个输出比特位。每组编码器3021中的N个编码器分别编码得到一个部分积项的N个输出比特位，即得到该部分积项。第一比特位和第二比特位可以是第二数值中相邻的两个比特位，或者是第二数值中的同一个比特位，后续实施例对此将进行更具体描述。
比如，第二数值为3bits的二进制数且表示为b[2:0]、N等于3，则每组编码器3021包括3个编码器。这3个编码器中，第1个编码器对应b[2:0]中的相邻两个比特位为b[0]和b[1]、第2个编码器对应b[2:0]中的相邻两个比特位为b[1]和b[2]、第3个编码器对应的第一比特位和第二比特位均为b[2:0]中的b[2]，即最后一个第3个编码器仅输入一个比特位b[2]同时作为该第一比特位和第二比特位。上述b[i]表示b[2:0]中从右向左的第i个比特位。
以上述第一数值为a[3:0]、第二数值为b[2:0]的举例为例：若第1组编码中第1个编码器对应第二数值b[2:0]中相邻两个比特位为b[0]和b[1]、对应的组选择信号为根据a[0]和a[1]产生的第一组选择信号(表示为A和B)，对应的符号控制输入信号为a[1]，则所述第1个编码器具体可用于：采用正相编码算子或者反相编码算子编码b[0]、b[1]、A、B和a[1]，得到第1个部分积项中的1个输出比特位。
具体的，当一个编码器采用正相编码算子时，该编码器可以称为正相编码器；当一个编码器采用反相编码算子时，该编码器可以称为反相编码器。下面分别对正相编码器和反相编码器进行具体描述。
正相编码器具体用于执行如下编码操作：若第一信号和第一比特位均为1、或者第二信号和第二比特位均为1，则该正相编码器得到的输出比特位为符号控制输入信号的反相；若第一信号和第一比特位中的至少一个为0、而且第二信号和第二比特位中的至少一个为0，则该正相编码器得到的输出比特位为符号控制输入信号。
图4为本申请实施例提供的一种正相编码器的逻辑框图，该逻辑框图中包括编码选通单元、取反单元和开关控制单元。该编码选通单元的功能为：若A与Sel_A同时为1、或B与Sel_B同时为1则输出1，否则输出0；该取反单元的功能为：对该编码选通单元的输出进行取反；该开关控制单元的功能为：若该取反单元的输出为1则输出S，若该取反单元的输出为0则输出/S。上述图4中的A表示第一信号、B表示第二信号、Sel_A表示第一比特位、Sel_B表示第二比特位、S表示符号控制输入信号、/S表示符号控制输入信号的反相、OUT表示输出比特位。
也即是，该正相编码器具体可以根据如下表1所示的逻辑表进行编码，表1中的x表示“0”或“1”中的任一个，A、B、Sel_A、Sel_B、S和OUT与图4中的A、B、Sel_A、Sel_B、S和OUT一致。
表1
A Sel_A B Sel_B S OUT
1 1 x x 0 1
1 1 x x 1 0
x x 1 1 0 1
x x 1 1 1 0
0 x 0 x 0 0
0 x 0 x 1 1
x 0 x 0 0 0
x 0 x 0 1 1
反相编码器，具体用于执行如下编码操作：若第一信号和第一比特位均为1、或者第二信号和第二比特位均为1，则该反相编码器得到的输出比特位为符号控制输入信号；若第一信号和第一比特位中的至少一个为0、而且第二信号和第二比特位中的至少一个为0，则该反相编码器得到的输出比特位为符号控制输入信号的反相。
图5为本申请实施例提供的一种反相编码器的逻辑框图，该逻辑框图中包括编码选通单元、取反单元和开关控制单元。该编码选通单元的功能为：若A与Sel_A同时为1、或B与Sel_B同时为1则输出1，否则输出0；该取反单元的功能为：对该编码选通单元的输出进行取反；该开关控制单元的功能为：若该取反单元的输出为0则输出S，若该取反单元的输出为1则输出/S。上述图5中的A表示第一信号、B表示第二信号、Sel_A表示第一比特位、Sel_B表示第二比特位、S表示符号控制输入信号、/S表示符号控制输入信号的反相、OUT表示输出比特位。
也即是，反相编码器具体可以根据如下表2所示的逻辑表进行编码，表2中的x表示“0”或“1”中的任一个，A、B、Sel_A、Sel_B、S和OUT与图5中的A、B、Sel_A、Sel_B、S和OUT一致。
表2
A Sel_A B Sel_B S OUT
1 1 x x 0 0
1 1 x x 1 1
x x 1 1 0 0
x x 1 1 1 1
0 x 0 x 0 1
0 x 0 x 1 0
x 0 x 0 0 1
x 0 x 0 1 0
W层反相压缩器303，用于采用反相压缩算子压缩P个部分积项，得到两个累加值。
具体的，当W为1时，W层反相压缩器303包括：第一层反相压缩器，用于按照从低数位到高数位顺序依次对P个部分积项的排列阵列中每个数位采用反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到包括两行的第一压缩阵列，每行对应一个累加值。当W是大于1的整数时，W层反相压缩器303包括：第一层反相压缩器至第W层反相压缩器；第一层反相压缩器，用于按照从低数位到高数位顺序依次对P个部分积项的排列阵列中每个数位采用反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到第一压缩阵列；第i层反相压缩器，用于按照从低数位到高数位顺序依次对第i-1压缩阵列中每个数位采用反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到第i压缩阵列，i的取值范围依次从2至W，第W压缩阵列包括两行，每行对应一个累加值。
其中，每层反相压缩器对每个数位的压缩是针对该数位上的三个比特位进行的，且不压缩该层反相压缩器压缩得到的进位输出位和当前求和位。P个部分积项的排列阵列中的每行包括一个部分积项，每列包括P个部分积项中对应同一数位的多个比特位对每个数位的压缩是针对该数位上的三个比特位进行的；其中，P个部分积项的排列阵列中的每行包括一个部分积项，每列包括P个部分积项中对应同一数位的多个比特位。
比如，假设P组编码器编码得到8个部分积项，每个部分积项包括16个比特位，则这8个部分积项的排列阵列可以如图6中的(a)所示，PP[1]至PP[8]分别表示8个部分积项，2 0、2 1、2 1、…、2 32表示不同的数位。数位是针对所述W层反相压缩器的输出结果而言的。类似于十进制中的个位、十位或百位，该数位用于表示输出结果的二进制数值中的一个位，例如W层反相压缩器的输出结果是32位二进制数，则输出结果包括32个数位。与数位相对的，比特位则对应0或1，表示一个二进制的信息。可以认为，一个数位是所述W层反相压缩器的输出结果中的一个比特位。
为便于理解，将图6中的(a)转换为图6中的(b)所示，对W层反相压缩器303中的每层反相压缩器的压缩过程进行举例说明。具体的，输出的结果有32个数位，第一层反相压缩器具体用于对该排列阵列中2 4至2 29中的每个数位对应的比特位，按每三个比特位进行压缩、不足三个比特位的保留，除2 4至2 29之外的其他数位对应的比特位不足三个比特位也保留，图6中的(b)中的每个实线矩形方框可用于表示第一层反相压缩器中的一个反相压缩器，第一层反相压缩器压缩得到的第1压缩阵列如图6中的(c)所示，图中的
Figure PCTCN2019119993-appb-000001
表示第一层反相压缩器输出的当前求和输出位，○表示第一层反相压缩器输出的进位输出位；第二层反相压缩器具体用于对第1压缩阵列中2 6至 2 23、以及2 26中的每个数位对应的比特位，按每三个比特位进行压缩、不足三个比特位的保留，除2 6至2 23、以及2 26之外的其他数位对应的比特位不足三个比特位也保留，图6中的(c)中的每个矩形方框可用于表示第二层反相压缩器中的一个反相压缩器，第二层反相压缩器压缩得到的第2压缩阵列如图6中的(d)所示，图中的
Figure PCTCN2019119993-appb-000002
表示第二层反相压缩器输出的当前求和输出位，◎表示第二层反相压缩器输出的进位输出位。后续第三层反相压缩器至第W层反相压缩器的具体压缩过程与上述第一层反相压缩器和第二层反相压缩器的具体压缩过程类似，本申请实施例在此不再赘述。
对每个数位的每三个比特位，每个反相压缩器具体用于进行以下压缩：若所述三个比特位均为0，则进位输出位为1，当前求和输出位为1；若所述三个比特位均为1，则进位输出位为0，当前求和输出位为0；若所述三个比特位中存在一个比特位为1、另外两个比特位为0，则进位输出位为1，当前求和输出位为0；若所述三个比特位中存在两个比特位为1、另外一个比特位为0，则进位输出位为0，当前求和输出位为1。
其中，进位输出位是指向当前压缩数位的下一数位的输出位，当前求和输出位是指当前压缩数位压缩后的输出位。比如，假设当前压缩数位为2 5、当前压缩数位的下一数位为2 6、对2 5的三个比特位，若这三个比特位均为0，则压缩后2 5对应产生1个1，2 6对应产生一个1。
图7为本申请实施例提供的一种反相压缩器的逻辑框图，该逻辑框图中包括反相进位输出单元和反相求和输出单元。该反相进位输出单元的功能为：若Ai、Bi和Ci中至少有2个有效(有效可以为1，也可以为0)，则输出无效(若有效为1，则无效为0，若有效为0，则无效为1)，否则输出有效。该反相求和输出单元的功能为：若Ai、Bi和Ci中存在2个有效、或全无效，则输出有效，否则输出无效，输入该反相求和输出单元的nCip1在有效时可用于区分Ai、Bi和Ci是2个有效还是全无效。上述图7中的Ai、Bi和Ci分别表示输入的三个比特位，nCip1表示进位输出位，nSi表示当前求和输出位。也即是，每层反相压缩器具体可以根据如下表3所示的逻辑表进行压缩，表3中的Ai、Bi和Ci分别表示输入的所述三个比特位，nCip1表示进位输出位，nSi表示当前求和输出位。
表3
Ai Bi Ci nCip1 nSi
0 0 0 1 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 0 0
进一步的，该乘法器还可以包括：一个或多个反相器，用于对W层反相压缩器303中的一个或多个反相压缩器输出的当前求和输出位和进位输出位的相位取反、或 对输入所述一个或多个反相压缩器的所述三个比特位中至少一个比特位的相位取反。
其中，W层反相压缩器303可以包括多层反相压缩器，多层反相压缩器中的每层可以包括至少一个反相压缩器，每个反相压缩器的输出相位可以根据需求进行设定，且每个反相压缩器的输出相位与输入相位是相反的，从而每个反相压缩器的输入相位也被设定。
需要说明的是，一个反相压缩器的输出相位可以是指该反相压缩器输出的当前求和输出位和进位输出位的相位，且当前求和输出位和进位输出位的相位是相同的，即同为正相或反相。一个反相压缩器的输入相位可以是指设定的输入该反相压缩器的所述三个比特位的相位，且设定的所述三个比特位的相位是相同的，即同为正相或反相。
当W层反相压缩器303中的一个或多个反相压缩器本身的输出相位与设定的输出相位不同时，所述一个或者多个反相器可用于对这一个或多个反相压缩器输出的当前求和输出位和进位输出位的相位取反，以使其与设定的输出相位一致。同理，当输入一个或多个反相压缩器的所述三个比特位中至少一个比特位的相位与设定的输入相位不同时，所述一个或者多个反相器可用于对输入所述一个或多个反相压缩器的所述三个比特位中至少一个比特位的相位取反，以使其与设定的输入相位一致。
在一种可能的实现方式中，每层反相压缩器包括的至少一个反相压缩器的输出相位可以按照如下方式设定：最后一层反相压缩器的输出相位设定为正相，倒数第二层反相压缩器的输出相位设定为反相，倒数第三层反相压缩器的输出相位设定为正相，……，以此类推，直到设定第一层反相压缩器的输出相位。这里的第一层反相压缩器可以是指按照从上到下的顺序、对每个数位对应的多个比特位进行压缩时的最上层的反相压缩器，第二层反相压缩器可以是指次上层的反相压缩器，……，以此类推。比如，W层反相压缩器303包括4层反相压缩器，则可以按照如下方式设定：第4层反相压缩器的输出相位设定为正相，第3层反相压缩器的输出相位设定为反相，第2层反相压缩器的输出相位设定为正相，第1层反相压缩器的输出相位设定为反相。
可选的，当某一反相压缩器本身的输出相位或输入相位、与设定的输出相位或输入相位不一致，且需要至少三个反相器进行取反才能满足时，可以局部调整该反相压缩器的输出相位的设定，来减少需要的反相器的数量。比如，当某一反相压缩器设定的输出相位为正相(此时该反相压缩器设定的输入相位为反相)时，若该该反相压缩器本身的输出相位为正相、且输入该反相压缩器的所述三个比特位本身的相位也为正相，则该反相压缩器需要三个反相器分别对所述三个比特位的相位取反之后，才能满足设定的输出相位和输入相位的要求；此时，通过重新设定该反相压缩器的输出相位为反相(此时该反相压缩器设定的输入相位为正相)，则该反相压缩器只需要两个反相器对两个输出位(即当前求和输出位和进位输出位)的输出相位取反之后，即可满足设定的输出相位和输入相位的要求。
进一步的，P组编码器302中的至少一个编码器采用的编码算子的相位与W层反相压缩器303中至少一层反相压缩器输出的当前求和输出位或进位输出位的相位有关。可选的，设定至少一个编码器中每个编码器采用的编码算子的相位与自身连接的反相压缩器的输入相位相同。其中，每个编码器采用的编码算子的相位可以是正相或反相。当一个编码器采用的编码算子的相位是正相(即采用正相编码算子)时，该编 码器即为上述正相编码器；当一个编码器采用的编码算子的相位是反相(即采用反相编码算子)时，该编码器即为上述反相编码器。
加法器304，用于接收上述两个累加值，并对这两个累加值求和以得到所述乘积。在W层反相压缩器303压缩P个部分积项得到这两个累加值后，W层反相压缩器303可以将这两个累加值发送给加法器304，加法器304在接收到这两个累加值时，对这两个累加值求和即可得到第一数值与第二数值的乘积。
为便于理解，下面以第一数值为a[10:0]、第二数值为b[12:0]为例，对本申请所述的乘法器进行举例说明。如图8所示，该乘法器可以包括6个预编码器、6组编码器和3层反相压缩器。
具体的，第1个预编码器用于根据a[0]和a[1]产生组选择信号S0和S1、以及符号控制输入信号a[1]；第2个预编码器用于根据a[1]、a[2]和a[3]产生组选择信号S2和S3、以及符号控制输入信号a[3]；第3个预编码器用于根据a[3]、a[4]和a[5]产生组选择信号S4和S5、以及符号控制输入信号a[5]；第4个预编码器用于根据a[5]、a[6]和a[7]产生组选择信号S6和S7、以及符号控制输入信号a[7]；第5个预编码器用于根据a[7]、a[8]和a[9]产生组选择信号S8和S9、以及符号控制输入信号a[9]；第6个预编码器用于根据a[9]和a[10]产生组选择信号S10、以及符号控制输入信号S_11。相应的，第1组编码器用于编码b[12:0]、S0、S1和a[1]，得到第1个部分积项PP[1]；第2组编码器用于编码b[12:0]、S2、S3和a[3]，得到第2个部分积项PP[2]；第3组编码器用于编码b[12:0]、S4、S5和a[5]，得到第3个部分积项PP[3]；第4组编码器用于编码b[12:0]、S6、S7和a[7]，得到第4个部分积项PP[4]；第5组编码器用于编码b[12:0]、S8、S9和a[9]，得到第5个部分积项PP[5]；第6组编码器用于编码b[12:0]、S10和S_11，得到第6个部分积项PP[6]。其中，每组编码器中的每个编码器分别用于编码b[12:0]中的一个比特位或者两个比特位，以及对应的组选择信号和符号控制输入信号，具体可以参见图8所示。最后，这6个部分积项PP[1]至PP[6]对应的排列阵列可以如图9所示，按照上述乘法器中W层反相压缩器303的相关描述，可以通过3层反相压缩器对图9所示的排列阵列进行压缩，详细的压缩过程与上述图6中的相关描述类似，本申请实施例在此不再赘述。
本申请实施例提供的乘法器中，P个预编码器中可以包括结构不同的预编码器，比如图8中的第1个预编码器包括非门和与门，第2至第5个预编码器包括异或门、同或门和或非门，第6个预编码器包括异或门和与门。另外，本申请实施例中同一组编码器的第1个编码器可以与其他编码器的结构不同，不同组的编码器的结构也可以不同，比如，图8中第1至第5组编码器的第1个编码器包括与门和异或门，第2-第13个编码器为正相编码器或者反相编码器，第6组编码器的每个编码器包括与门和同或门。
需要说明的是，图8中的PP[1]_i(i的取值范围为1至14)表示第一个部分积项PP[1]的第i个比特位，A表示第一信号，B表示第二信号，Sel_A表示第一比特位，Sel_B表示第二比特位，S表示符号控制输入信号，OUT表示输出比特位。
图10为本申请实施例提供的一种正相编码算子电路的结构示意图，该正相编码算子电路也可以称为正相编码器。该正相编码器包括：第一晶体管M1、第二晶体管M2、 第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14和第十五晶体管M15。
其中，第一晶体管M1和第二晶体管M2并联耦合在电源端和第一节点①之间；第三晶体管M3和第四晶体管M4并联耦合在第一节点①和第二节点②之间；第五晶体管M5和第七晶体管M7串联耦合在第二节点②和接地端之间；第六晶体管M6和第八晶体管M8串联耦合在第二节点②和接地端之间。第三晶体管M3和第五晶体管M5的控制端用于接收第一输入A；第一晶体管M1和第六晶体管M6的控制端用于接收第二输入Sel_A；第四晶体管M4和第七晶体管M7的控制端用于接收第三输入B；第二晶体管M2和第八晶体管M8的控制端用于接收第四输入Sel_B。
第九晶体管M9耦合在第五输入S的反相/S和输出端OUT之间，第九晶体管M9的控制端耦合于第二节点②，第二节点②的信号为/Y；第十晶体管M10耦合在第二节点②和输出端OUT之间，第十晶体管M10的控制端耦合于第五输入S的反相/S；第十一晶体管M11和第十三晶体管M13串联耦合在输出端OUT和接地端之间。第十一晶体管M11的控制端耦合于第二节点②；第十三晶体管M13的控制端用于接收第五输入S的反相/S；第十二晶体管M12耦合在输出端OUT和第二节点②之间，第十二晶体管M12的控制端用于接收第五输入S；第十四晶体管M14和第十五晶体管M15串联耦合在电源端和接地端之间，第十四晶体管M14和第十五晶体管M15的串联耦合节点耦合于第五输入S的反相/S；第十四晶体管M14和第十五晶体管M15的控制端用于接收第五输入S。
在本申请实施例中，上述第一输入A至第五输入S分别可以是上述乘法器实施例中关于正相编码器的相关描述中的第一信号、第一比特位、第二信号、第二比特位和符号控制输入信号。
可选的，第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第九晶体管M9、第十晶体管M10和第十四晶体管M14是PMOS晶体管；第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13和第十五晶体管M15是NMOS晶体管。相应的，上述控制端具体可以是指相应的PMOS晶体管或者NMOS晶体管的栅极。
需要说明的是，上述举例的第一晶体管M1至第十五晶体管M15可以是MOS晶体管，也可以是用双极型晶体管代替，图10中所示的各晶体管的类型仅为示例性的，并不对本申请实施例构成限制。
图11为本申请实施例提供的一种反相编码算子电路的结构示意图，该反相编码算子电路也可以称为反相编码器。该反相编码器包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14和第十五晶体管M15。
其中，第一晶体管M1和第二晶体管M2并联耦合在电源端和第一节点①之间；第三晶体管M3和第四晶体管M4并联耦合在第一节点①和第二节点②之间；第五晶体管M5和第七晶体管M7串联耦合在第二节点②和接地端之间；第六晶体管M6和第 八晶体管M8串联耦合在第二节点②和接地端之间；第三晶体管M3和第五晶体管M5的控制端用于接收第一输入A；第一晶体管M1和第六晶体管M6的控制端用于接收第二输入Sel_A；第四晶体管M4和第七晶体管M7的控制端用于接收第三输入B；第二晶体管M2和第八晶体管M8的控制端用于接收第四输入Sel_B。
第九晶体管M9和第十晶体管M10串联耦合在电源端和输出端OUT之间，第九晶体管M9的控制端耦合于第五输入S的反相/S，第十晶体管M10的控制端耦合于第二节点②，第二节点②的信号为/Y；第十一晶体管M11耦合在第二节点②与输出端OUT之间，第十一晶体管M11的控制端耦合于第五输入S；第十二晶体管M12耦合在输出端OUT和第五输入S的反相/S之间，第十二晶体管M12的控制端耦合于第二节点②；第十三晶体管M13耦合在输出端OUT和第二节点②之间，第十三晶体管M13的控制端耦合于第五输入S的反相/S；第十四晶体管M14和第十五晶体管M15串联耦合在电源端和接地端之间，第十四晶体管M14和第十五晶体管M15的串联耦合节点耦合于第五输入S的反相/S；第十四晶体管M14和第十五晶体M15管的控制端用于接收第五输入S。
在本申请实施例中，上述第一输入A至第五输入S分别可以是上述乘法器实施例中关于反相编码器的相关描述中的第一信号、第一比特位、第二信号、第二比特位和符号控制输入信号。
可选的，第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第九晶体管M9、第十晶体管M10、第十一晶体管M11和第十四晶体管M14是PMOS晶体管；第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第十二晶体管M12、第十三晶体管M13和第十五晶体管M15是NMOS晶体管。相应的，上述控制端具体可以是指相应的PMOS晶体管或者NMOS晶体管的栅极。
需要说明的是，上述举例的第一晶体管M1至第十五晶体管M15可以是MOS晶体管，也可以是用双极型晶体管代替，图11中所示的各晶体管的类型仅为示例性的，并不对本申请实施例构成限制。
图12为本申请实施例提供的一种反相压缩算子电路的结构示意图，该反相压缩算子电路也可以称为反相压缩器。该反相压缩器包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15、第十六晶体管M16、第十七晶体管M17、第十八晶体管M18、第十九晶体管M19、第二十晶体管M20、第二十一晶体管M21和第二十二晶体管M22。
其中，第一晶体管M1和第二晶体管M2并联耦合在电源端和第一节点①之间；第三晶体管M3耦合在第一节点①和第一输出端nCip1之间；第四晶体管M4耦合在第一输出端nCip1和第二节点②之间；第五晶体管M5和第六晶体管M6并联耦合在第二节点②和接地端之间；第七晶体管M7耦合在电源端和第三节点③之间；第八晶体管M8耦合在第三节点③和第一输出端nCip1之间；第九晶体管M9耦合在第一输出端nCip1和第四节点④之间；第十晶体管M10耦合在第四节点④和接地端之间；第十一晶体管M11和第十二晶体管M12串联耦合在第三节点③和第二输出端nSi之间； 第十三晶体管M13和第十四晶体管M14串联耦合在第二输出端nSi和第四节点④之间；第十五晶体管M15、第十六晶体管M16和第十七晶体管M17并联耦合在电源端和第五节点⑤之间；第十八晶体管M18耦合在第五节点⑤与第二输出端nSi之间；第十九晶体管M19耦合在第二输出端nSi与第六节点⑥之间；第二十晶体管M20、第二十一晶体管M21和第二十二晶体管M22并联耦合在第六节点⑥与接地端之间。
第三晶体管M3、第四晶体管M4、第十二晶体管M12、第十三晶体管M13、第十五晶体管M15和第二十晶体管M20的控制端用于接收第一输入Ai；第一晶体管M1、第五晶体管M5、第七晶体管M7、第十晶体管M10、第十六晶体管M16和第二十一晶体管M21的控制端用于接收第二输入Bi；第二晶体管M2、第六晶体管M6、第八晶体管M8、第九晶体管M9、第十一晶体管M11、第十四晶体管M14、第十七晶体管M17和第二十二晶体管M22的控制端用于接收第三输入Ci；第十八晶体管M18和第十九晶体管M19的控制端耦合于第一输出端nCip1。
在本申请实施例中，上述第一输入Ai、第二输入Bi和第三输入Ci可以是上述乘法器实施例中关于反相压缩器的相关描述中的所述三个比特位，第一输出端nCip1可以用于输出所述反相压缩器的进位输出位，第二输出端nSi可以用于输出所述反相压缩器的当前求和输出位。
可选的，第一晶体管M1、第二晶体管M2、第三晶体管M3、第七晶体管M7、第八晶体管M8、第十一晶体管M11、第十二晶体管M12、第十五晶体管M15、第十六晶体管M16、第十七晶体管M17和第十八晶体管M18是PMOS晶体管；第四晶体管M4、第五晶体管M5、第六晶体管M6、第九晶体管M9、第十晶体管M10、第十三晶体管M13、第十四晶体管M14、第十九晶体管M19、第二十晶体管M20、第二十一晶体管M21和第二十二晶体管M22是NMOS晶体管。相应的，上述控制端具体可以是指相应的PMOS晶体管或者NMOS晶体管的栅极。
需要说明的是，上述举例的第一晶体管M1至第二十二晶体管M22可以是MOS晶体管，也可以用双极型晶体管代替，图12中所示的各晶体管的类型仅为示例性的，并不对本申请实施例构成限制。
本申请实施例将采用上文所提供的正相编码器、反相编码器和反相压缩器的乘法器与现有基于标准编码器和标准加法器的乘法器进行了比较，具体如下表4和表5所示，作为本申请的一个实施例，其不限定于以下具体参数值。
表4
Figure PCTCN2019119993-appb-000003
从表4中可以看出，每个标准编码器使用的晶体管数量为22、占用面积为0.2736、 面积收益为1.18，每个正相编码器或反相编码器使用的晶体管数量为15、占用面积为0.23256、面积收益为1，每个标准加法器使用的晶体管数量为28、占用面积为0.2736、面积收益为1.10，每个反相压缩器使用的晶体管数量为24、占用面积为0.24816、面积收益为1。因此，本申请实施例提供的乘法器的面积小。
表5
Figure PCTCN2019119993-appb-000004
从表5中可以看出，标准编码器每编码1bit数据翻转4次、静态功耗为0.44522、静态功耗的收益为1.18、动态功耗的收益为1.09，正相编码器或反相编码器每编码1bit数据翻转3次、静态功耗为0.4084、静态功耗和动态功耗的收益均为1，标准加法器每压缩1bit数据翻转4次、静态功耗为0.57685、静态功耗的收益为1.10、动态功耗的收益为1.80，反相压缩器每压缩1bit数据翻转2次、静态功耗为0.32122、静态功耗和动态功耗的收益均为1。因此，本申请实施例提供的乘法器的功耗小。
本申请实施例提供的乘法器中的编码器通过采用正相编码算子或者反相编码算子进行编码，即该乘法器采用正相编码器或反相编码器进行编码，以及压缩器通过采用反相压缩器进行压缩，其实现方案比较简单，例如能够减小乘法器中MOS晶体管的数量，从而减小乘法器的面积。此外，该乘法器每编码或压缩1bit数据时对应的编码器或压缩器的翻转次数较小，从而该乘法器的功耗小。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种乘法器，其特征在于，用于实现M比特位的第一数值与N比特位的第二数值的相乘，M和N是大于1的整数，包括：P组编码器和W层反相压缩器，所述P组编码器中的每组编码器包括N个编码器，W是正整数，P是大于1的整数；
    所述每组编码器，用于采用正相编码算子或者反相编码算子编码所述第二数值中的部分比特位、对应于所述每组编码器的组选择信号和符号控制输入信号以得到一个部分积项，所述组选择信号和所述符号控制输入信号是根据所述第一数值中的部分比特位产生的，所述P组编码器编码得到P个部分积项；
    所述W层反相压缩器，用于采用反相压缩算子压缩所述P个部分积项，得到两个累加值，所述两个累加值之和为所述第一数值与所述第二数值的乘积。
  2. 根据权利要求1所述的乘法器，其特征在于，所述N个编码器中每个编码器对应所述第二数值中的第一比特位和第二比特位，所述组选择信号包括第一信号和第二信号；所述每个编码器，具体用于：采用正相编码算子或者反相编码算子编码所述第一比特位、所述第二比特位、所述组选择信号和所述符号控制输入信号得到一个部分积项的一个输出比特位。
  3. 根据权利要求2所述的乘法器，其特征在于，当一个编码器采用正相编码算子时，该编码器是正相编码器，且具体用于执行如下编码操作：
    若所述第一信号和所述第一比特位均为1、或者所述第二信号和所述第二比特位均为1，则该编码器得到的所述输出比特位为所述符号控制输入信号的反相；
    若所述第一信号和所述第一比特位中的至少一个为0、而且所述第二信号和所述第二比特位中的至少一个为0，则该编码器得到的所述输出比特位为所述符号控制输入信号。
  4. 根据权利要求2所述的乘法器，其特征在于，当一个编码器采用反相编码算子时，该编码器是反相编码器，且具体用于执行如下编码操作：
    若所述第一信号和所述第一比特位均为1、或者所述第二信号和所述第二比特位均为1，则该编码器得到的所述输出比特位为所述符号控制输入信号；
    若所述第一信号和所述第一比特位中的至少一个为0、而且所述第二信号和所述第二比特位中的至少一个为0，则该编码器得到的所述输出比特位为所述符号控制输入信号的反相。
  5. 根据权利要求1-4任一项所述的乘法器，其特征在于，W为1，所述W层反相压缩器包括：第一层反相压缩器；
    所述第一层反相压缩器，用于按照从低数位到高数位顺序依次对所述P个部分积项的排列阵列中每个数位采用所述反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到包括两行的第一压缩阵列，每行对应一个累加值；
    对每个数位的压缩是针对该数位上的每三个比特位进行的；所述P个部分积项的排列阵列中的每行包括一个部分积项，每列包括所述P个部分积项中对应同一数位的多个比特位。
  6. 根据权利要求1-4任一项所述的乘法器，其特征在于，W是大于1的整数，所 述W层反相压缩器包括：第一层反相压缩器至第W层反相压缩器；
    所述第一层反相压缩器，用于按照从低数位到高数位顺序依次对所述P个部分积项的排列阵列中每个数位采用所述反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到第一压缩阵列；
    所述第i层反相压缩器，用于按照从低数位到高数位顺序依次对第i-1压缩阵列中每个数位采用所述反相压缩算子进行压缩，直到每个数位对应的剩余比特位少于三个，得到第i压缩阵列，i的取值范围依次从2至W；
    所述第W压缩阵列包括两行，每行对应一个累加值；
    其中，每层反相压缩器对每个数位的压缩是针对该数位上的三个比特位进行的；所述P个部分积项的排列阵列中的每行包括一个部分积项，每列包括所述P个部分积项中对应同一数位的多个比特位。
  7. 根据权利要求5或6所述的乘法器，其特征在于，对每个数位的三个比特位，每个反相压缩器具体用于进行以下压缩：
    若所述三个比特位均为0，则进位输出位为1，当前求和输出位为1；
    若所述三个比特位均为1，则进位输出位为0，当前求和输出位为0；
    若所述三个比特位中存在一个比特位为1、另外两个比特位为0，则进位输出位为1，当前求和输出位为0；
    若所述三个比特位中存在两个比特位为1、另外一个比特位为0，则进位输出位为0，当前求和输出位为1。
  8. 根据权利要求7所述的乘法器，其特征在于，同一数位对应的编码器采用的编码算子的相位与反相压缩器输出的当前求和输出位或进位输出位的相位有关；
    其中，该同一数位对应的编码器是指编码得到该同一数位对应的输出比特位的编码器，该同一数位对应的反相压缩器是指压缩该同一数位的三个比特位的反相压缩器。
  9. 根据权利要求8所述的乘法器，其特征在于，所述乘法器还包括：
    一个或多个反相器，用于对所述W层反相压缩器中的一个或多个反相压缩器输出的当前求和输出位和进位输出位的相位取反、或对输入所述一个或多个反相压缩器的所述三个比特位中至少一个比特位的相位取反。
  10. 根据权利要求1-9任一项所述的乘法器，其特征在于，所述乘法器还包括：
    预编码器，用于接收所述第一数值，并根据所述第一数值中的所述部分比特位产生所述组选择信号和所述符号控制输入信号。
  11. 根据权利要求1-10任一项所述的乘法器，其特征在于，所述乘法器还包括：
    加法器，用于接收所述两个累加值，并对所述两个累加值求和以得到所述乘积。
  12. 一种算子电路，其特征在于，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管和第十五晶体管；其中，
    所述第一晶体管和所述第二晶体管并联耦合在电源端和第一节点之间；
    所述第三晶体管和所述第四晶体管并联耦合在所述第一节点和第二节点之间；
    所述第五晶体管和所述第七晶体管串联耦合在所述第二节点和接地端之间；
    所述第六晶体管和所述第八晶体管串联耦合在所述第二节点和所述接地端之间；
    所述第三晶体管和所述第五晶体管的控制端用于接收第一输入；
    所述第一晶体管和所述第六晶体管的控制端用于接收第二输入；
    所述第四晶体管和所述第七晶体管的控制端用于接收第三输入；
    所述第二晶体管和所述第八晶体管的控制端用于接收第四输入；
    所述第九晶体管耦合在第五输入的反相和输出端之间，所述第九晶体管的控制端耦合于所述第二节点；
    所述第十晶体管耦合在所述第二节点和所述输出端之间，所述第十晶体管的控制端耦合于所述第五输入的反相；
    所述第十一晶体管和所述第十三晶体管串联耦合在所述输出端和所述接地端之间；
    所述第十一晶体管的控制端耦合于所述第二节点；
    所述第十三晶体管的控制端用于接收所述第五输入的反相；
    所述第十二晶体管耦合在所述输出端和所述第二节点之间，所述第十二晶体管的控制端用于接收所述第五输入；
    所述第十四晶体管和所述第十五晶体管串联耦合在所述电源端和所述接地端之间，所述第十四晶体管和所述第十五晶体管的串联耦合节点耦合于所述第五输入的反相；
    所述第十四晶体管和所述第十五晶体管的控制端用于接收所述第五输入。
  13. 根据权利要求12所述的算子电路，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第九晶体管、所述第十晶体管和所述第十四晶体管是PMOS晶体管；
    所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管和所述第十五晶体管是NMOS晶体管。
  14. 一种算子电路，其特征在于，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管和第十五晶体管；其中，
    所述第一晶体管和所述第二晶体管并联耦合在电源端和第一节点之间；
    所述第三晶体管和所述第四晶体管并联耦合在所述第一节点和第二节点之间；
    所述第五晶体管和所述第七晶体管串联耦合在所述第二节点和接地端之间；
    所述第六晶体管和所述第八晶体管串联耦合在所述第二节点和所述接地端之间；
    所述第三晶体管和所述第五晶体管的控制端用于接收第一输入；
    所述第一晶体管和所述第六晶体管的控制端用于接收第二输入；
    所述第四晶体管和所述第七晶体管的控制端用于接收第三输入；
    所述第二晶体管和所述第八晶体管的控制端用于接收第四输入；
    所述第九晶体管和所述第十晶体管串联耦合在所述电源端和输出端之间，所述第九晶体管的控制端耦合于第五输入的反相，所述第十晶体管的控制端耦合于所述第二 节点；
    所述第十一晶体管耦合在所述第二节点与所述输出端之间，所述第十一晶体管的控制端耦合于所述第五输入；
    所述第十二晶体管耦合在所述输出端和所述第五输入的反相之间，所述第十二晶体管的控制端耦合于所述第二节点；
    所述第十三晶体管耦合在所述输出端和所述第二节点之间，所述第十三晶体管的控制端耦合于所述第五输入的反相；
    所述第十四晶体管和所述第十五晶体管串联耦合在所述电源端和所述接地端之间，所述第十四晶体管和所述第十五晶体管的串联耦合节点耦合于所述第五输入的反相；
    所述第十四晶体管和所述第十五晶体管的控制端用于接收所述第五输入。
  15. 根据权利要求14所述的算子电路，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管和所述第十四晶体管是PMOS晶体管；
    所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第十二晶体管、所述第十三晶体管和所述第十五晶体管是NMOS晶体管。
  16. 一种算子电路，其特征在于，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管、第二十晶体管、第二十一晶体管和第二十二晶体管；其中，
    所述第一晶体管和所述第二晶体管并联耦合在电源端和第一节点之间；
    所述第三晶体管耦合在所述第一节点和第一输出端之间；
    所述第四晶体管耦合在所述第一输出端和第二节点之间；
    所述第五晶体管和所述第六晶体管并联耦合在所述第二节点和接地端之间；
    所述第七晶体管耦合在所述电源端和第三节点之间；
    所述第八晶体管耦合在所述第三节点和所述第一输出端之间；
    所述第九晶体管耦合在所述第一输出端和第四节点之间；
    所述第十晶体管耦合在所述第四节点和所述接地端之间；
    所述第十一晶体管和所述第十二晶体管串联耦合在所述第三节点和第二输出端之间；
    所述第十三晶体管和所述第十四晶体管串联耦合在所述第二输出端和所述第四节点之间；
    所述第十五晶体管、所述第十六晶体管和所述第十七晶体管并联耦合在所述电源端和第五节点之间；
    所述第十八晶体管耦合在所述第五节点与所述第二输出端之间；
    所述第十九晶体管耦合在所述第二输出端与第六节点之间；
    所述第二十晶体管、所述第二十一晶体管和所述第二十二晶体管并联耦合在所述第六节点与所述接地端之间；
    所述第三晶体管、所述第四晶体管、所述第十二晶体管、所述第十三晶体管、所述第十五晶体管和所述第二十晶体管的控制端用于接收第一输入；
    所述第一晶体管、所述第五晶体管、所述第七晶体管、所述第十晶体管、所述第十六晶体管和所述第二十一晶体管的控制端用于接收第二输入；
    所述第二晶体管、所述第六晶体管、所述第八晶体管、所述第九晶体管、所述第十一晶体管、所述第十四晶体管、所述第十七晶体管和所述第二十二晶体管的控制端用于接收第三输入；
    所述第十八晶体管和所述第十九晶体管的控制端耦合于所述第一输出端。
  17. 根据权利要求16所述的算子电路，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第七晶体管、所述第八晶体管、所述第十一晶体管、所述第十二晶体管、所述第十五晶体管、所述第十六晶体管、所述第十七晶体管和所述第十八晶体管是PMOS晶体管；
    所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第九晶体管、所述第十晶体管、所述第十三晶体管、所述第十四晶体管、所述第十九晶体管、所述第二十晶体管、所述第二十一晶体管和所述第二十二晶体管是NMOS晶体管。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023015442A1 (zh) * 2021-08-10 2023-02-16 华为技术有限公司 一种乘法器
EP4336345A4 (en) * 2021-07-30 2024-10-02 Huawei Tech Co Ltd ACCUMULATOR, MULTIPLIER AND OPERATOR CIRCUIT

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6877022B1 (en) * 2001-02-16 2005-04-05 Texas Instruments Incorporated Booth encoding circuit for a multiplier of a multiply-accumulate module
US20150193203A1 (en) * 2014-01-07 2015-07-09 Nvidia Corporation Efficiency in a fused floating-point multiply-add unit
CN107977191A (zh) * 2016-10-21 2018-05-01 中国科学院微电子研究所 一种低功耗并行乘法器
CN110058840A (zh) * 2019-03-27 2019-07-26 西安理工大学 一种基于4-Booth编码的低功耗乘法器

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL179619C (nl) * 1974-04-18 1987-05-18 Philips Nv Digitale signaalverwerkingsinrichting voor het realiseren van een vooraf bepaalde overdrachtskarakteristiek.
US4153938A (en) * 1977-08-18 1979-05-08 Monolithic Memories Inc. High speed combinatorial digital multiplier
US4730340A (en) * 1980-10-31 1988-03-08 Harris Corp. Programmable time invariant coherent spread symbol correlator
JP3153370B2 (ja) * 1993-01-14 2001-04-09 三菱電機株式会社 乗算装置
US6195392B1 (en) * 1998-06-30 2001-02-27 U.S. Philips Corporation Method and arrangement for generating program clock reference values (PCRS) in MPEG bitstreams
KR20010019352A (ko) * 1999-08-26 2001-03-15 윤종용 곱셈기의 압축기
JP4177125B2 (ja) 2003-01-22 2008-11-05 三菱電機株式会社 演算装置及び演算装置の演算方法
US7028068B1 (en) * 2003-02-04 2006-04-11 Advanced Micro Devices, Inc. Alternate phase dual compression-tree multiplier
US8064520B2 (en) * 2003-09-07 2011-11-22 Microsoft Corporation Advanced bi-directional predictive coding of interlaced video
US20110064214A1 (en) * 2003-09-09 2011-03-17 Ternarylogic Llc Methods and Apparatus in Alternate Finite Field Based Coders and Decoders
US8577026B2 (en) * 2010-12-29 2013-11-05 Ternarylogic Llc Methods and apparatus in alternate finite field based coders and decoders
US20140055290A1 (en) * 2003-09-09 2014-02-27 Peter Lablans Methods and Apparatus in Alternate Finite Field Based Coders and Decoders
CN100405288C (zh) * 2004-05-27 2008-07-23 扬智科技股份有限公司 乘法器的符号延伸方法及结构
JP4988627B2 (ja) 2008-03-05 2012-08-01 ルネサスエレクトロニクス株式会社 フィルタ演算器及び動き補償装置
JP5456766B2 (ja) * 2008-05-12 2014-04-02 クゥアルコム・インコーポレイテッド プログラム可能なプロセッサにおける随意選択的なガロア域計算の実行
US10003342B2 (en) * 2014-12-02 2018-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Compressor circuit and compressor circuit layout
US10002219B2 (en) 2015-03-25 2018-06-19 Samsung Electronics Co., Ltd. Method for placing parallel multiplier
US9876488B2 (en) * 2015-11-02 2018-01-23 Mediatek Inc. Flip-flop circuit with data-driven clock

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6877022B1 (en) * 2001-02-16 2005-04-05 Texas Instruments Incorporated Booth encoding circuit for a multiplier of a multiply-accumulate module
US20150193203A1 (en) * 2014-01-07 2015-07-09 Nvidia Corporation Efficiency in a fused floating-point multiply-add unit
CN107977191A (zh) * 2016-10-21 2018-05-01 中国科学院微电子研究所 一种低功耗并行乘法器
CN110058840A (zh) * 2019-03-27 2019-07-26 西安理工大学 一种基于4-Booth编码的低功耗乘法器

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ASADI POOYA: "A New network multiplier using modified high order encoder and optimized hybrid adder in CMOS technology", INFORMATION SCIENCES LETTERS, vol. 2, no. 3, 1 September 2013 (2013-09-01), pages 159 - 164, XP055813313, ISSN: 2090-9551, DOI: 10.12785/isl/020305 *
WU MEI-QI , ZHAO HONG-LIANG , LIU XING-HUI , KANG DA-WEI , LI WEI: "A design of multiplier based on modified Booth-4 algorithm and Wallace tree", ELECTRONIC DESIGN ENGINEERING, vol. 27, no. 16, 24 May 2019 (2019-05-24), pages 145 - 150, XP055813311, ISSN: 1674-6236, DOI: 10.14022/j.cnki.dzsjgc.20190523.001 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4336345A4 (en) * 2021-07-30 2024-10-02 Huawei Tech Co Ltd ACCUMULATOR, MULTIPLIER AND OPERATOR CIRCUIT
WO2023015442A1 (zh) * 2021-08-10 2023-02-16 华为技术有限公司 一种乘法器
EP4336346A4 (en) * 2021-08-10 2024-07-10 Huawei Tech Co Ltd MULTIPLIER

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