WO2021083161A1 - 一种时间测量装置和方法 - Google Patents
一种时间测量装置和方法 Download PDFInfo
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- WO2021083161A1 WO2021083161A1 PCT/CN2020/124138 CN2020124138W WO2021083161A1 WO 2021083161 A1 WO2021083161 A1 WO 2021083161A1 CN 2020124138 W CN2020124138 W CN 2020124138W WO 2021083161 A1 WO2021083161 A1 WO 2021083161A1
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
- G01S7/486—Receivers
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- This application relates to electronic circuits, and in particular to a time measurement device and method.
- a ranging system such as lidar
- a Field Programmable Gate Array (Field Programmable Gate Array, FPGA) can be used to implement time measurement.
- FPGA Field Programmable Gate Array
- the condition that the flip-flop or latch cannot reach a confirmable state within a certain period of time is called metastable state. For example, if the data transmission does not meet the conditions of the flip-flop, or the release of the reset signal during the reset process is not satisfied with the recovery time of the effective clock edge, a metastable phenomenon may occur.
- the output of the flip-flop is after the effective clock edge. It is in an uncertain state for a relatively long period of time. During this period of time, the output of the trigger is in an oscillating state between 0 and 1.
- the present application provides a time measurement device and method used in a lidar ranging system, which can eliminate the influence of metastable state in FPGA and improve the accuracy of time measurement.
- the present application provides a time measurement device, including a signal splitter, a plurality of measurement channels, and an arithmetic operation unit;
- the signal splitter is configured to receive a signal to be tested and divide the signal to be tested into a plurality of signals to be tested Sub-signal;
- each measurement channel of the plurality of measurement channels is used to measure one of the plurality of sub-signals to be measured;
- each measurement channel of the plurality of measurement channels includes: delay A module configured to perform a first delay on the input sub-signal to be measured to obtain a signal after the first delay; a measurement module configured to measure the signal after the first delay to obtain a first measurement result;
- the compensation module is configured to compensate the first measurement result according to the first delay time to obtain a compensated second measurement result;
- the arithmetic operation unit is configured to include many in a set of second measurement results When there are a preset number of similar time measurement results, the final measurement result is calculated according to the similar time measurement results.
- the time measurement device calculates the final measurement result according to the similar time measurement results, including: calculating the average value of all similar time measurement results to obtain the final measurement result; or determining the highest of the similar time measurement results After the value and the lowest value are deleted, the average value of the remaining similar time measurement results is calculated to obtain the final measurement result.
- the number of the multiple measurement channels in the time measurement device is N, and the preset number of similar time measurement results is a minimum integer not less than (N+1)/2.
- the measurement module includes: a plurality of second delay sub-modules; a plurality of triggers, and the input terminal of each trigger of the plurality of triggers is connected to the corresponding plurality of The output terminal of each second delay submodule of the two delay submodules is connected.
- the similar time measurement results include time measurement results in the set of second measurement results whose mutual difference is less than a preset threshold; wherein, the preset threshold is at least It is related to the second delay of the plurality of second delay sub-modules. .
- the compensation module includes a subtractor configured to subtract the first delay from the first measurement result to obtain the second measurement result.
- the clock period of the time measurement device is set to a metastable time window greater than 2 times.
- the first delay for the first delay module in each of the multiple measurement channels to delay the input signal is set as an arithmetic sequence distribution.
- the time interval T of the first delay time is 1/N system cycles.
- This application also provides a time measurement method, including the following steps:
- Each of the plurality of measurement channels is used to measure each of the plurality of sub-signals to be measured
- the final measurement result is calculated according to the similar time measurement results.
- calculating the final measurement result according to the similar time measurement results includes: calculating the average of all similar time measurement results to obtain the final measurement result; or combining the similar time measurement results with After deleting the highest value and the lowest value in, calculate the average value of the remaining similar time measurement results to get the final measurement result.
- the number of the multiple measurement channels is N
- the preset number of similar time measurement results is a minimum integer not less than (N+1)/2.
- the first delay for delaying the input signal by the first delay module in each of the multiple measurement channels is set as an arithmetic sequence distribution.
- the time interval T of the first delay time is 1/N system cycles.
- Fig. 1 is a schematic structural diagram of a time measuring device according to an embodiment of the present application.
- Fig. 2 is a working principle diagram of a measurement module in a time measurement device according to an embodiment of the present application.
- Fig. 3 is a flowchart of a time measurement method according to an embodiment of the present application.
- Fig. 1 is a schematic structural diagram of a time measuring device according to an embodiment of the present application.
- the time measurement device in the embodiment of the present application includes a signal splitter 11, a plurality of measurement channels 12, and an arithmetic operation unit 13.
- the signal splitter 11 is configured to receive a signal to be measured, and to The measured signal is divided into multiple sub-signals to be measured; each of the multiple measurement channels 12 (N measurement channels are taken as an example in Figure 1) is used to measure one of the multiple sub-signals to be measured
- Each measurement channel of the plurality of measurement channels 12 includes: a first delay module YSA, configured to perform a first delay on the input sub-signal to be measured to obtain a signal after the first delay; a measurement module CL, configured To measure the signal after the first delay to obtain the first measurement result; the compensation module BC is configured to compensate the first measurement result according to the first delay to obtain the compensated second measurement result; the arithmetic operation unit 13 When there are no less than a preset number of similar time measurement results in a set of second measurement results after compensation, the final measurement result is calculated according to the similar time measurement results.
- the arithmetic operation module 13 can also output an error prompt message.
- calculating the final measurement result based on the similar time measurement results is to obtain the final measurement result by calculating the average value of all similar time measurement results.
- the final measurement result is calculated based on the similar time measurement result, and after deleting the highest value and the lowest value in the similar time measurement result, the average value of the remaining similar time measurement results is calculated to obtain The final measurement result.
- the number of multiple measurement channels is N.
- the preset number may be It is an integer rounded up to (N+1)/2, that is, the smallest integer not less than (N+1)/2.
- Fig. 2 is a working principle diagram of a measurement module in a time measurement device according to an embodiment of the present application.
- the measurement module CL includes a trigger CF, which is implemented using a multi-stage delay module chain plus a trigger.
- the input terminal of each of the multiple flip-flops CF is connected to the output terminal of the corresponding second delay sub-module YSB through the tap CT.
- each second delay sub-module is For the same delay.
- each second delay sub-module corresponds to a carry link delay.
- each second delay The time sub-module YSB outputs to the data input terminal of the corresponding flip-flop CF.
- Each flip-flop uses the clock signal of the clock counter 15 of the same source to latch the level of each tap CT input.
- a total of N bits of latched data are generated. These latched data enter the N-bit encoder 14 to generate the corresponding code.
- the coding method generally adopts thermometer coding, and the judgment is 0-1 Level conversion is used to calculate the level of the corresponding second delay sub-module YSB, and the overall measurement time interval is obtained by adding the level of the corresponding second delay sub-module to the coarse-grained count value of the corresponding clock .
- the time of each second delay sub-module cannot be strictly consistent, therefore, even if the metastable state does not occur during the measurement process, the measurement results obtained by each measurement channel are not the same. It will not be exactly the same. Therefore, similar time measurement results can be defined as time measurement results included in a set of second measurement results whose mutual difference is less than a preset threshold; wherein, the preset threshold is at least the same as the second delay of the second delay sub-module.
- the preset threshold may be an integer multiple of the second delay of the second delay sub-module, for example, 1 time or 2 times.
- the first delay module YSA and/or the second delay sub-module YSB can be formed by connecting multiple inverters in series, and the measurement channel can be set according to the delay requirement of each measurement channel.
- the first delay module and/or the second delay sub-module can also adopt any FPGA delay unit, such as the logic unit of the advance bit chain.
- the first delay module and the second delay sub-module are The implementation of the module is not specifically limited.
- the compensation module BC may be a subtractor, and the second measurement result is obtained by subtracting the first delay of the first delay module YSA from the measured amount of time.
- the arithmetic operation unit 13 calculates the final measurement result according to the similar time measurement result.
- the clock period can be set to a metastable time window greater than 2 times, so that the measurement results of most measurement channels are not affected by the metastable state, so as to further improve the measurement accuracy.
- the first delay module YSA can delay the input signal by ⁇ T 1 , ⁇ T 2 ,..., ⁇ T N to obtain the delayed signal, and these delays are all greater than 0 and less than one clock cycle (The period of the clock signal in Figure 2), through these different time intervals to ensure that most signals will not fall into the time window corresponding to the metastable state of the sampling clock.
- the first measurement results of the N measurement modules CL performing time measurement on the first delayed signal are T 1 , T 2 , ..., T N.
- the first delay of each measurement channel can be set to an arithmetic sequence distribution.
- the first delay time interval T is 1/N system cycles, and this setting can achieve metastable state. Appears a uniform probability distribution, reaching the overall optimal probability distribution.
- the system period is the period of the sampling clock signal.
- Fig. 3 is a flowchart of a time measurement method according to an embodiment of the present application. As shown in FIG. 3, the time measurement method of the embodiment of the present application includes the steps:
- S1 Use a signal splitter to receive the signal to be tested, and divide the signal to be tested into multiple sub-signals to be tested;
- S3 Use the delay module in each of the multiple measurement channels to perform a first delay on the input sub-signal to be measured to obtain a signal after the first delay;
- calculating the final measurement result based on the similar time measurement results includes: calculating the average of all similar time measurement results to obtain the final measurement result; or combining the similar time measurement results with After deleting the highest value and the lowest value in, calculate the average value of the remaining similar time measurement results to get the final measurement result.
- the number of multiple measurement channels is N
- the preset number of similar time measurement results is the smallest integer not less than (N+1)/2.
- the measurement module CL includes a plurality of second delay sub-modules YSB; and a plurality of flip-flops CF, and the input terminal of each of the plurality of flip-flops CF passes through
- the tap CT is connected to the output end of each second delay sub-module of the corresponding plurality of second delay sub-modules YSB.
- similar time measurement results include time measurement results in a set of second measurement results whose mutual difference is less than a preset threshold; wherein, the preset threshold is at least the same as the multiple first measurement results.
- the second delay of the second delay sub-module is related.
- the compensation module BC includes a subtractor for subtracting the first delay from the first measurement result to obtain the second measurement result.
- the clock period of the time measurement device is set to a metastable time window greater than 2 times.
- the first delay in which the first delay module in each of the multiple measurement channels delays the input signal is set as an arithmetic sequence distribution.
- the time interval T of the first delay time is 1/N system cycles.
- the embodiment of the application eliminates the influence of metastable state on the measurement result in the time measurement device, and at the same time, improves the accuracy of the measurement result through multi-channel parallel measurement.
- the measurement principle when parallel measurement is performed through N channels, metastable state occurs If the channel is L, the corresponding measurement accuracy is the single-channel measurement accuracy/
- the devices and methods described herein are not limited to specific hardware or software configurations, and can find applicability in many computing or processing environments.
- the device and method can be implemented in hardware or software, or a combination of hardware and software.
- the apparatus and method can be implemented in one or more computer programs, where the computer program can be understood as including one or more processor-executable instructions.
- the computer program can be executed on one or more programmable processors, and can be stored in one or more storage media (including volatile and non-volatile memory and/or storage elements) readable by the processor, a Or multiple input devices, and/or one or more output devices. Therefore, the processor can access one or more input devices to obtain input data, and can access one or more output devices to transfer output data.
- Input and/or output devices may include one or more of the following: random access memory (RAM), redundant array of independent disks (RAID), floppy disk drive, CD, DVD, magnetic disk, internal hard drive, external hard drive, memory
- RAM random access memory
- RAID redundant array of independent disks
- floppy disk drive CD, DVD, magnetic disk
- internal hard drive internal hard drive
- external hard drive memory
- a stick or other storage device that can be accessed by the processor provided herein, where the above examples are not exhaustive and are only for illustration and not limitation.
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Abstract
一种时间测量装置,包括信号分路器(11),配置为接收待测信号,将待测信号分为多个待测子信号;多个测量通道(12)中的每个测量通道用于测量多个待测子信号中的一个待测子信号;每个测量通道包括:延时模块、测量模块、补偿模块;算数运算单元(13),配置为在一组第二测量结果中存在不少于预设数量的相近的时间测量结果时,根据相近的时间测量结果计算最终测量结果。以上方案能够消除激光雷达测距系统中由于亚稳态造成的测量不准确的问题,提高了时间测量的准确性,进而提高了测距系统的精度。还提供了一种时间测量方法。
Description
相关申请的交叉引用
本申请基于申请号为201911060092.1、申请日为2019年11月1日的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本申请作为参考。
本申请涉及电子电路,尤其涉及一种时间测量装置和方法。
在激光雷达等测距系统中,为了得到测距结果,需要先测量发射激光脉冲和接收激光脉冲之间的时间间隔,将时间间隔乘以光速即可得到激光雷达与目标物体之间的距离。由于光速非常快,时间间隔的测量精度会严重影响最终的测距精度。因此,高精度的时间测量装置对于提升激光雷达的测量精度具有重要的意义。
在现有技术中,可以采用现场可编程门阵列(Field Programmable Gate Array,FPGA)等实现时间测量。在FPGA中,触发器或锁存器无法在某个规定时间段内达到一个可确认的状态的情况被称为亚稳态。例如,如果数据传输不满足触发器的条件,或者复位过程中复位信号的释放相对于有效时钟沿的恢复时间不满足,则可能产生亚稳态现象,此时触发器输出端在有效时钟沿之后比较长的一段时间处于不确定的状态,在这段时间里触发器输出端在0和1之间处于振荡状态。即使之后稳定到0或者1,其稳定的状态也是随机的,与输入没有必然的联系,造成最终的时间测量结果出现错误。因此,如何消除亚稳态的影响,是采用FPGA实现时间测量时需 要解决的问题。
发明内容
本申请提供一种用于激光雷达测距系统中的时间测量装置和方法,能够消除FPGA中亚稳态的影响,提高时间测量的准确度。
本申请提出的技术方案如下:
本申请提供一种时间测量装置,包括信号分路器、多个测量通道、算数运算单元;所述信号分路器,配置为接收待测信号,将所述待测信号分为多个待测子信号;所述多个测量通道中的每个测量通道用于测量所述多个待测子信号中的一个待测子信号;所述多个测量通道中的每个测量通道包括:延时模块,配置为对输入的待测子信号进行第一延时,得到第一延时后的信号;测量模块,配置为对所述第一延时后的信号进行测量,得到第一测量结果;补偿模块,配置为根据所述第一延时对所述第一测量结果进行补偿,得到补偿后的第二测量结果;所述算数运算单元,配置为在一组第二测量结果中存在不少于预设数量的相近的时间测量结果时,根据所述相近的时间测量结果计算最终测量结果。
可选地,所述时间测量装置根据所述相近的时间测量结果计算最终测量结果,包括:计算全部相近的时间测量结果的平均值,得到最终测量结果;或者将相近的时间测量结果中的最高值和最低值删除后,计算余下的相近的时间测量结果的平均值,得到最终测量结果。
可选地,所述时间测量装置中的所述多个测量通道的数量为N个,相近的时间测量结果的所述预设数量为不小于(N+1)/2的最小整数。
可选地,所述测量模块包括:多个第二延时子模块;多个触发器,所述多个触发器中的每个触发器的输入端分别通过抽头与对应的所述多个第二延时子模块的每个第二延时子模块的输出端连接。
可选地,所述时间测量装置中,所述相近的时间测量结果包括在所述 一组第二测量结果中的彼此差值小于预设阈值的时间测量结果;其中,所述预设阈值至少与所述多个第二延时子模块的第二延时相关。。
可选地,所述补偿模块包括减法器,配置为将所述第一测量结果减去所述第一延时,得到所述第二测量结果。
可选地,所述时间测量装置的时钟周期设置为大于2倍的亚稳态时间窗口。
可选地,所述多个测量通道中的每个测量通道中的第一延时模块对输入的信号进行延时的第一延时设置为等差数列分布。
可选地,所述第一延时时间的时间间隔T为1/N个系统周期。
本申请还提供了一种时间测量方法,包括以下步骤:
采用信号分路器接收待测信号,将所述待测信号分为多个待测子信号;
采用多个测量通道中的每个测量通道测量所述多个待测子信号中的每个待测子信号;
采用所述多个测量通道中的每个测量通道中的延时模块对输入的待测子信号进行第一延时,得到第一延时后的信号;
采用所述多个测量通道中的每个测量通道中的测量模块对所述第一延时后的信号进行测量,得到第一测量结果;
采用所述多个测量通道中的每个测量通道中的补偿模块根据所述第一延时对所述第一测量结果进行补偿,得到补偿后的第二测量结果;
采用算数运算单元在一组第二测量结果中存在不少于预设数量的相近的时间测量结果时,根据所述相近的时间测量结果计算最终测量结果。
可选地,所述时间测量方法中,根据所述相近的时间测量结果计算最终测量结果,包括:计算全部相近的时间测量结果的平均值,得到最终测量结果;或者将相近的时间测量结果和中的最高值和最低值删除后,计算余下的相近的时间测量结果的平均值,得到最终测量结果。
可选地,所述时间测量方法中,所述多个测量通道的数量为N个,相近的时间测量结果的所述预设数量为不小于(N+1)/2的最小整数。
可选地,所述时间测量方法中,所述多个测量通道中的每个测量通道中的第一延时模块对输入的信号进行延时的第一延时设置为等差数列分布。
可选地,所述时间测量方法中,所述第一延时时间的时间间隔T为1/N个系统周期。
采用本申请实施例的技术方案,能够消除激光雷达测距系统中由于亚稳态造成的测量不准确的问题,提高时间测量的准确性,进而提高测距系统的精度。
应当理解的是,以上的一般描述和后文的细节描述仅是示例性和解释性的,并不能限制本公开。
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案,下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本申请的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是根据本申请的一个实施例的时间测量装置的结构示意图。
图2是根据本申请的一个实施例的时间测量装置中测量模块的工作原理图。
图3是根据本申请的一个实施例的时间测量方法的流程图。
这里将详细地对示例性实施例进行说明,其示例表示在附图中。下面 的描述涉及附图时,除非另有表示,不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反,它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的系统的例子。
图1是根据本申请的一个实施例的时间测量装置的结构示意图。如图1所示,本申请实施例的时间测量装置包括信号分路器11、多个测量通道12、算数运算单元13,所述信号分路器11配置为接收待测信号,将所述待测信号分为多个待测子信号;多个测量通道12(图1中以N个测量通道为例)中的每个测量通道用于测量多个待测子信号中的一个待测子信号;多个测量通道12中的每个测量通道包括:第一延时模块YSA,配置为对输入的待测子信号进行第一延时,得到第一延时后的信号;测量模块CL,配置为对第一延时后的信号进行测量,得到第一测量结果;补偿模块BC,配置为根据第一延时对第一测量结果进行补偿,得到补偿后的第二测量结果;算数运算单元13,在补偿后的一组第二测量结果中存在不少于预设数量的相近的时间测量结果时,根据相近的时间测量结果计算最终测量结果。
根据本申请的一个实施例,当补偿后的第二测量结果各不相近时,无法判断哪个测量通道的测量结果为正确测量结果,此时,可以认为本次测量错误,抛弃本次测量结果。当本次测量错误时,算数运算模块13还可以输出错误提示信息。
根据本申请的一个实施例,根据相近的时间测量结果计算最终测量结果,是通过计算全部相近的时间测量结果的平均值,得到最终测量结果。
根据本申请的另一个实施例,根据相近的时间测量结果计算最终测量结果,将相近的时间测量结果和中的最高值和最低值删除后,计算余下的相近的时间测量结果的平均值,得到最终测量结果。
在本申请的一个实施例中,多个测量通道的数量为N个,对于在补偿 后的一组第二测量结果中存在不少于预设数量的相近的时间测量结果,该预设数量可以为(N+1)/2向上取整的整数,即不小于(N+1)/2的最小整数。
图2是根据本申请的一个实施例的时间测量装置中测量模块的工作原理图。根据本申请的一个实施例,测量模块CL包括触发器CF,使用多级延时模块链加触发器的方式实现。如图2所示,多个触发器CF中的每个触发器的输入端分别通过抽头CT与对应的第二延时子模块YSB的输出端连接,每个第二延时子模块理论上均为相同的延时。对于FPGA实现而言,每个第二延时子模块对应一个进位链路延时,如多路选择器(MUXCY)这种超前进位加法器的进位链上的延时,每一个第二延时子模块YSB输出到对应的触发器CF的数据输入端,每个触发器均采用同源的时钟计数器15的时钟信号对输入的各抽头CT的电平进行锁存,对于一个包含N个第二延时子模块YSB的延时链而言,共计产生N比特的锁存数据,这些锁存数据进入N比特编码器14,生成对应的编码,编码方法一般采用温度计编码,通过判断0-1电平的转换来计算对应的第二延时子模块YSB的级数,通过相应的第二延时子模块的级数加上对应的时钟的粗粒度的计数值,得到整体的测量时间的间隔。
根据本申请的一个实施例,由于在实际电路实现过程中,各个第二延时子模块的时间无法严格一致,因此,即使在测量过程中没有发生亚稳态,各测量通道测量得到的结果也不会完全一致。因此,相近的时间测量结果可以定义为包括在一组第二测量结果中的彼此差值小于预设阈值的时间测量结果;其中,预设阈值至少与第二延时子模块的第二延时相关。根据本申请的一个实施例,预设阈值可以是第二延时子模块的第二延时的整数倍,例如1倍或2倍。
根据本申请的一个实施例,第一延时模块YSA和/或第二延时子模块YSB可以由多个反向器串联而成,可以根据每一个测量通道的延时需要, 设置该测量通道上第一延时模块YSA和/或第二延时子模块中反向器的数目。第一延时模块和/或第二延时子模块也可以采用任意FPGA的延时单元,例如超前进位链的逻辑单元,在本实施例中对第一延时模块和第二延时子模块的实现方式不作具体限定。
根据本申请的一个实施例,补偿模块BC可以为减法器,通过将测量出来的时间量减去第一延时模块YSA的第一延时,得到第二测量结果。根据本申请的一个实施例,补偿模块BC根据第一延时模块YSA的第一延时时间对每一路的测量结果进行补偿,即将每一路的第一测量结果分别减去该路的第一延时时间得到该路的第二测量结果t
1=T
1-ΔT
1,t
2=T
2-ΔT
2,……,t
N=T
N-ΔT
N。由于亚稳态的发生具有一定的概率,且亚稳态发生后会导致测量结果出现随机错误导致测量结果出现较大的偏差。因此,当补偿后的第二测量结果中存在至少预设数量个相近的时间测量结果时,算数运算单元13根据相近时间测量结果计算最终测量结果。
根据本申请的一个实施例,时钟周期可以设置为大于2倍的亚稳态时间窗口,使得多数测量通道的测量结果不受亚稳态影响,以进一步提高测量精度。
根据本申请的一个实施例,第一延时模块YSA可以对输入的信号分别延时ΔT
1,ΔT
2,……,ΔT
N得到延时后的信号,这些延时均大于0小于一个时钟周期(图2中时钟信号的周期),通过这些不同的时间间隔来确保大多数信号不会落入到采样时钟亚稳态对应的时间窗口内。之后N个测量模块CL对第一延时后的信号进行时间测量的第一测量结果分别为T
1,T
2,……,T
N。
根据本申请的一个实施例,可以将每一路测量通道的第一延时设置为等差数列分布,例如,第一延时时间间隔T为1/N个系统周期,这样设置可以实现亚稳态出现呈现均匀概率分布,达到整体最优的概率分布。这里, 系统周期是采样时钟信号的周期。实际设置可以为ΔT
1=T,ΔT
2=2T,……,ΔT
N=N×T。
图3是根据本申请的一个实施例的时间测量方法的流程图。如图3所示,本申请实施例的时间测量方法包括步骤:
S1:采用信号分路器接收待测信号,将所述待测信号分为多个待测子信号;
S2:采用多个测量通道中的每个测量通道测量所述多个待测子信号中的每个待测子信号;
S3:采用所述多个测量通道中的每个测量通道中的延时模块对输入的待测子信号进行第一延时,得到第一延时后的信号;
S4:采用所述多个测量通道中的每个测量通道中的测量模块对所述第一延时后的信号进行测量,得到第一测量结果;
S5:采用所述多个测量通道中的每个测量通道中的补偿模块根据所述第一延时对所述第一测量结果进行补偿,得到补偿后的第二测量结果;
S6:采用算数运算单元在一组第二测量结果中存在不少于预设数量的相近的时间测量结果时,根据所述相近的时间测量结果计算最终测量结果。
根据本申请的一个实施例,时间测量方法中,根据相近的时间测量结果计算最终测量结果,包括:计算全部相近的时间测量结果的平均值,得到最终测量结果;或者将相近的时间测量结果和中的最高值和最低值删除后,计算余下的相近的时间测量结果的平均值,得到最终测量结果。
根据本申请的一个实施例,时间测量方法中,多个测量通道的数量为N个,相近的时间测量结果的所述预设数量为不小于(N+1)/2的最小整数。
根据本申请的一个实施例,时间测量方法中,测量模块CL包括多个第二延时子模块YSB;和多个触发器CF,多个触发器CF中的每个触发器的输入端分别通过抽头CT与对应的多个第二延时子模块YSB的每个第二延 时子模块的输出端连接。
根据本申请的一个实施例,时间测量方法中,相近的时间测量结果包括在一组第二测量结果中的彼此差值小于预设阈值的时间测量结果;其中,预设阈值至少与多个第二延时子模块的第二延时相关。
根据本申请的一个实施例,时间测量方法中,补偿模块BC包括减法器,用于将第一测量结果减去第一延时,得到第二测量结果。
根据本申请的一个实施例,时间测量方法中,时间测量装置的时钟周期设置为大于2倍的亚稳态时间窗口。
根据本申请的一个实施例,时间测量方法中,多个测量通道中的每个测量通道中的第一延时模块对输入的信号进行延时的第一延时设置为等差数列分布。
根据本申请的一个实施例,时间测量方法中,第一延时时间的时间间隔T为1/N个系统周期。
本文描述的装置和方法不限于特定的硬件或软件配置,并且可以在许多计算或处理环境中找到适用性。该装置和方法可以以硬件或软件,或硬件和软件的组合来实现。该装置和方法可以在一个或多个计算机程序中实现,其中,计算机程序可以被理解为包括一个或多个处理器可执行指令。计算机程序可以在一个或多个可编程处理器上执行,并且可以存储在处理器可读取的一个或多个存储介质(包括易失性和非易失性存储器和/或存储元件),一个或多个输入设备,和/或一个或多个输出设备。因此,处理器可以访问一个或多个输入设备以获得输入数据,并且可以访问一个或多个输 出设备以传递输出数据。输入和/或输出设备可以包括以下一项或多项:随机存取存储器(RAM)、独立磁盘冗余阵列(RAID)、软盘驱动器、CD、DVD、磁盘、内部硬盘驱动器、外部硬盘驱动器、记忆棒或其他能够在此被提供的处理器访问的存储设备,其中,上述示例不是穷举性的,仅用于说明而非限制。
本申请的特征和益处通过参考实施例进行说明。相应地,本申请明确地不应局限于这些说明一些可能的非限制性特征的组合的示例性的实施例,这些特征可单独或者以特征的其它组合的形式存在。
以上所述实施例,仅为本申请的具体实施方式,用以说明本申请的技术方案,而非对其限制,本申请的保护范围并不局限于此,尽管参照前述实施例对本申请进行了详细的说明,本领域的普通技术人员应当理解:任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化,或者对其中部分技术特征进行等同替换;而这些修改、变化或者替换,并不使相应技术方案的本质脱离本申请实施例技术方案的精神和范围,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以权利要求的保护范围为准。
Claims (14)
- 一种时间测量装置,包括信号分路器、多个测量通道、算数运算单元;所述信号分路器,配置为接收待测信号,将所述待测信号分为多个待测子信号;所述多个测量通道中的每个测量通道用于测量所述多个待测子信号中的一个待测子信号;所述多个测量通道中的每个测量通道包括:延时模块,配置为对输入的待测子信号进行第一延时,得到第一延时后的信号;测量模块,配置为对所述第一延时后的信号进行测量,得到第一测量结果;补偿模块,配置为根据所述第一延时对所述第一测量结果进行补偿,得到补偿后的第二测量结果;所述算数运算单元,配置为在一组第二测量结果中存在不少于预设数量的相近的时间测量结果时,根据所述相近的时间测量结果计算最终测量结果。
- 根据权利要求1所述的时间测量装置,其特征在于,根据所述相近的时间测量结果计算最终测量结果,至少包括:计算全部相近的时间测量结果的平均值,得到最终测量结果;或者将相近的时间测量结果中的最高值和最低值删除后,计算余下的相近的时间测量结果的平均值,得到最终测量结果。
- 根据权利要求1所述的时间测量装置,其特征在于,所述多个测量通道的数量为N个,相近的时间测量结果的所述预设数量为不小于(N+1)/2的最小整数。
- 根据权利要求1所述的时间测量装置,其特征在于,所述测量模 块包括:多个第二延时子模块;多个触发器,所述多个触发器中的每个触发器的输入端分别通过抽头与对应的所述多个第二延时子模块的每个第二延时子模块的输出端连接。
- 根据权利要求4所述的时间测量装置,其特征在于,所述相近的时间测量结果包括在所述一组第二测量结果中的彼此差值小于预设阈值的时间测量结果;其中,所述预设阈值至少与所述多个第二延时子模块的第二延时相关。
- 根据权利要求1至5任一项所述的时间测量装置,其特征在于,所述补偿模块包括减法器,配置为将所述第一测量结果减去所述第一延时,得到所述第二测量结果。
- 根据权利要求1至5任一项所述的时间测量装置,其特征在于,所述时间测量装置的时钟周期设置为大于2倍的亚稳态时间窗口。
- 根据权利要求1至5任一项所述的时间测量装置,其特征在于,所述多个测量通道中的每个测量通道中的第一延时模块对输入的信号进行延时的第一延时时间设置为等差数列分布。
- 根据权利要求8所述的时间测量装置,其特征在于,所述第一延时时间的时间间隔T为1/N个系统周期。
- 一种时间测量方法,其特征在于,包括以下步骤:采用信号分路器接收待测信号,将所述待测信号分为多个待测子信号;采用多个测量通道中的每个测量通道测量所述多个待测子信号中的每个待测子信号;采用所述多个测量通道中的每个测量通道中的延时模块对输入的待测子信号进行第一延时,得到第一延时后的信号;采用所述多个测量通道中的每个测量通道中的测量模块对所述第一延时后的信号进行测量,得到第一测量结果;采用所述多个测量通道中的每个测量通道中的补偿模块根据所述第一延时对所述第一测量结果进行补偿,得到补偿后的第二测量结果;采用算数运算单元在一组第二测量结果中存在不少于预设数量的相近的时间测量结果时,根据所述相近的时间测量结果计算最终测量结果。
- 根据权利要求10所述的时间测量方法,其特征在于,根据所述相近的时间测量结果计算最终测量结果,包括:计算全部相近的时间测量结果的平均值,得到最终测量结果;或者将相近的时间测量结果和中的最高值和最低值删除后,计算余下的相近的时间测量结果的平均值,得到最终测量结果。
- 根据权利要求10或11所述的时间测量方法,其特征在于,所述多个测量通道的数量为N个,相近的时间测量结果的所述预设数量为不小于(N+1)/2的最小整数。
- 根据权利要求10或11所述的时间测量方法,其特征在于,所述多个测量通道中的每个测量通道中的第一延时模块对输入的信号进行延时的第一延时时间设置为等差数列分布。
- 根据权利要求13所述的时间测量方法,其特征在于,所述第一延时时间的时间间隔T为1/N个系统周期,N为所述多个测量通道的数量。
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