WO2021072806A1 - 显示面板驱动装置及其配置方法 - Google Patents

显示面板驱动装置及其配置方法 Download PDF

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Publication number
WO2021072806A1
WO2021072806A1 PCT/CN2019/114196 CN2019114196W WO2021072806A1 WO 2021072806 A1 WO2021072806 A1 WO 2021072806A1 CN 2019114196 W CN2019114196 W CN 2019114196W WO 2021072806 A1 WO2021072806 A1 WO 2021072806A1
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WIPO (PCT)
Prior art keywords
pin
timing controller
flash memory
memory chip
time
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PCT/CN2019/114196
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English (en)
French (fr)
Inventor
方晓莉
谢剑军
Original Assignee
深圳市华星光电技术有限公司
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Publication of WO2021072806A1 publication Critical patent/WO2021072806A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel driving device and a configuration method thereof.
  • LCD Liquid Crystal Display
  • a liquid crystal display panel consists of a color filter substrate (CF, Color Filter), a thin film transistor substrate (TFT, Thin Film Transistor), a liquid crystal (LC, Liquid Crystal) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame ( Sealant) composition.
  • CF color filter substrate
  • TFT Thin Film Transistor
  • LC liquid crystal
  • Sealant Sealant
  • the external drive circuit generally includes: a printed circuit board (Printed). Circuit Board, PCB) on the timing control chip (TCON), power management chip (Power manage IC) and programmable gamma correction chip (P-gamma IC), etc., where the timing control chip is mainly used for low-voltage differential (Low-Voltage Differential Signaling (LVDS) signals are converted into Mini-LVDS signals with low amplitude and high transmission frequency and generate timing signals for driving the liquid crystal panel.
  • the power management chip is mainly used to generate various voltages for driving the liquid crystal display panel.
  • the horse correction chip is mainly used to generate gamma voltage.
  • timing controller of the liquid crystal display device With the increase in the size and resolution of liquid crystal display devices, the requirements for the timing controller of the liquid crystal display device are getting higher and higher. For ultra-high-definition 120Hz or 8K 120Hz liquid crystal display devices, a single timing controller cannot meet the production requirements. To this end, a technical solution including multiple chip drives is proposed, that is, multiple timing controllers are set in the liquid crystal display device to work at the same time, and each timing controller correspondingly controls a corresponding sub-region, that is, each timing controller can only obtain And process the data (such as video data) in its corresponding sub-area. Each timing controller is equipped with a flash memory chip (Flash), that is, each timing controller is connected to a flash memory chip (for example, two timing controllers require two flash memories).
  • Flash flash memory chip
  • each timing controller obtains its corresponding drive code (Code) from its corresponding flash memory chip.
  • code drive code
  • each timing controller corresponds to a flash memory chip
  • the number of flash memory chips is too large, which requires a large amount of Wiring space, and each flash memory chip needs a set of connection lines, for example, each flash memory chip needs chip select (CS), write protection (WP), input (DI), output (Do) and clock (CLK) five connections Wire to connect the timing controller, and also need a ground wire to ground, and a power wire to connect to the power supply. Too many wires will cause the control circuit board (Control Board, CB) cost and wiring complexity increase; and the actual function of flash memory chips is only to store the driver code.
  • CS chip select
  • WP write protection
  • DI input
  • Do output
  • CLK clock
  • the purpose of the present invention is to provide a display panel driving device, which can reduce the number of flash memory chips, simplify circuit wiring difficulty, reduce product costs, and improve storage resource utilization.
  • the purpose of the present invention is also to provide a configuration method of a display panel driving device, which can reduce the number of flash memory chips, simplify circuit wiring difficulty, reduce product costs, and improve storage resource utilization.
  • the present invention provides a display panel driving device, including: a first timing controller, a second timing controller connected to the first timing controller, and a second timing controller connected to the first timing controller The first flash memory chip;
  • the first flash memory chip is used to store a first driving code and a second driving code
  • the first timing controller is used to load a first driving code from the first flash memory chip at a first time, establish a driving configuration according to the first driving code, and load a second driving code from the first flash memory chip at a second time, and Transmitted to the second timing controller;
  • the second timing controller is used for receiving a second driving code, and establishing a driving configuration according to the second driving code.
  • the first timing controller includes a first pin, a second pin, and a pin direct connection module, and the pin direct connection module is respectively connected to the first pin and the second pin;
  • the first flash memory chip is connected to the first pin, and the second timing controller is connected to the second pin;
  • the pin direct connection module is used to control the first pin to be connected to the second pin at a second time, and to control the first pin to be disconnected from the second pin at a time other than the second time.
  • the display panel driving device further includes a second flash memory chip, a chip selection module, and a debugging and burning module;
  • the first timing controller includes a first pin, a second pin, a third pin, and a pin direct connection module.
  • the pin direct connection module is respectively connected to the first pin, the second pin, and The third pin;
  • the first flash memory chip is connected to the first pin
  • the second timing controller and the second flash memory chip are both connected to the chip selection module
  • the chip selection module is connected to the second pin
  • the debug programming module Connect the third pin
  • the first timing controller is further configured to receive Mura repair data from the debugging and burning module at the third time, and transmit the Mura repair data to the second flash memory chip;
  • the pin direct connection module is used to control the connection between the first pin and the second pin at the second time, and control the connection between the second pin and the third pin at the third time, and to control the connection between the second and third pins at the second time and Control the second pin to disconnect from the first pin and the second pin to disconnect from the third pin at times other than the third time;
  • the chip selection module is used for controlling the second pin to be connected to the second timing controller at the second time, and controlling the second pin to be connected to the second flash memory chip at a time other than the second time.
  • the first flash memory chip includes a first storage address and a second storage address, and the first driving code and the second driving code are respectively stored in the first storage address and the second storage address.
  • the display panel driving device further includes a first circuit board and a second circuit board connected to the first circuit board; the first timing controller, the second timing controller and the first flash memory chip are all arranged on the first circuit board Above, the second flash memory chip is arranged on the second circuit board.
  • the present invention also provides a configuration method of a display panel driving device, which includes the following steps:
  • a display panel driving device includes a first timing controller, a second timing controller connected to the first timing controller, and a first flash memory chip connected to the first timing controller ;
  • the first timing controller loads the first driving code from the first flash memory chip, and establishes the driving configuration of the first timing controller according to the first driving code;
  • the first timing controller loads the second drive code from the first flash memory chip and transmits it to the second timing controller, and the second timing controller receives the second drive code and drives it according to the second drive code.
  • the code builds the drive configuration.
  • the first timing controller includes a first pin, a second pin, and a pin direct connection module, the pin direct connection module is respectively connected to the first pin and the second pin; the first flash memory The chip is connected to the first pin, and the second timing controller is connected to the second pin;
  • the pin direct connection module controls the first pin to be connected to the second pin, and controls the first pin to be disconnected from the second pin at times other than the second time.
  • the display panel driving device further includes a second flash memory chip, a chip selection module, and a debugging and burning module;
  • the first timing controller includes a first pin, a second pin, a third pin, and a pin direct connection module.
  • the pin direct connection module is respectively connected to the first pin, the second pin, and The third pin;
  • the first flash memory chip is connected to the first pin
  • the second timing controller and the second flash memory chip are both connected to the chip selection module
  • the chip selection module is connected to the second pin
  • the debug programming The module is connected to the third pin
  • the first timing controller receives Mura repair data from the debugging and burning module, and transmits the Mura repair data to the second flash memory chip;
  • the pin direct connection module controls the first pin to be connected to the second pin
  • the chip selection module controls the second pin to connect to the second timing controller
  • the pin direct connection module controls the connection of the second pin and the third pin
  • the chip selection module controls the second pin to connect to the second flash memory chip
  • the pin direct connection module controls the second pin to be disconnected from the first pin and the second pin to be disconnected from the third pin.
  • the first flash memory chip includes a first storage address and a second storage address; the first driving code and the second driving code are respectively stored at the first storage address and the second storage address.
  • the display panel driving device further includes a first circuit board and a second circuit board connected to the first circuit board; the first timing controller, the second timing controller and the first flash memory chip are all arranged on the first circuit board Above, the second flash memory chip is arranged on the second circuit board.
  • the present invention provides a display panel driving device, including: a first timing controller, a second timing controller connected to the first timing controller, and a second timing controller connected to the first timing controller
  • the first flash memory chip is used to store the first drive code and the second drive code
  • the first timing controller is used to load the first drive code from the first flash memory chip at the first time, and according to the first
  • a driving code establishes a driving configuration, and at a second time, the second driving code is loaded from the first flash memory chip and transmitted to the second timing controller
  • the second timing controller is used for receiving the second driving code and according to the second timing controller.
  • the driver code establishes the driver configuration, which can realize the configuration of two timing controllers through one flash memory chip, which can reduce the number of flash memory chips, simplify circuit wiring difficulty, reduce product costs, and improve storage resource utilization.
  • the present invention also provides a configuration method of a display panel driving device, which can reduce the number of flash memory chips, simplify circuit wiring difficulty, reduce product costs, and improve storage resource utilization.
  • FIG. 1 is a schematic diagram of the first embodiment of the display panel driving device of the present invention
  • FIG. 2 is a schematic diagram of a second embodiment of the display panel driving device of the present invention.
  • FIG. 3 is a flowchart of a configuration method of the display panel driving device of the present invention.
  • the present invention provides a display panel driving device, including: a first timing controller 10, a second timing controller 20 connected to the first timing controller 10, and the first timing controller 10 connected first flash memory chip 30;
  • the first flash memory chip 30 is used to store a first driving code and a second driving code
  • the first timing controller 10 is used to load a first driving code from the first flash memory chip 30 at a first time, establish a driving configuration according to the first driving code, and load a second driving code from the first flash memory chip 30 at a second time.
  • the drive code is transmitted to the second timing controller 20;
  • the second timing controller 20 is used for receiving a second driving code, and establishing a driving configuration according to the second driving code.
  • the first timing controller 10 includes a first pin 11, a second pin 12, and a pin direct connection module 13.
  • the pin direct connection module 13 is respectively connected to the first pin 11 and the second pin 12;
  • the first flash memory chip 30 is connected to the first pin 11, and the second timing controller 20 is connected to the second pin 12;
  • the pin direct connection module 13 is used to control the first pin 11 to be connected to the second pin 12 at the second time, and to control the first pin 11 to be disconnected from the second pin 12 at a time other than the second time. open.
  • the first pin 11 and the second pin 12 are both serial peripheral interface (Serial Peripheral Interface, SPI) pins.
  • SPI Serial Peripheral Interface
  • the first timing controller 10 and the second timing controller 20 respectively correspondingly drive two different areas in the display panel, for example, to distinguish the left half and the right half of the display panel respectively.
  • the display panel is preferably 8K 120Hz LCD panel.
  • the storage capacity of the first flash memory chip 30 needs to be greater than the sum of the first driver code, the second driver code, the header file (Headfile), and other data that must be configured.
  • the display panel driving device further includes a first circuit board 100.
  • the first timing controller 10, the second timing controller 20, and the first flash memory chip 30 are all arranged on the first circuit board 100.
  • the first circuit board 100 is a control circuit board (Control Board) of the display device.
  • the first flash memory chip 30 includes a first storage address and a second storage address
  • the first driving code and the second driving code are stored in the first storage address and the second storage address, respectively
  • the first A timing controller 10 distinguishes the first driving code and the second driving code according to the difference of addresses.
  • the first timing controller 10 loads the first driving code from the first storage address to perform the first timing controller 10
  • the first timing controller 10 loads the second drive code from the second storage address, and passes the second drive code through The directly connected first pin 11 and the second pin 12 are transmitted to the second timing controller 20 to perform the configuration of the second timing controller 20.
  • the time taken by the first timing controller 10 to load its first drive code is less than 200ms, and then the time taken to load the second drive code and transmit it to the second timing controller 20 is less than 200ms.
  • the total time for both the device 10 and the second timing controller 20 to complete the configuration is less than 500 ms.
  • the display panel driving device further includes a second flash memory chip 40, a chip selection module 50, and a debugging and programming module 60;
  • the first timing controller 10 includes a first pin 11', a second pin 12', a third pin 14', and a pin direct connection module 13', and the pin direct connection module 13' is respectively connected to the The first pin 11', the second pin 12' and the third pin 14';
  • the first flash memory chip 30 is connected to the first pin 11'
  • the second timing controller 20 and the second flash memory chip 40 are both connected to the chip selection module 50
  • the chip selection module 50 is connected to the second lead Pin 12'
  • the debugging and programming module is connected to the third pin 14';
  • the first timing controller 10 is further configured to receive Mura repair data from the debugging and burning module 60 at the third time, and transmit the Mura repair data (ie, Demura data) to the second flash memory chip 40;
  • the pin direct connection module 13' is used to control the connection between the first pin 11' and the second pin 12' at the second time, and control the second pin 12' and the third pin at the third time 14' is connected, and the second pin 12' is controlled to be disconnected from the first pin 11' and the second pin 12' is disconnected from the third pin 14' at times other than the second time and the third time;
  • the chip selection module 50 is used to control the second pin 12' to be connected to the second timing controller 20 at a second time, and to control the second pin 12' to be connected to the second flash memory chip 40 at a time other than the second time.
  • the display driving device further includes a first circuit board 100 and a second circuit board 200 connected to the first circuit board 100; the first timing controller 10, the second timing controller 20, and a first flash memory chip 30 are all arranged on the first circuit board 100, the second flash memory chip is arranged on the second circuit board 200, the first circuit board 100 is a control circuit board (Control Board) of the display device, and the second circuit The board 200 is an X-Board of the display device.
  • the first circuit board 100 is a control circuit board (Control Board) of the display device
  • the second circuit The board 200 is an X-Board of the display device.
  • the first pin 11', the second pin 12' and the third pin 13' are all Serial Peripheral Interface (SPI) pins.
  • SPI Serial Peripheral Interface
  • the first timing controller 10 and the second timing controller 20 respectively correspondingly drive two different areas in the display panel, for example, to distinguish the left half and the right half of the display panel respectively.
  • the display panel is preferably 8K 120Hz LCD panel.
  • the storage capacity of the first flash memory chip 30 needs to be greater than the sum of the first driver code, the second driver code, the header file (Headfile), and other data that must be configured.
  • the first flash memory chip 30 includes a first storage address and a second storage address
  • the first driving code and the second driving code are stored in the first storage address and the second storage address, respectively
  • the first A timing controller 10 distinguishes the first driving code and the second driving code according to the difference of addresses.
  • the first timing controller 10 loads the first The drive code is used to configure the first timing controller 10, and then the pin direct connection module 13' controls the first pin 11' and the second pin 12' to be connected together, and the first timing controller 10 reads from the second storage address Load the second driving code, and transmit the second driving code to the second timing controller 20 through the directly connected first pin 11' and the second pin 12', and perform the configuration of the second timing controller 20; And when debugging Mura repair data (that is, the third time), the pin direct connection module 13' controls the third pin 14' and the second pin 12' to be connected together, and the chip selection module 50 receives the second control signal and selects the Two flash memory chips 40.
  • the burning and debugging module 60 stores the Mura repair data into the second flash memory chip 40 through the second pin 12' and the third pin 14', and is used for non-configuration or burning and debugging of Mura repair
  • the pin direct connection module 13' controls the third pin 14' to be disconnected from the second pin 12' and the first pin 11' to the second pin 12'
  • the first timing controller 10 slaves
  • the second flash memory chip 40 reads the Mura repair data.
  • the display panel driving device of the present invention two timing controllers only need one flash memory chip. Compared with the technical solution in the prior art that each timing controller requires one flash memory chip, the present invention
  • the display panel driving device can effectively reduce the number of flash memory chips. As the number of flash memory chips decreases, the connecting lines used to connect the flash memory chips in the printed circuit board are also reduced, and the wiring complexity is effectively simplified and improved.
  • the area utilization rate of the printed circuit board promotes the development of the size of the printed circuit board in the direction of miniaturization, and reduces product costs and enhances product competitiveness.
  • the present invention also provides a method for configuring a display panel driving device, which includes the following steps:
  • a display panel driving device includes a first timing controller 10, a second timing controller 20 connected to the first timing controller 10, and a second timing controller 20 connected to the first timing controller 10
  • the first timing controller 10 loads the first driving code from the first flash memory chip 30, and establishes the driving configuration of the first timing controller 10 according to the first driving code;
  • the first timing controller 10 loads the second driving code from the first flash memory chip 30 and transmits it to the second timing controller 20, and the second timing controller 20 receives the second driving code, and The driver configuration is established according to the second driver code.
  • the first timing controller 10 includes a first pin 11, a second pin 12, and a pin direct connection module 13.
  • the pin direct connection module 13 is respectively connected to the first pin 11 and the second pin 12;
  • the first flash memory chip 30 is connected to the first pin 11, and the second timing controller 20 is connected to the second pin 12;
  • the pin direct connection module 13 controls the first pin 11 to be connected to the second pin 12, and controls the first pin 11 to be disconnected from the second pin 12 at times other than the second time.
  • the first pin 11 and the second pin 12 are both serial peripheral interface (Serial Peripheral Interface, SPI) pins.
  • SPI Serial Peripheral Interface
  • the first timing controller 10 and the second timing controller 20 respectively correspondingly drive two different areas in the display panel, for example, to distinguish the left half and the right half of the display panel respectively.
  • the display panel is preferably 8K 120Hz LCD panel.
  • the storage capacity of the first flash memory chip 30 needs to be greater than the sum of the first driver code, the second driver code, the header file (Headfile), and other data that must be configured.
  • the display panel driving device further includes a first circuit board 100.
  • the first timing controller 10, the second timing controller 20, and the first flash memory chip 30 are all arranged on the first circuit board 100.
  • the first circuit board 100 is a control circuit board (Control Board) of the display device.
  • the first flash memory chip 30 includes a first storage address and a second storage address
  • the first driving code and the second driving code are stored in the first storage address and the second storage address, respectively
  • the first A timing controller 10 distinguishes the first driving code and the second driving code according to the difference of addresses.
  • the display panel driving device further includes a second flash memory chip 40, a chip selection module 50, and a debugging and burning module 60;
  • the first timing controller 10 includes a first pin 11', a second pin 12', a third pin 14', and a pin direct connection module 13', and the pin direct connection module 13' is respectively connected to the The first pin 11', the second pin 12' and the third pin 14';
  • the first flash memory chip 30 is connected to the first pin 11'
  • the second timing controller 20 and the second flash memory chip 40 are both connected to the chip selection module 50
  • the chip selection module 50 is connected to the second lead Pin 12'
  • the debugging and programming module is connected to the third pin 14';
  • the first timing controller 10 receives Mura repair data from the debugging and burning module 60, and transmits the Mura repair data to the second flash memory chip 40;
  • the pin direct connection module 13' controls the first pin 11' to connect to the second pin 12'
  • the chip selection module 50 controls the second pin 12' to connect to the second timing controller 20 ;
  • the pin direct connection module 13' controls the connection of the second pin 12' and the third pin 14';
  • the chip selection module 50 controls the second pin 12' to connect to the second flash memory chip 40;
  • the pin direct connection module 13' controls the second pin 12' to be disconnected from the first pin 11' and the second pin 12' and the third pin 14' disconnected.
  • the display driving device further includes a first circuit board 100 and a second circuit board 200 connected to the first circuit board 100; the first timing controller 10, the second timing controller 20, and a first flash memory chip 30 are all arranged on the first circuit board 100, the second flash memory chip is arranged on the second circuit board 200, the first circuit board 100 is a control circuit board (Control Board) of the display device, and the second circuit The board 200 is an X-Board of the display device.
  • the first circuit board 100 is a control circuit board (Control Board) of the display device
  • the second circuit The board 200 is an X-Board of the display device.
  • the first pin 11', the second pin 12' and the third pin 13' are all Serial Peripheral Interface (SPI) pins.
  • SPI Serial Peripheral Interface
  • the first timing controller 10 and the second timing controller 20 respectively correspondingly drive two different areas in the display panel, for example, to distinguish the left half and the right half of the display panel respectively.
  • the display panel is preferably 8K 120Hz LCD panel.
  • the storage capacity of the first flash memory chip 30 needs to be greater than the sum of the first driver code, the second driver code, the header file (Headfile), and other data that must be configured.
  • the first flash memory chip 30 includes a first storage address and a second storage address
  • the first driving code and the second driving code are stored in the first storage address and the second storage address, respectively
  • the first A timing controller 10 distinguishes the first driving code and the second driving code according to the difference of addresses.
  • the present invention can effectively reduce the number of flash memory chips. As the number of flash memory chips decreases, the connecting lines used to connect the flash memory chips in the printed circuit board are also reduced, and the wiring complexity is effectively simplified and improved.
  • the area utilization rate of the printed circuit board promotes the development of the size of the printed circuit board in the direction of miniaturization, and reduces product costs and enhances product competitiveness.
  • the present invention provides a display panel driving device, including: a first timing controller, a second timing controller connected to the first timing controller, and a second timing controller connected to the first timing controller A flash memory chip; the first flash memory chip is used to store the first drive code and the second drive code; the first timing controller is used to load the first drive code from the first flash memory chip at the first time, and according to the first The drive code establishes the drive configuration, and loads the second drive code from the first flash memory chip at the second time and transmits it to the second timing controller; the second timing controller is used to receive the second drive code and drive according to the second Code establishment drive configuration can realize the configuration of two timing controllers through one flash memory chip, which can reduce the number of flash memory chips, simplify circuit wiring difficulty, reduce product costs, and improve storage resource utilization.
  • the present invention also provides a configuration method of a display panel driving device, which can reduce the number of flash memory chips, simplify circuit wiring difficulty, reduce product costs, and improve storage resource utilization.

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Abstract

一种显示面板驱动装置及其配置方法。显示面板驱动装置包括：第一时序控制器（10）、与第一时序控制器（10）相连的第二时序控制器（20）以及与第一时序控制器（10）相连的第一闪存芯片（30）；第一闪存芯片（30）用于存储第一驱动代码及第二驱动代码；第一时序控制器（10）用于在第一时间从第一闪存芯片（30）加载第一驱动代码，并依据第一驱动代码建立驱动配置，以及在第二时间从第一闪存芯片（30）加载第二驱动代码，并传输至第二时序控制器（20）；第二时序控制器（20）用于接收第二驱动代码，并依据第二驱动代码建立驱动配置，能够实现通过一个闪存芯片完成两个时序控制器的配置，能够减少闪存芯片数量，简化电路布线难度，降低产品成本，提升存储资源利用率。

Description

显示面板驱动装置及其配置方法 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板驱动装置及其配置方法。
 背景技术
随着显示技术的发展，液晶显示器（Liquid Crystal Display，LCD）等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
通常液晶显示面板由彩膜基板（CF，Color Filter）、薄膜晶体管基板（TFT，Thin Film Transistor)、夹于彩膜基板与薄膜晶体管基板之间的液晶（LC，Liquid Crystal）及密封胶框（Sealant）组成。
液晶显示面板工作时需要通过外部驱动电路进行驱动，所述外部驱动电路一般包括：设于一印刷电路板（ Printed Circuit Board ，PCB）上的时序控制芯片（TCON）、电源管理芯片（Power manage IC）及可编程伽马校正芯片（P-gamma IC）等，其中，所述时序控制芯片主要用于将低压差分（Low-Voltage Differential Signaling，LVDS）信号转化为低幅值传输频率高的Mini-LVDS信号以及产生驱动液晶面板的时序讯号，所述电源管理芯片主要用于产生驱动液晶显示面板各类电压，所述可编程伽马校正芯片主要用于产生伽马电压。
随着液晶显示装置的尺寸及分辨率的提升，对于液晶显示装置的时序控制器的要求也越来越高，对于超高清120Hz或8K 120Hz的液晶显示装置，单一的时序控制器难以满足生产要求，为此，提出了包括多个芯片驱动的技术方案，即液晶显示装置中设置多个时序控制器同时工作，每个时序控制器对应控制一个相应子区域，即每个时序控制器只能获取并处理与其对应子区域内的资料(如视频数据)，每个时序控制器设置一个闪存芯片（Flash），即每个时序控制器与一个闪存芯片连接（如两个时序控制器需要两个闪存芯片），各个时序控制器分别从其对应的闪存芯片中获取其对应的驱动代码（Code），但是，由于每个时序控制器对应一个闪存芯片，导致闪存芯片的数量过多，需占用大量的布线空间，并且每一个闪存芯片均需要一套连接线，例如每一个闪存芯片均需要片选（CS）、写保护（WP）、输入（DI）、输出（Do）及时钟（CLK）五条连接线来连接时序控制器，同时还需要一接地线接地，一电源线连接电源，连接线数量过多又会导致控制电路板（Control Board，CB）的成本及布线复杂程度增加；而闪存芯片的实际作用仅为存储驱动代码，在多个芯片驱动时，多个闪存芯片的存在实际使用存在冗余，存储资源又未得到充分利用的同时，从而现有的每个时序控制器对应一个闪存芯片的方案，不仅会占用大量的布线空间，还增加了布线成本及布线复杂程度，同时资源也得到有效利用，完全不符合电路板设计简单明了的原则。
 技术问题
本发明的目的在于提供一种显示面板驱动装置，能够减少闪存芯片数量，简化电路布线难度，降低产品成本，提升存储资源利用率。
本发明的目的还在于提供一种显示面板驱动装置的配置方法，能够减少闪存芯片数量，简化电路布线难度，降低产品成本，提升存储资源利用率。
 技术解决方案
为实现上述目的，本发明提供了一种显示面板驱动装置，包括：第一时序控制器、与所述第一时序控制器相连的第二时序控制器以及与所述第一时序控制器相连的第一闪存芯片；
所述第一闪存芯片用于存储第一驱动代码及第二驱动代码；
所述第一时序控制器用于在第一时间从第一闪存芯片加载第一驱动代码，并依据第一驱动代码建立驱动配置，以及在第二时间从第一闪存芯片加载第二驱动代码，并传输至第二时序控制器；
所述第二时序控制器用于接收第二驱动代码，并依据第二驱动代码建立驱动配置。
所述第一时序控制器包括第一引脚、第二引脚以及引脚直连模块，所述引脚直连模块分别连接所述第一引脚以及第二引脚；
所述第一闪存芯片连接所述第一引脚，所述第二时序控制器连接第二引脚；
所述引脚直连模块用于在第二时间在控制第一引脚与第二引脚相连，在除第二时间以外的时间控制第一引脚与第二引脚断开。
所述显示面板驱动装置还包括第二闪存芯片、选片模块及调试烧录模块；
所述第一时序控制器包括第一引脚、第二引脚、第三引脚以及引脚直连模块，所述引脚直连模块分别连接所述第一引脚、第二引脚及第三引脚；
所述第一闪存芯片连接所述第一引脚，所述第二时序控制器第二闪存芯片均连接所述选片模块，所述选片模块连接第二引脚，所述调试烧录模块连接第三引脚；
所述第一时序控制器还用于在第三时间从调试烧录模块接收Mura修复数据，并将Mura修复数据传输至第二闪存芯片；
所述引脚直连模块用于在第二时间在控制第一引脚与第二引脚连接，在第三时间控制所述第二引脚及第三引脚连接，在除第二时间及第三时间以外的时间控制第二引脚与第一引脚断开且第二引脚与第三引脚断开；
所述选片模块用于在第二时间控制第二引脚连接第二时序控制器，在除第二时间以外的时间控制第二引脚连接第二闪存芯片。
所述第一闪存芯片包括第一存储地址及第二存储地址，所述第一驱动代码及第二驱动代码分别存储于所述第一存储地址及第二存储地址。
所述显示面板驱动装置还包括第一电路板及与第一电路板相连的第二电路板；所述第一时序控制器、第二时序控制器以及第一闪存芯片均设于第一电路板上，所述第二闪存芯片设于第二电路板上。
本发明还提供一种显示面板驱动装置的配置方法，包括如下步骤：
提供一显示面板驱动装置，所述显示面板驱动装置包括第一时序控制器、与所述第一时序控制器相连的第二时序控制器以及与所述第一时序控制器相连的第一闪存芯片；
于所述第一闪存芯片内存储第一驱动代码及第二驱动代码；
在第一时间，所述第一时序控制器从第一闪存芯片加载第一驱动代码，并依据第一驱动代码建立第一时序控制器的驱动配置；
在第二时间，所述第一时序控制器从第一闪存芯片加载第二驱动代码，并传输至第二时序控制器，所述第二时序控制器接收第二驱动代码，并依据第二驱动代码建立驱动配置。
所述第一时序控制器包括第一引脚、第二引脚以及引脚直连模块，所述引脚直连模块分别连接所述第一引脚以及第二引脚；所述第一闪存芯片连接所述第一引脚，所述第二时序控制器连接第二引脚；
在第二时间，所述引脚直连模块控制第一引脚与第二引脚相连，在除第二时间以外的时间控制第一引脚与第二引脚断开。
所述显示面板驱动装置还包括第二闪存芯片、选片模块及调试烧录模块；
所述第一时序控制器包括第一引脚、第二引脚、第三引脚以及引脚直连模块，所述引脚直连模块分别连接所述第一引脚、第二引脚及第三引脚；
所述第一闪存芯片连接所述第一引脚，所述第二时序控制器及第二闪存芯片均连接所述选片模块，所述选片模块连接第二引脚，所述调试烧录模块连接第三引脚；
在第三时间，所述第一时序控制器从调试烧录模块接收Mura修复数据，并将Mura修复数据传输至第二闪存芯片；
在第二时间，所述引脚直连模块控制第一引脚与第二引脚连接，所述选片模块控制第二引脚连接第二时序控制器；
在第三时间，所述引脚直连模块控制所述第二引脚及第三引脚连接；
在除第二时间以外的时间，所述选片模块控制第二引脚连接第二闪存芯片；
在除第二时间及第三时间以外的时间，所述引脚直连模块控制第二引脚与第一引脚断开且第二引脚与第三引脚断开。
所述第一闪存芯片包括第一存储地址及第二存储地址；于所述第一存储地址及第二存储地址分别存储所述第一驱动代码及第二驱动代码。
所述显示面板驱动装置还包括第一电路板及与第一电路板相连的第二电路板；所述第一时序控制器、第二时序控制器以及第一闪存芯片均设于第一电路板上，所述第二闪存芯片设于第二电路板上。
 有益效果
本发明的有益效果：本发明提供一种显示面板驱动装置，包括：第一时序控制器、与所述第一时序控制器相连的第二时序控制器以及与所述第一时序控制器相连的第一闪存芯片；所述第一闪存芯片用于存储第一驱动代码及第二驱动代码；所述第一时序控制器用于在第一时间从第一闪存芯片加载第一驱动代码，并依据第一驱动代码建立驱动配置，以及在第二时间从第一闪存芯片加载第二驱动代码，并传输至第二时序控制器；所述第二时序控制器用于接收第二驱动代码，并依据第二驱动代码建立驱动配置，能够实现通过一个闪存芯片完成两个时序控制器的配置，能够减少闪存芯片数量，简化电路布线难度，降低产品成本，提升存储资源利用率。本发明还提供一种显示面板驱动装置的配置方法，能够减少闪存芯片数量，简化电路布线难度，降低产品成本，提升存储资源利用率。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的显示面板驱动装置的第一实施例的示意图；
图2为本发明的显示面板驱动装置的第二实施例的示意图；
图3为本发明的显示面板驱动装置的配置方法的流程图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种显示面板驱动装置，包括：第一时序控制器10、与所述第一时序控制器10相连的第二时序控制器20以及与所述第一时序控制器10相连的第一闪存芯片30；
所述第一闪存芯片30用于存储第一驱动代码及第二驱动代码；
所述第一时序控制器10用于在第一时间从第一闪存芯片30加载第一驱动代码，并依据第一驱动代码建立驱动配置，以及在第二时间从第一闪存芯片30加载第二驱动代码，并传输至第二时序控制器20；
所述第二时序控制器20用于接收第二驱动代码，并依据第二驱动代码建立驱动配置。
具体地，如图1所示，在本发明的第一实施例中，所述第一时序控制器10包括第一引脚11、第二引脚12以及引脚直连模块13，所述引脚直连模块13分别连接所述第一引脚11以及第二引脚12；
所述第一闪存芯片30连接所述第一引脚11，所述第二时序控制器20连接第二引脚12；
所述引脚直连模块13用于在第二时间在控制第一引脚11与第二引脚12相连，在除第二时间以外的时间控制第一引脚11与第二引脚12断开。
优选地，所述第一引脚11以及第二引脚12均为串行外设接口（Serial Peripheral Interface，SPI）引脚。
具体地，所述第一时序控制器10及第二时序控制器20分别对应驱动显示面板中两个不同的区域，例如分别区别显示面板的左半区和右半区，所述显示面板优选为8K 120Hz的液晶显示面板。
具体地，所述第一闪存芯片30的存储容量需要大于所述第一驱动代码、第二驱动代码、头部文件（Headfile）及其他必须配置的数据量之和。
进一步地，所述显示面板驱动装置还包括第一电路板100，所述第一时序控制器10、第二时序控制器20以及第一闪存芯片30均设于第一电路板100上，所述第一电路板100为显示装置的控制电路板（Control Board）。
具体地，所述第一闪存芯片30包括第一存储地址及第二存储地址，所述第一驱动代码及第二驱动代码分别存储于所述第一存储地址及第二存储地址，所述第一时序控制器10依据地址的不同区别第一驱动代码及第二驱动代码。
在本发明的第一实施例中，配置时，所述第一电路板100上电后，所述第一时序控制器10从第一存储地址加载第一驱动代码，进行第一时序控制器10的配置，接着引脚直连模块13控制第一引脚11与第二引脚12连接至一起，第一时序控制器10从第二存储地址加载第二驱动代码，并将第二驱动代码经过直连的第一引脚11及第二引脚12传输至第二时序控制器20，进行第二时序控制器20的配置。
值得一提的是，所述第一时序控制器10加载完自身第一驱动代码所用时间小于200ms，接着加载第二驱动代码并传送给第二时序控制器20所用时间小于200ms，第一时序控制器10及第二时序控制器20均配置完成的总时间小于500ms。
请参阅图2，在本发明的第二实施例中，相比于第一实施例，所述显示面板驱动装置还包括第二闪存芯片40、选片模块50及调试烧录模块60；
所述第一时序控制器10包括第一引脚11’、第二引脚12’、第三引脚14’以及引脚直连模块13’，所述引脚直连模块13’分别连接所述第一引脚11’、第二引脚12’及第三引脚14’；
所述第一闪存芯片30连接所述第一引脚11’，所述第二时序控制器20及第二闪存芯片40均连接所述选片模块50，所述选片模块50连接第二引脚12’，所述调试烧录模块连接第三引脚14’；
所述第一时序控制器10还用于在第三时间从调试烧录模块60接收Mura修复数据，并将显示不良（Mura）修复数据（即Demura数据）传输至第二闪存芯片40；
所述引脚直连模块13’用于在第二时间在控制第一引脚11’与第二引脚12’连接，在第三时间控制所述第二引脚12’及第三引脚14’连接，在除第二时间及第三时间以外的时间控制第二引脚12’与第一引脚11’断开且第二引脚12’与第三引脚14’断开；
所述选片模块50用于在第二时间控制第二引脚12’连接第二时序控制器20，在除第二时间以外的时间控制第二引脚12’连接第二闪存芯片40。
具体地，所述显示驱动装置还包括第一电路板100及与第一电路板100相连的第二电路板200；所述第一时序控制器10、第二时序控制器20以及第一闪存芯片30均设于第一电路板100上，所述第二闪存芯片设于第二电路板200上，所述第一电路板100为显示装置的控制电路板（Control Board），所述第二电路板200为显示装置的X板（X-Board）。
优选地，所述第一引脚11’、第二引脚12’及第三引脚13’均为串行外设接口（Serial Peripheral Interface，SPI）引脚。
具体地，所述第一时序控制器10及第二时序控制器20分别对应驱动显示面板中两个不同的区域，例如分别区别显示面板的左半区和右半区，所述显示面板优选为8K 120Hz的液晶显示面板。
具体地，所述第一闪存芯片30的存储容量需要大于所述第一驱动代码、第二驱动代码、头部文件（Headfile）及其他必须配置的数据量之和。
具体地，所述第一闪存芯片30包括第一存储地址及第二存储地址，所述第一驱动代码及第二驱动代码分别存储于所述第一存储地址及第二存储地址，所述第一时序控制器10依据地址的不同区别第一驱动代码及第二驱动代码。
在本发明的第二实施例中，配置时（包括第一时间及第二时间），所述第一电路板100上电后，所述第一时序控制器10从第一存储地址加载第一驱动代码，进行第一时序控制器10的配置，接着引脚直连模块13’控制第一引脚11’与第二引脚12’连接至一起，第一时序控制器10从第二存储地址加载第二驱动代码，并将第二驱动代码经过直连的第一引脚11’及第二引脚12’传输至第二时序控制器20，进行第二时序控制器20的配置；烧录及调试Mura修复数据时（即第三时间），引脚直连模块13’控制第三引脚14’与第二引脚12’连接至一起，选片模块50接收第二控制信号，选中第二闪存芯片40，所述烧录及调试模块60经由第二引脚12’及第三引脚14’将Mura修复数据存储至第二闪存芯片40中，在非配置或烧录及调试Mura修复数据时，引脚直连模块13’ 控制第三引脚14’与第二引脚12’断开及第一引脚11’与第二引脚12’断开，第一时序控制器10从第二闪存芯片40读取Mura修复数据。
需要说明的是，在本发明的显示面板驱动装置中，两个时序控制器仅需要一个闪存芯片，相比于现有技术中每一个时序控制器均需要一个闪存芯片的技术方案，本发明的显示面板驱动装置，能够有效减少闪存芯片的数量，随着闪存芯片数量的减少，印刷电路板的中用于连接闪存芯片的连接线也随之减少，布线复杂程度得到有效的简化，同时提升了印刷电路板的面积利用率，促进印刷电路板尺寸向小型化方向发展，并且降低产品成本，增强产品竞争力。
请参阅图3，本发明还提供一种显示面板驱动装置的配置方法，包括如下步骤：
提供一显示面板驱动装置，所述显示面板驱动装置包括第一时序控制器10、与所述第一时序控制器10相连的第二时序控制器20以及与所述第一时序控制器10相连的第一闪存芯片30；
于所述第一闪存芯片30存储第一驱动代码及第二驱动代码；
在第一时间，所述第一时序控制器10从第一闪存芯片30加载第一驱动代码，并依据第一驱动代码建立第一时序控制器10的驱动配置；
在第二时间，所述第一时序控制器10从第一闪存芯片30加载第二驱动代码，并传输至第二时序控制器20，所述第二时序控制器20接收第二驱动代码，并依据第二驱动代码建立驱动配置。
具体地，如图2所示，在本发明的第一实施例中，所述第一时序控制器10包括第一引脚11、第二引脚12以及引脚直连模块13，所述引脚直连模块13分别连接所述第一引脚11以及第二引脚12；所述第一闪存芯片30连接所述第一引脚11，所述第二时序控制器20连接第二引脚12；
在第二时间，所述引脚直连模块13控制第一引脚11与第二引脚12相连，在除第二时间以外的时间控制第一引脚11与第二引脚12断开。
优选地，所述第一引脚11以及第二引脚12均为串行外设接口（Serial Peripheral Interface，SPI）引脚。
具体地，所述第一时序控制器10及第二时序控制器20分别对应驱动显示面板中两个不同的区域，例如分别区别显示面板的左半区和右半区，所述显示面板优选为8K 120Hz的液晶显示面板。
具体地，所述第一闪存芯片30的存储容量需要大于所述第一驱动代码、第二驱动代码、头部文件（Headfile）及其他必须配置的数据量之和。
进一步地，所述显示面板驱动装置还包括第一电路板100，所述第一时序控制器10、第二时序控制器20以及第一闪存芯片30均设于第一电路板100上，所述第一电路板100为显示装置的控制电路板（Control Board）。
具体地，所述第一闪存芯片30包括第一存储地址及第二存储地址，所述第一驱动代码及第二驱动代码分别存储于所述第一存储地址及第二存储地址，所述第一时序控制器10依据地址的不同区别第一驱动代码及第二驱动代码。
在本发明的第二实施例中，所述显示面板驱动装置还包括第二闪存芯片40、选片模块50、调试烧录模块60；
所述第一时序控制器10包括第一引脚11’、第二引脚12’、第三引脚14’以及引脚直连模块13’，所述引脚直连模块13’分别连接所述第一引脚11’、第二引脚12’及第三引脚14’；
所述第一闪存芯片30连接所述第一引脚11’，所述第二时序控制器20及第二闪存芯片40均连接所述选片模块50，所述选片模块50连接第二引脚12’，所述调试烧录模块连接第三引脚14’；
在第三时间，所述第一时序控制器10从调试烧录模块60接收Mura修复数据，并将Mura修复数据传输至第二闪存芯片40；
在第二时间，所述引脚直连模块13’控制第一引脚11’与第二引脚12’连接，所述选片模块50控制第二引脚12’连接第二时序控制器20；
在第三时间，所述引脚直连模块13’控制所述第二引脚12’及第三引脚14’连接；
在除第二时间以外的时间，所述选片模块50控制第二引脚12’连接第二闪存芯片40；
在除第二时间及第三时间以外的时间，所述引脚直连模块13’控制第二引脚12’与第一引脚11’断开且第二引脚12’与第三引脚14’断开。
具体地，所述显示驱动装置还包括第一电路板100及与第一电路板100相连的第二电路板200；所述第一时序控制器10、第二时序控制器20以及第一闪存芯片30均设于第一电路板100上，所述第二闪存芯片设于第二电路板200上，所述第一电路板100为显示装置的控制电路板（Control Board），所述第二电路板200为显示装置的X板（X-Board）。
优选地，所述第一引脚11’、第二引脚12’及第三引脚13’均为串行外设接口（Serial Peripheral Interface，SPI）引脚。
具体地，所述第一时序控制器10及第二时序控制器20分别对应驱动显示面板中两个不同的区域，例如分别区别显示面板的左半区和右半区，所述显示面板优选为8K 120Hz的液晶显示面板。
具体地，所述第一闪存芯片30的存储容量需要大于所述第一驱动代码、第二驱动代码、头部文件（Headfile）及其他必须配置的数据量之和。
具体地，所述第一闪存芯片30包括第一存储地址及第二存储地址，所述第一驱动代码及第二驱动代码分别存储于所述第一存储地址及第二存储地址，所述第一时序控制器10依据地址的不同区别第一驱动代码及第二驱动代码。
需要说明的是，在本发明的显示面板驱动方法中，两个时序控制器仅需要一个闪存芯片，相比于现有技术中每一个时序控制器均需要一个闪存芯片的技术方案，本发明的显示面板驱动方法，能够有效减少闪存芯片的数量，随着闪存芯片数量的减少，印刷电路板的中用于连接闪存芯片的连接线也随之减少，布线复杂程度得到有效的简化，同时提升了印刷电路板的面积利用率，促进印刷电路板尺寸向小型化方向发展，并且降低产品成本，增强产品竞争力。
综上所述，本发明提供一种显示面板驱动装置，包括：第一时序控制器、与所述第一时序控制器相连的第二时序控制器以及与所述第一时序控制器相连的第一闪存芯片；所述第一闪存芯片用于存储第一驱动代码及第二驱动代码；所述第一时序控制器用于在第一时间从第一闪存芯片加载第一驱动代码，并依据第一驱动代码建立驱动配置，以及在第二时间从第一闪存芯片加载第二驱动代码，并传输至第二时序控制器；所述第二时序控制器用于接收第二驱动代码，并依据第二驱动代码建立驱动配置，能够实现通过一个闪存芯片完成两个时序控制器的配置，能够减少闪存芯片数量，简化电路布线难度，降低产品成本，提升存储资源利用率。本发明还提供一种显示面板驱动装置的配置方法，能够减少闪存芯片数量，简化电路布线难度，降低产品成本，提升存储资源利用率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种显示面板驱动装置，包括：第一时序控制器、与所述第一时序控制器相连的第二时序控制器以及与所述第一时序控制器相连的第一闪存芯片；
    所述第一闪存芯片用于存储第一驱动代码及第二驱动代码；
    所述第一时序控制器用于在第一时间从第一闪存芯片加载第一驱动代码，并依据第一驱动代码建立驱动配置，以及在第二时间从第一闪存芯片加载第二驱动代码，并传输至第二时序控制器；
    所述第二时序控制器用于接收第二驱动代码，并依据第二驱动代码建立驱动配置。
  2. 如权利要求1所述的显示面板驱动装置，其中，所述第一时序控制器包括第一引脚、第二引脚以及引脚直连模块，所述引脚直连模块分别连接所述第一引脚以及第二引脚；
    所述第一闪存芯片连接所述第一引脚，所述第二时序控制器连接第二引脚；
    所述引脚直连模块用于在第二时间在控制第一引脚与第二引脚相连，在除第二时间以外的时间控制第一引脚与第二引脚断开。
  3. 如权利要求1所述的显示面板驱动装置，还包括第二闪存芯片、选片模块及调试烧录模块；
    所述第一时序控制器包括第一引脚、第二引脚、第三引脚以及引脚直连模块，所述引脚直连模块分别连接所述第一引脚、第二引脚及第三引脚；
    所述第一闪存芯片连接所述第一引脚，所述第二时序控制器及第二闪存芯片均连接所述选片模块，所述选片模块连接第二引脚，所述调试烧录模块连接第三引脚；
    所述第一时序控制器还用于在第三时间从调试烧录模块接收Mura修复数据，并将Mura修复数据传输至第二闪存芯片；
    所述引脚直连模块用于在第二时间在控制第一引脚与第二引脚连接，在第三时间控制所述第二引脚及第三引脚连接，在除第二时间及第三时间以外的时间控制第二引脚与第一引脚断开且第二引脚与第三引脚断开；
    所述选片模块用于在第二时间控制第二引脚连接第二时序控制器，在除第二时间以外的时间控制第二引脚连接第二闪存芯片。
  4. 如权利要求1所述的显示面板驱动装置，其中，所述第一闪存芯片包括第一存储地址及第二存储地址，所述第一驱动代码及第二驱动代码分别存储于所述第一存储地址及第二存储地址。
  5. 如权利要求3所述的显示面板驱动装置，还包括第一电路板及与第一电路板相连的第二电路板；所述第一时序控制器、第二时序控制器以及第一闪存芯片均设于第一电路板上，所述第二闪存芯片设于第二电路板上。
  6. 一种显示面板驱动装置的配置方法，包括如下步骤：
    提供一显示面板驱动装置，所述显示面板驱动装置包括第一时序控制器、与所述第一时序控制器相连的第二时序控制器以及与所述第一时序控制器相连的第一闪存芯片；
    于所述第一闪存芯片内存储第一驱动代码及第二驱动代码；
    在第一时间，所述第一时序控制器从第一闪存芯片加载第一驱动代码，并依据第一驱动代码建立第一时序控制器的驱动配置；
    在第二时间，所述第一时序控制器从第一闪存芯片加载第二驱动代码，并传输至第二时序控制器，所述第二时序控制器接收第二驱动代码，并依据第二驱动代码建立驱动配置。
  7. 如权利要求6所述的显示面板驱动装置的配置方法，其中，所述第一时序控制器包括第一引脚、第二引脚以及引脚直连模块，所述引脚直连模块分别连接所述第一引脚以及第二引脚；所述第一闪存芯片连接所述第一引脚，所述第二时序控制器连接第二引脚；
    在第二时间，所述引脚直连模块控制第一引脚与第二引脚相连，在除第二时间以外的时间控制第一引脚与第二引脚断开。
  8. 如权利要求6所述的显示面板驱动装置的配置方法，其中，所述显示面板驱动装置还包括第二闪存芯片、选片模块及调试烧录模块；
    所述第一时序控制器包括第一引脚、第二引脚、第三引脚以及引脚直连模块，所述引脚直连模块分别连接所述第一引脚、第二引脚及第三引脚；所述第一闪存芯片连接所述第一引脚，所述第二时序控制器及第二闪存芯片均连接所述选片模块，所述选片模块连接第二引脚，所述调试烧录模块连接第三引脚；
    在第三时间，所述第一时序控制器从调试烧录模块接收Mura修复数据，并将Mura修复数据传输至第二闪存芯片；
    在第二时间，所述引脚直连模块控制第一引脚与第二引脚连接，所述选片模块控制第二引脚连接第二时序控制器；
    在第三时间，所述引脚直连模块控制所述第二引脚及第三引脚连接；
    在除第二时间以外的时间，所述选片模块控制第二引脚连接第二闪存芯片；
    在除第二时间及第三时间以外的时间，所述引脚直连模块控制第二引脚与第一引脚断开且第二引脚与第三引脚断开。
  9. 如权利要求6所述的显示面板驱动装置的配置方法，其中，所述第一闪存芯片包括第一存储地址及第二存储地址；于所述第一存储地址及第二存储地址分别存储所述第一驱动代码及第二驱动代码。
  10. 如权利要求8所述的显示面板驱动装置的配置方法，其中，所述显示面板驱动装置还包括第一电路板及与第一电路板相连的第二电路板；所述第一时序控制器、第二时序控制器以及第一闪存芯片均设于第一电路板上，所述第二闪存芯片设于第二电路板上。
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