WO2021070246A1 - 演算増幅器 - Google Patents

演算増幅器 Download PDF

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Publication number
WO2021070246A1
WO2021070246A1 PCT/JP2019/039650 JP2019039650W WO2021070246A1 WO 2021070246 A1 WO2021070246 A1 WO 2021070246A1 JP 2019039650 W JP2019039650 W JP 2019039650W WO 2021070246 A1 WO2021070246 A1 WO 2021070246A1
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Prior art keywords
voltage
differential pair
offset
differential
current
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English (en)
French (fr)
Japanese (ja)
Inventor
友和 小島
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
    • H03F3/345—DC amplifiers in which all stages are DC-coupled with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Definitions

  • the present invention relates to an operational amplifier.
  • Patent Document 1 describes a differential pair composed of a MIMO (Metal Oxide Semiconductor) transistor and a second differential pair using an NMOS transistor. An operational amplifier in which and is arranged in parallel is described.
  • MIMO Metal Oxide Semiconductor
  • the input voltage is amplified by the MIMO differential pair in the low potential region, and the input voltage is amplified by the NMOS differential pair in the high potential region, so that the entire voltage from ground to power supply voltage is amplified.
  • the amplification degree can be secured in the range.
  • the NMOS differential pair and the MIMO differential pair operate alternately depending on whether the common mode input voltage is higher or lower than (1/2) of the power supply voltage. Therefore, the offset correction is executed by separately providing the active load and the current source for the NMOS differential pair and the epitaxial differential pair and providing the trimming means for adjusting the driving ability of each current source.
  • the polarity of the offset amount deviation due to temperature fluctuation differs between the MIMO differential pair and the NMOS differential pair.
  • the threshold voltages of the NMOS transistors and the NMOS transistors decrease as the temperature rises from the state where the offset voltages of the NMOS differential pair and the NMOS differential pair are corrected at a certain temperature.
  • an offset voltage on the positive side is generated in the NMOS differential pair, but an offset voltage is generated on the negative side in the epitaxial differential pair.
  • the behavior of the offset voltage differs between the MIMO differential pair and the NMOS differential pair.
  • the present invention has been made to solve such a problem, and an object of the present invention is to supply the first and second voltages to all the voltages from the first voltage to the second voltage.
  • an operational amplifier that operates with the voltage range as the input / output range, the offset voltage in the entire voltage range is suppressed by simple control.
  • an operational amplifier that operates by supplying a first voltage and a second voltage, with first and second input nodes to which the input voltage is input and an output to which the output voltage is output.
  • the active load is composed of a first conductive field effect transistor and is connected between the first power supply node and the first and second differential nodes that supply the first voltage.
  • the first differential pair is connected between the first and second differential nodes and the second power supply node that supplies the second voltage, and is composed of a second conductive field effect transistor. Will be done.
  • the second differential pair is connected in parallel with the first differential pair between the first and second differential nodes and the second power supply node, and is a second conductive field effect transistor. Consists of. Each of the first and second differential pairs creates a current difference between the first and second differential nodes according to the voltage difference between the first and second input nodes.
  • the output stage is configured to change the voltage of the output node in the range from the first voltage to the second voltage according to the current difference between the first and second differential nodes.
  • the field effect transistors forming the first differential pair have a threshold voltage of zero or less and a second differential pair.
  • the field effect transistors that make up the above have a threshold voltage higher than zero.
  • the field effect transistors forming the first differential pair have a threshold voltage of zero or more, while the second conductive type has a second.
  • the field effect transistors that make up the differential pair have a threshold voltage lower than zero.
  • the offset correction circuit corrects the offset voltage between the first and second input nodes generated by the first differential pair or the offset voltage between the first and second input nodes generated by the second differential pair. A correction current or a correction voltage is generated in the first differential pair or the second differential pair.
  • an active load is applied in the entire voltage range.
  • the conductive type of the field effect transistors that make up the differential pair is the same, there is no need to switch the control by the offset correction circuit for temperature fluctuations and power supply voltage fluctuations, that is, with simple control over the entire voltage range. It is possible to suppress the offset voltage.
  • FIG. It is a conceptual diagram explaining the use example of the operational amplifier which concerns on this embodiment. It is a block diagram explaining the structural example of the operational amplifier which concerns on Embodiment 1.
  • FIG. It is a circuit diagram explaining the structural example of the operational amplifier which concerns on Embodiment 1.
  • FIG. It is a 1st circuit diagram explaining the structural example of the variable current source shown in FIG.
  • FIG. It is a 2nd circuit diagram explaining the structural example of the variable current source shown in FIG.
  • It is a 1st conceptual diagram which shows the characteristic of the transconductivity with respect to the input voltage input to the gate of each of the E-type NMOS transistor, the D-type NMOS transistor, and the native NMOS transistor which form a differential pair.
  • FIG. It is a circuit diagram for demonstrating the structural example of the offset correction circuit which concerns on modification 3 of Embodiment 1.
  • FIG. It is a circuit diagram explaining the structural example of the operational amplifier which concerns on Embodiment 2.
  • FIG. It is a conceptual diagram explaining the operation of the input voltage detection circuit shown in FIG. It is a circuit diagram explaining the structural example of the input voltage detection circuit shown in FIG. It is a circuit diagram explaining the 1st example of the current supply part shown in FIG. It is a circuit diagram explaining the 2nd example of the current supply part shown in FIG. It is a circuit diagram explaining the 3rd example of the current supply part shown in FIG. It is a circuit diagram explaining the 1st example of the level shift part shown in FIG. It is a circuit diagram explaining the 2nd example of the level shift part shown in FIG. It is a circuit diagram explaining the 3rd example of the level shift part shown in FIG.
  • FIG. 1 is a conceptual diagram illustrating an example of using an operational amplifier according to the present embodiment.
  • the operational amplifier 100 has a non-inverting input node Nip, an inverting input node Nin, and an output node No.
  • the voltages of the non-inverting input node Nippon and the inverting input node are referred to as input voltages Vimp and Vinn, and the voltage of the output node No. is referred to as an output voltage Vout.
  • the operational amplifier 100 is connected to a ground node Ng that supplies the ground voltage GND and a power node Nd that supplies the power supply voltage VDD.
  • a ground node Ng that supplies the ground voltage GND
  • a power node Nd that supplies the power supply voltage VDD.
  • each of the input voltages Vimp, Vinn, and the output voltage Vout changes within the voltage range of GND to VDD. That is, the operational amplifier 100 operates as a rail-to-rail input / output operational amplifier.
  • the operational amplifier 100 operates as a voltage follower amplifier in which the output node No. and the inverting input node Nin are connected.
  • Vnp Vsns
  • Vsns the operational amplifier 100 can be used in any mode different from the voltage follower connection.
  • FIG. 2 is a block diagram illustrating a configuration example of the operational amplifier according to the first embodiment.
  • the operational amplifier 100 includes a first differential pair 310, a second differential pair 320, an active load 330, and a bias voltage generator 340 for the output stage.
  • the output stage 350, offset correction circuits 410 and 420, and a control circuit 600 are provided.
  • the active load 330 is composed of a first conductive field effect transistor.
  • the first differential pair 310 and the second differential pair 320 are composed of a second conductive type field effect transistor which is an opposite conductive type to the first conductive type.
  • the active load 330 is connected between the differential nodes Nd1 and Nd2 and the power supply node Nd.
  • the first differential pair 310 and the second differential pair 320 are connected in parallel between the differential nodes Nd1 and Nd2 and the ground node Ng.
  • the active load 330 is connected to each of the first differential pair 310 and the second differential pair 320 via the differential nodes Nd1 and Nd2.
  • Input voltages Vinp and Vinn are input to each of the first differential pair 310 and the second differential pair 320 from the non-inverting input node Nip and the inverting input node Nin.
  • the active load 330 and the bias voltage generating unit 340 for the output stage are connected between the power supply node Nd and the grounding node Ng.
  • the output stage 350 is connected to the power supply node Nd, the ground node Ng, the output node No, the active load 330, and the bias voltage generation unit 340. As will be described later, the output stage 350 is configured to change the output voltage Vout of the output node No. within the range of the ground voltage GND to the power supply voltage VDD according to the current difference between the differential nodes Nd1 and Nd2.
  • the first differential pair 310 and the second differential pair 320 are composed of N-type MOSFETs (hereinafter, also simply referred to as “NMOS transistors”), and the active load 330 is a P-type MOSFET (hereinafter, also referred to as “NMOS transistor”).
  • NMOS transistor P-type MOSFET
  • an example composed of also referred to simply as a “NMR transistor” will be described. That is, in the following examples, the P type corresponds to one embodiment of the "first conductive type”, and the N type corresponds to one embodiment of the "second conductive type”.
  • the power supply node Nd connected to the active load 330 corresponds to one embodiment of the "first power supply node", and the power supply voltage VDD corresponds to the "first voltage”.
  • the ground node Ng connected to the first differential pair 310 and the second differential pair 320 corresponds to one embodiment of the "second power supply node", and the ground voltage GND is "second voltage”. Corresponds to.
  • the offset correction circuit 410 corrects the offset voltage generated in the first differential pair 310 based on the control signal SG1 from the control circuit 600.
  • the offset correction circuit 420 corrects the offset voltage generated in the second differential pair 320 based on the control signal SG2 from the control circuit 600.
  • the control circuit 600 generates the control signal SG1 of the offset correction circuit 410 and the control signal SG2 of the offset correction circuit 420 based on the output voltage Vout.
  • the first differential pair 310 has the NMOS transistors 311 to 313.
  • the NMOS transistors 311, 312 are configured to have a threshold voltage Vt such that a drain current flows when the gate-source voltage (hereinafter, also simply referred to as “gate voltage”) is 0 [V].
  • the NMOS transistors 311, 312 can be composed of a depletion type NMOS transistor or a native NMOS transistor.
  • NMOS transistor having a threshold voltage Vt ⁇ 1 a depletion type NMOS transistor and a native NMOS transistor are collectively referred to as a (D / N) type NMOS transistor.
  • a normal enhancement type NMOS transistor having Vt> 0 is basically simply referred to as an "NMOS transistor", but when compared with a (D / N) type, it is an E-type NMOS transistor. Also written as. Further, the enhancement type epitaxial transistor is also simply referred to as a epitaxial transistor.
  • the (D / N) type NMOS transistor 311 is connected between the differential node Nd1 and the node Nx.
  • the (D / N) type NMOS transistor 312 is connected between the differential node Nd2 and the node Nx.
  • the gate of the (D / N) type NMOS transistor 311 is connected to the non-inverting input node Nippon (input voltage Vinp), and the gate of the (D / N) type NMOS transistor 312 is connected to the inverting input node Nin (input voltage Vinn). Be connected.
  • (D / N) MOSFET transistors 311 and 312 form a differential pair in which the input voltages Vinp and Vinn are input to the gate.
  • the NMOS transistor 313 is connected between the node Nx and the ground node Ng, and the bias voltage vbn0 is input to the gate.
  • the NMOS transistor 313 operates as a bias tail current source for differential amplification, supplying a current corresponding to the bias voltage vbn0.
  • the second differential pair 320 has NMOS transistors 321 to 323.
  • the NMOS transistor 321 is connected between the differential node Nd1 and the node Ny.
  • the NMOS transistor 322 is connected between the differential node Nd2 and the node Ny.
  • the gate of the NMOS transistor 321 is connected to the non-inverting input node Nippon (input voltage Vinp), and the gate of the NMOS transistor 322 is connected to the inverting input node Nin (input voltage Vinn). Therefore, in the second differential pair 320, the E-type NMOS transistors 321 and 322 form a differential pair in which the input voltages Vinp and Vinn are input to the gate.
  • the NMOS transistor 323 is connected between the node Ny and the ground node Ng, and the bias voltage vbn0 is input to the gate.
  • the active load 330 has epitaxial transistors 331 to 334.
  • the epitaxial transistor 331 is connected between the power supply node Nd and the differential node Nd1.
  • the epitaxial transistor 332 is connected between the power supply node Nd and the differential node Nd2.
  • the MIMO transistor 333 is connected between the differential nodes Nd1 and N3, and the MIMO transistor 334 is connected between the differential nodes Nd2 and N4.
  • the gates of the epitaxial transistors 331 and 332 are connected to the node N4.
  • a common bias voltage vbp3 is input to the gates of the epitaxial transistors 333 and 334.
  • the polyclonal transistors 331 and 332 operate as an active load, and the epitaxial transistors 333 and 334 are cascode-connected to the active load.
  • the bias voltage generation unit 340 has an NMOS transistors 341 to 346 and a NMOS transistors 347 and 348.
  • the NMOS transistor 345 and the NMOS transistor 347 are connected in parallel between the nodes N4 and N6.
  • the NMOS transistors 341 and 343 are connected in series between the node N6 and the grounded node Ng.
  • the NMOS transistor 346 and the NMOS transistor 348 are connected in parallel between the nodes N3 and N5.
  • the NMOS transistors 342 and 344 are connected in series between the node N5 and the grounded node Ng via the node N7.
  • a bias voltage vbn1 is input to the gate of the NMOS transistor 345, and a bias voltage vbn2 is input to the gate of the NMOS transistor 346.
  • a bias voltage vbp1 is input to the gate of the epitaxial transistor 347, and a bias voltage vbp2 is input to the gate of the epitaxial transistor 348.
  • a bias voltage vbn3 is commonly input to the gates of the NMOS transistors 341 and 342.
  • the gates of the NMOS transistors 343 and 344 are connected to the node N6.
  • the NMOS transistors 343 and 344 operate as active loads, and the NMOS transistors 341 and 342 are cascode-connected to the active load. Further, the NMOS transistors 345, 346 and the NMOS transistors 347, 348 operate as floating current sources.
  • the output stage 350 is of a push-pull type and has a NMOS transistor 351p, an NMOS transistor 351n, and capacitors 352 and 353.
  • the PRIVATE transistor 351p is connected between the power supply node Nd and the output node No.
  • the NMOS transistor 351n is connected between the output node No. and the ground node Ng.
  • the gate of the NMOS transistor 351p is connected to the node N3, and the gate of the NMOS transistor 351n is connected to the node N5.
  • the NMOS transistor 351n operates so as to discharge the source current to the output node No. in response to the increase in the current of the differential node Nd1 in response to the increase in the input voltage Vinp.
  • the MIMO transistor 351p operates so as to suck the sink current from the output node No. in response to the increase in the current of the differential node Nd2 in response to the decrease in the input voltage Vinp.
  • the bias voltage generation unit 340 can operate so as to bias the gate voltage of the NMOS transistor 351p and the NMOS transistor 351n so that the so-called class AB amplification operation is realized.
  • the currents of the MPa transistor 351p and the NMOS transistor 351n are set to be about the same as the current flowing through the NMOS transistors 313 and 323 (bias tail current source) except during the amplification operation period, while the currents are the same during the amplification operation.
  • bias voltage By controlling the bias voltage so that a current of several hundred times to several thousand times the current flows, class AB operation becomes possible.
  • a current source, a current mirror circuit, or the like can be simply arranged instead of the bias voltage generating unit 340.
  • the capacitor 352 is connected between the differential node Nd1 and the output node No.
  • the capacitor 353 is connected between the output node No. and the node N7. Capacitors 352 and 353 operate as phase compensation capacitances.
  • the (D / N) type NMOS transistors 311 and 312 correspond to the "first field effect transistor” and the “second field effect transistor”. Further, the NMOS transistor 313 constitutes a "first current source transistor”.
  • the E-type NMOS transistors 321 and 322 correspond to the "third field effect transistor” and the "fourth field effect transistor”. Further, the NMOS transistor 323 constitutes a "second current source transistor”.
  • the offset correction circuit 410 includes an offset current generation circuit 411 electrically connected between the drains of the (D / N) type NMOS transistors 311 and 312 constituting the first differential pair 310 and the power supply node Nd. Including.
  • the offset current generation circuit 411 includes a selection switch 511 and a variable current source 521, and a selection switch 512 and a variable current source 522.
  • the selection switch 511 and the variable current source 521 are connected in series between the power supply node Nd and the (D / N) type NMOS transistor 311 (drain).
  • the selection switch 512 and the variable current source 522 are connected in series between the power supply node Nd and the (D / N) type NMOS transistor 312 (drain).
  • FIG. 4 shows a configuration example of the variable current sources 521 and 522.
  • each of the variable current sources 521 and 522 has a current source 550 to 552 and a switch 560 to 562.
  • the current sources 550 to 552 are connected in series with each of the switches 560 to 562.
  • the current source 550 and the switch 560, the current source 551 and the switch 561, and the current source 552 and the switch 562 are connected in parallel.
  • the switch 560 is turned on and off in response to the control signal dctrl0 from the control circuit 600 (FIG. 2). Similarly, the switch 561 turns on and off in response to the control signal dctrl1 from the control circuit 600, and the switch 562 turns on and off in response to the control signal dctrl2 from the control circuit 600.
  • the control signals dctrl0 to dctrl2 are set to "0" when the switches 560 to 562 are turned off, while they are set to "1" when the switches 560 to 562 are turned on.
  • the current source 550 supplies a constant current I0
  • the current source 551 supplies a constant current I1
  • the current source 552 supplies a constant current I2. Therefore, the correction current Ic11 (Ic12) from the variable current source 521 (522) is variably controlled by the combination of the control signals dctrl0 to dctrl2.
  • the correction current Ic11 (Ic12) can be controlled to 0 or I0 to 7 ⁇ I0 by the eight combinations up to ().
  • the selection switch 511 is turned on and off in response to the control signal SC11 from the control circuit 600 (FIG. 1), and the selection switch 512 is in response to the control signal SC12 from the control circuit 600 (FIG. 1). Turn on and off.
  • the selection switch 511 is turned on, the correction current Ic11 from the variable current source 521 is supplied to the (D / N) type NMOS transistor 311 (drain).
  • the selection switch 512 is turned on, the correction current Ic12 from the variable current source 522 is supplied to the (D / N) type NMOS transistor 312 (drain).
  • one of the correction currents Ic11 and Ic12 is turned on and the other is turned off by turning on one of the selection switches 511 and 512, so that one of the correction currents Ic11 and Ic12 is a (D / N) type NMOS transistor 311 or 312 (drain). ), It is assumed that the offset correction of the first differential pair 310 is performed. In this case, the control signals dctrl0 to dctrl2 can be shared between the variable current sources 521 and 522. On the other hand, when the offset correction of the first differential pair 310 is unnecessary, both the selection switches 511 and 512 are turned off.
  • the control signal SG1 shown in FIG. 2 corresponds to a comprehensive description of the above-mentioned control signals SC11, SC12, dctrl0 to dctrl2.
  • the offset correction circuit 420 includes an offset current generation circuit 421 electrically connected between the drains of the E-type NMOS transistors 321 and 322 constituting the second differential pair 320 and the power supply node Nd. ..
  • the offset current generation circuit 421 includes a selection switch 513 and a variable current source 523, and a selection switch 514 and a variable current source 524.
  • the selection switch 513 and the variable current source 523 are connected in series between the power supply node Nd and the (D / N) type NMOS transistor 321 (drain).
  • the selection switch 514 and the variable current source 524 are connected in series between the power supply node Nd and the (D / N) type NMOS transistor 322 (drain).
  • the offset current generation circuits 411 and 421 correspond to an embodiment of the "first offset current generation circuit".
  • FIG. 5 shows a configuration example of the variable current sources 523 and 524.
  • each of the variable current sources 523 and 524 has a current source 570-573 and a switch 580-583.
  • the current sources 570 to 573 are connected in series with each of the switches 580 to 583.
  • the current source 570 and switch 580, the current source 571 and switch 581, the current source 57 2 and switch 582, and the current source 573 and switch 583 are connected in parallel.
  • the switches 580 to 583 are turned on and off according to the control signals ector0 to ector3 from the control circuit 600 (FIG. 2), respectively.
  • the control signals ector0 to ector3 are set to "0" when the switches 580 to 583 are turned off, while they are set to "1" when the switches 581 to 583 are turned on.
  • the current source 570 supplies a constant current I0
  • the current source 571 supplies a constant current I1
  • the current source 572 supplies a constant current I2
  • the current source 573 supplies a constant current I3.
  • the correction current Ic21 (Ic22) from the variable current source 523 (524) is variably controlled by the combination of the control signals dctrl0 to dctrl3.
  • the correction current Ic21 (Ic22) can be controlled to 0 or I0 to 15 ⁇ I0 by 16 combinations.
  • the selection switch 513 is turned on and off in response to the control signal SC21 from the control circuit 600 (FIG. 1), and the selection switch 514 is in response to the control signal SC22 from the control circuit 600 (FIG. 1). Turn on and off.
  • the selection switch 513 is turned on, the correction current Ic21 from the variable current source 523 is supplied to the E-type NMOS transistor 321 (drain).
  • the selection switch 514 is turned on, the correction current Ic22 from the variable current source 524 is supplied to the E-type NMOS transistor 322 (drain).
  • the offset correction of the differential pair by the E-type NMOS transistors 321 and 322 can be executed by the current difference between the correction currents Ic21 and Ic22.
  • the control signals ector0 to ector3 can be shared between the variable current sources 523 and 524.
  • both the selection switches 513 and 514 are turned off.
  • the control signal SG2 shown in FIG. 2 corresponds to a comprehensive description of the above-mentioned control signals SC21, SC22, and ector0 to ector3.
  • the manufacturing variation of the threshold voltage of the E-type NMOS transistor is larger than the manufacturing variation of the threshold voltage of the D-type NMOS transistor and the native NMOS transistor. Therefore, by setting the output current range as described above, the offset amount that can be corrected by the second differential pair 320 (E type) is set by the first differential pair 310 ((D / N) type). It can be larger than the correctable offset amount of. The details of the offset correction will be described in detail later.
  • FIGS. 6 and 7 show the inputs to the gates of the depletion-type (D-type) NMOS transistors, native NMOS transistors, and enhancement-type (E-type) NMOS transistors that make up the differential pair.
  • the characteristics line of the transistor with respect to the voltage Vinp is shown.
  • the differential pair is composed of an NMOS transistor
  • the input voltage Vimp corresponds to the gate-source voltage of the NMOS transistor.
  • the input voltage Vimp corresponds to the threshold voltage Vt (Vt> 0) of the E-type NMOS transistor.
  • Vt the threshold voltage of the E-type NMOS transistor.
  • Id 0
  • the gm operates in a region (saturation region) where gm does not change with the rise of the input voltage Vimp. To do. Therefore, the second differential pair 320 by the E-type NMOS transistor cannot perform differential amplification in the region A of 0 ⁇ Vimp ⁇ Vte.
  • the fabrication of a depletion type NMOS transistor may lead to an increase in cost, it is cost-effective to configure the first differential pair 310 with a native NMOS transistor obtained by fabrication an NMOS on a P substrate. It is advantageous from.
  • the native NMOS transistor has a characteristic that the threshold voltage Vt is in the vicinity of 0 [V]. Therefore, even if the transistors 311, 312 of the first differential pair 310 are configured by using the native NMOS transistors having the characteristic of the threshold voltage Vt ⁇ 0, there is a difference in the voltage region of 0 ⁇ Vimp ⁇ Vte. Dynamic amplification can be performed.
  • FIG. 7 shows another example of the characteristics of a native NMOS transistor.
  • the input voltage Vimp is close to the power supply voltage VDD and is composed of a D-type NMOS transistor or a native NMOS transistor.
  • the input voltage Vinp is set in a state where the transistors 311, 312 (D-type NMOS transistor or native NMOS transistor) constituting the first differential pair 310 are connected to the differential nodes Nd1 and Nd2.
  • the threshold voltage is 0 or negative, so that the voltage of the differential node Nd1 is also in the vicinity of the power supply voltage VDD.
  • the Vds (drain-source voltage) of the epitaxial transistors 331 and 332 constituting the active load becomes almost 0, which makes the differential amplification operation difficult.
  • the NMOS transistors 321 and 322 (E type) constituting the second differential pair 320
  • the voltage of the differential node Nd1 is the power supply voltage. It is lower than VDD by the threshold voltage Vt of the E-type NMOS transistor.
  • the above threshold voltage Vt (for example, about 0.8 [V]) can be secured as Vds of the epitaxial transistors 331 and 332 constituting the active load, so that the differential amplification operation becomes possible.
  • FIG. 8 shows a characteristic diagram of transconductance with respect to the input voltage of the first differential pair 310 and the second differential pair 320. Also in FIG. 8, the transconductance gm of the transistors forming the differential pair is shown on the vertical axis.
  • the (D / N) type NMOS transistors 311, 312 can operate in the saturation region.
  • the E-type NMOS transistors 321 and 322 operate in the off state or in the unsaturated region, the degree of amplification by the second differential pair 320 becomes small. Therefore, in the region A, the differential amplification operation by the first differential pair 310 becomes dominant. Therefore, the offset voltage in the region A is mainly caused by the characteristic variation (mainly the difference in the threshold voltage) between the (D / N) type NMOS transistors 311 and 312 of the first differential pair 310. ..
  • the E-type NMOS transistors 321 and 322 can operate in the saturation region, while as described above, the (D / N) type NMOS transistors 311.
  • the degree of amplification by the first differential pair 310 according to 312 becomes smaller. Therefore, in the region C, the differential amplification operation by the second differential pair 320 becomes dominant. Therefore, the offset voltage in the region C is mainly caused by the characteristic variation (mainly the difference in the threshold voltage) between the E-type NMOS transistors 321 and 322 of the second differential pair 320.
  • the (D / N) type NMOS transistors 311, 312 and the E-type NMOS transistors 321 and 322 can operate in the saturation region. Therefore, in the region C, the differential amplification operation is executed by both the first differential pair 310 and the second differential pair 320. Therefore, the offset voltage in the region B corresponds to the squared average value of the offset amount in the first differential pair 310 and the offset amount in the second differential pair 320.
  • the differential amplification operation can be executed with the entire ground voltage GND to the power supply voltage VDD as the input / output range.
  • Vout Vinp when there is no offset.
  • offset correction is required to keep the offset voltage Vofs within a predetermined spec range.
  • the offset voltage Vofs is the characteristic difference between the two transistors in which the input voltages Vinp and Vinn are input to the gate in each of the first differential pair 310 and the second differential pair 320.
  • the difference in the gate-source voltage Vgs due to the threshold voltage difference between the two transistors is the main factor of the offset voltage Vofs. Therefore, by compensating for the difference in the gate-source voltage Vgs, it is possible to perform offset correction for minimizing the offset voltage.
  • the (D / N) MOSFET transistor 311 to which the input voltage Vinp is input and the (D / N) NMOS transistor 312 to which the input voltage Vinn is input Due to the difference in the voltage between the gate and the source due to the threshold voltage difference between them, an offset voltage is generated between the non-inverting input node Nippon and the inverting input node Nin.
  • the offset correction circuit 410 is provided to correct the offset voltage generated by the first differential pair 310.
  • the second differential pair 320 due to the threshold voltage difference between the E-type MOSFET transistor 321 to which the input voltage Vinp is input and the E-type NMOS transistor 322 to which the input voltage Vinn is input. As a result of the difference in the voltage between the gate and the source, an offset voltage is generated between the non-inverting input node Nippon and the inverting input node Nin.
  • the offset correction circuit 410 is provided to correct the offset voltage generated by the first differential pair 310.
  • the offset correction in the second differential pair 320 will be typically described.
  • a positive offset voltage Vofs occurs, that is, when the output voltage Vout is too high with respect to the input voltage Vimp
  • the gate-source voltage of the E-type NMOS transistor 321 becomes the E-type NMOS transistor 322. It is estimated that the voltage is higher than the gate-source voltage (on the Vinn side).
  • the gain coefficient ⁇ is an element constant determined by the surface average mobility ⁇ , the channel length L, the channel width W, and the gate capacitance Cox per unit area, as shown in the following equation (3).
  • the overdrive voltage Vov can be expressed by the following equation (4) as a function of the drain current Id.
  • Vov ⁇ (2 ⁇ Id / ⁇ )... (4) Therefore, by using the correction currents Id21 and Id22 of the offset current generation circuit 421 to intentionally make a difference in the drain currents Id of the NMOS transistors 321 and 322, the overdrive voltage Vov of the NMOS transistors 321 and 322 is intentionally set.
  • a voltage difference ( ⁇ Vov) can be provided. That is, by providing the overdrive voltage difference ⁇ Vov so as to cancel the threshold voltage difference ⁇ Vt of the NMOS transistors 321 and 322, the gate between the NMOS transistors 321 and 322 caused by the threshold voltage difference ⁇ .
  • the offset of the source voltage (Vgs) can be corrected.
  • the correction current Ic22 of the offset current generation circuit 421 determines the correction amount of the offset voltage corresponding to the increase in the overdrive voltage Vov according to the equation (4). Therefore, the correction amount of the offset voltage Vofs can be finely adjusted by changing the correction current Ic22 by the control signals ectl0 to ctrl3.
  • FIG. 9 shows a conceptual diagram illustrating an example of offset correction processing in the operational amplifier according to the first embodiment.
  • the vertical axis of FIG. 9 shows the output voltage Vout at the time of the offset test.
  • Vout Vtest.
  • the allowable lower limit voltage Vtmin and the allowable upper limit voltage Vtmax are predetermined in accordance with the specifications of the offset voltage. That is, if the output voltage Vout is within the range of Vtmin ⁇ Vout ⁇ Vtmax, the offset voltage specification is satisfied.
  • a correction code based on a combination of control signals ector0 to ector3 is shown.
  • control circuit 600 stores the values of the control signals cull0 to cull3 and SC21 and SC22 obtained in the offset test. Then, when the operational amplifier 100 is operated, the offset voltage generated by the second differential pair 320 can be corrected within the specifications by outputting the stored control signals ectll0 to ctrel3 and SC21, SC22.
  • the correction current Ic21 can be adjusted by the control signals eject0 to eject3. Therefore, at the time of the offset test, the control signals ector0 to ector3 for keeping the output voltage Vout within the range of Vtmin ⁇ Vout ⁇ Vtmax can be obtained by the same processing as described with reference to FIG.
  • the control signals vector0 to offset3 are stored in the control circuit 600.
  • the operational amplifier 100 when the operational amplifier 100 is operated, by outputting the stored control signals ectll0 to ctrel3 and SC21, SC22, the offset correction generated by the second differential pair 320 for keeping the offset voltage Vofs within the specifications is performed.
  • the voltage can be corrected within the specifications.
  • the offset correction in the first differential pair 310 can be similarly executed by using the offset current generation circuit 411.
  • the (D / N) type NMOS transistor 311 when a positive offset voltage Vofs occurs, that is, when the output voltage Vout is too high with respect to the input voltage Vimp, the (D / N) type NMOS transistor 311 (Vimp). It is estimated that the gate-source voltage on the side) is higher than the gate-source voltage on the (D / N) type NMOS transistor 312 (Vinn side). In this case, the Vgs of the (D / N) type NMOS transistor 311 (Vinp side) is decreased, or the Vgs of the (D / N) type NMOS transistor 312 (Vinn side) is increased to increase (D / N). It is necessary to perform offset correction so that the Vgs between the N) type NMOS transistors 311, 312 are aligned.
  • the control signals dctrl0 to dctrl2 can be stored in the control circuit 600.
  • the (D / N) type NMOS transistor 312 when a negative offset voltage Vofs occurs, that is, when the output voltage Vout is too low with respect to the input voltage Vimp, the (D / N) type NMOS transistor 312 ( It is estimated that the gate-source voltage on the Vinn side) is higher than the gate-source voltage on the (D / N) type NMOS transistor 311 (Vimp side). In this case, the Vgs of the (D / N) type NMOS transistor 312 (Vinn side) is decreased, or the Vgs of the (D / N) type NMOS transistor 311 (Vinp side) is increased to increase (D / N). It is necessary to perform offset correction so that the Vgs between the N) type NMOS transistors 311, 312 are aligned.
  • the overdrive voltage Vov of 311 (Vimp side) can be increased.
  • an appropriate offset correction can be realized by increasing the Vgs of the (D / N) type NMOS transistor 311.
  • the control signals dctrl0 to dctrl2 for setting the output voltage Vout within the range of Vtmin ⁇ Vout ⁇ Vtmax can be obtained by the same processing as described with reference to FIG.
  • the control signals dctrl0 to dctrl2 can be stored in the control circuit 600.
  • FIG. 10 shows a conceptual diagram for explaining the characteristics of the offset voltage with respect to the input voltage of the operational amplifier 100 according to the first embodiment.
  • FIG. 10 shows the characteristics of the offset voltage Vofs when the offset correction is not executed.
  • the offset voltage Vofs has a different value in the voltage range of the input voltage Vimp, specifically, in each of the regions A to C in FIG.
  • region A an offset voltage is generated due to the offset (mainly the threshold voltage difference) between the (D / N) type NMOS transistors 311 and 312 of the first differential pair 310.
  • region C an offset voltage is generated due to an offset (mainly, a threshold voltage difference) between the E-type NMOS transistors 321 and 322 of the second differential pair 320.
  • the first differential pair 310 including the necessity of offset correction, is included.
  • the control signals SC11, SC12, dctrl0 to dctrl2 for obtaining an appropriate offset correction amount (correction current Ic11 or Ic12) in the differential pair 310 can be obtained.
  • the second differential pair 320 includes the necessity of offset correction. It is possible to obtain the control signals SC21, SC22, and voltage0 to voltage3 for obtaining an appropriate offset correction amount (correction current Ic21 or Ic22) in the differential pair 320 of 2.
  • the offset correction of the first differential pair 310 and the second differential pair 320 acts comprehensively. Therefore, it is preferable that the offset correction amount in the first differential pair 310 and the offset correction amount in the second differential pair 320 are set to different values from those in the area A and the area C, respectively.
  • control signals cull0 to ector3 for determining the correction currents Ic21 or Ic22 supplied to the second differential pair 320 can be set to different values between the region C and the region B. .. Further, it is also possible to further divide the region B into a plurality of voltage ranges and set the values of the control signals ector0 to ector2 separately.
  • control signals dctrl0 to dctrl2 for determining the correction currents Ic11 or Ic12 supplied to the first differential pair 310 can be set to different values in the area A and the area B. Further, it is also possible to further divide the region B into a plurality of voltage ranges and set the values of the control signals dctrl0 to dctrl2 separately.
  • FIG. 10 further shows the temperature dependence of the offset voltage Vofs.
  • the active load 330 composed of the NMOS transistors and the first differential pair 310 and the second differential pair 320 composed of the NMOS transistors pass through the regions A to C.
  • a differential amplification operation is performed by at least one of the. That is, the conductive type (P type) of the active load and the conductive type (N type) of the differential pair are common throughout the regions A to C. Therefore, it is understood that the polarity (increase / decrease) of the change in the offset voltage Vofs with respect to the temperature change (increase / decrease) is common in the regions A to C.
  • FIG. 11 shows a conceptual diagram for explaining the characteristics of the offset voltage with respect to the input voltage of the operational amplifier described in Patent Document 1.
  • the differential amplification operation is executed by the P-type differential pair and the N-type active load in the low voltage side region. ..
  • the differential amplification operation is executed by the N-type differential pair and the P-type active load. Therefore, the polarity (increase / decrease) of the change in the offset voltage Vofs with respect to the temperature change (increase / decrease) is different between the region on the high voltage side and the region on the low voltage side. For example, in the example of FIG.
  • the conductive type (P type) of the active load and the conductive type (N) of the differential pair are passed through the entire voltage region (region A to region C) of the input voltage Vinp. Since the type) is common, the polarity (increase / decrease) of the temperature change (increase / decrease) and the change of the offset voltage with respect to the power supply voltage fluctuation is common. Therefore, the offset correction control states (control signals SG1 and SG2) set by the offset test at a certain temperature (for example, normal temperature) are used as they are, and even if temperature fluctuations and power supply voltage fluctuations occur, appropriate offset corrections are common. It is possible to execute. That is, it is possible to suppress the offset voltage in the entire voltage range of the input voltage Vinp by simple control.
  • FIG. 12 is a circuit diagram for explaining the configuration of the offset correction circuit according to the first modification of the first embodiment.
  • the offset correction circuit 410 of the first differential pair 310 further includes an offset current generation circuit 412 in addition to the offset current generation circuit 411.
  • the offset correction circuit 420 of the second differential pair 320 further includes an offset current generating circuit 422 in addition to the offset current generating circuit 421.
  • the configuration of other parts of the operational amplifier 100 is the same as that of the first embodiment.
  • the configuration of the offset current generation circuits 411 and 421 is the same as that of the first embodiment. The description of the common parts with the first embodiment will not be repeated.
  • the offset current generation circuit 412 is electrically connected between the sources of the (D / N) type NMOS transistors 311 and 312 constituting the first differential pair 310 and the ground node Ng.
  • the offset current generation circuit 412 includes a selection switch 531 and a variable current source 541, and a selection switch 532 and a variable current source 542.
  • the selection switch 531 and the variable current source 541 are connected in series between the (D / N) type NMOS transistor 311 (source) and the ground node Ng.
  • the selection switch 532 and the variable current source 542 are connected in series between the (D / N) type NMOS transistor 312 (source) and the ground node Ng.
  • FIG. 13 shows a configuration example of the variable current sources 541 and 542.
  • each of the variable current sources 541 and 542 has switches 620-622 and current sources 630-632.
  • the current sources 630 to 632 are connected in series with each of the switches 620 to 622.
  • the switch 620 and the current source 630, the switch 621 and the current source 631, and the switch 622 and the current source 632 are connected in parallel.
  • the switches 620 to 622 are turned on and off according to the control signals dctrl0 # to dctrl2 # from the control circuit 600 (FIG. 2), respectively.
  • the control signals dctrl0 # to dctrl2 # are set to "0" when the switches 620 to 622 are turned off, while they are set to "1" when the switches 620 to 622 are turned on.
  • the current source 630 supplies a constant current I0
  • the current source 631 supplies a constant current I1
  • the current source 632 supplies a constant current I2.
  • I1 2 ⁇ I0
  • I2 2 ⁇ I1
  • the correction current Id11 0, while when the selection switch 531 is on, the correction current Id11 by the variable current source 541 is generated.
  • the correction current Id12 0, while when the selection switch 532 is on, the correction current Id12 by the variable current source 542 is generated.
  • the correction current Id11 by the offset current generation circuit 412 also acts to increase the drain current of the (D / N) type NMOS transistor 311 in the same manner as the correction current Ic11 (offset current generation circuit 411).
  • the correction current Id12 by the offset current generation circuit 412 acts to increase the drain current of the (D / N) type NMOS transistor 312, similarly to the correction current Ic12 (offset current generation circuit 411).
  • the correction current Id11 is generated by turning on the selection switch 531.
  • the positive offset voltage Vofs Vout> Vimp
  • the selection switch 532 of the correction current Id12 is turned on and off according to the control signal SC12 common to the selection switch 512 of the correction current Ic12.
  • the control signal SC12 "1”
  • the correction currents Ic12 and Id12 both increase the Vgs of the (D / M) type NMOS transistor 312, thereby causing a positive offset of the first differential pair 310.
  • the correction amount of the voltage Vofs (Vout> Vimp) can be increased.
  • the selection switch 531 of the correction current Id11 can be turned on and off according to the control signal SC11 common to the selection switch 511 of the correction current Ic11.
  • the control signal SC11 "1”
  • the Vgs of the (D / M) type NMOS transistor 311 is increased by both the correction currents Ic11 and Id11, so that the negative offset voltage of the first differential pair 310 is increased.
  • the correction amount of Vofs (Vout ⁇ Vimp) can be increased.
  • control signal SG1 shown in FIG. 2 corresponds to a comprehensive description of the above-mentioned control signals SC11, SC12, dctrl0 to dctrl2, dctrl0 # to dctrl2 #.
  • the offset current generation circuit 422 is electrically connected between the sources of the E-type NMOS transistors 321 and 322 constituting the second differential pair 320 and the ground node Ng.
  • the offset current generation circuit 422 includes a selection switch 533 and a variable current source 543, and a selection switch 534 and a variable current source 544.
  • the selection switch 533 and the variable current source 543 are connected in series between the E-type NMOS transistor 321 (source) and the ground node Ng.
  • the selection switch 534 and the variable current source 544 are connected in series between the E-type NMOS transistor 322 (source) and the ground node Ng.
  • the offset current generating circuits 412 and 422 correspond to an embodiment of the "second offset current generating circuit".
  • FIG. 14 shows a configuration example of the variable current sources 543 and 544.
  • each of the variable current sources 543 and 544 has switches 590-593 and current sources 610-613.
  • the current sources 610 to 613 are connected in series with each of the switches 590 to 593.
  • the switch 590 and the current source 610, the switch 591 and the current source 611, the switch 592 and the current source 612, and the switch 593 and the current source 613 are connected in parallel.
  • the switches 590 to 593 are turned on and off according to the control signals ector0 # to cull3 # from the control circuit 600 (FIG. 2), respectively.
  • the control signals ector0 # to ector3 # are set to "0" when the switches 590 to 593 are turned off, while they are set to "1" when the switches 590 to 593 are turned on.
  • the current source 610 supplies a constant current I0
  • the current source 611 supplies a constant current I1
  • the current source 612 supplies a constant current I2
  • the current source 613 supplies a constant current I3.
  • I1 2 ⁇ I0
  • I2 2 ⁇ I1
  • I3 2 ⁇ I2
  • the maximum values of the correction currents Id21 and Id22 of the offset current generation circuit 422 are larger than the maximum values of the correction currents Id11 and Id12 of the offset current generation circuit 412.
  • the offset amount that can be compensated by the second differential pair 320 (E type) is compensated by the first differential pair 310 ((D / N) type). It can be larger than the possible offset amount.
  • the correction current Id21 0, while when the selection switch 533 is on, the correction current Id21 by the variable current source 543 is generated.
  • the correction current Id22 0, while when the selection switch 534 is on, the correction current Id22 by the variable current source 544 is generated.
  • the correction current Id21 by the offset current generation circuit 422 acts to increase the drain current of the E-type NMOS transistor 321 in the same manner as the correction current Ic21 (offset current generation circuit 421).
  • the correction current Id22 by the offset current generation circuit 422 acts to increase the drain current of the E-type NMOS transistor 322, similarly to the correction current Ic22 (offset current generation circuit 421).
  • the correction current Id22 is generated by turning on the selection switch 534, so that the Vgs of the E-type NMOS transistor 322 (Vinn side) is increased by supplying the correction current Ic22. By doing so, the positive offset voltage Vofs (Vout> Vimp) can be corrected.
  • the selection switch 534 of the correction current Id22 is turned on and off according to the control signal SC22 common to the selection switch 514 of the correction current Ic22.
  • the control signal SC22 "1”
  • the Vgs of the E-type NMOS transistor 322 is increased by both the correction currents Ic22 and Id22, so that the positive offset voltage Vofs (Vout> of the second differential pair 320 is used.
  • the correction amount of Vimp) can be increased.
  • the selection switch 533 of the correction current Id21 can be turned on and off according to the control signal SC21 common to the selection switch 512 of the correction current Ic21.
  • the control signal SC21 "1”
  • the Vgs of the E-type NMOS transistor 321 is increased by both the correction currents Ic21 and Id21, so that the negative offset voltage Vofs (Vout ⁇ Vout ⁇ The correction amount of Vimp) can be increased.
  • the control signal SG2 shown in FIG. 2 corresponds to the above-mentioned control signals SC21, SC22, ector0 to ector2, and ector0 # to ector2 # in a comprehensive manner.
  • the offset correction circuits 410 and 420 are configured to include the offset current generation circuits 421 and 422 on the source side of the field effect transistors forming the differential pair. ..
  • the correction currents Id21 and Id22 by the offset current generation circuits 421 and 422 also suppress the offset voltage by relatively increasing one of the source-gate voltages of the two NMOS transistors constituting the differential pair. Can be done.
  • the offset correction circuits 410 and 420 include both the offset current generation circuit (drain side) 411 and 421 and the offset current generation circuit (source side) 421 and 422 to form a differential pair.
  • the offset correction circuits 410 and 420 can be configured only by the source-side offset current generation circuits 421 and 422.
  • FIG. 15 is a circuit diagram for explaining the configuration of the offset correction circuit according to the second modification of the first embodiment.
  • the offset correction circuit 410 of the first differential pair 310 includes an offset correction resistance circuit 413.
  • the offset correction circuit 420 of the second differential pair 320 includes an offset correction resistor circuit 423.
  • the configuration of other parts of the operational amplifier 100 is the same as that of the first embodiment. The description of the common parts with the first embodiment will not be repeated.
  • the offset correction resistance circuit 413 is a variable resistance circuit 414 connected between the (D / N) type NMOS transistor 311 (source) and the node Nx, and the (D / N) type NMOS transistor 312 (source) and the node Nx. It has a variable resistance circuit 415 connected between them.
  • FIG. 16 shows a configuration example of the variable resistance circuits 414 and 415.
  • each of the variable resistance circuits 414 and 415 has resistance elements 640 to 642 and bypass switches 650 to 652.
  • the resistor elements 640 to 642 are connected in series between the node Nx and the (D / N) type NMOS transistor 311 or 312 (source).
  • the bypass switches 650 to 652 are connected in parallel with each of the resistance elements 640 to 642.
  • the bypass switches 650 to 652 are turned on and off according to the control signals dcmp0 to dcmp2 from the control circuit 600 (FIG. 2).
  • the bypass switches 650 to 652 are turned on and off according to the control signals dcmp0 # to dcmp2 # from the control circuit 600 (FIG. 2).
  • the control signals dcmp0 to dcmp2 and dcmp0 # to dcmp2 # are set to "0" when the bypass switch 650 to 652 is turned off, while being set to "1" when the bypass switch 650 to 652 is turned on. ..
  • variable resistance circuit 414 the electrical resistance value (offset correction resistance) between the (D / N) type NMOS transistor 311 and the node Nx changes stepwise according to the control signals dcmp0 to dcmp2. Thereby, the voltage drop amount ⁇ Vx1 generated in the variable resistance circuit 414 can also be adjusted stepwise.
  • variable resistance circuit 415 the electrical resistance value (offset correction resistance) between the (D / N) type NMOS transistor 312 and the node Nx changes stepwise according to the control signals dcmp0 # to dcmp2 #.
  • the voltage drop amount ⁇ Vx2 generated in the variable resistance circuit 415 can also be adjusted stepwise.
  • the electric resistance value of the resistance element 641 can be double the electric resistance value of the resistance element 640
  • the electric resistance value of the resistance element 642 can be double the electric resistance value of the resistance element 641.
  • each of the voltage drop amounts ⁇ Vx1 and ⁇ Vx2 can be adjusted in eight stages by the control signals dcmp0 to dcmp2 and the control signals dcmp0 # to dcmp2 #.
  • the "correction voltage” is generated by setting only one of the voltage drops ⁇ Vx1 and ⁇ Vx2 to zero.
  • Vout> Vimp When a positive offset voltage is generated (Vout> Vimp), the Vgs of the (D / N) type NMOS transistor 311 (Vinp side) is higher than the Vgs of the (D / N) type NMOS transistor 312 (Vinn side). Is presumed. In this case, the voltage drop ⁇ Vx2 (variable resistance circuit 415) on the (D / N) type NMOS transistor 312 side is obtained from the voltage drop ⁇ Vx1 (variable resistance circuit 414) on the (D / N) MOSFET 311 side.
  • the above-mentioned difference in Vgs can be offset. That is, by setting ⁇ Vx2> ⁇ Vx1, it is possible to generate a “correction voltage” for correcting the positive offset voltage.
  • the above-mentioned" correction voltage can be generated.
  • the voltage drop amount ⁇ Vx1 (variable resistance circuit 414) on the (D / N) type NMOS transistor 311 side is set to the (D / N) type NMOS transistor 312 side.
  • the voltage drop amount ⁇ Vx2 (variable resistance circuit 415) is made larger, the above-mentioned difference in Vgs can be offset. That is, by setting ⁇ Vx1> ⁇ Vx2, it is possible to generate a “correction voltage” for correcting the negative offset voltage.
  • ⁇ Vx1> 0 the above-mentioned "correction voltage" can be realized.
  • control signals dcmp0 to dcmp2 and the control signals dcmp0 # to dcmp2 # for obtaining an appropriate correction voltage can be obtained by the same offset test as described with reference to FIG.
  • the offset correction resistor circuit 423 is connected between the variable resistor circuit 424 connected between the E-type NMOS transistor 321 (source) and the node Nx, and the E-type NMOS transistor 322 (source) and the node Nx. It has a variable resistance circuit 425.
  • FIG. 17 shows a configuration example of the variable resistance circuits 424 and 425.
  • each of the variable resistance circuits 424 and 425 has resistance elements 660 to 663 and bypass switches 670 to 673.
  • the resistance elements 660 to 663 are connected in series between the node Nx and the E-type NMOS transistor 321 or 322.
  • Bypass switches 670 to 673 are connected in parallel with each of the resistance elements 660 to 663.
  • the bypass switches 670 to 673 are turned on and off according to the control signals ecmp0 to ecmp3 from the control circuit 600 (FIG. 2).
  • the bypass switches 670 to 673 are turned on and off according to the control signals ecmp0 # to ecmp3 # from the control circuit 600.
  • the control signals ecmp0 to ecmp3 and ecmp0 # to ecmp3 # are set to "0" when the bypass switch 670 to 673 is turned off, while being set to "1" when the bypass switch 670 to 673 is turned on. ..
  • variable resistance circuit 424 the electrical resistance value (that is, offset correction resistance) between the E-type NMOS transistor 321 and the node Nx changes stepwise according to the control signals ecmp0 to ecmp3. Thereby, the voltage drop amount ⁇ Vy1 generated in the variable resistance circuit 424 can also be adjusted stepwise.
  • variable resistance circuit 425 the electrical resistance value (that is, the offset correction resistance) between the E-type NMOS transistor 322 and the node Ny changes stepwise according to the control signals ecmp0 # to ecmp3 #.
  • the voltage drop amount ⁇ Vy2 generated in the variable resistance circuit 425 can also be adjusted stepwise.
  • the electric resistance value of the resistance element 661 is twice the electric resistance value of the resistance element 660
  • the electric resistance value of the resistance element 662 is twice the electric resistance value of the resistance element 661
  • the electric resistance value of the resistance element 663 is set.
  • the electric resistance value can be double the electric resistance value of the resistance element 662.
  • the maximum value of the voltage drops ⁇ Vy1 and ⁇ Vy2 that can be generated by the variable resistance circuits 424 and 425 is larger than the maximum value of the voltage drops ⁇ Vx1 and ⁇ Vx2 that can be generated by the variable resistance circuits 414 and 415.
  • the offset amount that can be compensated by the second differential pair 320 (E type) is increased by the first differential pair 310 ((D / N) type) as in the first embodiment and the first modification thereof. It can be made larger than the offset amount that can be compensated by.
  • the "correction voltage” is generated by setting only one of the voltage drops ⁇ Vy1 and ⁇ Vy2 to zero.
  • Vout> Vimp When a positive offset voltage is generated (Vout> Vimp), it is estimated that the Vgs of the E-type NMOS transistor 321 (Vinp side) is higher than the Vgs of the E-type NMOS transistor 322 (Vinn side) as described above. Be done. In this case, the voltage drop amount ⁇ Vy2 (variable resistance circuit 425) on the E-type NMOS transistor 322 side is made larger than the voltage drop amount ⁇ Vy1 (variable resistance circuit 424) on the E-type NMOS transistor 321 side.
  • the difference in Vgs can be offset. That is, by setting ⁇ Vy2> ⁇ Vy1, it is possible to generate a “correction voltage” for correcting the positive offset voltage.
  • ⁇ Vy2> 0 the above-mentioned “correction voltage” can be generated.
  • Vout ⁇ Vimp negative offset voltage
  • the voltage drop amount ⁇ Vy1 (variable resistance circuit 424) on the E-type NMOS transistor 321 side and the voltage drop amount ⁇ Vy2 (variable resistance circuit) on the E-type NMOS transistor 322 side are used.
  • the above-mentioned difference in Vgs can be offset. That is, by setting ⁇ Vy1> ⁇ Vy2, it is possible to generate a “correction voltage” for correcting the negative offset voltage.
  • ⁇ Vy1> 0 the above-mentioned “correction voltage” can be generated.
  • control signals ecmp0 to ecmp3 or the control signals ecmp0 # to ecmp3 # for obtaining an appropriate correction voltage can be obtained by the same offset test as described with reference to FIG.
  • the offset correction circuits 410 and 420 are configured to include the offset correction resistance circuits 413 and 423.
  • the correction voltage generated by the variable resistance circuits 414,415,424,425 can cancel the difference (offset) between the gate and source voltages between the two NMOS transistors that make up the differential pair. it can. Thereby, the offset voltage can be suppressed.
  • the offset correction amount can be adjusted by the electric resistance value of the resistance element. Therefore, the offset correction amount is adjusted by the current amount. Compared with the 421 and the offset current generation circuits 421 and 422, the offset correction amount can be adjusted with high accuracy.
  • the first differential pair (D / N type) 310 and the second differential pair (E type) are subjected to the "source degeneration" described in Non-Patent Document 1.
  • the gm of an E-type NMOS transistor is higher than the gm of a D-type or native NMOS transistor.
  • the offset voltage is more likely to be generated in the E-type NMOS transistor. Therefore, the offset correction resistance value connected to the source of the E-type NMOS transistors 321 and 322 of the second differential pair 320 is the source of the (D / N) -type NMOS transistors 311, 312 of the first differential pair 310. It tends to be larger than the offset correction resistance value connected to.
  • the decrease in gm is large in the E-type NMOS transistor, while the decrease in gm is small in the D-type or native NMOS transistor.
  • the offset correction by the resistance element is in the direction of balancing the amplification degree between the first differential pair 310 and the second differential pair 320, in the direction of balancing the E-type NMOS transistor and (D / N type).
  • the gm of the NMOS transistor can be changed.
  • FIG. 18 is a circuit diagram for explaining a configuration example of the offset correction circuit according to the third modification of the first embodiment.
  • the offset correction circuit 410 includes both the offset current generation circuit (drain side) 411 and the offset current generation circuit (source side) 412, and the offset correction resistance circuit. 413 and is included.
  • the offset correction circuit 420 includes both the offset current generation circuit 421 (drain side) and the offset current generation circuit (source side) 422, and the offset correction resistance circuit 423.
  • the offset voltage correction amount is adjusted by providing both the offset current generation circuits 411, 421, 421 and 422 and the offset correction resistance circuits 413 and 423. Can be expanded. In particular, by providing the offset correction resistance circuits 413 and 423, it is possible to adjust the offset correction amount with high accuracy. Due to these effects, the offset voltage can be sufficiently suppressed in the entire voltage range of the input voltage Vimp.
  • the offset correction resistance value added by the offset correction resistance circuits 413 and 423 is large, there is a concern that the differential amplification operation by the first differential pair 310 or the second differential pair 320 may be delayed. .. Therefore, for the entire offset correction amount required to keep the offset voltage Vofs within the specifications from the state without offset correction, the correction amount due to the correction current generated by the offset current generation circuits 411, 421, 421, 422 is offset-corrected. It is preferable that the amount is larger than the amount of correction by the correction voltage generated by the resistance circuits 413 and 423.
  • the offset voltage is reduced by rough adjustment by at least one of the offset current generating circuits 411 and 421 and the offset current generating circuits 421 and 422, and then the offset correction resistor circuit.
  • the fine adjustment by 413 and 423 and keeping the offset voltage within the specifications the above-mentioned sharing of the offset correction amount can be realized.
  • the offset correction circuit 410 is composed of at least one of the offset current generation circuit (drain side) 411, the offset current generation circuit (source side) 412, and the offset correction resistance circuit 413. be able to.
  • the offset correction circuit 420 can be composed of at least one of an offset current generation circuit (drain side) 421, an offset current generation circuit 422 (source side), and an offset correction resistance circuit 423.
  • Embodiment 2 In the second embodiment, a configuration in which the first differential pair 310 and the second differential pair 320 are operated alternately will be described.
  • FIG. 19 is a circuit diagram illustrating a configuration example of the operational amplifier according to the second embodiment.
  • the operational amplifier 100 according to the second embodiment is different from the operational amplifier of the first embodiment (FIG. 3) in that it further includes an input voltage detection circuit 300 and a selection circuit 305.
  • the first differential pair 310 and the second differential pair 320 are connected in parallel between the differential nodes Nd1 and Nd2 and the ground node Ng via the selection circuit 305.
  • the active load 330 is connected to both the first differential pair 310 and the second differential pair 320 via the differential nodes Nd1 and Nd2 and the selection circuit 305.
  • the input voltage detection circuit 300 generates detection signals Vdet and Vdett according to the level of the input voltage Vimp. One of the detection signals Vdet and Vdett is set to "1" or "0" in a complementary manner.
  • the detection signals Vdet and Vdett are input to the selection circuit 305.
  • the selection circuit 305 electrically connects one of the first differential pair 310 and the second differential pair 320 to the differential nodes Nd1 and Nd2 according to the detection signals Vdet and Vdett, while the other is different. Electrically disconnected from the dynamic nodes Nd1 and Nd2.
  • the selection circuit 305 has NMOS transistors 314 and 315.
  • the NMOS transistor 314 is connected in series with the (D / N) type NMOS transistor 311 between the differential node Nd1 and the node Nx.
  • the NMOS transistor 315 is connected in series between the differential node Nd2 and the node Nx with the (D / N) type NMOS transistor 312.
  • a detection signal Vdet is input to the gates of the NMOS transistors 314 and 315.
  • Each of the NMOS transistors 314 and 315 operates as a selection switch that turns on when the detection signal Vdet is "1" and turns off when the detection signal Vdet is "0".
  • the selection circuit 305 further includes NMOS transistors 324 and 325.
  • the NMOS transistor 324 is connected in series with the E-type NMOS transistor 321 between the differential node Nd1 and the node Ny.
  • the NMOS transistor 325 is connected in series with the E-type NMOS transistor 322 between the differential node Nd2 and the node Ny.
  • a detection signal Vdett is input to the gates of the NMOS transistors 324 and 325.
  • Each of the NMOS transistors 324 and 325 operates as a selection switch that turns on when the detection signal Vdett is "1" and turns off when the detection signal Vdett is "0".
  • one of the NMOS transistors 314 and 315 and the NMOS transistors 324 and 325 is selectively turned on and the other is turned off according to the detection signals Vdet and Vdett.
  • the differential pair by the (D / N) type NMOS transistors 311, 312 is connected to the differential nodes Nd1 and Nd2. It is. In this case, since the second differential pair 320 is separated from the differential nodes Nd1 and Nd2, the differential amplification operation is executed only by the first differential pair 310.
  • the differential pair by the E-type NMOS transistors 321 and 322 is connected to the differential nodes Nd1 and Nd2. Be done. In this case, since the first differential pair 310 is separated from the differential nodes Nd1 and Nd2, the differential amplification operation is executed only by the second differential pair 320.
  • the first differential pair 310 and the second differential pair 320 are selectively selected according to the detection signals Vdett and Vdett, and are differential. Performs an amplification operation. Since the other parts of the configuration shown in FIG. 19 are the same as those in the first embodiment (FIG. 3), the detailed description will not be repeated.
  • FIG. 20 is a conceptual diagram illustrating the operation of the input voltage detection circuit 300.
  • the boundary value V ⁇ can be set to be equivalent to the boundary value Vs2 of the area B and the area C in FIG. In this way, in the region C where the differential amplification operation by the second differential pair 320 is originally dominant, the second differential pair 320 is selectively connected to the differential nodes Nd1 and Nd2. .. Further, in the region A in which the differential amplification operation by the first differential pair 310 is dominant, the first differential pair 310 is selectively connected to the differential nodes Nd1 and Nd2.
  • the first differential pair 310 in the region B in which the differential amplification operation is executed by both the first differential pair 310 and the second differential pair 320, the first differential pair 310 is selectively different. It is connected to the dynamic nodes Nd1 and Nd2.
  • the boundary value V ⁇ is composed of only the voltage range of the input voltage Vinp such that the voltage region of Vinp> V ⁇ operates in the saturation region of the E-type NMOS transistors 321 and 322 constituting the first differential pair 310. If so, it is possible to set the voltage side lower than the boundary value Vs2 of the region B and the region C.
  • FIG. 21 is a circuit diagram illustrating a configuration example of the input voltage detection circuit 300.
  • the input voltage detection circuit 300 includes an NMOS transistor 361, a current supply unit 362, an NMOS transistor 363, a level shift unit 365, and a buffer 370.
  • the current supply unit 362 is connected between the power supply node Nd and the node N9, and supplies current from the power supply node Nd to the node N9.
  • 22 to 24 show a configuration example of the current supply unit 362.
  • node N9 corresponds to one embodiment of the “internal node”.
  • the current supply unit 362 can be configured by diode-connected NMOS transistors 364n. That is, the NMOS transistor 364n has a gate connected between the power supply node Nd and the node N9 and connected to the power supply node Nd.
  • the current supply unit 362 can also be configured by a diode-connected polyclonal transistor 364p. That is, the polyclonal transistor 364p has a gate connected between the power supply node Nd and the node N9 and connected to the node N9.
  • the current supply unit 362 can be configured by the resistance element 364r connected between the power supply node Nd and the node N9.
  • the NMOS transistor 361 is connected between the nodes N9 and N10.
  • the level shift unit 365 is connected between the nodes N10 and N11.
  • the NMOS transistor 363 is connected between the node N11 and the grounded node Ng.
  • the NMOS transistor 363 operates as a current source when a bias voltage vbn0 is input to the gate.
  • the level shift unit 365 is configured to generate a voltage drop ⁇ V by the current generated by the NMOS transistor 363. As a result, the source voltage of the NMOS transistor 361 rises by ⁇ V as compared with the case where the level shift unit 365 is not arranged.
  • the level shift unit 365 is a diode-connected NMOS transistor 366n, a diode-connected NMOS transistor 366p, or a resistance element connected between the node N11 and the ground node Ng. It can be configured by 366r.
  • buffer 370 has inverters 372 and 374 connected in series.
  • the inverter 372 generates a detection signal Vdett according to the voltage of the node N9. Specifically, the inverter 372 detects that the voltage of the node N9 is higher than the threshold voltage while setting the detection signal Vdett to the H level when the voltage of the node N9 is lower than the threshold voltage. Set the signal Vdett to L level.
  • the inverter 374 inverts the logic level of the output signal (detection signal Vdett) of the inverter 372 and outputs the detection signal Vdet.
  • the NMOS transistor 361 has the same characteristics (threshold voltage, transistor size, etc.) as the E-type NMOS transistor 321 that receives the input voltage Vinp at the gate in the second differential pair (E type) 320. It is composed of E-type NMOS transistors. Therefore, the NMOS transistor 361 corresponds to one embodiment of the "replica transistor".
  • the NMOS transistor 361 When the level shift unit 365 is not arranged, the NMOS transistor 361 is basically turned on or off in common with the E-type NMOS transistor 321 of the second differential pair 320.
  • the level shift unit 365 When the level shift unit 365 is provided, the source voltage of the NMOS transistor 361 is shifted to the power supply voltage VDD side (that is, the "first voltage” side) by ⁇ V. As a result, the NMOS transistor 361 is less likely to be turned on than the NMOS transistor 321 with respect to the gate voltage (input voltage Vimp) common to the NMOS transistor 321. Specifically, the level of the input voltage Vinp on which the NMOS transistor 361 is turned on is increased by the amount of voltage drop ⁇ V at the level shift unit 365.
  • the input voltage Vimp is limited to a voltage region higher than the threshold voltage of the E-type NMOS transistor 321. Therefore, a second differential pair 320 (E type) can be used.
  • the second differential pair 320 is limited to the voltage region of the input voltage Vinp (for example, region C in FIG. 20) in which the E-type NMOS transistor 321 can operate in the saturation region. It is also possible to use (E type). By providing the level shift unit 365 in this way, the second differential pair 320 (E type) can be used by limiting the voltage range to a more appropriate one.
  • the current supply unit 362 it is possible to prevent the source of the NMOS transistor 361 from being directly connected to the power supply node Nd.
  • the NMOS transistor 361 has an input voltage Vinp in a voltage region lower than expected, specifically, a voltage region lower than the threshold voltage of the E-type NMOS transistor 321. It can be suppressed to turn on.
  • the common active load 330 and the input voltage Vinp range are selectively selected.
  • differential amplification is performed with the entire ground voltage GND to power supply voltage VDD as the input / output range. The action can be performed.
  • the offset correction in the area B can be simplified. Specifically, an appropriate correction in the first differential pair 310 obtained by setting the test voltage Vtest within the voltage range of region A and performing an offset test similar to that of the first embodiment.
  • the quantity can also be used in common in region B. That is, the control signals SC11, SC12, and dctrl0 to dctrl2 of the offset correction circuit 410 can be commonly used in the area A and the area B to suppress the offset voltage in the input voltage region of Vimp ⁇ V ⁇ within the specifications.
  • an appropriate offset correction amount is obtained by an offset test performed by setting the test voltage Vtest within the voltage range of the region C, as in the first embodiment. Therefore, the offset voltage in the input voltage region of Vimp> V ⁇ can be suppressed within the specifications.
  • the control signals of the offset correction circuits 410 and 420 are not switched, that is, by a simpler control than that of the first embodiment.
  • the offset voltage in the entire voltage range of the input voltage Vinp can be suppressed.
  • the offset correction circuit 410 is composed of at least one of the offset current generation circuit (drain side) 411, the offset current generation circuit (source side) 412, and the offset correction resistance circuit 413. Can be done.
  • the offset correction circuit 420 can be configured by at least one of an offset current generation circuit (drain side) 421, an offset current generation circuit (source side) 422, and an offset correction resistance circuit 423.
  • the offset correction circuits 410 and 420 are arranged for both the first differential pair 310 and the second differential pair 320, but the first difference It is also possible to arrange the offset correction circuit only on one of the dynamic pair 310 and the second differential pair 320.
  • the characteristic variation (threshold voltage variation) of the (D / N) type NMOS transistor constituting the first differential pair 310 is the characteristic variation (characteristic variation) of the E-type NMOS transistor constituting the second differential pair 320.
  • the arrangement of the offset correction circuit 410 with respect to the first differential pair 310 is omitted, and only the offset correction circuit 420 of the second differential pair 320 is arranged. It is possible to.
  • an active load 330 is configured by a NMOS transistor, and a first differential pair 310 and a second differential pair 320 are configured by a D-type (or native) or E-type NMOS transistor. That is, a configuration example in which the P type corresponds to the "first conductive type" and the N type corresponds to the "second conductive type" has been described.
  • the active load 330 is configured by the NMOS transistor
  • the first differential pair 310 is configured by the D-type (or native) NMOS transistor
  • E is also possible to construct a second differential pair 320 with a type MIMO transistor.
  • the N type corresponds to one embodiment of the "first conductive type”
  • the P type corresponds to one embodiment of the "second conductive type”.
  • the conductive type (N / P) of the transistor is appropriately replaced, and the first differential pair 310, the second differential pair 320, and the active load 330 are used.
  • the power supply node Nd power supply voltage VDD
  • the grounding node Ng grounding voltage
  • first differential pair 310 and the second differential pair 320 are composed of epitaxial transistors, the same as in the offset current generating circuits 411 and 421 between the drain of these epitaxial transistors and the grounded node Ng. It is possible to provide the "first offset current generation circuit” of. Similarly, a “second offset current generation circuit” similar to the offset current generation circuits 421 and 422 can be provided between the source of these epitaxial transistors and the power supply node Nd. Further, it is possible to provide offset correction resistor circuits 413 and 423 between the source of these MIMO transistors and the power supply node Nd.
  • the N-type native transistor has a preferable characteristic in terms of cost that it can be manufactured on a generally used P substrate without the need for adding a mask when manufacturing an NMOS transistor.
  • the P-type native transistor and the D-type MOS transistor manufactured on the N substrate it is necessary to add a mask to the time when the E-type MOS transistor is manufactured.
  • a first differential pair is formed by a native NMOS transistor
  • a second differential pair 320 is formed by an E-type NMOS transistor
  • a NMOS transistor is used. It is advantageous in terms of manufacturing cost to configure the active load 330 by means of.
  • 100 arithmetic amplifier 300 input voltage detection circuit, 305 selection circuit, 310 first differential pair, 311, 312 NMOS transistor (depression type or native transistor), 313 to 315, 321 to 325, 331, 332, 341 ⁇ 346,351n, 3631,363,364n, 366n, 368 NMOS transistor (enhancement type), 333,334,347,348,351p, 364p, 366p MIMO transistor, 320 second differential pair, 330 active load, 340 Bias voltage generator, 350 output stage, 352,353 capacitor, 362 current supply unit, 364r, 366r resistance element (input voltage detection circuit), 365 level shift unit, 370 buffer, 372,374 inverter, 410,420 offset correction circuit , 411,421 offset current generation circuit (drain side), 421,422 offset current generation circuit (source side), 413,423 offset correction resistance circuit, 414,415,424,425 variable resistance circuit, 501-503 characteristic lines, 5

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2025028771A (ja) * 2023-08-18 2025-03-03 ルネサス デザイン （ユーケー） リミテッド レール・ツー・レールｎＭＯＳ増幅器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069353A (ja) * 2001-08-24 2003-03-07 Toshiba Corp 差動増幅回路および液晶表示装置駆動用半導体集積回路
JP2007531459A (ja) * 2004-03-31 2007-11-01 アナログ デバイセス インコーポレーテッド 差動段電圧オフセットトリム回路
JP2009302619A (ja) * 2008-06-10 2009-12-24 Toshiba Corp 演算増幅器
WO2011092767A1 (ja) * 2010-02-01 2011-08-04 パナソニック株式会社 演算増幅回路、信号駆動装置、表示装置及びオフセット電圧調整方法
US20130181775A1 (en) * 2012-01-18 2013-07-18 Quan Wan Rail-to rail input circuit
JP2014204291A (ja) * 2013-04-04 2014-10-27 富士電機株式会社 演算増幅回路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03196279A (ja) * 1989-12-25 1991-08-27 Nec Corp 演算増幅器
JPH03285409A (ja) * 1990-03-30 1991-12-16 Fujitsu Ltd 増幅器
DE19503036C1 (de) * 1995-01-31 1996-02-08 Siemens Ag Differenzverstärker

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069353A (ja) * 2001-08-24 2003-03-07 Toshiba Corp 差動増幅回路および液晶表示装置駆動用半導体集積回路
JP2007531459A (ja) * 2004-03-31 2007-11-01 アナログ デバイセス インコーポレーテッド 差動段電圧オフセットトリム回路
JP2009302619A (ja) * 2008-06-10 2009-12-24 Toshiba Corp 演算増幅器
WO2011092767A1 (ja) * 2010-02-01 2011-08-04 パナソニック株式会社 演算増幅回路、信号駆動装置、表示装置及びオフセット電圧調整方法
US20130181775A1 (en) * 2012-01-18 2013-07-18 Quan Wan Rail-to rail input circuit
JP2014204291A (ja) * 2013-04-04 2014-10-27 富士電機株式会社 演算増幅回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2025028771A (ja) * 2023-08-18 2025-03-03 ルネサス デザイン （ユーケー） リミテッド レール・ツー・レールｎＭＯＳ増幅器

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