WO2021070245A1 - 演算増幅器 - Google Patents

演算増幅器 Download PDF

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Publication number
WO2021070245A1
WO2021070245A1 PCT/JP2019/039649 JP2019039649W WO2021070245A1 WO 2021070245 A1 WO2021070245 A1 WO 2021070245A1 JP 2019039649 W JP2019039649 W JP 2019039649W WO 2021070245 A1 WO2021070245 A1 WO 2021070245A1
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Prior art keywords
voltage
differential
node
differential pair
input
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Ceased
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PCT/JP2019/039649
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English (en)
French (fr)
Japanese (ja)
Inventor
友和 小島
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to PCT/JP2019/039649 priority Critical patent/WO2021070245A1/ja
Priority to JP2021550972A priority patent/JP7301145B2/ja
Priority to US17/631,625 priority patent/US20220278662A1/en
Priority to CN201980101067.5A priority patent/CN114503430A/zh
Publication of WO2021070245A1 publication Critical patent/WO2021070245A1/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45269—Complementary non-cross coupled types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/3022—CMOS common source output SEPP amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45244—Indexing scheme relating to differential amplifiers the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45366—Indexing scheme relating to differential amplifiers the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor

Definitions

  • the present invention relates to an operational amplifier.
  • Patent Document 1 describes a first differential pair composed of a depletion type (D type) MOSFET (Metal Oxide Semiconductor) transistor.
  • D type depletion type MOSFET
  • E type enhancement type MOSFET
  • the input voltage is amplified by the first differential pair in the low potential region, and the input voltage is amplified by the second differential pair in the high potential region, thereby supplying power from the ground. Amplification can be ensured in the entire range up to the voltage.
  • Patent Document 1 describes the transconductance (gmdp) in the saturation region of the D-type PMOSFET constituting the first differential pair and the transformer in the saturation region of the E-type MPa constituting the second differential pair. It is described that the total transconductance (gm) of the operational amplifier is made constant between the low potential region and the high potential region by designing so that the conductance (gmp) is the same.
  • the bias current from the constant current source is differentiated between the first and second by turning on and off the polyclonal transistor in which a constant bias voltage (V1) is input to the gate according to the level of the input voltage. Distributed between pairs. Specifically, in the low potential region, the entire amount of the bias current is distributed to the second differential pair (E-type MIMO) by turning off the epitaxial transistor. On the other hand, in the high potential region, the entire amount of the bypass current is distributed to the first differential pair (D-type polyclonal) by turning on the epitaxial transistor.
  • V1 constant bias voltage
  • the total transconductance of the operational amplifier Is the mean squared conductance of the first differential pair or the second differential pair.
  • the bias current is distributed between the first and second differential pairs, and the distribution ratio also changes depending on the input voltage.
  • the conductance of each differential pair changes depending on the current passing through the differential pair.
  • the transconductance of the first and second differential pairs in the intermediate region is high in the low potential region where the total amount of bias current flows through only one of the first differential pair and the second differential pair. It varies from the transconductance aligned between the potential regions. As a result, it becomes difficult to make the amplification degree constant for the entire region of the input voltage.
  • the present invention has been made to solve such a problem, and an object of the present invention is to supply the first and second voltages to all the voltages from the first voltage to the second voltage.
  • an operational amplifier that operates with the voltage range as the input / output range, the degree of amplification in the entire voltage range is made constant.
  • an operational amplifier that operates by supplying a first voltage and a second voltage, and outputs the first and second input nodes to which the input voltage is input and the output voltage. It includes an output node, first and second differential nodes, an active load, a first differential pair, a second differential pair, an input voltage detection circuit, an output stage, and a selection circuit. ..
  • the active load is connected between the first power supply node that supplies the first voltage and the first and second differential nodes, and is composed of a first conductive type field effect transistor.
  • the first differential pair is connected between the first and second differential nodes and the second power supply node that supplies the second voltage, and is composed of a second conductive field effect transistor. The node.
  • the second differential pair is connected in parallel with the first differential pair between the first and second differential nodes and the second power supply node, and is provided by a second conductive field effect transistor. It is composed.
  • Each of the first and second differential pairs creates a current difference between the first and second differential nodes according to the voltage difference between the first and second input nodes.
  • the input voltage detection circuit generates a detection signal for selecting one of the first and second differential pairs according to the input voltage.
  • the output stage changes the voltage of the output node in the range from the first voltage to the second voltage according to the current difference between the first and second differential nodes.
  • the selection circuit electrically connects one of the first and second differential pairs to the first and second differential nodes and the other from the first and second differential nodes, depending on the detection signal. Electrically disconnect.
  • the field effect transistors forming the first differential pair When the first conductive type is P type and the second conductive type is N type, the field effect transistors forming the first differential pair have a threshold voltage of zero or less and a second differential pair. The field effect transistors that make up the above have a threshold voltage higher than zero.
  • the field effect transistors forming the first differential pair When the first conductive type is N type and the second conductive type is P type, the field effect transistors forming the first differential pair have a threshold voltage of zero or more, while the second conductive type has a second. The field effect transistors that make up the differential pair have a threshold voltage lower than zero.
  • the input voltages are the first and first. Differential to the input voltage in the entire voltage range by one of the first and second differential pairs selected according to which of the two voltage ranges and the active load common in the entire voltage range. By executing the amplification operation, the amplification degree in the entire voltage range can be made constant.
  • FIG. 1 is a 1st conceptual diagram which shows the characteristic of the transconductivity with respect to the input voltage input to a gate in each of an E-type NMOS transistor, a D-type NMOS transistor, and a native NMOS transistor constituting a differential pair. ..
  • FIG. 1 It is a circuit diagram explaining the 3rd example of the level shift part shown in FIG. It is a conceptual diagram explaining the 1st structural example of the input voltage detection circuit which concerns on Embodiment 2.
  • FIG. It is a circuit diagram explaining the 2nd structural example of the input voltage detection circuit which concerns on Embodiment 2.
  • FIG. It is a waveform diagram explaining the control example of the 1st and 2nd differential pairs which concerns on Embodiment 2.
  • FIG. 1 is a conceptual diagram illustrating an example of using an operational amplifier according to the present embodiment.
  • the operational amplifier 100 has a non-inverting input node Nip, an inverting input node Nin, and an output node No.
  • the voltages of the non-inverting input node Nippon and the inverting input node are referred to as input voltages Vimp and Vinn, and the voltage of the output node No. is referred to as an output voltage Vout.
  • the operational amplifier 100 is connected to a ground node Ng that supplies the ground voltage GND and a power node Nd that supplies the power supply voltage VDD.
  • a ground node Ng that supplies the ground voltage GND
  • a power node Nd that supplies the power supply voltage VDD.
  • each of the input voltages Vimp, Vinn, and the output voltage Vout changes within the voltage range of GND to VDD. That is, the operational amplifier 100 operates as a rail-to-rail input / output operational amplifier.
  • the operational amplifier 100 operates as a voltage follower amplifier in which the output node No. and the inverting input node Nin are connected.
  • Vnp Vsns
  • Vsns the operational amplifier 100 can be used in any mode different from the voltage follower connection.
  • FIG. 2 is a block diagram illustrating a configuration example of the operational amplifier according to the first embodiment.
  • the operational amplifier 100 includes an input voltage detection circuit 300, a selection circuit 305, a first differential pair 310, a second differential pair 320, and an active load 330.
  • a bias voltage generation unit 340 for the output stage and an output stage 350 are provided.
  • the active load 330 is composed of a first conductive field effect transistor.
  • the first differential pair 310 and the second differential pair 320 are composed of a second conductive type field effect transistor which is an opposite conductive type to the first conductive type.
  • the active load 330 is connected between the differential nodes Nd1 and Nd2 and the power supply node Nd.
  • the first differential pair 310 and the second differential pair 320 are connected in parallel between the differential nodes Nd1 and Nd2 and the ground node Ng via the selection circuit 305.
  • the active load 330 is connected to both the first differential pair 310 and the second differential pair 320 via the differential nodes Nd1 and Nd2 and the selection circuit 305.
  • Input voltages Vinp and Vinn are input to each of the first differential pair 310 and the second differential pair 320 from the non-inverting input node Nip and the inverting input node Nin.
  • the power supply node Nd connected to the active load 330 corresponds to one embodiment of the "first power supply node", and the power supply voltage VDD corresponds to the "first voltage”.
  • the ground node Ng connected to the first differential pair 310 and the second differential pair 320 corresponds to one embodiment of the "second power supply node", and the ground voltage GND is "second voltage”. Corresponds to.
  • the input voltage detection circuit 300 is set to either a logical high level (hereinafter, simply referred to as “H level”) or a logical low level (hereinafter, simply referred to as “L level”) according to the level of the input voltage Vinp.
  • the detection signals Vdet and Vdett are generated.
  • the detection signals Vdet and Vdett are set to complement each of the H level and the L level.
  • the detection signals Vdet and Vdett are input to the selection circuit 305.
  • the selection circuit 305 electrically connects one of the first differential pair 310 and the second differential pair 320 to the differential nodes Nd1 and Nd2 according to the detection signals Vdet and Vdett, while the other is different. Electrically disconnected from the dynamic nodes Nd1 and Nd2.
  • the active load 330 and the bias voltage generating unit 340 for the output stage are connected between the power supply node Nd and the grounding node Ng.
  • the output stage 350 is connected to the power supply node Nd, the ground node Ng, the output node No, the active load 330, and the bias voltage generation unit 340. As will be described later, the output stage 350 is configured to change the output voltage Vo of the output node No. within the range of the ground voltage GND to the power supply voltage VDD according to the current difference between the differential nodes Nd1 and Nd2.
  • the first differential pair 310 and the second differential pair 320 are composed of N-type MOSFETs (hereinafter, also simply referred to as “NMOS transistors”), and the active load 330 is a P-type MOSFET (hereinafter, also referred to as “NMOS transistor”).
  • NMOS transistor P-type MOSFET
  • an example composed of also referred to simply as a “NMR transistor” will be described. That is, in the following examples, the P type corresponds to one embodiment of the "first conductive type”, and the N type corresponds to one embodiment of the "second conductive type”.
  • the first differential pair 310 has the NMOS transistors 311, 312.
  • the NMOS transistors 311, 312 are configured to have a threshold voltage Vt such that a drain current flows when the gate-source voltage (hereinafter, also simply referred to as “gate voltage”) is 0 [V].
  • the NMOS transistors 311, 312 can be composed of a depletion type NMOS transistor or a native NMOS transistor.
  • NMOS transistor having a threshold voltage Vt ⁇ 1 a depletion type NMOS transistor and a native NMOS transistor are collectively referred to as a (D / N) type NMOS transistor.
  • a normal enhancement type NMOS transistor having Vt> 0 is basically simply referred to as an "NMOS transistor", but when compared with a (D / N) type, it is an E-type NMOS transistor. Also written as. Further, the enhancement type epitaxial transistor is also simply referred to as a epitaxial transistor.
  • the selection circuit 305 has NMOS transistors 314 and 315.
  • the (D / N) type NMOS transistor 311 and the NMOS transistor 314 are connected in series between the differential node Nd1 and the node Nb1.
  • the (D / N) type NMOS transistor 312 and the NMOS transistor 315 are connected in series between the differential node Nd2 and the node Nb1.
  • the gate of the (D / N) type NMOS transistor 311 is connected to the non-inverting input node Nippon (input voltage Vinp), and the gate of the (D / N) type NMOS transistor 312 is connected to the inverting input node Nin (input voltage Vinn). Be connected.
  • (D / N) MOSFET transistors 311 and 312 form a differential pair in which the input voltages Vinp and Vinn are input to the gate.
  • a detection signal Vdet is input to the gates of the NMOS transistors 314 and 315. Therefore, each of the NMOS transistors 314 and 315 operates as a selection switch that turns on at the H level of the detection signal Vdet and turns off at the L level.
  • the NMOS transistor 313 is connected between the node Nb1 and the ground node Ng, and the bias voltage vbn0 is input to the gate.
  • the NMOS transistor 313 operates as a bias tail current source for differential amplification, supplying a current corresponding to the bias voltage vbn0.
  • the second differential pair 320 has NMOS transistors 321 and 322.
  • the selection circuit 305 further includes NMOS transistors 324 and 325.
  • the NMOS transistors 321 and 324 are connected in series between the differential nodes Nd1 and Nb2.
  • the NMOS transistors 322 and 325 are connected in series between the differential nodes Nd2 and Nb2.
  • the gate of the NMOS transistor 321 is connected to the non-inverting input node Nippon (input voltage Vinp), and the gate of the NMOS transistor 322 is connected to the inverting input node Nin (input voltage Vinn). Therefore, in the second differential pair 320, the E-type NMOS transistors 321 and 322 form a differential pair in which the input voltages Vinp and Vinn are input to the gate.
  • a detection signal Vdett is input to the gates of the NMOS transistors 324 and 325. Therefore, each of the NMOS transistors 324 and 325 operates as a selection switch that turns on at the H level of the detection signal Vdett and turns off at the L level.
  • the NMOS transistor 323 is connected between the node Nb2 and the ground node Ng, and the bias voltage vbn0 is input to the gate.
  • the current of the NMOS transistor 313 and the current of the NMOS transistor 323 are designed to be equivalent.
  • the active load 330 has epitaxial transistors 331 to 334.
  • the epitaxial transistor 331 is connected between the power supply node Nd and the differential node Nd1.
  • the epitaxial transistor 332 is connected between the power supply node Nd and the differential node Nd2.
  • the MIMO transistor 333 is connected between the differential nodes Nd1 and N3, and the MIMO transistor 334 is connected between the differential nodes Nd2 and N4.
  • the gates of the epitaxial transistors 331 and 332 are connected to the node N4.
  • a common bias voltage vbp3 is input to the gates of the epitaxial transistors 333 and 334.
  • the polyclonal transistors 331 and 332 operate as an active load, and the epitaxial transistors 333 and 334 are cascode-connected to the active load.
  • the bias voltage generation unit 340 has an NMOS transistors 341 to 346 and a NMOS transistors 347 and 348.
  • the NMOS transistor 345 and the NMOS transistor 347 are connected in parallel between the nodes N4 and N6.
  • the NMOS transistors 341 and 343 are connected in series between the node N6 and the grounded node Ng.
  • the NMOS transistor 346 and the NMOS transistor 348 are connected in parallel between the nodes N3 and N5.
  • the NMOS transistors 342 and 344 are connected in series between the node N5 and the grounded node Ng via the node N7.
  • a bias voltage vbn1 is input to the gate of the NMOS transistor 345, and a bias voltage vbn2 is input to the gate of the NMOS transistor 346.
  • a bias voltage vbp1 is input to the gate of the NMOS transistor 347, and a bias voltage vbp2 is input to the gate of the NMOS transistor 348.
  • a bias voltage vbn3 is commonly input to the gates of the NMOS transistors 341 and 342.
  • the gates of the NMOS transistors 343 and 344 are connected to the node N6.
  • the NMOS transistors 343 and 344 operate as active loads, and the NMOS transistors 341 and 342 are cascode-connected to the active load. Further, the NMOS transistors 345, 346 and the NMOS transistors 347, 348 operate as floating current sources.
  • the output stage 350 is of a push-pull type and has a NMOS transistor 351p, an NMOS transistor 351n, and capacitors 352 and 353.
  • the PRIVATE transistor 351p is connected between the power supply node Nd and the output node No.
  • the NMOS transistor 351n is connected between the output node No. and the ground node Ng.
  • the gate of the NMOS transistor 351p is connected to the node N3, and the gate of the NMOS transistor 351n is connected to the node N5.
  • the NMOS transistor 351n operates so as to discharge the source current to the output node No. in response to the increase in the current of the differential node Nd1 in response to the increase in the input voltage Vinp.
  • the MIMO transistor 351p operates so as to suck the sink current from the output node No. in response to the increase in the current of the differential node Nd2 in response to the decrease in the input voltage Vinp.
  • the bias voltage generation unit 340 can operate so as to bias the gate voltage of the NMOS transistor 351p and the NMOS transistor 351n so that the so-called class AB amplification operation is realized.
  • the currents of the MPa transistor 351p and the NMOS transistor 351n are set to be about the same as the current flowing through the NMOS transistors 313 and 323 (bias tail current source) except during the amplification operation period, while the currents are the same during the amplification operation.
  • bias voltage By controlling the bias voltage so that a current of several hundred times to several thousand times the current flows, class AB operation becomes possible.
  • a current source, a current mirror circuit, or the like can be simply arranged instead of the bias voltage generating unit 340.
  • the capacitor 352 is connected between the differential node Nd1 and the output node No.
  • the capacitor 353 is connected between the output node No. and the node N7. Capacitors 352 and 353 operate as phase compensation capacitances.
  • the selection circuit 305 Since the detection signals Vdet and Vdett are complementarily set to H level and L level, in the selection circuit 305, one of the NMOS transistors 314 and 315 and the NMOS transistors 324 and 325 is selectively turned on and the other is turned off. Be done.
  • the differential pair by the (D / N) type NMOS transistors 311, 312 is connected to the differential nodes Nd1 and Nd2.
  • the (D / N) type NMOS transistors 311 and 312 correspond to the "first field effect transistor” and the “second field effect transistor”. Further, the NMOS transistors 314 and 315 form a "first selection switch”, and the NMOS transistors 313 form a "first current source transistor”.
  • the E-type NMOS transistors 321 and 322 correspond to the "third field effect transistor” and the "fourth field effect transistor”. Further, the NMOS transistors 324 and 325 constitute a “second selection switch”, and the NMOS transistors 323 constitute a "second current source transistor”.
  • the input voltage Vimp is higher than the input voltage Vte corresponding to the threshold voltage Vt (Vt> 0) of the E-type NMOS transistor.
  • Vte threshold voltage
  • Id 0
  • the region of Vimp> Vte Id> 0 because gm rises, and when the input voltage Vimp rises beyond a certain voltage, the region (saturation region) in which gm does not change with respect to the rise of the input voltage Vimp becomes.
  • the second differential pair 320 by the E-type NMOS transistor cannot perform differential amplification in the region A of 0 ⁇ Vimp ⁇ Vte.
  • the fabrication of a depletion type NMOS transistor may lead to an increase in cost, it is cost-effective to configure the first differential pair 310 with a native NMOS transistor obtained by fabrication an NMOS on a P substrate. It is advantageous from.
  • the native NMOS transistor has a characteristic that the threshold voltage Vt is in the vicinity of 0 [V]. Therefore, even if the transistors 311, 312 of the first differential pair 310 are configured by using the native NMOS transistors having the characteristic of the threshold voltage Vt ⁇ 0, the voltage region (region) of 0 ⁇ Vimp ⁇ Vte Differential amplification can be performed in A).
  • the differential in the region A (0 ⁇ Vimp ⁇ Vte) is provided by the first differential pair 310 composed of the D-type NMOS transistor or the D-type NMOS transistor. Amplification operation can be realized.
  • FIG. 5 shows another example of the characteristics of a native NMOS transistor.
  • the amplification operation is difficult with the first differential pair 310 composed of the D-type NMOS transistor or the native NMOS transistor.
  • the input voltage Vinp is set in a state where the transistors 311, 312 (D-type NMOS transistor or native NMOS transistor) constituting the first differential pair 310 are connected to the differential nodes Nd1 and Nd2.
  • the threshold voltage is 0 or negative, so that the voltage of the differential node Nd1 is also in the vicinity of the power supply voltage VDD.
  • the Vds (drain-source voltage) of the epitaxial transistors 331 and 332 constituting the active load becomes almost 0, which makes the differential amplification operation difficult.
  • the NMOS transistors 321 and 322 (E type) constituting the second differential pair 320
  • the voltage of the differential node Nd1 is the power supply voltage. It is lower than VDD by the threshold voltage Vt of the E-type NMOS transistor.
  • the above threshold voltage Vt (for example, about 0.8 [V]) can be secured as Vds of the epitaxial transistors 331 and 332 constituting the active load, so that the differential amplification operation becomes possible.
  • the boundary value V ⁇ of the region C can be set within the range of the input voltage Vinp corresponding to the gate voltage range in which the E-type NMOS transistors 321 and 322 operate in the saturation region.
  • region B Vte ⁇ Vimp ⁇ V ⁇
  • a drain current is generated even in the E-type MOS transistor. Therefore, in region B, differential amplification is possible with both the first differential pair 310 (D / N type) and the second differential pair 320 (E type). Therefore, in Patent Document 1, in the intermediate voltage region corresponding to the region B, the bias current is shared and differentialed by both the differential pair by the E-type MIMO transistor and the differential pair by the D-type epitaxial transistor. Amplification is in progress.
  • the operational amplifier 100 in both the region A and the region B other than the region C, only the first differential pair 310 by the D-type NMOS transistor or the native NMOS transistor is used for the difference.
  • the region A and the region B form an embodiment of the "first voltage range”
  • the region C forms an embodiment of the "second voltage range”.
  • the input voltage Vinp (Timp Vte) when the gate-source voltage of the E-type NMOS transistors 321 and 322 is equal to the threshold voltage Vt, that is, the input voltage Vinp corresponding to the threshold voltage Vt is ". It is understood that it is included in the "first voltage range”.
  • FIG. 6 is a circuit diagram illustrating a configuration example of the input voltage detection circuit 300.
  • the input voltage detection circuit 300 includes an NMOS transistor 361, a current supply unit 362, an NMOS transistor 363, a level shift unit 365, and a buffer 370.
  • the current supply unit 362 is connected between the power supply node Nd and the node N9, and supplies current from the power supply node Nd to the node N9.
  • 7 to 9 show a configuration example of the current supply unit 362.
  • node N9 corresponds to one embodiment of the “internal node”.
  • the current supply unit 362 can be configured by diode-connected NMOS transistors 364n. That is, the NMOS transistor 364n has a gate connected between the power supply node Nd and the node N9 and connected to the power supply node Nd.
  • the current supply unit 362 can also be configured by a diode-connected polyclonal transistor 364p. That is, the polyclonal transistor 364p has a gate connected between the power supply node Nd and the node N9 and connected to the node N9.
  • the current supply unit 362 can be configured by the resistance element 364r connected between the power supply node Nd and the node N9.
  • the NMOS transistor 361 is connected between the nodes N9 and N10.
  • the level shift unit 365 is connected between the nodes N10 and N11.
  • the NMOS transistor 363 is connected between the node N11 and the grounded node Ng.
  • the NMOS transistor 363 operates as a current source when a bias voltage vbn0 is input to the gate.
  • the NMOS transistor 363 constitutes a "third current source transistor”.
  • the level shift unit 365 is configured to generate a voltage drop ⁇ V by the current generated by the NMOS transistor 363. As a result, the source voltage of the NMOS transistor 361 rises by ⁇ V as compared with the case where the level shift unit 365 is not arranged.
  • the level shift unit 365 is a diode-connected NMOS transistor 366n, a diode-connected NMOS transistor 366p, or a resistance element connected between the node N11 and the ground node Ng. It can be configured by 366r.
  • buffer 370 has inverters 372 and 374 connected in series.
  • the inverter 372 generates a detection signal Vdett according to the voltage of the node N9. Specifically, the inverter 372 detects that the voltage of the node N9 is higher than the threshold voltage while setting the detection signal Vdett to the H level when the voltage of the node N9 is lower than the threshold voltage. Set the signal Vdett to L level.
  • the inverter 374 inverts the logic level of the output signal (detection signal Vdett) of the inverter 372 and outputs the detection signal Vdet.
  • the differential pair (first differential pair) by the (D / N) type NMOS transistors 311, 312 is used.
  • a differential amplification operation is performed using 310).
  • a differential pair (second differential pair 320) by the E-type NMOS transistors 321 and 322 is used by turning on the NMOS transistors 324 and 325 (turning off the NMOS transistors 314 and 315). , The differential amplification operation is performed.
  • the input voltage Vinp which is the boundary value at which the NMOS transistor 361 is turned on, corresponds to the boundary value V ⁇ of the region B and the region C shown in FIGS. 4 and 5.
  • the NMOS transistor 361 has the same characteristics (threshold voltage, transistor size, etc.) as the E-type NMOS transistor 321 that receives the input voltage Vinp at the gate in the second differential pair (E type) 320. It is composed of E-type NMOS transistors. Therefore, the NMOS transistor 361 corresponds to one embodiment of the "replica transistor".
  • the NMOS transistor 361 When the level shift unit 365 is not arranged, the NMOS transistor 361 is basically turned on or off in common with the E-type NMOS transistor 321 of the second differential pair 320.
  • the boundary value V ⁇ corresponds to the threshold voltage Vt (that is, Vte in FIGS. 4 and 5) of the NMOS transistor (E type) 361 and the NMOS transistor (E type) 321. Therefore, even if the level shift unit 365 is not arranged, the detection signal Vdedn is generated so as to select the second differential pair 320 (E type) in conjunction with the operable range of the E type NMOS transistor 321. be able to.
  • the level shift unit 365 When the level shift unit 365 is provided, the source voltage of the NMOS transistor 361 is shifted to the power supply voltage VDD side (that is, the "first voltage” side) by ⁇ V. As a result, the NMOS transistor 361 is less likely to be turned on than the NMOS transistor 321 with respect to the gate voltage (input voltage Vimp) common to the NMOS transistor 321. Specifically, the level of the input voltage Vinp on which the NMOS transistor 361 is turned on is increased by the amount of voltage drop ⁇ V at the level shift unit 365.
  • the boundary value V ⁇ Vte + ⁇ V shown in FIGS. 4 and 5 can be set.
  • the input voltage Vimp is limited to a voltage region higher than the threshold voltage of the E-type NMOS transistor 321. Therefore, a second differential pair 320 (E type) can be used.
  • the second differential pair 320 (E type) can be used by limiting the voltage range to a more appropriate one.
  • the current supply unit 362 it is possible to prevent the source of the NMOS transistor 361 from being directly connected to the power supply node Nd.
  • the NMOS transistor 361 has an input voltage Vinp in a voltage region lower than expected, specifically, a voltage region lower than the threshold voltage of the E-type NMOS transistor 321. It can be suppressed to turn on.
  • the common active load 330 and the first differential pair selected according to the range of the input voltage Vinp are combined with either 310 (D / N type) or the second differential pair 320 (E type), the differential amplification operation is executed with the entire ground voltage GND to power supply voltage VDD as the input / output range. Can be done.
  • both the differential pair using the E-type NMOS transistor and the differential pair using the D-type (or native) NMOS transistor are differentially amplified by using a part of the bias current. There is no voltage range to perform the operation. This facilitates constant overall transconductance (gm) of the operational amplifier over the entire voltage region (eg, between regions A to C in FIGS. 4 and 5).
  • the output resistance rA corresponds to the output resistance of the epitaxial transistors 331 and 332 of the active load 330.
  • the output resistance rD corresponds to the output resistance of the NMOS transistors 311, 312, 321 and 322 constituting the differential pair.
  • the drain current Id of the NMOS transistor in the saturation region is represented by the following equation (1) using the gain coefficient ⁇ and the channel length modulation constant ⁇ .
  • the gain coefficient ⁇ is an element constant determined by the surface average mobility ⁇ , the channel length L, the channel width W, and the gate capacitance Cox per unit area, as shown in the following equation (2).
  • dId / dVds (W / L) ⁇ ⁇ ⁇ Cox... (2)
  • a common active regardless of whether the first differential pair 310 (D / N) or the second differential pair 320 (E type) is used for differential amplification.
  • a load 330 (op amp transistors 331, 332) is used.
  • the bias tail current of the first differential pair 310 in the differential amplification operation in the region A and the region B is equivalent to the bias tail current of the second differential pair 320 in the differential amplification operation in the region C. Is.
  • the output resistance rD of the transistors forming the differential pair is maintained at the same value throughout the regions A to C.
  • the gm of the differential pair is determined by the transistor size, tail current, mobility, gate oxide film thickness, etc. of the NMOS transistors 311, 312, 321 and 322 constituting the differential pair.
  • the transistor size of the NMOS transistors 311, 312 is set.
  • the region A within the entire voltage range A can be made constant in each of the regions C.
  • Embodiment 2 In the second embodiment, an improvement example for the operational amplifier according to the first embodiment will be described.
  • FIG. 13 is a conceptual diagram illustrating a first configuration example of the input voltage detection circuit according to the second embodiment.
  • the supply current Id0 by the NMOS transistor 363 (FIG. 6) of the input voltage detection circuit 300 is the NMOS transistor 313 (FIG. 6) of the first differential pair 310. It is set to be larger than the supply current Id1 according to 3) and the supply current Id2 due to the second differential pair 320 NMOS transistor 323 (FIG. 3).
  • the transistor size (W / L ratio) of the transistor 363 is set to the transistor size (W / L ratio) of the transistor 363 so that the supply current Id0 is N times the supply currents Id1 and Id2 (N: N> 1 real number).
  • the size (W / L ratio) is set to N times, Id0> Id1 and Id0> Id2 can be realized.
  • the gate voltage (vbn0) of the transistor 363 should be higher than the gate voltage (vbn0) of the transistors 313 and 323.
  • the supply current Id0 can be made larger than the supply currents Id1 and Id2. This also allows the operating speed of the input voltage detection circuit 300 to be higher than the speed of the differential amplification operation of the first differential pair 310 and the second differential pair 320.
  • the first differential pair 310 and the second differential pair 320 are selectively connected to the active load 330 according to the level of the input voltage Vimp.
  • the amplification degree in the entire voltage range is constant. Therefore, when the operating speed of the input voltage detection circuit 300 is lower than the operating speed of the first differential pair 310 and the second differential pair 320, the first differential pair 310 and the second differential pair 320 There is a concern that noise or distortion may occur in the differential amplification operation due to the effect of the switching operation of, that is, the on / off switching of the NMOS transistors 314 and 315 and the NMOS transistors 324 and 325.
  • the supply current Id0 to the NMOS transistor 361 is set to the supply current Id1 to the NMOS transistors 311, 312, 321 and 322 constituting the differential pair.
  • Id2 N> 1
  • the operating speed of the input voltage detection circuit 300 is made higher than the speed of the differential amplification operation in the first differential pair 310 and the second differential pair 320. can do.
  • the operating speed of the input voltage detection circuit 300 is the operating speed of the first differential pair 310 and the second differential pair 320.
  • it can be increased to ⁇ N times (when operating in the strong inversion saturated region) or N times (when operating in the weak inversion region).
  • the range is N ⁇ 10.
  • FIG. 14 is a circuit diagram illustrating a second configuration example of the input voltage detection circuit according to the second embodiment.
  • the input voltage detection circuit 300 further includes an NMOS transistor 368 and a switch 369 as compared with the configuration of the first embodiment (FIG. 6). Is different.
  • the NMOS transistor 368 and the switch 369 are connected in series between the node N11 and the grounded node Ng.
  • the NMOS transistor 368 receives a bias voltage vbn0 at the gate and operates as a current source.
  • the switch 369 turns on and off according to the detection signal Vdet output by the inverter 374. Specifically, the switch 369 is turned on at the H level of the detection signal Vdet, while it is turned off at the L level of the detection signal Vdet. Since the configuration of the other parts of the input voltage detection circuit 300 shown in FIG. 14 is the same as that in FIG. 6, the description of the common parts with FIG. 6 is not repeated.
  • the voltage drop amount ⁇ V1 of the level shift unit 365 is generated by the supply current of only the NMOS transistor 363.
  • a voltage drop amount ⁇ V2 larger than the above ⁇ V1 is generated in the level shift portion 365 due to the sum of the supply currents of the NMOS transistors 363 and 368 connected in parallel (the voltage drop amount ⁇ V2 is larger than that of the ⁇ V1).
  • the detection signal Vdet H level (that is, when Vimp ⁇ V ⁇ ), when the input voltage Vimp rises above Vte + ⁇ V2, that is, the input voltage Vimp exceeds Vte + ⁇ V2 and the power supply voltage VDD (first).
  • the detection signal changes from H level to L level due to the turn-on of the NMOS transistor 361.
  • the detection signal Vdet L level (that is, when Vimp> V ⁇ )
  • the input voltage Vimp is lower than Vte + ⁇ V1
  • the input voltage Vimp exceeds Vte + ⁇ V1 and the ground voltage GND (that is, When approaching the second voltage)
  • the detection signal changes from the L level to the H level due to the turn-off of the NMOS transistor 361.
  • the boundary value V ⁇ (first boundary value) when the detection signal Vdet changes from the H level to the L level according to the increase in the input voltage Vimp becomes equivalent to Vte + ⁇ V2.
  • the boundary value V ⁇ (second boundary value) when the detection signal Vdet changes from the L level to the H level according to the decrease in the input voltage Vimp becomes equivalent to Vte + ⁇ V1. That is, the first boundary value can be set closer to the power supply voltage VDD than the second boundary value.
  • FIG. 15 is a waveform diagram illustrating a control example of the first and second differential pairs according to the second embodiment.
  • the gate voltage of the NMOS transistors 313 and 323 operating as the bias tail current source is variably controlled.
  • the leakage current in the non-selected differential pair can be reduced.
  • the power consumption of the operational amplifier 100 can be reduced.
  • an active load 330 is configured by a NMOS transistor, and a first differential pair 310 and a second differential pair 320 are configured by a D-type (or native) or E-type NMOS transistor. That is, a configuration example in which the P type corresponds to the "first conductive type" and the N type corresponds to the "second conductive type" has been described.
  • the active load 330 is configured by the NMOS transistor
  • the first differential pair 310 is configured by the D-type (or native) NMOS transistor
  • E is also possible to construct a second differential pair 320 with a type MIMO transistor.
  • the N type corresponds to one embodiment of the "first conductive type”
  • the P type corresponds to one embodiment of the "second conductive type”.
  • the conductive type (N / P) of the transistor is appropriately replaced, and the first differential pair 310, the second differential pair 320, and the active load 330 are used.
  • the power supply node Nd power supply voltage VDD
  • the grounding node Ng grounding voltage
  • the N-type native transistor has a preferable characteristic in terms of cost that it can be manufactured on a generally used P substrate without the need for adding a mask when manufacturing an NMOS transistor.
  • the P-type native transistor and the D-type MOS transistor manufactured on the N substrate it is necessary to add a mask to the time when the E-type MOS transistor is manufactured.
  • a first differential pair is formed by a native NMOS transistor
  • a second differential pair 320 is formed by an E-type NMOS transistor
  • a NMOS transistor is used. It is advantageous in terms of manufacturing cost to configure the active load 330 by means of.
  • 100 arithmetic amplifier 300 input voltage detection circuit, 305 selection circuit, 310 first differential pair, 311, 312 NMOS transistor (depression type or native transistor), 313 to 315, 321 to 325, 331, 332, 341 ⁇ 346,351n, 3631,363,364n, 366n, 368 NMOS transistor (enhancement type), 333,334,347,348,351p, 364p, 366p MIMO transistor, 320 second differential pair, 330 active load, 340 Bias voltage generator, 350 output stage, 352,353 capacitor, 362 current supply unit, 364r, 366r resistance element, 365 level shift unit, 369 switch, 370 buffer, 372,374 inverter, GND ground voltage, Id0 to Id2 supply current (Current source transistor), N3 to N7, N9 to N11, Nb1, Nb2 node, Nd power supply node, Nd1, Nd2 differential node, Ng grounding node, Nin invert

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PCT/JP2019/039649 2019-10-08 2019-10-08 演算増幅器 Ceased WO2021070245A1 (ja)

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US17/631,625 US20220278662A1 (en) 2019-10-08 2019-10-08 Operational Amplifier
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US20240429887A1 (en) * 2023-06-21 2024-12-26 Qualcomm Incorporated Operational transconductance amplifier with boosted transconductance
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