WO2021068344A1 - 一种液晶显示电路、液晶显示电路驱动方法及显示面板 - Google Patents

一种液晶显示电路、液晶显示电路驱动方法及显示面板 Download PDF

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Publication number
WO2021068344A1
WO2021068344A1 PCT/CN2019/118186 CN2019118186W WO2021068344A1 WO 2021068344 A1 WO2021068344 A1 WO 2021068344A1 CN 2019118186 W CN2019118186 W CN 2019118186W WO 2021068344 A1 WO2021068344 A1 WO 2021068344A1
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Prior art keywords
signal line
switch
clock signal
liquid crystal
crystal display
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PCT/CN2019/118186
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English (en)
French (fr)
Inventor
徐洪远
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Tcl华星光电技术有限公司
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Priority to US16/620,878 priority Critical patent/US20220004068A1/en
Publication of WO2021068344A1 publication Critical patent/WO2021068344A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction

Definitions

  • This application relates to the field of panel manufacturing technology, and in particular to a liquid crystal display circuit, a liquid crystal display circuit driving method, and a display panel.
  • LCD(Liquid Crystal display (liquid crystal display) is a widely used flat panel display, which mainly realizes picture display by modulating the intensity of the light field of the backlight source through a liquid crystal switch.
  • VA mode is a common display mode that has the advantages of high contrast, wide viewing angle, and no friction alignment.
  • VA display uses a vertically rotating liquid crystal, the difference in the birefringence of the liquid crystal molecules is relatively large, resulting in a serious color shift problem under a large viewing angle.
  • the purpose of the embodiments of the present application is to provide a liquid crystal display circuit, a liquid crystal display circuit driving method, and a display panel, which can solve the existing technical problem of color shift.
  • An embodiment of the application provides a liquid crystal display circuit, including:
  • a plurality of pixel units are arranged in a rectangular array, and each pixel unit includes a first pixel area and a second pixel area;
  • a plurality of data lines for connecting with the pixel unit to input data information to the pixel unit each data line includes a first signal line and a second signal line;
  • a plurality of scan lines are used to connect with the pixel unit to transmit driving signals to the pixel unit;
  • a first clock signal line connected to the first signal line
  • a second clock signal line connected to the second signal line
  • the first clock signal line controls the first signal line
  • the second clock signal line controls the second signal line
  • the first clock signal line and the second clock signal line are turned on or off alternately to So that the first pixel area and the second pixel area are at different potentials.
  • the first signal line is provided with a first switch
  • the second signal line is provided with a second switch
  • the first clock signal line is connected to the first switch
  • the second The clock signal line is connected to the second switch.
  • the first switch controls the first signal line
  • the second switch controls the second signal line
  • the first signal line and the second signal line have opposite polarities
  • the first switch is a P-type switch
  • the second switch is an N-type switch
  • two adjacent pixel units in the same column have opposite polarities.
  • the refresh frequency of the two clock signal lines is 120HZ.
  • the first switch and the second switch are the same type of switch.
  • An embodiment of the present application also provides a method for driving a liquid crystal display circuit, including:
  • each pixel unit includes a first pixel area and a second pixel area;
  • each data line includes a first signal line and a second signal line;
  • the first clock signal line controls the first signal line
  • the second clock signal line controls the second signal line
  • the first clock signal line and the second clock signal line are turned on or off alternately to So that the first pixel area and the second pixel area are at different potentials.
  • the first signal line is provided with a first switch
  • the second signal line is provided with a second switch
  • the first clock signal line is connected to the first switch
  • the second signal line is connected to the first switch.
  • the clock signal line is connected to the second switch.
  • the first switch controls the first signal line
  • the second switch controls the second signal line
  • the first signal line and the second signal line have opposite polarities
  • the first switch is a P-type switch
  • the second switch is an N-type switch
  • two adjacent pixel units in the same column have opposite polarities.
  • the refresh frequency of the two clock signal lines is 120HZ.
  • the first switch and the second switch are the same type of switch.
  • An embodiment of the application provides a display panel including a liquid crystal display circuit.
  • the liquid crystal display circuit includes a plurality of pixel units arranged in a rectangular array, and each pixel unit includes a first pixel area and a second pixel area;
  • a plurality of data lines for connecting with the pixel unit to input data information to the pixel unit each data line includes a first signal line and a second signal line;
  • a plurality of scan lines are used to connect with the pixel unit to transmit driving signals to the pixel unit;
  • a first clock signal line connected to the first signal line
  • a second clock signal line connected to the second signal line
  • the first clock signal line controls the first signal line
  • the second clock signal line controls the second signal line
  • the first clock signal line and the second clock signal line are turned on or off alternately to So that the first pixel area and the second pixel area are at different potentials.
  • the first signal line is provided with a first switch
  • the second signal line is provided with a second switch
  • the first clock signal line is connected to the first switch
  • the second signal line is connected to the first switch.
  • the clock signal line is connected to the second switch.
  • the first switch controls the first signal line
  • the second switch controls the second signal line
  • the first signal line and the second signal line have opposite polarities
  • the first switch is a P-type switch
  • the second switch is an N-type switch
  • two adjacent pixel units in the same column have opposite polarities.
  • the refresh rate of the two clock signal lines is 120 Hz.
  • a plurality of pixel units are arranged in a rectangular array, and each pixel unit includes a first pixel area and a second pixel area.
  • a plurality of data lines are used for connecting with the pixel unit to input data information to the pixel unit, and each data line includes a first signal line and a second signal line.
  • a plurality of scan lines are used to connect with the pixel unit to transmit driving signals to the pixel unit, a first clock signal line is connected with the first signal line, and a second clock signal line is connected with the second signal line.
  • the first clock signal line controls the first signal line
  • the second clock signal line controls the second signal line
  • the first clock signal line and the second clock signal line are turned on or off alternately to So that the first pixel area and the second pixel area are at different potentials. Because the liquid crystal display circuit of the present application divides the data line into two signal lines, the two signal lines alternately control signal transmission through two clock signal lines, and input different potentials to the first pixel area and the second pixel area respectively, So as to achieve the effect of low color cast.
  • FIG. 1 is a schematic diagram of a circuit structure of a liquid crystal display circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of another circuit structure of a liquid crystal display circuit provided by an embodiment of the application.
  • FIG. 3 is a timing diagram of a driving method of a liquid crystal display circuit provided by an embodiment of the application.
  • the embodiment of the present application provides a liquid crystal display circuit 100, a driving method of the liquid crystal display circuit 100, and a display panel.
  • the liquid crystal display circuit 100 is described in detail below.
  • FIG. 1 is a schematic diagram of a circuit structure of a liquid crystal display circuit 100 provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of another circuit structure of the liquid crystal display circuit 100 provided by an embodiment of the application.
  • an embodiment of the present application provides a liquid crystal display circuit 100.
  • the liquid crystal display circuit 100 includes a plurality of pixel units 10, a plurality of data lines 20, a plurality of scan lines 30, a first clock signal line 40 and a second clock signal line 50.
  • the plurality of pixel units 10 are arranged in a rectangular array, and each pixel unit 10 includes a first pixel area 11 and a second pixel area 12.
  • a plurality of data lines 20 are used to connect with the pixel unit 10 to input data information to the pixel unit 10, and each data line 20 includes a first signal line 21 and a second signal line 22.
  • a plurality of scan lines 30 are used to connect to the pixel unit 10 to transmit driving signals to the pixel unit 10.
  • the first clock signal line 40 is connected to the first signal line 21, and the second clock signal line 50 is connected to the second signal line. 22Connect. Wherein, the first clock signal line 40 controls the first signal line 21, the second clock signal line 50 controls the second signal line 22, the first clock signal line 40 and the second clock signal line 50 is turned on or off alternately so that the first pixel region 11 and the second pixel region 12 are at different potentials.
  • the second clock signal line 50 turns on the data line 20 to input a high potential to the first pixel area 11, and the first clock signal line 40 turns on afterwards so that the data line 20 inputs a low potential to the second pixel area 12, so that the first The one pixel area 11 and the second pixel area 12 are at different potentials, thereby achieving the effect of low color shift.
  • the first signal line 21 is provided with a first switch 60
  • the second signal line 22 is provided with a second switch 70
  • the first clock signal line 40 is connected to the first switch 60
  • the The second clock signal line 50 is connected to the second switch 70.
  • the first switch 60 controls the first signal line 21, the second switch 70 controls the second signal line 22, and the first signal line 21 and the second signal line 22 have opposite polarities. . Using this structure can avoid radio frequency radiation.
  • the first switch 60 is a P-type switch
  • the second switch 70 is an N-type switch.
  • the first switch 60 and the second switch 70 can also adopt the same type of switch.
  • the structural forms of the first switch 60 and the second switch 70 in the embodiment of the present application are specifically limited.
  • two adjacent pixel units 10 in the same column have opposite polarities.
  • a plurality of pixel units 10 are arranged in a rectangular array, and each pixel unit 10 includes a first pixel area 11 and a second pixel area 12.
  • a plurality of data lines 20 are used to connect with the pixel unit 10 to input data information to the pixel unit 10, and each data line 20 includes a first signal line 21 and a second signal line 22.
  • a plurality of scan lines 30 are used to connect to the pixel unit 10 to transmit driving signals to the pixel unit 10.
  • the first clock signal line 40 is connected to the first signal line 21, and the second clock signal line 50 is connected to the second signal line. 22Connect.
  • the first clock signal line 40 controls the first signal line
  • the second clock signal line 50 controls the second signal line
  • the first clock signal line 40 and the second clock signal line 50 is turned on or off alternately so that the first pixel region 11 and the second pixel region 12 are at different potentials.
  • the liquid crystal display circuit 100 of the present application divides the data line 20 into two signal lines, the two signal lines alternately control the transmission of signals through two clock signal lines, and respectively input to the first pixel area 11 and the second pixel area 12 Different potentials, so as to achieve the effect of low color shift.
  • FIG. 3 is a timing diagram of the driving method of the liquid crystal display circuit provided by an embodiment of the application.
  • a method for driving a liquid crystal display circuit includes:
  • each pixel unit includes a first pixel area and a second pixel area;
  • each data line includes a first signal line and a second signal line;
  • the first clock signal line controls the first signal line
  • the second clock signal line controls the second signal line
  • the first clock signal line and the second clock signal line are turned on or off alternately to So that the first pixel area and the second pixel area are at different potentials.
  • the second clock signal line turns on the data line to input a high potential to the first pixel area
  • the first clock signal line turns on to make the data line input a low potential to the second pixel area, so that the first pixel area and the second pixel area are turned on.
  • the pixel area is at different potentials, so as to achieve the effect of low color shift.
  • the refresh frequency of the display panel is 60 Hz
  • the refresh frequency of the two clock signal lines is 120 Hz.
  • the first signal line is provided with a first switch
  • the second signal line is provided with a second switch
  • the first clock signal line is connected to the first switch
  • the second clock signal line is connected to The second switch is connected.
  • the first switch controls the first signal line
  • the second switch controls the second signal line
  • the first signal line and the second signal line have opposite polarities. Using this structure can avoid radio frequency radiation.
  • the first switch is a P-type switch
  • the second switch is an N-type switch
  • the first switch and the second switch can also use the same type of switch.
  • the structural forms of the first switch and the second switch in the embodiment of the present application are specifically limited.
  • two adjacent pixel units in the same column have opposite polarities.
  • An embodiment of the present application also provides a display panel, which includes the above-mentioned liquid crystal display circuit. Since the liquid crystal display circuit has been described in detail in the above embodiments. Here, I won't repeat them too much.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

本液晶显示电路包括多个像素单元呈矩形阵列排布，每一个像素单元（10）包括第一像素区（11）和第二像素区（12），多条数据线用于与像素单元连接以输入数据信息至像素单元，每一条数据线（20）包括第一信号线（21）和第二信号线（22），多条扫描线（30）用于与像素单元（10）连接以传输驱动信号至像素单元（10），第一时钟信号线（40）与所述第一信号线（21）连接，第二时钟信号线（50）与所述第二信号线（22）连接，其中，第一时钟信号线（40）控制所述第一信号线（21），所述第二时钟信号线（50）控制所述第二信号线（22），第一时钟信号线（40）和第二时钟信号线（50）交替打开或关闭以使得所述第一像素区（11）和第二像素区（12）处于不同的电位。本液晶显示电路可以实现低色偏的效果。

Description

一种液晶显示电路、液晶显示电路驱动方法及显示面板 技术领域
本申请涉及面板制造技术领域，特别涉及一种液晶显示电路、液晶显示电路驱动方法及显示面板。
 背景技术
LCD(Liquid crystal displays，液晶显示器)是一种被广泛应用的平板显示器，主要是通过液晶开关调制背光源光场强度来实现画面显示。
LCD有很多种显示模式，其中，VA模式是一种具有高对比度、宽视野角、无须摩擦配向等优势的常见显示模式。但由于VA显示采用垂直转动的液晶，液晶分子双折射率的差异比较大，导致大视角下色偏（color shift）问题比较严重。
因此，提供一种新的液晶显示电路能够降低色偏，为本领域技术人员亟待解决的技术问题。
 技术问题
本申请实施例的目的在于提供一种液晶显示电路、液晶显示电路驱动方法及显示面板，能够解决现有中色偏的技术问题。
 技术解决方案
本申请实施例提供一种液晶显示电路，包括：
多个像素单元，呈矩形阵列排布，每一个像素单元包括第一像素区和第二像素区；
多条数据线，用于与像素单元连接以输入数据信息至像素单元，每一条数据线包括第一信号线和第二信号线；
多条扫描线，用于与像素单元连接以传输驱动信号至像素单元；
第一时钟信号线，与所述第一信号线连接；
第二时钟信号线，与所述第二信号线连接；
其中，所述第一时钟信号线控制所述第一信号线，所述第二时钟信号线控制所述第二信号线，所述第一时钟信号线和第二时钟信号线交替打开或关闭以使得所述第一像素区和第二像素区处于不同的电位。
在一些实施例中：所述第一信号线上设置有第一开关，所述第二信号线设置有第二开关，所述第一时钟信号线与所述第一开关连接，所述第二时钟信号线与所述第二开关连接。
在一些实施例中，所述第一开关控制所述第一信号线，所述第二开关控制所述第二信号线，所述第一信号线和所述第二信号线极性相反。
在一些实施例中，所述第一开关为P型开关，所述第二开关为N型开关。
在一些实施例中，同一列相邻两个像素单元具有相反的极性。
在一些实施例中，两个时钟信号线的刷新频率为120HZ。
在一些实施例中，所述第一开关和第二开关为同一类型的开关。
本申请实施例还提供一种液晶显示电路驱动方法，包括：
提供多个像素单元，所述多个像素单元呈矩形阵列排布，每一个像素单元包括第一像素区和第二像素区；
提供多条数据线，所述提供多条数据线用于与像素单元连接以输入数据信息至像素单元，每一条数据线包括第一信号线和第二信号线；
提供多条扫描线，所述提供多条扫描线用于与像素单元连接以传输驱动信号至像素单元；
提供第一时钟信号线，所述第一时钟信号线与所述第一信号线连接；
提供第二时钟信号线，所述第二时钟信号线与所述第二信号线连接；
其中，所述第一时钟信号线控制所述第一信号线，所述第二时钟信号线控制所述第二信号线，所述第一时钟信号线和第二时钟信号线交替打开或关闭以使得所述第一像素区和第二像素区处于不同的电位。
在一些实施例中，所述第一信号线上设置有第一开关，所述第二信号线设置有第二开关，所述第一时钟信号线与所述第一开关连接，所述第二时钟信号线与所述第二开关连接。
在一些实施例中，所述第一开关控制所述第一信号线，所述第二开关控制所述第二信号线，所述第一信号线和所述第二信号线极性相反。
在一些实施例中，所述第一开关为P型开关，所述第二开关为N型开关。
在一些实施例中，同一列相邻两个像素单元具有相反的极性.
在一些实施例中，两个时钟信号线的刷新频率为120HZ。
在一些实施例中，所述第一开关和第二开关为同一类型的开关。
本申请实施例提供一种显示面板，包括液晶显示电路，液晶显示电路包括多个像素单元，呈矩形阵列排布，每一个像素单元包括第一像素区和第二像素区；
多条数据线，用于与像素单元连接以输入数据信息至像素单元，每一条数据线包括第一信号线和第二信号线；
多条扫描线，用于与像素单元连接以传输驱动信号至像素单元；
第一时钟信号线，与所述第一信号线连接；
第二时钟信号线，与所述第二信号线连接；
其中，所述第一时钟信号线控制所述第一信号线，所述第二时钟信号线控制所述第二信号线，所述第一时钟信号线和第二时钟信号线交替打开或关闭以使得所述第一像素区和第二像素区处于不同的电位。
在一些实施例中，所述第一信号线上设置有第一开关，所述第二信号线设置有第二开关，所述第一时钟信号线与所述第一开关连接，所述第二时钟信号线与所述第二开关连接。
在一些实施例中，所述第一开关控制所述第一信号线，所述第二开关控制所述第二信号线，所述第一信号线和所述第二信号线极性相反。
在一些实施例中，所述第一开关为P型开关，所述第二开关为N型开关。
在一些实施例中，同一列相邻两个像素单元具有相反的极性。
在一些实施例中，当显示面板的刷新频率为60 HZ，两个时钟信号线的刷新频率为120HZ。
 有益效果
本申请实施例中，多个像素单元呈矩形阵列排布，每一个像素单元包括第一像素区和第二像素区。多条数据线用于与像素单元连接以输入数据信息至像素单元，每一条数据线包括第一信号线和第二信号线。多条扫描线用于与像素单元连接以传输驱动信号至像素单元，第一时钟信号线与所述第一信号线连接，第二时钟信号线与所述第二信号线连接。其中，所述第一时钟信号线控制所述第一信号线，所述第二时钟信号线控制所述第二信号线，所述第一时钟信号线和第二时钟信号线交替打开或关闭以使得所述第一像素区和第二像素区处于不同的电位。由于本申请液晶显示电路，将数据线分为两条信号线，两条信号线分通过两个时钟信号线交替控制信号的传输，分别向第一像素区和第二像素区输入不同的电位，从而实现低色偏的效果。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的液晶显示电路的电路结构示意图。
图2为本申请实施例提供的液晶显示电路的另一电路结构示意图。
图3为本申请实施例提供的液晶显示电路的驱动方式的时序图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种液晶显示电路100、液晶显示电路100驱动方法及显示面板。以下对液晶显示电路100详细介绍。
请参阅图1和图2，图1为本申请实施例提供的液晶显示电路100的电路结构示意图。图2为本申请实施例提供的液晶显示电路100的另一电路结构示意图。其中，本申请实施例提供一种液晶显示电路100。液晶显示电路100包括多个像素单元10、多条数据线20、多条扫描线30、第一时钟信号线40以及第二时钟信号线50。多个像素单元10呈矩形阵列排布，每一个像素单元10包括第一像素区11和第二像素区12。多条数据线20用于与像素单元10连接以输入数据信息至像素单元10，每一条数据线20包括第一信号线21和第二信号线22。多条扫描线30用于与像素单元10连接以传输驱动信号至像素单元10，第一时钟信号线40与所述第一信号线21连接，第二时钟信号线50与所述第二信号线22连接。其中，所述第一时钟信号线40控制所述第一信号线21，所述第二时钟信号线50控制所述第二信号线22，所述第一时钟信号线40和第二时钟信号线50交替打开或关闭以使得所述第一像素区11和第二像素区12处于不同的电位。
需要说明的是，第二时钟信号线50开启数据线20输入高电位到第一像素区11，第一时钟信号线40后开启使得数据线20输入低电位到第二像素区12，从而使得第一像素区11和第二像素区12处于不同的电位，从而实现低色偏的效果。
其中，所述第一信号线21上设置有第一开关60，所述第二信号线22设置有第二开关70，所述第一时钟信号线40与所述第一开关60连接，所述第二时钟信号线50与所述第二开关70连接。通过这种结构可以实现第一时钟信号线40和第二时钟信号线50的交替开关或者关闭，从而实现低色偏的效果。
其中，所述第一开关60控制所述第一信号线21，所述第二开关70控制所述第二信号线22，所述第一信号线21和所述第二信号线22极性相反。采用这种结构能够避免射频放射。
其中，所述第一开关60为P型开关，所述第二开关70为N型开关。当然，第一开关60和第二开关70也可以采用同一类型的开关。本申请实施例中第一开关60和第二开关70的结构形式做具体限定。
其中，同一列相邻两个像素单元10具有相反的极性。
本申请实施例中，多个像素单元10呈矩形阵列排布，每一个像素单元10包括第一像素区11和第二像素区12。多条数据线20用于与像素单元10连接以输入数据信息至像素单元10，每一条数据线20包括第一信号线21和第二信号线22。多条扫描线30用于与像素单元10连接以传输驱动信号至像素单元10，第一时钟信号线40与所述第一信号线21连接，第二时钟信号线50与所述第二信号线22连接。其中，所述第一时钟信号线40控制所述第一信号线21，所述第二时钟信号线50控制所述第二信号线22，所述第一时钟信号线40和第二时钟信号线50交替打开或关闭以使得所述第一像素区11和第二像素区12处于不同的电位。由于本申请液晶显示电路100，将数据线20分为两条信号线，两条信号线分通过两个时钟信号线交替控制信号的传输，分别向第一像素区11和第二像素区12输入不同的电位，从而实现低色偏的效果。
请参与图3，图3为本申请实施例提供的液晶显示电路的驱动方式的时序图。其中，一种液晶显示电路驱动方法，包括：
提供多个像素单元，所述多个像素单元呈矩形阵列排布，每一个像素单元包括第一像素区和第二像素区；
提供多条数据线，所述提供多条数据线用于与像素单元连接以输入数据信息至像素单元，每一条数据线包括第一信号线和第二信号线；
提供多条扫描线，所述提供多条扫描线用于与像素单元连接以传输驱动信号至像素单元；
提供第一时钟信号线，所述第一时钟信号线与所述第一信号线连接；
提供第二时钟信号线，所述第二时钟信号线与所述第二信号线连接；
其中，所述第一时钟信号线控制所述第一信号线，所述第二时钟信号线控制所述第二信号线，所述第一时钟信号线和第二时钟信号线交替打开或关闭以使得所述第一像素区和第二像素区处于不同的电位。
需要说明的是，第二时钟信号线开启数据线输入高电位到第一像素区，第一时钟信号线后开启使得数据线输入低电位到第二像素区，从而使得第一像素区和第二像素区处于不同的电位，从而实现低色偏的效果。
具体的，当显示面板的刷新频率为60 HZ，两个时钟信号线的刷新频率为120HZ。
其中，所述第一信号线上设置有第一开关，所述第二信号线设置有第二开关，所述第一时钟信号线与所述第一开关连接，所述第二时钟信号线与所述第二开关连接。通过这种结构可以实现第一时钟信号线和第二时钟信号线的交替开关或者关闭，从而实现低色偏的效果。
其中，所述第一开关控制所述第一信号线，所述第二开关控制所述第二信号线，所述第一信号线和所述第二信号线极性相反。采用这种结构能够避免射频放射。
其中，所述第一开关为P型开关，所述第二开关为N型开关。当然，第一开关和第二开关也可以采用同一类型的开关。本申请实施例中第一开关和第二开关的结构形式做具体限定。
其中，同一列相邻两个像素单元具有相反的极性。
本申请实施例还提供一种显示面板，显示面板包括上述所述的液晶显示电路。由于液晶显示电路已经在上述实施例中做了详细描述。在此，不再过多赘述。
以上对本申请实施例提供的一种液晶显示电路、液晶显示电路驱动方法及显示面板。进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种液晶显示电路，其中，包括：
    多个像素单元，呈矩形阵列排布，每一个像素单元包括第一像素区和第二像素区；
    多条数据线，用于与像素单元连接以输入数据信息至像素单元，每一条数据线包括第一信号线和第二信号线；
    多条扫描线，用于与像素单元连接以传输驱动信号至像素单元；
    第一时钟信号线，与所述第一信号线连接；
    第二时钟信号线，与所述第二信号线连接；
    其中，所述第一时钟信号线控制所述第一信号线，所述第二时钟信号线控制所述第二信号线，所述第一时钟信号线和第二时钟信号线交替打开或关闭以使得所述第一像素区和第二像素区处于不同的电位。
  2. 根据权利要求1所述的液晶显示电路，其中，所述第一信号线上设置有第一开关，所述第二信号线设置有第二开关，所述第一时钟信号线与所述第一开关连接，所述第二时钟信号线与所述第二开关连接。
  3. 根据权利要求2所述的液晶显示电路，其中，所述第一开关控制所述第一信号线，所述第二开关控制所述第二信号线，所述第一信号线和所述第二信号线极性相反。
  4. 根据权利要求3所述的液晶显示电路，其中，所述第一开关为P型开关，所述第二开关为N型开关。
  5. 根据权利要求4所述的液晶显示电路，其中，同一列相邻两个像素单元具有相反的极性。
  6. 根据权利要求1项所述的液晶显示电路，其中，两个时钟信号线的刷新频率为120HZ。
  7. 根据权利要求2所述的液晶显示电路，其中，所述第一开关和第二开关为同一类型的开关。
  8. 一种液晶显示电路驱动方法，其中，包括：
    提供多个像素单元，所述多个像素单元呈矩形阵列排布，每一个像素单元包括第一像素区和第二像素区；
    提供多条数据线，所述提供多条数据线用于与像素单元连接以输入数据信息至像素单元，每一条数据线包括第一信号线和第二信号线；
    提供多条扫描线，所述提供多条扫描线用于与像素单元连接以传输驱动信号至像素单元；
    提供第一时钟信号线，所述第一时钟信号线与所述第一信号线连接；
    提供第二时钟信号线，所述第二时钟信号线与所述第二信号线连接；
    其中，所述第一时钟信号线控制所述第一信号线，所述第二时钟信号线控制所述第二信号线，所述第一时钟信号线和第二时钟信号线交替打开或关闭以使得所述第一像素区和第二像素区处于不同的电位。
  9. 根据权利要求8所述的液晶显示电路驱动方法，其中，所述第一信号线上设置有第一开关，所述第二信号线设置有第二开关，所述第一时钟信号线与所述第一开关连接，所述第二时钟信号线与所述第二开关连接。
  10. 根据权利要求9所述的液晶显示电路驱动方法，其中，所述第一开关控制所述第一信号线，所述第二开关控制所述第二信号线，所述第一信号线和所述第二信号线极性相反。
  11. 根据权利要求10所述的液晶显示电路驱动方法，其中，所述第一开关为P型开关，所述第二开关为N型开关。
  12. 根据权利要求11所述的液晶显示电路驱动方法，其中，同一列相邻两个像素单元具有相反的极性.
  13. 根据权利要求8项所述的液晶显示电路驱动方法，其中，两个时钟信号线的刷新频率为120HZ。
  14. 根据权利要求9所述的液晶显示电路驱动方法，其中，所述第一开关和第二开关为同一类型的开关。
  15. 一种显示面板，其中，包括液晶显示电路，液晶显示电路包括多个像素单元，呈矩形阵列排布，每一个像素单元包括第一像素区和第二像素区；
    多条数据线，用于与像素单元连接以输入数据信息至像素单元，每一条数据线包括第一信号线和第二信号线；
    多条扫描线，用于与像素单元连接以传输驱动信号至像素单元；
    第一时钟信号线，与所述第一信号线连接；
    第二时钟信号线，与所述第二信号线连接；
    其中，所述第一时钟信号线控制所述第一信号线，所述第二时钟信号线控制所述第二信号线，所述第一时钟信号线和第二时钟信号线交替打开或关闭以使得所述第一像素区和第二像素区处于不同的电位。
  16. 根据权利要求15所述的显示面板，其中，所述第一信号线上设置有第一开关，所述第二信号线设置有第二开关，所述第一时钟信号线与所述第一开关连接，所述第二时钟信号线与所述第二开关连接。
  17. 根据权利要求16所述的显示面板，其中，所述第一开关控制所述第一信号线，所述第二开关控制所述第二信号线，所述第一信号线和所述第二信号线极性相反。
  18. 根据权利要求16所述的显示面板，其中，所述第一开关为P型开关，所述第二开关为N型开关。
  19. 根据权利要求15所述的显示面板，其中，同一列相邻两个像素单元具有相反的极性。
  20. 根据权利要求16所述的显示面板，其中，当显示面板的刷新频率为60 HZ，两个时钟信号线的刷新频率为120HZ。
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