WO2021065803A1 - 半導体素子の製造方法及び半導体装置 - Google Patents

半導体素子の製造方法及び半導体装置 Download PDF

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WO2021065803A1
WO2021065803A1 PCT/JP2020/036647 JP2020036647W WO2021065803A1 WO 2021065803 A1 WO2021065803 A1 WO 2021065803A1 JP 2020036647 W JP2020036647 W JP 2020036647W WO 2021065803 A1 WO2021065803 A1 WO 2021065803A1
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semiconductor
mask
manufacturing
opening
semiconductor layer
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PCT/JP2020/036647
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English (en)
French (fr)
Inventor
東　克典
直佳 小松
達郎 澤田
佑介 中里
知央 平山
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京セラ株式会社
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Priority to CN202080059243.6A priority Critical patent/CN114402422A/zh
Priority to EP20872323.9A priority patent/EP4040468A1/en
Priority to JP2021551254A priority patent/JPWO2021065803A1/ja
Priority to US17/763,043 priority patent/US20220359196A1/en
Publication of WO2021065803A1 publication Critical patent/WO2021065803A1/ja

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Definitions

  • the present disclosure relates to a method for manufacturing a semiconductor element and a semiconductor device.
  • ELO epi Lateral Overgrowth
  • a mask having an opening and a processed mask for providing a predetermined structure in a peripheral upper surface region of the opening is provided on the surface of the substrate and exposed from the opening.
  • a semiconductor is epitaxially grown from the surface of the substrate to the peripheral upper surface region to produce a semiconductor device having a semiconductor layer to which the predetermined structure is transferred.
  • the semiconductor element is manufactured as follows.
  • a mask 12 made of SiO2 is formed on the upper surface of the GaN layer on the surface layer of the substrate 11 shown in FIG. 1A.
  • the lower surface of the GaN layer on the surface layer of the substrate 11 may be supported by other than GaN such as a silicon substrate (not shown).
  • a silicon substrate not shown
  • it may be a sapphire substrate or a SiC (Silicon Carbide) substrate.
  • As the material of the mask 12 other materials such as SiN, AlN, Al2O3, and Ga2O3 may be applied.
  • the mask 12 may be amorphous.
  • the mask 12 has an opening 12a.
  • a region is selected according to the shape of the peripheral upper surface region of the opening 12a.
  • the area selection is based on the shape with the step 12b, and is a selection to divide the area above and below the step.
  • the step 12b surrounds the opening 12a in a circle, and the lower step is formed on the opening 12a side and the upper step is formed in a region away from the opening 12a. That is, the boundary line of the region divided by the region selection surrounds the opening 12a.
  • Such a shape with a step 12b is formed by a well-known photolithography technique, wet etching, dry etching, or the like.
  • GaN is epitaxially grown from the surface of the substrate 11 exposed from the opening 12a to the peripheral upper surface region to form the GaN layer 13.
  • the GaN layer 13 since the GaN layer 13 is grown on the peripheral upper surface region where the region has been selected, the GaN layer 13 extends over the different regions where the region is selected.
  • the different regions selected in the region are the lower stage and the upper stage with the step 12b as a boundary. Therefore, the GaN layer 13 extends not only to the lower stage but also to the upper stage.
  • the stepped shape is transferred to the lower surface of the GaN layer 13.
  • the influence of the region selection in the present embodiment is the transfer of the shape to the semiconductor layer.
  • the doping amount of the n-type impurity is controlled in the GaN layer 13 so that the electron carrier concentration is less than 10 17 cm -3.
  • the n-type impurity may be, for example, Si (Silicon).
  • Si Si
  • the GaN layer 14 having a high impurity concentration is epitaxially grown so as to cover the GaN layer 13, and the state shown in FIG. 1A is obtained.
  • the semiconductor element having the semiconductor layer (GaN layer 13) on which the influence of the region selection on the upper surface of the mask 12 remains is produced.
  • the surface of the semiconductor layer (upper surface of the GaN layer 14) opposite to the substrate 11 is joined to the support substrate 15.
  • the bonding via metal or the direct bonding may be used to reduce the resistance of the connection.
  • a back surface electrode 16 is formed on the upper surface of the support substrate 15 by, for example, sputtering.
  • the back surface electrode 16 is, for example, an Al layer plated with Ti, Ni, or Au.
  • the back surface electrode may be formed after the upper surface electrode metal film 19 described later is formed.
  • a support substrate 15 having a back surface electrode 16 in advance may be used.
  • the support substrate 15 may be a semiconductor having a high impurity concentration so as to have a low resistance.
  • the semiconductor layers 13 and 14 are separated from the substrate 11 in a state where the surface of the semiconductor layer (the upper surface of the GaN layer 14) is bonded to the support substrate 15.
  • the mask 12 is melted by wet etching or dry etching, and then the crystal near the opening 12a is cracked by ultrasonic waves or the like to peel it off from the substrate 11.
  • the top and bottom are turned upside down as shown in FIG. 1D.
  • a step 13b lowered by one step is formed around the surface 13a separated from the substrate 11 of the semiconductor layer 13, and a step 13c lowered by one step is formed around the surface 13a.
  • the steps 13b-13c are used as a mesa structure.
  • an insulating film 17 having an opening surrounding the surface 13a and covering the mesa structure (13b-13c) is formed.
  • a Schottky metal film 18 that is Schottky bonded to the GaN layer 13 exposed in the opening of the insulating film 17 is formed.
  • the Schottky metal film 18 covers the opening of the insulating film 17.
  • the upper surface electrode metal film 19 extending to the mesa structure (13b-13c) is formed on the Schottky metal film 18 and the insulating film 17.
  • the top electrode metal film 19 forms a so-called field plate on the insulating film 17.
  • the semiconductor element 100 is manufactured.
  • the semiconductor element 100 is a Schottky barrier diode.
  • a mesa structure was formed on the semiconductor element 100 by transferring the shape of the mask 12.
  • the shape may have two or more steps.
  • FIG. 1A not only a step that goes up from the opening 12a toward the periphery but also a step that goes down can be implemented. Therefore, a convex shape can be formed by forming a shape that once goes up and goes down.
  • a trench structure can also be formed by transferring the convex shape of the mask 12. Therefore, the mesa structure may be a trench structure.
  • one or a plurality of trench structures and a mesa structure at the outermost edge can be formed from the center of the semiconductor element 100 toward the periphery.
  • the shape may be a step with an inclination or a structure with rounded corners.
  • the manufacturing process described above is carried out simultaneously and in parallel so as to manufacture a plurality of semiconductor elements 100 at the same time. That is, a plurality of openings 12a are formed in the mask 12, and one semiconductor element is associated with one opening to simultaneously manufacture a plurality of semiconductor elements.
  • Each semiconductor element 100 can be separated into individual pieces and individually used as a semiconductor device.
  • the support substrate 15 and the back surface electrode 16 are shared by the plurality of semiconductor elements 100 as shown in FIG. 2 and mounted as shown in FIG. 3 to be used as a semiconductor device. Can be done. As shown in FIG.
  • a common back electrode 16 is die-bonded to one electrode pad 201 on the mounting substrate 200, and each top electrode metal film 19 is connected to another electrode pad 202 by a bonding wire 203.
  • the plurality of semiconductor elements 100 are manufactured so as to be arranged side by side in a certain direction X.
  • the semiconductor element 100 has a long shape in a direction Y substantially orthogonal to the direction X in which the semiconductor element 100 is arranged in a plan view (arrow view A). It is easy to increase the junction area of the diode by arranging them in such a shape.
  • the opening 12a of the mask 12 in the manufacturing process is assumed to have a substantially rectangular shape in a plan view perpendicular to the substrate 11.
  • the long side direction of this rectangle is the direction perpendicular to the drawing in FIG.
  • the semiconductor layers 13 and 14 and the semiconductor element 100 mainly composed of the semiconductor layers 13 and 14 have a substantially rectangular shape in which the long side direction of the opening 12a of the mask 12 is the long side direction (Y) in a plan view. Will have.
  • the region selection on the mask 12 is due to a predetermined element selectively arranged, and the influence of the region selection on the semiconductor layer is the diffusion of the element into the semiconductor layer.
  • an element is arranged on the mask 12 instead of the step of the first embodiment.
  • the P-type impurity 12p is arranged.
  • the method of arranging the P-type impurity 12p is not particularly limited, but a method of introducing the P-type impurity 12p into the mask 12 may be used as shown in FIG. 4A. Sputtering, heat diffusion and the like can be applied as the introduction method.
  • region selection that is, region selection for dividing the region in which the P-type impurity 12p is arranged and another region is performed.
  • a compound containing P-type impurities (a compound containing a substance that diffuses into the semiconductor layer 13) may be arranged on the mask 12. As the arrangement position, it may be arranged so as to be formed first and embedded so as not to affect the outer shape of the mask 12, or it may be arranged on the mask 12.
  • the region selection by the shape and the region selection by the substance are performed at the same time. That is, the mask 12 whose region is selected according to the shape and the substance is provided.
  • the P-type impurity 12p is arranged in a ring shape surrounding the opening 12a.
  • the GaN layers 13 and 14 are formed by epitaxial growth in the same manner as in the first embodiment (FIG. 4B). Then, a part of the P-type impurity 12p moves to the GaN layer 13 and diffuses into the GaN layer 13, and the P-type region 13p is formed in the GaN layer 13. At this time, the diffusion of the P-type impurities 12p may be naturally carried out in a high temperature state during the epitaxial growth of the GaN layers 13 and 14, or a separate heating step for diffusing the P-type impurities 12p may be further provided.
  • an insulating film 20 having an opening on the surface of the GaN layer 13 is formed as shown in FIG. 4C. Further, a Schottky metal film 21 that is Schottky-bonded to the N-type region of the GaN layer 13 and a metal ring 22 that is ohmic-bonded to the P-type region 13p are formed through the opening of the insulating film 20 to form a guard ring. From the above, the Schottky barrier diode 101 with a guard ring can be manufactured. The contents described with reference to FIGS. 2 and 3 can be carried out in the same manner.
  • a third embodiment which is still another embodiment, will be described.
  • This embodiment is a partial modification of the second embodiment to manufacture a semiconductor device 102 in which a PN junction and a Schottky junction coexist.
  • FIGS. 5A and 5B the same manufacturing process as in the second embodiment is carried out. Arbitrarily select the number and arrangement of P-type impurities 12p.
  • FIG. 5C the separation from the substrate 11 and the mask 12 and the formation of the back surface electrode 16 are completed, and the top surface electrode metal film 30 is formed on the surface of the GaN layer 13. The top electrode metal film 30 is bonded to the P-type region 13p and the N-type region of the GaN layer 13.
  • a top electrode metal film 30 is formed by ohmic contacting the P-type region 13p and Schottky bonding to the N-type region adjacent to the P-type region 13p.
  • the semiconductor element 102 in which the PN junction and the Schottky junction coexist can be manufactured.
  • the contents described with reference to FIGS. 2 and 3 can be carried out in the same manner.
  • a structure can be formed on the surface of the semiconductor layers 13 and 14 epitaxially grown on the mask 12 in contact with the upper surface of the mask 12 due to the influence of region selection on the mask 12.
  • a pressure-resistant structure such as a mesa step, a field plate, and a guard ring.
  • this embodiment is shown as an example, and can be implemented in various other embodiments, and components are omitted as long as the gist of the invention is not deviated. , Can be replaced or changed.
  • various structures other than those illustrated by appropriately combining the first embodiment, the second embodiment, and the third embodiment may be formed.
  • N-type impurities may be diffused in the GaN layer instead of the P-type impurities.
  • the region selection based on the shape and the region selection based on the arrangement of substances have been described, but the region selection applied to the mask is physically or chemically due to a macro or micro structural change with respect to the mask.
  • Region selection by shape is also possible by changing the slope or surface roughness, and the shape is transferred. Even if the substance is the same, the region may be selected depending on the crystal structure or the crystal orientation.
  • the present disclosure can be used for a method for manufacturing a semiconductor element and a semiconductor device.
  • Substrate 12 Mask 12a Mask opening 12b Step 12p P-type impurity 13 GaN layer (semiconductor layer) 13p P-type region 14 GaN layer (semiconductor layer) 15 Support substrate 16 Back electrode 17 Insulation film 18 Schottky metal film 19 Top electrode metal film 20 Insulation film 21 Shotkey metal film 22 Metal ring (guard ring) 30 Top electrode metal film 100 Semiconductor element (diode) 200 Mounting board 201 Electrode pad 202 Electrode pad 203 Bonding wire

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Abstract

半導体素子の製造方法は、基板１１の表面上に、開口１２ａを有し該開口の周囲上面領域に所定の構造を設ける加工を施したマスク１２を設け、開口から露出する基板の表面から周囲上面領域上まで半導体をエピタキシャル成長させ、前記所定の構造を転写した半導体層１３を有する半導体素子を作製する。一つには、所定の構造は段差のある形状によるものである。他の一つには、所定の構造は選択的に配置された元素によるものであり、転写された元素は半導体層へ移動する。

Description

半導体素子の製造方法及び半導体装置
　本開示は、半導体素子の製造方法及び半導体装置に関する。
　従来、ＥＬＯ(Epitaxial Lateral Overgrowth)と呼ばれる、基板上に設けた成長マスクの開口にＧａＮ(Galium Nitride)層を結晶成長させ、さらに成長マスク上で横方向に結晶成長させる技術があった（特許第４６３８９５８号公報）。
　本開示の１つの態様の半導体素子の製造方法は、基板の表面上に、開口を有し該開口の周囲上面領域に所定の構造を設ける加工を施したマスクを設け、前記開口から露出する前記基板の表面から前記周囲上面領域上まで半導体をエピタキシャル成長させ、前記所定の構造を転写した半導体層を有する半導体素子を作製する。
本開示の第１実施形態を説明するための断面模式図である。 本開示の第１実施形態を説明するための断面模式図である。 本開示の第１実施形態を説明するための断面模式図である。 本開示の第１実施形態を説明するための断面模式図である。 本開示の第１実施形態を説明するための断面模式図である。 本開示の第１実施形態を説明するための断面模式図である。 本開示の第１実施形態を説明するための模式的斜視図である。 本開示の第２実施形態を説明するための断面模式図である。 本開示の第２実施形態を説明するための断面模式図である。 本開示の第２実施形態を説明するための断面模式図である。 本開示の第３実施形態を説明するための断面模式図である。 本開示の第３実施形態を説明するための断面模式図である。 本開示の第３実施形態を説明するための断面模式図である。
　以下に本開示の一実施形態につき図面を参照して説明する。
〔第１実施形態〕
　まず、第１実施形態の半導体素子の製造方法及び半導体装置につき説明する。
（製造方法）
　次の通り半導体素子を製造する。
　図１Ａに示す基板１１表層のＧａＮ層の上面にＳｉＯ２によるマスク１２を形成する。なお、基板１１表層のＧａＮ層の下面は、シリコン基板（不図示）等のＧａＮ以外で支持されているものであってもよい。例えばサファイア基板やＳｉＣ(Silicon Carbide)基板であってもよい。マスク１２の材料としてはＳｉＮ、ＡｌＮ、Ａｌ２Ｏ３、Ｇａ２Ｏ３等他のものを適用してもよい。マスク１２は、アモルファス状のものであってもよい。
　マスク１２は、開口１２ａを有する。本実施形態では、開口１２ａの周囲上面領域に形状により領域選択を施した。そして、領域選択は段差１２ｂのある形状によるもので、段差の上と下に領域を分ける選択である。段差１２ｂは、開口１２ａの回りを一周して囲むものであり、開口１２ａ側が下の段、開口１２ａから離れた領域に上の段が形成されている。すなわち、領域選択によって分けられた領域の境界線は、開口１２ａを囲む。このような段差１２ｂのある形状は、周知のフォトリソグラフィ技術、ウエットエッチング又はドライエッチング等により形成する。
　次に、上述したＥＬＯ技術を用いて開口１２ａから露出する基板１１の表面から周囲上面領域上までＧａＮをエピタキシャル成長させ、ＧａＮ層１３を形成する。このとき、領域選択が施された周囲上面領域上までＧａＮ層１３を成長させるから、ＧａＮ層１３は領域選択された異なる領域に及ぶこととなる。本実施形態では、領域選択された異なる領域とは、段差１２ｂを境にして下の段と、上の段である。したがって、ＧａＮ層１３は、当該下の段のみならず、上の段まで及ぶ。
　その結果、ＧａＮ層１３の下面に段差形状が転写される。このように本実施形態における領域選択の影響は、形状の半導体層への転写である。
　ＧａＮ層１３は、１０17ｃｍ-3未満の電子キャリア濃度となるよう、ｎ型不純物のドープ量が、コントロールされる。ｎ型不純物は、例えばＳｉ(Silicon)であってもよい。これにより、デバイス動作時に電圧が加わったときの空乏層が広がる耐圧層を形成することができる。
　さらに本実施形態では所望の不純物濃度プロファイルを得るため、ＧａＮ層１３を覆うように高不純物濃度のＧａＮ層１４をエピタキシャル成長させ、図１Ａに示す状態とする。
　以上のようにしてマスク１２上面への領域選択の影響の残った半導体層（ＧａＮ層１３）を有する半導体素子を作製する。
　次に図１Ｂに示すように基板１１に対する反対側の半導体層の面（ＧａＮ層１４の上面）を支持基板１５に接合する。接合は、金属を介した接合や、直接接合を用い接続の抵抗を低減してもよい。
　次に図１Ｃに示すように、支持基板１５の上面に裏面電極１６を例えばスパッタ等で形成する。裏面電極１６は、例えば、Ａｌ層にＴｉ、Ｎｉ、Ａｕめっきを施したものである。
　なお、裏面電極の形成は、後述の上面電極金属膜１９が形成された後に形成されてもよい。又は予め裏面電極１６を有する支持基板１５を用いてもよい。支持基板１５は、低抵抗となるよう、高不純物濃度の半導体であってもよい。
　次に、半導体層の面（ＧａＮ層１４の上面）を支持基板１５に接合した状態で半導体層１３，１４を基板１１から分離する。先にマスク１２をウエットエッチング又はドライエッチング等で溶解させ、その後、超音波等で開口１２ａの近傍の結晶に亀裂を入れることで、基板１１から剥離する。
　分離後、上下を逆にすると図１Ｄに示す通りとなる。
　図１Ｄに示す通り、半導体層１３の基板１１から分離した面１３ａに対し、周囲に一段下がった段１３ｂ、さらにその周囲に一段下がった段１３ｃが形成されている。段差１３ｂ－１３ｃをメサ構造として利用する。
　次に、面１３ａを囲む開口を有し、メサ構造（１３ｂ－１３ｃ）を覆う絶縁膜１７を形成する。
　次に、絶縁膜１７の開口に露出するＧａＮ層１３にショットキー接合するショットキー金属膜１８を形成する。ショットキー金属膜１８により、絶縁膜１７の開口は覆われる。
　次に、ショットキー金属膜１８上及び絶縁膜１７上にメサ構造（１３ｂ－１３ｃ）まで延設された上面電極金属膜１９を形成する。上面電極金属膜１９は絶縁膜１７上で所謂フィールドプレートを形成する。
　以上により半導体素子１００が製造される。ここでは、半導体素子１００はショットキーバリアダイオードである。
　以上のようにマスク１２の形状の転写により、半導体素子１００にメサ構造を形成した。
　なお、以上の実施形態に拘わらず、形状は、段差が２箇所以上あるものであってもよい。また、図１Ａにおいて開口１２ａから周囲に向かって上へ上がる段差ののみならず、下へ下がる段差も実施することができる。したがって、一旦上へ上がって下へ下がる形状とすることで凸な形状も形成できる。マスク１２の凸な形状を転写することで、トレンチ構造も形成することができる。したがって、上記メサ構造は、トレンチ構造としてもよい。また、半導体素子１００の中心から周辺に向かって１又は複数のトレンチ構造と、最外縁のメサ構造とを形成することもできる。
　また、形状は、傾斜を設けた段差や、角部を丸めた構造であってもよい。
　以上説明した製造プロセスを、図２に示すように複数の半導体素子１００を同時に製造するように同時並行して実施する。すなわち、マスク１２に開口１２ａを複数形成し、一の開口に対し一の半導体素子を対応させて、複数の半導体素子を同時に作製する。
　各半導体素子１００は、個片に分離して個別に半導体装置として利用することもできる。しかし、大容量化が必要な場合は、図２に示す通りの複数の半導体素子１００で支持基板１５及び裏面電極１６を共有したまま、図３に示すように実装して半導体装置として利用することができる。
　図３に示すように、共通の裏面電極１６を実装基板２００上の一の電極パッド２０１にダイボンディングし、個々の上面電極金属膜１９をボンディングワイヤー２０３により他の電極パッド２０２に接続する。
　このように実装することで、複数のダイオードを並列接続して大容量化し利用することができる。このとき、複数の半導体素子１００を一定方向Ｘに並べて配置するように製造する。半導体素子１００は、平面視（矢視Ａ）で、その並ぶ方向Ｘに対する略直交方向Ｙに長尺な形状とする。このような形状と、並びとすることで、ダイオードの接合面積を大きくすることが容易である。
　そのために、上記製造プロセスにおけるマスク１２の開口１２ａを、基板１１に垂直な平面視で略長方形の形状を有するものとする。この長方形の長辺方向は、図２において図面に垂直な方向である。略長方形の開口１２ａからのエピタキシャル成長により、半導体層１３，１４及びこれを主体とする半導体素子１００は平面視でマスク１２の開口１２ａの長辺方向を長辺方向（Ｙ）とする略長方形の形状を有するものとなる。
〔第２実施形態〕
　次に他の実施形態である第２実施形態につき説明する。
　本実施形態にあっては、マスク１２への領域選択は選択的に配置された所定の元素によるものであり、領域選択の半導体層への影響は、当該元素の半導体層への拡散である。
　図４Ａに示すようにマスク１２に対し、上記第１実施形態の段差に代えて元素を配置する。ここでは、Ｐ型不純物１２ｐを配置する。Ｐ型不純物１２ｐの配置方法は、特に限定されるものではないが、図４Ａに示すようにマスク１２内に導入する方法でもよい。導入方法としてはスパッタリング、熱拡散等を適用し得る。これにより領域選択、すなわち、Ｐ型不純物１２ｐが配置された領域と他の領域とに分ける領域選択を施す。
　また、Ｐ型不純物を含む化合物（半導体層１３へ拡散させる物質を含む化合物）をマスク１２に対して配置してもよい。その配置位置としては、先に形成しマスク１２の外形に影響がないように埋め込むように配置してもよいし、マスク１２上に配置してもよい。マスク１２上面に段差のある形状が形成される場合は、形状による領域選択と物質による領域選択とを同時に施したこととなる。すなわち、形状及び物質により領域選択が施されたマスク１２が設けられる。Ｐ型不純物１２ｐを、開口１２ａを囲むリング状に配置する。
　以上の元素による領域選択をマスク１２に施した後、上記第１実施形態と同様にＧａＮ層１３，１４をエピタキシャル成長により形成する（図４Ｂ）。
　すると、Ｐ型不純物１２ｐの一部がＧａＮ層１３に移動するとともに、ＧａＮ層１３に拡散し、ＧａＮ層１３内にＰ型領域１３ｐが形成される。このときＰ型不純物１２ｐの拡散は、ＧａＮ層１３，１４のエピタキシャル成長時における高温状態で自然に行われてもよいし、別途Ｐ型不純物１２ｐを拡散させるための加熱工程を更に設けてもよい。
　支持基板１５の接合、裏面電極１６の形成も同様に実施した後、図４Ｃに示すようにＧａＮ層１３の表面に開口を有する絶縁膜２０を形成する。さらに絶縁膜２０の開口を介して、ＧａＮ層１３のＮ型領域にショットキー接合するショットキー金属膜２１及び、Ｐ型領域１３ｐにオーミック接合する金属リング２２を形成してガードリングとする。
　以上によりガードリング付きのショットキーバリアダイオード１０１を製造することができる。図２及び図３を参照して説明した内容は同様に実施することができる。
〔第３実施形態〕
　さらに他の実施形態である第３実施形態につき説明する。
　本実施形態は、上記第２実施形態に対して一部変更し、ＰＮ接合とショットキー接合が併存した半導体素子１０２を製造するものである。
　図５Ａ，図５Ｂに示すように上記第２実施形態と同様の製造プロセスを実施する。任意にＰ型不純物１２ｐの本数、配置は選択する。
　図５Ｃに示すように基板１１及びマスク１２からの分離、裏面電極１６までの形成を終え、ＧａＮ層１３の表面に上面電極金属膜３０を形成する。
　上面電極金属膜３０は、ＧａＮ層１３のＰ型領域１３ｐ及びＮ型領域に接合する。すなわち、Ｐ型領域１３ｐにオーミック接合し、Ｐ型領域１３ｐに隣接したＮ型領域にショットキー接合する上面電極金属膜３０を形成する。
　以上によりＰＮ接合とショットキー接合が併存した半導体素子１０２を製造することができる。図２及び図３を参照して説明した内容は同様に実施することができる。
　以上の本開示の実施形態によれば、マスク１２上でエピタキシャル成長させた半導体層１３，１４の当該マスク１２の上面に接する面に、マスク１２への領域選択の影響による構造を形成することができ、半導体層１３，１４を基板１１から分離して同構造を素子上面側とすることで、メサ段差、フィールドプレート、ガードリング等の耐圧構造の基礎とすることができる。
　以上本開示の実施形態を説明したが、この実施形態は、例として示したものであり、この他の様々な形態で実施が可能であり、発明の要旨を逸脱しない範囲で、構成要素の省略、置き換え、変更を行うことができる。
　例えば第１実施形態、第２実施形態及び第３実施形態を適宜組み合せて例示した以外の種々の構造を形成してもよい。
　例えば第２実施形態及び第３実施形態において、Ｐ型不純物の代わりにＮ型不純物をＧａＮ層に拡散させてもよい。
　以上の実施形態では、形状による領域選択と、物質の配置による領域選択につき説明したが、マスクに施す領域選択は、物理的又は化学的に当該マスクに対しマクロ的又はミクロ的な構造の変化による領域選択が施され、その選択（選別）で分けられた領域にそれぞれ対応して、その上に成長するエピタキシャル膜に異なった影響を残すものであればよい。
　形状による領域選択は、傾斜の変化又は表面粗さの変化によっても可能であり、その形状が転写される。物質が同じでも結晶構造又は結晶方位が異なることで領域選択してもよい。
　本開示は、半導体素子の製造方法及び半導体装置に利用することができる。
１１   基板
１２   マスク
１２ａ マスクの開口
１２ｂ 段差
１２ｐ Ｐ型不純物
１３   ＧａＮ層（半導体層）
１３ｐ Ｐ型領域
１４   ＧａＮ層（半導体層）
１５   支持基板
１６   裏面電極
１７   絶縁膜
１８   ショットキー金属膜
１９   上面電極金属膜
２０   絶縁膜
２１   ショットキー金属膜
２２   金属リング（ガードリング）
３０   上面電極金属膜
１００ 半導体素子（ダイオード）
２００ 実装基板
２０１ 電極パッド
２０２ 電極パッド
２０３ ボンディングワイヤー

Claims (14)

  1. 基板の表面上に、開口を有し該開口の周囲上面領域に所定の構造を設ける加工を施したマスクを設け、
    前記開口から露出する前記基板の表面から前記周囲上面領域上まで半導体をエピタキシャル成長させ、前記所定の構造を転写した半導体層を有する半導体素子を作製する半導体素子の製造方法。
  2. 前記所定の構造は段差のある形状である請求項１に記載の半導体素子の製造方法。
  3. 前記形状の転写により、前記半導体素子にメサ構造又はトレンチ構造を形成する請求項２に記載の半導体素子の製造方法。
  4. 前記加工した領域は、前記開口を囲む請求項１から請求項３のうちいずれか一に記載の半導体素子の製造方法。
  5. 前記マスクを除去し、
    前記基板に対する反対側の前記半導体層の面を支持基板に接合した状態として前記半導体層を前記基板から分離し、
    その後、前記半導体層の前記基板から分離した面を囲む開口を有し、前記メサ構造又はトレンチ構造を覆う絶縁膜を形成し、
    その後、前記絶縁膜の開口を覆い、前記絶縁膜上に前記メサ構造又はトレンチ構造まで延設された金属膜を形成する請求項３に記載の半導体素子の製造方法。
  6. 前記所定の構造は、前記マスクに選択的に所定の元素を配置するものであり、
    前記転写により、当該元素が前記半導体層へ移動する請求項１に記載の半導体素子の製造方法。
  7. 前記所定の元素を前記マスク内に導入することで、前記マスクに配置する請求項１又は請求項６に記載の半導体素子の製造方法。
  8. 前記所定の元素を含む化合物を配置することで、前記マスクに前記所定の元素を配置する請求項１又は請求項６に記載の半導体素子の製造方法。
  9. 前記加工した領域は、前記開口を囲む請求項６又は請求項７に記載の半導体素子の製造方法。
  10. エピタキシャル成長させる前記半導体をＮ型とし、
    前記元素としてＰ型不純物を前記半導体層へ拡散させてＰ型領域を前記半導体層内に形成した後、
    前記マスクを除去し、
    前記基板に対する反対側の前記半導体層の面を支持基板に接合した状態として前記半導体層を前記基板から分離し、
    その後、前記Ｐ型領域に接合する金属リングを形成してガードリングとする請求項９に記載の半導体素子の製造方法。
  11. エピタキシャル成長させる前記半導体をＮ型とし、
    前記物質としてＰ型不純物を前記半導体層へ拡散させてＰ型領域を前記半導体層内に形成した後、
    前記マスクを除去し、
    前記基板に対する反対側の前記半導体層の面を支持基板に接合した状態として前記半導体層を前記基板から分離し、
    その後、前記Ｐ型領域にオーミック接合し、前記Ｐ型領域に隣接した前記Ｎ型領域にショットキー接合する金属膜を形成する請求項９に記載の半導体素子の製造方法。
  12. 前記マスクの開口は平面視で略長方形の形状を有し、
    前記半導体層は平面視で前記マスクの開口の長辺方向を長辺方向とする略長方形の形状を有する請求項１から請求項１１のうちいずれか一に記載の半導体素子の製造方法。
  13. 前記マスクに開口を複数形成し、一の開口に対し一の半導体素子を対応させて、複数の半導体素子を同時に作製する請求項１から請求項１２のうちいずれか一に記載の半導体素子の製造方法。
  14. 請求項１から請求項１３のうちいずれか一に記載の半導体素子の製造方法により製造された半導体素子を含む半導体装置。
PCT/JP2020/036647 2019-09-30 2020-09-28 半導体素子の製造方法及び半導体装置 WO2021065803A1 (ja)

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JPS4638958B1 (ja) 1962-03-20 1971-11-16
US20050186757A1 (en) * 2004-02-20 2005-08-25 National Chiao Tung University Method for lift off GaN pseudomask epitaxy layer using wafer bonding way
JP2008546181A (ja) * 2005-05-17 2008-12-18 アンバーウェーブ システムズ コーポレイション 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法
JP2011066390A (ja) * 2009-08-20 2011-03-31 Pawdec:Kk 半導体素子の製造方法
US20130115763A1 (en) * 2011-11-04 2013-05-09 ASM International. N.V. Methods for forming doped silicon oxide thin films
US20190252186A1 (en) * 2018-02-12 2019-08-15 QROMIS, Inc. Method and system for forming doped regions by diffusion gallium nitride materials

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JPS4638958B1 (ja) 1962-03-20 1971-11-16
US20050186757A1 (en) * 2004-02-20 2005-08-25 National Chiao Tung University Method for lift off GaN pseudomask epitaxy layer using wafer bonding way
JP2008546181A (ja) * 2005-05-17 2008-12-18 アンバーウェーブ システムズ コーポレイション 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法
JP2011066390A (ja) * 2009-08-20 2011-03-31 Pawdec:Kk 半導体素子の製造方法
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US20190252186A1 (en) * 2018-02-12 2019-08-15 QROMIS, Inc. Method and system for forming doped regions by diffusion gallium nitride materials

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