CN114402422A - 半导体元件的制造方法及半导体装置 - Google Patents

半导体元件的制造方法及半导体装置 Download PDF

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CN114402422A
CN114402422A CN202080059243.6A CN202080059243A CN114402422A CN 114402422 A CN114402422 A CN 114402422A CN 202080059243 A CN202080059243 A CN 202080059243A CN 114402422 A CN114402422 A CN 114402422A
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semiconductor
mask
manufacturing
opening
substrate
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东克典
小松直佳
泽田达郎
中里佑介
平山知央
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Kyocera Corp
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Abstract

半导体元件的制造方法：在基板(11)的表面上设置具有开口(12a)并对该开口的周围上表面区域实施了设置给定的构造的加工的掩模(12)，使半导体从自开口露出的基板的表面外延生长到周围上表面区域上为止，制作具有转印了所述给定的构造的半导体层(13)的半导体元件。一个给定的构造为基于具有台阶的形状的构造。另一个给定的构造为基于选择性地配置的元素的构造，被转印的元素向半导体层移动。

Description

半导体元件的制造方法及半导体装置
技术领域
本公开涉及半导体元件的制造方法及半导体装置。
背景技术
一直以来，存在如下技术：在被称为ELO(Epitaxial Lateral Overgrowth，外延横向过度生长)的、在设置于基板上的生长掩模的开口使GaN(Galium Nitride，氮化镓)层晶体生长、进而在生长掩模上在横向上晶体生长(JP专利第4638958号公报)。
发明内容
本公开的1个方式的半导体元件的制造方法，在基板的表面上设置具有开口且在该开口的周围上表面区域实施了设有给定的构造的加工的掩模，使半导体从自所述开口露出的所述基板的表面外延生长到所述周围上表面区域上为止，制作具有转印了所述给定的构造的半导体层的半导体元件。
附图说明
图1A为用于说明本公开的第1实施方式的截面示意图。
图1B为用于说明本公开的第1实施方式的截面示意图。
图1C为用于说明本公开的第1实施方式的截面示意图。
图1D为用于说明本公开的第1实施方式的截面示意图。
图1E为用于说明本公开的第1实施方式的截面示意图。
图2为用于说明本公开的第1实施方式的截面示意图。
图3为用于说明本公开的第1实施方式的示意性立体图。
图4A为用于说明本公开的第2实施方式的截面示意图。
图4B为用于说明本公开的第2实施方式的截面示意图。
图4C为用于说明本公开的第2实施方式的截面示意图。
图5A为用于说明本公开的第3实施方式的截面示意图。
图5B为用于说明本公开的第3实施方式的截面示意图。
图5C为用于说明本公开的第3实施方式的截面示意图。
具体实施方式
以下，参照附图对本公开的一实施方式进行说明。
〔第1实施方式〕
首先，对第1实施方式的半导体元件的制造方法及半导体装置进行说明。
(制造方法)
如下制造半导体元件。
在图1A所示的基板11表层的GaN层的上表面形成包括SiO2的掩模12。另外，基板11表层的GaN层的下表面也可由硅基板(未图示)等的GaN以外的材料支承。例如，也可为蓝宝石基板、SiC(Silicon Carbide，碳化硅)基板。作为掩模12的材料也可适用SiN、AlN、Al2O3、Ga2O3等其他材料。掩模12也可为非晶状的掩模。
掩模12具有开口12a。在本实施方式中，根据形状对开口12a的周围上表面区域实施了区域选择。而且，区域选择为基于具有台阶12b的形状的选择，是在台阶上和下划分区域的选择。台阶12b围绕开口12a一周地包围，在开口12a侧形成有下级，在远离开口12a的区域形成有上级。即，通过区域选择而分开的区域的边界线包围开口12a。这样的具有台阶12b的形状通过公知的光刻技术、湿蚀刻或者干蚀刻等形成。
接下来，采用上述的ELO技术，使GaN从自开口12a露出的基板11的表面到周围上表面区域上为止外延生长，形成GaN层13。此时，由于使GaN层13生长到实施了区域选择的周围上表面区域上为止，因而GaN层13到达进行了区域选择的不同的区域。本实施方式中，所谓进行了区域选择的不同的区域以台阶12b为边界而为下级和上级。因此，GaN层13不仅到达该下级，还到达上级。
其结果，在GaN层13的下表面转印台阶形状。如上所述，本实施方式中的区域选择的影响为形状向半导体层的转印。
控制n型杂质的掺杂量，使得GaN层13成为小于1017cm-3的电子载流子浓度。n型杂质例如也可为Si(Silicon)。由此，能够形成在设备工作时施加了电压时的耗尽层扩展的耐压层。
进而，在本实施方式中，为了得到所期望的杂质浓度分布，使高杂质浓度的GaN层14外延生长以覆盖GaN层13，成为图1A所示的状态。
如以上那样，制作具有残留有对掩模12上表面的区域选择的影响的半导体层(GaN层13)的半导体元件。
接下来，如图1B所示那样，将相对于基板11的相反一侧的半导体层的面(GaN层14的上表面)与支承基板15接合。接合也可采用经由金属的接合、直接接合来减小连接的电阻。
接下来，如图1C所示那样，在支承基板15的上表面通过例如溅射等形成背面电极16。背面电极16例如是对Al层实施了Ti、Ni、Au镀敷所得到的电极。
另外，背面电极的形成也可以在形成了后述的上表面电极金属膜19之后形成。或者也可以采用预先具有背面电极16的支承基板15。支承基板15也可为高杂质浓度的半导体，以成为低电阻。
接下来，在将半导体层的表面(GaN层14的上表面)与支承基板15接合了的状态下从基板11分离半导体层13、14。首先，采用湿蚀刻或者干蚀刻等溶解掩模12，此后，通过采用超声波等使龟裂进入开口12a附近的晶体，从而从基板11剥离。
分离后，如果使上下颠倒，则成为图1D所示那样。
如图1D所示那样，相对于从半导体层13的基板11分离的面13a，在周围形成有下降了一级的台阶13b、在其周围又下降了一级的台阶13c。将台阶13b-13c用作台面构造。
接下来，形成具有包围表面13a的开口、且覆盖台面构造(13b-13c)的绝缘膜17。
接下来，在绝缘膜17的开口露出的GaN层13形成进行肖特基接合的肖特基金属膜18。通过肖特基金属膜18覆盖绝缘膜17的开口。
接下来，在肖特基金属膜18上以及绝缘膜17上形成延伸设置到台面构造(13b-13c)为止的上表面电极金属膜19。上表面电极金属膜19在绝缘膜17上形成所谓的场电极(field plate)。
通过以上方法来制造半导体元件100。在此，半导体元件100为肖特基势垒二极管。
如上所述，通过掩模12的形状的转印，在半导体元件100形成了台面构造。
另外，无论以上的实施方式如何，形状都可以是台阶为2处以上的形状。此外，在图1A中，不仅能够实施从开口12a朝向周围向上上升的台阶，还能够实施向下下降的台阶。因此，通过设为暂时向上上升而向下下降的形状，也能形成凸的形状。通过转印掩模12的凸的形状，也能够形成沟槽构造。因此，上述台面构造也可为沟槽构造。此外，能够从半导体元件100的中心朝向周边形成一个或者多个沟槽构造和最外缘的台面构造。
此外，形状也可为设置了倾斜的台阶、磨圆了角部的构造。
如图2所示那样，同时制造多个半导体元件100，同时并行地实施以上说明的制造过程。即，在掩模12形成多个开口12a，使一个半导体元件对应一个开口，同时制作多个半导体元件。
各半导体元件100也可以分离成单片而单独地用作半导体装置。但是，在需要大容量化的情况下，能够在如图2所示那样的多个半导体元件100中共用支承基板15以及背面电极16保持不变的情况下，如图3所示那样，进行安装而作为半导体装置。
如图3所示那样，将公共的背面电极16芯片接合于安装基板200上的一个电极焊盘201，将各个上表面电极金属膜19通过键合线203与其他的电极焊盘202连接。
通过如上所述进行安装，能够将多个二极管并联连接而大容量化并利用。此时，制造为将多个半导体元件100在一定方向X上排列地配置。半导体元件100在俯视(箭头A)下，在相对于其排列方向X的大致正交方向Y上呈长条的形状。通过这样的形状和排列，容易增大二极管的接合面积。
因此，将上述制造过程中的掩模12的开口12a设为在与基板11垂直的俯视下具有大致长方形的形状。该长方形的长边方向在图2中是与附图垂直的方向。通过从大致长方形的开口12a的外延生长，半导体层13、14以及以它们为主体的半导体元件100具有在俯视下掩模12的开口12a的长边方向为长边方向(Y)的大致长方形的形状。
〔第2实施方式〕
接下来，对作为其他实施方式的第2实施方式进行说明。
在本实施方式中，对掩模12的区域选择是基于选择性地配置的给定的元素进行的选择，对区域选择的半导体层的影响是该元素向半导体层的扩散。
如图4A所示那样，对于掩模12，代替上述第1实施方式的台阶而配置元素。在此，配置P型杂质12p。P型杂质12p的配置方法没有特别限定，但也可以为如图4A所示那样导入到掩模12内的方法。作为导入方法，可以应用溅射、热扩散等。由此，实施区域选择、即实施分为配置有P型杂质12p的区域和其他区域的区域选择。
此外，也可以在掩模12配置包括P型杂质的化合物(包括向半导体层13扩散的物质在内的化合物)。作为其配置位置，既可以先形成，以不影响掩模12的外形地埋入，也可配置在掩模12上。在掩模12的上表面形成有具有台阶的形状的情况下，同时实施了基于形状的区域选择和基于物质的区域选择。即，设置有根据形状以及物质实施了区域选择的掩模12。将P型杂质12p配置为包围开口12a的环状。
在对掩模12实施了基于以上元素的区域选择之后，与上述第1实施方式同样地通过外延生长来形成GaN层13、14(图4B)。
于是，P型杂质12p的一部分移动到GaN层13，并且扩散到GaN层13，在GaN层13内形成有P型区域13p。此时，P型杂质12p的扩散也可以在GaN层13、14的外延生长时的高温状态下自然地进行，也可以另外设置用于使P型杂质12p扩散的加热工序。
在同样地实施了支承基板15的接合、背面电极16的形成之后，如图4C所示那样，在GaN层13的表面形成具有开口的绝缘膜20。进而，经由绝缘膜20的开口，形成与GaN层13的N型区域进行肖特基接合的肖特基金属膜21以及与P型区域13p进行欧姆接合的金属环22而形成保护环。
通过以上方法，能够制造带保护环的肖特基势垒二极管101。参照图2以及图3说明的内容能够同样地实施。
〔第3实施方式〕
进一步说明作为其他实施方式的第3实施方式。
本实施方式为对上述第2实施方式进行了一部分变更来制造PN结与肖特基结并存的半导体元件102的实施方式。
如图5A、图5B所示那样，实施与上述第2实施方式同样的制造过程。任意地选择P型杂质12p的个数、配置。
如图5C所示那样，结束从基板11以及掩模12的分离、到背面电极16的形成，在GaN层13的表面形成上表面电极金属膜30。
上表面电极金属膜30与GaN层13的P型区域13p以及N型区域接合。即，与P型区域13p进行欧姆接合，在与P型区域13p相邻的N型区域形成进行肖特基接合的上表面电极金属膜30。
通过以上方法，能够制造PN结和肖特基结并存的半导体元件102。参照图2以及图3进行了说明的内容能够同样地进行实施。
根据以上的本公开的实施方式，能够在使外延生长到掩模12上的半导体层13、14的与该掩模12的上表面相接的面形成基于区域选择对掩模12的影响的构造，通过将半导体层13、14从基板11分离而将该构造设为元件上表面侧，从而能够设为台面台阶、场电极、保护环等耐压构造的基础。
以上说明了本公开的实施方式，但该实施方式作为例子而示出的，能够以其他各种方式实施，在不脱离发明的主旨的范围内，能够进行结构要素的省略、置换、变更。
例如，也可以适当组合第1实施方式、第2实施方式以及第3实施方式而例示的以外的各种构造。
例如，在第2实施方式以及第3实施方式中，也可使N型杂质代替P型杂质扩散到GaN层。
在以上的实施方式中，对基于形状的区域选择、基于物质的配置的区域选择进行了说明，但对掩模实施的区域选择为如下选择即可：只要是物理上或者化学上对该掩模实施基于宏观或者微观构造的变化的区域选择，并与通过该选择(区分)分开的区域分别对应地在其上生长的外延膜残留不同的影响的区域选择。
基于形状的区域选择也能根据倾斜的变化或者表面粗糙度的变化来选择，其形状被转印。即使物质相同，也可通过晶体构造或者晶体取向不同而进行区域选择。
产业上的可利用性
本公开能够利用于半导体元件的制造方法及半导体装置。
-符号说明-
11 基板
12 掩模
12a 掩模的开口
12b 台阶
12p P型杂质
13 GaN层(半导体层)
13p P型区域
14 GaN层(半导体层)
15 支承基板
16 背面电极
17 绝缘膜
18 肖特基金属膜
19 上表面电极金属膜
20 绝缘膜
21 肖特基金属膜
22 金属环(保护环)
30 上表面电极金属膜
100 半导体元件(二极管)
200 安装基板
201 电极焊盘
202 电极焊盘
203 键合线。

Claims (14)

1.一种半导体元件的制造方法，
在基板的表面上设置具有开口且在该开口的周围上表面区域实施了设有给定的构造的加工的掩模，
使半导体从自所述开口露出的所述基板的表面外延生长到所述周围上表面区域上为止，制作具有转印了所述给定的构造的半导体层的半导体元件。
2.根据权利要求1所述的半导体元件的制造方法，其中，
所述给定的构造为具有台阶的形状。
3.根据权利要求2所述的半导体元件的制造方法，其中，
通过所述形状的转印在所述半导体元件形成台面构造或者沟槽构造。
4.根据权利要求1～3中任一项所述的半导体元件的制造方法，其中，
所述进行了加工的区域包围所述开口。
5.根据权利要求3所述的半导体元件的制造方法，其中，
除去所述掩模，
作为将相对于所述基板的相反一侧的所述半导体层的面与支承基板进行了接合的状态而将所述半导体层从所述基板分离，
此后，形成具有将从所述半导体层的所述基板分离了的面包围的开口，并覆盖所述台面构造或者沟槽构造的绝缘膜，
此后，形成覆盖所述绝缘膜的开口，并在所述绝缘膜上延伸设置到所述台面构造或者沟槽构造为止的金属膜。
6.根据权利要求1所述的半导体元件的制造方法，其中，
所述给定的构造为对所述掩模选择性地配置给定的元素的构造，
通过所述转印而相应元素向所述半导体层移动。
7.根据权利要求1或6所述的半导体元件的制造方法，其中，
通过将所述给定的元素导入所述掩模内，从而配置于所述掩模。
8.根据权利要求1或6所述的半导体元件的制造方法，其中，
通过配置包括所述给定的元素的化合物，从而在所述掩模配置所述给定的元素。
9.根据权利要求6或7所述的半导体元件的制造方法，其中，
所述进行了加工的区域包围所述开口。
10.根据权利要求9所述的半导体元件的制造方法，其中，
将使外延生长的所述半导体设为N型，
在使P型杂质作为所述元素向所述半导体层扩散而在所述半导体层内形成了P型区域之后，
除去所述掩模，
作为将相对于所述基板的相反一侧的所述半导体层的面与支承基板相接合的状态将所述半导体层从所述基板分离，
此后，形成与所述P型区域接合的金属环作为保护环。
11.根据权利要求9所述的半导体元件的制造方法，其中，
将使外延生长的所述半导体设为N型，
在使P型杂质作为所述物质向所述半导体层扩散而在所述半导体层内形成了P型区域之后，
除去所述掩模，
作为将相对于所述基板的相反一侧的所述半导体层的面与支承基板相接合的状态将所述半导体层从所述基板分离，
此后，形成与所述P型区域进行欧姆接合且与相邻于所述P型区域的所述N型区域进行肖特基接合的金属膜。
12.根据权利要求1～11中任一项所述的半导体元件的制造方法，其中，
所述掩模的开口在俯视下具有大致长方形的形状，
所述半导体层在俯视下具有将所述掩模的开口的长边方向设为长边方向的大致长方形的形状。
13.根据权利要求1～12中任一项所述的半导体元件的制造方法，其中，
在所述掩模形成了多个开口，使一个半导体元件对应一个开口来同时制作多个半导体元件。
14.一种半导体装置，包括通过权利要求1～13中任一项所述的半导体元件的制造方法制造的半导体元件。
CN202080059243.6A 2019-09-30 2020-09-28 半导体元件的制造方法及半导体装置 Pending CN114402422A (zh)

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