WO2021063302A1 - 功分器、调节方法、功率分配方法、存储介质及电子装置 - Google Patents

功分器、调节方法、功率分配方法、存储介质及电子装置 Download PDF

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WO2021063302A1
WO2021063302A1 PCT/CN2020/118315 CN2020118315W WO2021063302A1 WO 2021063302 A1 WO2021063302 A1 WO 2021063302A1 CN 2020118315 W CN2020118315 W CN 2020118315W WO 2021063302 A1 WO2021063302 A1 WO 2021063302A1
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power
impedance
dividing unit
power divider
equal
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PCT/CN2020/118315
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English (en)
French (fr)
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黄蓓
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深圳市中兴微电子技术有限公司
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Priority to KR1020217035273A priority Critical patent/KR102670636B1/ko
Priority to JP2021566123A priority patent/JP7417633B2/ja
Priority to EP20872242.1A priority patent/EP3952018A4/en
Priority to US17/624,339 priority patent/US20220320703A1/en
Publication of WO2021063302A1 publication Critical patent/WO2021063302A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/12—Coupling devices having more than two ports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/12—Coupling devices having more than two ports
    • H01P5/16—Conjugate devices, i.e. devices having at least one port decoupled from one other port
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/12—Coupling devices having more than two ports
    • H01P5/16—Conjugate devices, i.e. devices having at least one port decoupled from one other port
    • H01P5/19—Conjugate devices, i.e. devices having at least one port decoupled from one other port of the junction type

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  • the present disclosure relates to the field of communications, for example, to a power divider, an adjustment method, a power distribution method, a storage medium, and an electronic device.
  • a power divider is a microwave device that divides the energy of one input signal into two or multiple outputs.
  • the power divider is often in the form of equal division (3dB), but there are also unequal power division ratios.
  • the power divider is usually divided into one to two (one input and two outputs) power divider, one to three (one input and three outputs) power divider and so on.
  • the main technical parameters of the power splitter are: power loss (including insertion loss, distribution loss and reflection loss), voltage standing wave ratio of each port, isolation between output ports, amplitude balance, phase balance, power capacity and Bandwidth, etc.
  • the simplest structure of the power divider is a T-junction.
  • the T-junction power divider is a simple three-port network. There are usually lossless T-junction power dividers and resistive power dividers.
  • the lossless T-junction power splitter cannot match at all ports, and there is no isolation between the output ports; while the resistive power splitter can match at all ports, but it is not lossless, and the isolation is still not good.
  • the Wilkinson power divider can achieve port matching, and the transmission loss is very small.
  • the introduction of isolation resistance in the output part allows a relatively good isolation between multiple output ports, and is widely used in circuits.
  • the traditional Wilkinson power divider is based on the impedance transformation characteristics of the quarter wavelength, and realizes the input and output matching.
  • the one-to-two N power divider uses multiple one-to-two Wilkinson power dividers.
  • the splitter cascade is realized.
  • This traditional design method requires at least a quarter-wavelength of the microstrip line length for each section of one-to-two power divider, which not only increases the loss, but also takes up a large area and increases the cost. Said it is not conducive to integration.
  • 1 is a partial schematic view of two Wilkinson power splitter
  • FIG. 2 is a partial schematic view of a Wilkinson power divider 2 of N, as shown in FIGS.
  • the Wilkinson one-to-two N power divider has a total of N-level power dividers, the first level has a one-to-two power divider, and the second level has two one-to-two power dividers...the Nth level has 2 (N-1) one-to-two power dividers, these 2 N -1 identical power dividers are connected to form a one-to-two N power divider.
  • the overall structure diagram is shown in Figure 2. However, since the length of the signal line between the input and output of each one-to-two power divider is a fixed quarter wavelength, this not only increases the area of the power divider, but also brings greater loss.
  • the present disclosure provides a power divider, an adjustment method, a power distribution method, a storage medium, and an electronic device, so as to at least solve the problem of a longer signal line length of the power divider resulting in a larger area of the power divider.
  • a power divider including:
  • each power division unit includes an input port and two output ports, each of the cascade structure
  • the K-level power subunit meets the following relationships:
  • the input impedance of the K-th power dividing unit is conjugate matched with the output impedance of the unit connected to the input port of the K-th power dividing unit, and the output impedance of the K-th power dividing unit is matched with the output impedance of the K-th power dividing unit.
  • the load impedance of the K-th power division unit is conjugate matched, where N, K, and M are all positive integers greater than or equal to 1.
  • An adjustment method is also provided, which is applied to a power splitter, including:
  • the power divider includes M power dividing units, the M power dividing units are cascaded to form an N-stage cascade structure, and each power dividing unit includes an input port and two outputs port.
  • a power distribution method includes: using the above-mentioned power divider for power distribution.
  • a computer-readable storage medium is also provided, and a computer program is stored in the computer-readable storage medium, wherein the computer program is configured to execute the above adjustment method when running.
  • An electronic device including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the above-mentioned adjustment method.
  • Figure 1 is a schematic diagram of the structure of a one-to-two Wilkinson power divider
  • Figure 2 is a schematic diagram of the structure of a 2N Wilkinson power splitter
  • Fig. 3 is a structural block diagram of a power divider provided by an embodiment of the present invention.
  • Figure 4 is a flowchart of an adjustment method provided by an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an implementation process of a miniaturized power splitter according to an optional embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a one-to-sixteen power divider provided by an optional embodiment of the present invention.
  • FIG. 7 is a schematic diagram of insertion loss from input port to sixteen output ports of a one-to-sixteen power divider provided by an optional embodiment of the present invention.
  • FIG. 3 is a structural block diagram of a power divider provided by an embodiment of the present invention. As shown in FIG. 3, it includes:
  • each power division unit includes an input port and two output ports
  • the K-th level power division unit in the cascade structure Meet the following relationships:
  • the input impedance of the K-th power dividing unit is conjugate matched to the output impedance of the unit connected to the input port of the K-th power dividing unit, and the output impedance of the K-th power dividing unit is matched with the load of the K-th power dividing unit Impedance conjugate matching, where N, K, and M are all positive integers greater than or equal to 1.
  • the input impedance of each level of power division unit is conjugate matched with the output impedance of the unit connected to the input end of each level of power division unit, and the output impedance of each level of power division unit is equal to that of each level of power division unit.
  • the load impedance of the unit is conjugate matched, that is, the inter-stage impedance of the power divider is no longer limited to a fixed impedance value, and can be a specified complex impedance, thus shortening the length of the one-to-two power divider of each stage.
  • the long signal line length of the power divider leads to the problem of a larger area of the power divider, which reduces the overall area of the power divider and also reduces the loss of the power divider.
  • the input impedance of the first-level power dividing unit is conjugate matched with the target source impedance of the power divider, and the first-level power dividing unit The output impedance of the unit is conjugate matched to the target load impedance of the power divider, where the target source impedance and target load impedance of the power divider are preset; when M is greater than or equal to 3, N is greater than or equal to 2 and K is equal to In the case of 1, the input impedance of the first-level power dividing unit is conjugated to the target source impedance of the power divider, and the output impedance of the first-level power dividing unit is conjugated to the load impedance of the first-level power dividing unit; When M is greater than or equal to 3, N is greater than or equal to 2, and K is greater than or equal to 2 and less than N, the input impedance of the K-th power subunit is conjugate matched with the output impedance of the K-1th
  • the power divider further includes: an isolation impedance unit, wherein the isolation impedance unit is connected between two output ports of the power dividing unit, and the isolation impedance unit is configured to adjust the output impedance of the power dividing unit to adjust the output impedance of the power dividing unit.
  • the output impedance of the power dividing unit is conjugated to the load impedance of the power dividing unit.
  • the isolation impedance unit includes a resistor and a capacitor connected in parallel.
  • the input impedance and/or output impedance corresponding to all or part of the intermediate ports in the power divider are not equal to the power divider
  • the input impedance or output impedance of part or all of the middle port may not be equal to the target source impedance or target load impedance of the power divider, where the middle port It is the input port or output port between the input port of the power divider and the output port of the power divider in the power divider; for example, it includes the output port from the first-stage power divider unit of the power divider to the last one of the power divider. All the ports of the input ports of the first-level power dividing unit also include the output ports of the first-level power dividing unit and the input ports of the last-level power dividing unit.
  • FIG. 4 is a flowchart of an adjustment method provided by an embodiment of the present invention. , As shown in Figure 4, including:
  • Step S402 Adjust the input impedance of the K-th power dividing unit so that the input impedance of the K-th power dividing unit is conjugate matched with the output impedance of the unit connected to the input port of the K-th power dividing unit.
  • Step S404 Adjust the output impedance of the K-th power dividing unit so that the output impedance of the K-th power dividing unit is conjugate matched with the load impedance of the K-th power dividing unit, where N, K, and M are all greater than or equal to A positive integer of 1, where the power divider includes M power divider units, M power divider units are cascaded to form an N-level cascade structure, and each power divider unit includes one input port and two output ports.
  • Load impedance conjugate matching that is, the inter-stage impedance of the power divider is no longer limited to a fixed impedance value, and can be a specified complex impedance, thus shortening the length of the one-to-two power divider of each stage, and solves the related technology
  • the longer signal line length of the power divider leads to the problem of a larger area of the power divider, which reduces the overall area of the power divider and also reduces the loss of the power divider.
  • the input impedance of the K-th power dividing unit is adjusted so that the input impedance of the K-th power dividing unit is conjugate matched to the output impedance of the unit connected to the input port of the K-th power dividing unit ; Adjust the output impedance of the K-th power dividing unit to make the output impedance of the K-th power dividing unit and the load impedance of the K-th power dividing unit conjugate match, including:
  • N, M, and K are all 1, adjust the input impedance of the first-level power divider to match the target source impedance of the power divider, and adjust the output impedance and power divider of the first-level power divider
  • the target load impedance of the power divider is conjugate matched, where the target source impedance and the target load impedance of the power divider are preset; when M is greater than or equal to 3, N is greater than or equal to 2, and K is equal to 1, adjust the first The input impedance of the first-level power dividing unit is conjugate matched with the target source impedance of the power divider, and the output impedance of the first-level power dividing unit is adjusted to match the load impedance of the first-level power dividing unit; when M is greater than or equal to 3 , When N is greater than or equal to 2 and K is greater than or equal to 2 and less than N, adjust the input impedance of the K-th power subunit to match the output impedance of the K-1th power subunit,
  • the output impedance of the K-th power division unit is adjusted in the following manner:
  • the input impedance and/or output impedance corresponding to all or part of the intermediate ports in the adjusted power divider are not equal to The target source impedance or target load impedance of the power divider, where the middle port is the input port or output port between the power divider input port and the power divider output port in the power divider.
  • a power distribution method including: using the power divider as described in any of the foregoing embodiments to perform power distribution.
  • the embodiment of the present invention provides a design method for a miniaturized power divider, by which a power divider whose area is reduced to at least one-third of the original and transmission loss is also reduced.
  • FIG. 5 is a schematic diagram of the implementation process of a miniaturized power divider according to an optional embodiment of the present invention. As shown in FIG. 5, the method of the miniaturized power divider according to the embodiment of the present invention includes the following steps:
  • the first step First, clearly require the source impedance Z S and load impedance Z L of the 2 N power divider. For example, set the target source impedance and target load impedance of the power divider in advance to make the input and output impedance of the power divider and the source Impedance and load impedance are conjugate matched.
  • Step 2 Realize the one-to-two power divider from the input Z in1 to the output matching the load Z L1.
  • the characteristic impedance of the microstrip line used by the power splitter is Z 01 , and the arm length is l 1 .
  • the output impedance of the first-stage one-to-two power divider is conjugate matched to the load impedance to obtain good transmission characteristics.
  • the two output ports of the first-stage one-to-two power divider are connected by an isolation impedance, and the isolation impedance Z 1 can be formed by a resistor R 1 and a capacitor C 1 in parallel.
  • the isolation resistor R 1 and the capacitor C 1 not only improve the isolation, but also adjust the output impedance to achieve conjugate matching with the load impedance.
  • the third step realize the one-to-two power divider from the input impedance Z in2 to the output and the load Z L2 matching, and cascade with the power divider designed in the second step to realize the one-to-four power divider.
  • the characteristic impedance of the microstrip line used by the power splitter is Z 02 and the arm length is l 2 .
  • the output impedance of the second-stage one-to-two power divider is conjugate matched to the load impedance to obtain good transmission characteristics.
  • the two output ports of the second-stage one-to-two power divider are connected by an isolation impedance, and the isolation impedance Z 2 is connected in parallel by a resistor R 2 and a capacitor C 2.
  • the isolation resistor R 2 and the capacitor C 2 not only improve the isolation, but also adjust the output impedance to achieve conjugate matching with the load impedance.
  • Step 4 Realize the one-to-two power divider from the input impedance Z ink to the output matched with the load Z Lk , and cascade with the power divider designed in the third step to realize the one-to-two k power divider.
  • k 2,3,...,N-1.
  • the load impedances of the k-th one-to-two power divider are respectively Z Lk .
  • the relationship between Z ink and Z Lk is:
  • Z 0k is the characteristic impedance of the k-th stage one-to-two power divider
  • l k is the length of the k-th stage one-to-two power divider
  • Z Lk is the load impedance of the k-th stage one-to-two power divider
  • Z ink is the input impedance of the k-th stage one-to-two power divider
  • ⁇ 2 ⁇ / ⁇
  • ⁇ is the wavelength.
  • the output impedance of the k-th one-to-two power divider is conjugate matched to the load impedance to obtain good transmission characteristics.
  • the two output ports of the k-th one-to-two power divider are connected by an isolation impedance, and the isolation impedance Z k is connected in parallel by a resistor R k and a capacitor C k.
  • the isolation resistance R k and the capacitance C k not only play a role in improving the isolation, but also can adjust the output impedance to achieve conjugate matching with the load impedance.
  • Step 5 Realize the one-to-two power divider from the input impedance Z inN to the output and load Z LN matching, and cascade with the power divider designed in the fourth step to realize the one-to-two N power divider.
  • the input end of the N-th stage one-to-two power divider matches the output impedance Z L(N-1) * of the (N-1)-th stage one-to-two power divider, and the N-th stage one-to-two power divider matches
  • the characteristic impedance of the microstrip line used by the power splitter is Z 0N , and the arm length is l N.
  • the output impedance of the N-th stage one-to-two power divider is conjugate matched to the load impedance to obtain good transmission characteristics.
  • the two output ports of the N-th one-to-two power divider are connected by an isolation impedance, and the isolation impedance Z N is connected in parallel by a resistor R N and a capacitor CN.
  • the isolation resistance R N and the capacitor CN not only play a role in improving the isolation, but also can adjust the output impedance to achieve conjugate matching with the load impedance.
  • Step 6 Cascade the above-mentioned power dividers to form a one-to-two N power divider.
  • the one-to-two N power divider designed in the embodiment of the present invention has N levels, and is composed of 2 N -1 power dividers connected.
  • the first stage has a one-to-two power divider
  • the second stage has two one-to-two power dividers
  • the third stage has four one-to-two power dividers
  • the Nth stage has 2 (N- 1) A power divider.
  • the input end of the first-stage one-to-two power divider is connected to the source impedance, and the signal is transmitted from the source impedance to the input end of the first-stage one-to-two power divider, and the power is achieved through the first-stage one-to-two power divider. Allocated in two equal parts.
  • the two output terminals of the first-stage one-to-two power divider are respectively connected to the input terminals of the second-stage two one-to-two power dividers, and the signal passes through the first and second-stage power dividers to achieve power division into four. distribution.
  • the two output terminals of the N-1 stage one-to-two power divider are respectively connected to the input terminals of the N-th stage two one-to-two power dividers, and the signal achieves the power of 2 through the N-stage power divider.
  • N is divided equally.
  • the traditional Wilkinson power divider adopts a quarter-wavelength power divider arm length to achieve 50ohm matching from the output port to the input port.
  • the multi-stage one-to-two power divider adopts flexible impedance matching without restriction In a quarter wavelength, the effect of reducing the arm length of the power splitter and reducing the size of the power splitter can be achieved.
  • This method is applicable and effective whether in board-level circuits or in chip circuits.
  • the one-to-sixteen power divider based on the theoretical design described in the embodiment of the present invention effectively solves the problems of the above-mentioned traditional power divider.
  • the overall structure diagram of the one-to-sixteen power divider is shown in FIG. 6. 6 is a specific example of the one-to-two N power divider in Figure 3.
  • ⁇ g is the wavelength of the signal in the medium of the microstrip line
  • ⁇ is the wavelength of the signal in the vacuum
  • ⁇ r is the dielectric constant of the medium in the microstrip line.
  • Z in and Z L are not fixed 50 ohms, but an intermediate impedance value that can be realized.
  • the arm length l of the power divider is not a quarter wavelength, but a value determined by the input and output impedance.
  • the power divider in the embodiment of the present invention is composed of a microstrip line, the signal line is the top thick metal E1 layer, the bottom M1 metal is used as the ground plane, the working frequency band is 37GHz-40GHz, the quarter wavelength is about 1200 ⁇ m, and the input and output impedance is 50ohm.
  • the input impedance needs to be matched with 50 ohm, and the output impedance does not need to be matched with 50 ohm, so the length of the microstrip line The length of a quarter wavelength is not required.
  • the characteristic impedance of the designed microstrip line is 50ohm, the output impedance of the output port is 56ohm-j25ohm, and the length is 387 ⁇ m, which is one third of a quarter wavelength.
  • the isolation between output ports is optimized by isolation resistance and capacitance.
  • the input impedance is designed to be 56ohm+j25ohm to match the first section of the power divider, and a microstrip with a characteristic impedance of 50ohm is also used.
  • the line realizes the function of one-to-two power distribution.
  • the length of the microstrip line is 330 ⁇ m, which is one third of a quarter wavelength.
  • the output impedance of the output port is 40ohm-j40ohm, and the isolation between the output ports is optimized by isolation resistance and capacitance.
  • the input impedance is designed to be 40ohm+j40ohm to match the second-section power divider, and a microstrip with a characteristic impedance of 50ohm is also used.
  • the line realizes the function of one-to-two power distribution, and the length of the microstrip line is 290 ⁇ m.
  • the output impedance of the output port is 30ohm-j42ohm, and the isolation between the output ports is optimized by isolation resistance and capacitance.
  • the input impedance is designed to be 30 ohm+j42 ohm to match the third-section power divider, and the output impedance must match the 50 ohm load.
  • the isolation between output ports is optimized by isolation resistance and capacitance.
  • the above-mentioned first-stage one-to-two power divider, second-stage one-to-two power divider, third-stage one-to-two power divider, and fourth-stage one-to-two power divider are cascaded to obtain sixteen equal power dividers Divider.
  • the one-to-sixteen power divider involved in the embodiment of the present invention includes one first-stage one-to-two power divider, two second-stage one-to-two power dividers, four third-stage one-to-two power dividers and eight A fourth-level one-to-two power divider.
  • each stage of the one-to-two power divider of the traditional Wilkinson power divider is a quarter wavelength, while the length of each stage of the one-to-two power divider in the power divider designed in the embodiment of the present invention is only the traditional power divider. 1/3 of the length of the device.
  • the total area of the power divider is 1.3mm*1.3mm, which greatly reduces the area cost of the chip compared with the traditional power divider.
  • the power divider designed in the embodiment of the present invention also reduces the transmission loss.
  • the designed one-to-sixteen power divider has a loss of less than 1dB, the isolation of multiple output ports is also less than -20dB, and the return loss of the input port S11 ⁇ -10dB.
  • the return loss, insertion loss and isolation curves of the designed one-to-sixteen power divider are shown in Figure 7.
  • a one-to-sixteen power divider is designed with good performance indicators and an area reduced to about one-third of the traditional Wilkinson power divider, which greatly saves In order to reduce the cost of circuit design, it is suitable to be promoted in circuit design.
  • the method of the above embodiment can be implemented by software plus a necessary general hardware platform, or by hardware.
  • the technical solution of the present disclosure can essentially be embodied in the form of a software product, the computer software product is stored in a storage medium (such as Read-Only Memory, ROM)/Random Access Memory (Random Access Memory, RAM), magnetic disk,
  • a storage medium such as Read-Only Memory, ROM)/Random Access Memory (Random Access Memory, RAM), magnetic disk,
  • the optical disc includes multiple instructions to enable a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in the embodiment of the present invention.
  • the embodiment of the present invention also provides a computer-readable storage medium, and a computer program is stored in the computer-readable storage medium, wherein the computer program is configured to execute the steps in any of the foregoing method embodiments when running. .
  • the foregoing computer-readable storage medium may be configured to store a computer program for executing the following steps:
  • Load impedance conjugate matching that is, the inter-stage impedance of the power divider is no longer limited to a fixed impedance value, and can be a specified complex impedance, thus shortening the length of the one-to-two power divider of each stage, and solves the related technology
  • the longer signal line length of the power divider leads to the problem of a larger area of the power divider, which reduces the overall area of the power divider and also reduces the loss of the power divider.
  • the foregoing storage medium may include, but is not limited to: U disk, ROM, RAM, mobile hard disk, magnetic disk, or optical disk, and other media that can store computer programs.
  • An embodiment of the present invention also provides an electronic device including a memory and a processor, the memory is stored with a computer program, and the processor is configured to run the computer program to execute the steps in any of the foregoing method embodiments.
  • the aforementioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the aforementioned processor, and the input-output device is connected to the aforementioned processor.
  • the foregoing processor may be configured to execute the following steps through a computer program:
  • Load impedance conjugate matching that is, the inter-stage impedance of the power divider is no longer limited to a fixed impedance value, and can be a specified complex impedance, thus shortening the length of the one-to-two power divider of each stage, and solves the related technology
  • the longer signal line length of the power divider leads to the problem of a larger area of the power divider, which reduces the overall area of the power divider and also reduces the loss of the power divider.
  • the above-mentioned multiple modules or multiple steps of the present disclosure can be implemented by a general computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be It is implemented by the program code executable by the computing device, so that they can be stored in the storage device to be executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, Or they can be made into multiple integrated circuit modules respectively, or multiple modules or steps of them can be made into a single integrated circuit module to achieve. In this way, the present disclosure is not limited to any specific combination of hardware and software.

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Abstract

本文公开了一种功分器、调节方法、功率分配方法、存储介质及电子装置。该功分器包括M个功分单元，其中，M个功分单元级联形成N级的级联结构，每个功分单元包括一个输入端口和两个输出端口，级联结构中的每个第K级功分单元满足以下关系：第K级功分单元的输入阻抗与第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配，并且，第K级功分单元的输出阻抗与第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数。

Description

功分器、调节方法、功率分配方法、存储介质及电子装置
本申请要求在2019年09月30日提交中国专利局、申请号为201910944533.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及通信领域，例如涉及一种功分器、调节方法、功率分配方法、存储介质及电子装置。
背景技术
由于移动通信、电子对抗以及卫星通讯等向着小型化、宽频带以及更高的工作频段发展，使得对频率和带宽的要求也向着高频率、宽频带的方向发展。在第五代移动通信系统(the 5th Generation mobile communication system，5G)技术迅猛发展的时代，毫米波频段由于其大带宽和高容量的特性被广泛地研究。由于高频信号在传输的过程中会有大的损耗从而影响通信质量，因此需要应用多通道相控阵技术，而功率分配器(功分器)是其中必不可少的一部分。随着对射频器件集成小型化的需求，微波集成电路形式的功分器开始被研究。功分器的性能将影响整个系统的性能，因此设计出小型化的功分器具有重要的意义。
功分器，是一种将一路输入信号能量分成两路或者多路输出的微波器件，功分器经常是等分(3dB)的形式，但也有不相等的功分比。功分器按输出通常分为一分二(一个输入两个输出)功分器、一分三(一个输入三个输出)功分器等。功分器的主要技术参数有：功率损耗(包括插入损耗、分配损耗和反射损耗)，每个端口的电压驻波比，输出端口间的隔离度、幅度平衡度、相位平衡度，功率容量和频带宽度等。
功分器的最简单的结构是T型结，T型结功分器是一个简单的三端口网络，通常有无耗T型结功分器和电阻性功分器。无耗T型结功分器不能在全部端口匹配，另外输出端口之间没有任何的隔离；而电阻性功分器能在全部端口匹配，但不是无耗的，而且隔离度依然不好。而Wilkinson功分器既能做到端口匹配，传输损耗又很小，另外因输出部分引入隔离电阻使得输出多个端口之间获得了比较好的隔离度，在电路中被广泛应用。
传统的Wilkinson功分器都是基于四分之一波长的阻抗变换特性，实现输入输出匹配的一分二等分功分器，而一分2 N功分器则通过多个一分二Wilkinson功分器级联实现。这种传统的设计方法使得每节一分二功分器都需要至少四分之一波长的微带线长度，不仅增大了损耗，也占用了过大的面积，提高了成本， 对于芯片来说也不利于集成。图1是一分二Wilkinson功分器的结构示意图，图2是一分2 N Wilkinson功分器的结构示意图，如图1和图2所示，输入端口和输出端口均与特性阻抗Z 0＝50ohm匹配，输入输出之间的四分之一波长线的特性阻抗为
Figure PCTCN2020118315-appb-000001
隔离电阻为2Z 0。由偶-奇模分析可知该功率分配器能实现信号的两等分。而Wilkinson一分2 N功分器共有N级功分器，第一级有一个一分二功分器，第二级有2个一分二功分器......第N级有2 (N-1)个一分二功分器，这2 N-1个完全一样的功分器连接组成一分2 N功分器，整体结构示意图如图2所示。但是由于每一个一分二功分器输入与输出之间的信号线的长度是固定的四分之一波长，这不仅增加了功分器的面积，还带来了较大的损耗。
发明内容
本公开提供了一种功分器、调节方法、功率分配方法、存储介质及电子装置，以至少解决功分器信号线长度较长导致功分器面积较大的问题。
提供了一种功分器，包括：
M个功分单元，其中，所述M个功分单元级联形成N级的级联结构，每个功分单元包括一个输入端口和两个输出端口，所述级联结构中的每个第K级功分单元满足以下关系：
所述第K级功分单元的输入阻抗与所述第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配，并且，所述第K级功分单元的输出阻抗与所述第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数。
还提供了一种调节方法，应用于功分器中，包括：
调节每个第K级功分单元的输入阻抗以使所述第K级功分单元的输入阻抗与所述第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配；
调节所述第K级功分单元的输出阻抗以使所述第K级功分单元的输出阻抗与所述第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数，所述功分器包括M个功分单元，所述M个功分单元级联形成N级的级联结构，每个功分单元包括一个输入端口和两个输出端口。
还提供了一种功率分配方法，包括：利用上述的功分器进行功率分配。
还提供了一种计算机可读的存储介质，所述计算机可读的存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述调节方法。
还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述调节方法。
附图说明
图1是一分二Wilkinson功分器的结构示意图；
图2是一分2 N Wilkinson功分器的结构示意图；
图3是本发明实施例提供的一种功分器的结构框图；
图4是本发明实施例提供的一种调节方法的流程图；
图5是本发明可选实施例提供的一种小型化功分器实施流程示意图；
图6是本发明可选实施例提供的一种一分十六功分器的结构示意图；
图7是本发明可选实施例提供的一种一分十六功分器输入端口到十六个输出端口的插入损耗的示意图。
具体实施方式
下文中将参考附图并结合实施例来说明本公开。
本文中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
实施例1
本发明实施例提供了一种功分器，图3是本发明实施例提供的一种功分器的结构框图，如图3所示，包括：
M个功分单元，其中，M个功分单元级联形成N级的级联结构，每个功分单元均包括一个输入端口和两个输出端口，级联结构中的第K级功分单元满足以下关系：
第K级功分单元的输入阻抗与第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配，并且，第K级功分单元的输出阻抗与第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数。
通过本发明实施例，由于每级功分单元的输入阻抗与每级功分单元的输入端所连接的单元的输出阻抗共轭匹配，并且，每级功分单元的输出阻抗与每级功分单元的负载阻抗共轭匹配，即，功分器的级间阻抗不再局限在固定的阻抗值，可以是一个指定的复数阻抗，因此缩短了每级一分二功分器的长度，解决了相关技术中功分器信号线长度较长导致功分器面积较大的问题，实现了功分器整体面积的减少，并且还降低了功分器损耗。
在一个可选的实施方式中，在N、M和K均为1的情况下，第1级功分单元的输入阻抗与功分器的目标源阻抗共轭匹配，并且，第1级功分单元的输出 阻抗与功分器的目标负载阻抗共轭匹配，其中，功分器的目标源阻抗和目标负载阻抗是预先设定的；在M大于或等于3，N大于或等于2以及K等于1的情况下，第1级功分单元的输入阻抗与功分器的目标源阻抗共轭匹配，第1级功分单元的输出阻抗与第1级功分单元的负载阻抗共轭匹配；在M大于或等于3，N大于或等于2以及K大于或等于2且小于N的情况下，第K级功分单元的输入阻抗与第K-1级功分单元的输出阻抗共轭匹配，并且，第K级功分单元的输出阻抗与第K级功分单元的负载阻抗共轭匹配，其中，K为[2，N-1]中的任意正整数；在M大于或等于3，N大于或等于2并且K等于N的情况下，第K级功分单元的输入阻抗与第K-1级功分单元的输出阻抗共轭匹配，并且，第K级功分单元的输出阻抗与功分器的目标负载阻抗共轭匹配。
在一个可选的实施方式中，功分器还包括：隔离阻抗单元，其中，隔离阻抗单元连接在功分单元的两个输出端口之间，隔离阻抗单元设置为调节功分单元的输出阻抗以使功分单元的输出阻抗与功分单元的负载阻抗共轭匹配。
在一个可选的实施方式中，隔离阻抗单元包括并联的电阻和电容。
在一个可选的实施方式中，在M大于或等于3以及N大于或等于2的情况下，功分器中的全部或部分中间端口所对应的输入阻抗和/或输出阻抗不等于功分器的目标源阻抗或者目标负载阻抗，其中，中间端口为功分器中功分器输入端口和功分器输出端口之间的输入端口或者输出端口。
当功分器包括两级或者两级以上的功分单元结构时，部分或者全部的中间端口的输入阻抗或者输出阻抗可以不等于该功分器的目标源阻抗或者目标负载阻抗，其中，中间端口为功分器中，功分器输入端口和功分器输出端口之间的输入端口或者输出端口；例如包括从功分器的第一级功分单元的输出端口直至该功分器的最后一级功分单元的输入端口中的所有端口，也包括第一级功分单元的输出端口和最后一级功分单元的输入端口。
根据本发明的另一个实施例，提供了一种调节方法，应用于功分器中，例如上述实施例所述的功分器，图4是本发明实施例提供的一种调节方法的流程图，如图4所示，包括：
步骤S402，调节第K级功分单元的输入阻抗以使第K级功分单元的输入阻抗与第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配。
步骤S404，调节第K级功分单元的输出阻抗以使第K级功分单元的输出阻抗与第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数，其中，功分器包括M个功分单元，M个功分单元级联形成N级的级联结构，每个功分单元包括一个输入端口和两个输出端口。
通过上述步骤，由于每级功分单元的输入阻抗与每级功分单元的输入端所连接的单元的输出阻抗共轭匹配，并且，每级功分单元的输出阻抗与每级功分单元的负载阻抗共轭匹配，即，功分器的级间阻抗不再局限在固定的阻抗值，可以是一个指定的复数阻抗，因此缩短了每级一分二功分器的长度，解决了相关技术中功分器信号线长度较长导致功分器面积较大的问题，实现了功分器整体面积的减少，并且还降低了功分器损耗。
在一个可选的实施方式中，调节第K级功分单元的输入阻抗以使第K级功分单元的输入阻抗与第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配；调节第K级功分单元的输出阻抗以使第K级功分单元的输出阻抗与第K级功分单元的负载阻抗共轭匹配，包括：
在N、M和K均为1的情况下，调节第1级功分单元的输入阻抗与功分器的目标源阻抗共轭匹配，并且，调节第1级功分单元的输出阻抗与功分器的目标负载阻抗共轭匹配，其中，功分器的目标源阻抗和目标负载阻抗是预先设定的；在M大于或等于3，N大于或等于2以及K等于1的情况下，调节第1级功分单元的输入阻抗与功分器的目标源阻抗共轭匹配，调节第1级功分单元的输出阻抗与第1级功分单元的负载阻抗共轭匹配；在M大于或等于3，N大于或等于2以及K大于或等于2且小于N的情况下，调节第K级功分单元的输入阻抗与第K-1级功分单元的输出阻抗共轭匹配，并且，调节第K级功分单元的输出阻抗与第K级功分单元的负载阻抗共轭匹配，其中，K为[2，N-1]中的任意正整数；在M大于或等于3，N大于或等于2并且K等于N的情况下，调节第K级功分单元的输入阻抗与第K-1级功分单元的输出阻抗共轭匹配，并且，调节第K级功分单元的输出阻抗与功分器的目标负载阻抗共轭匹配。
在一个可选的实施方式中，通过以下方式调节第K级功分单元的的输出阻抗：
调节功分单元的特性阻抗和/或微带线长度；和/或，利用隔离阻抗单元调节功分单元的输出阻抗，其中，隔离阻抗单元连接在功分单元的两个输出端口之间。
在一个可选的实施方式中，在M大于或等于3以及N大于或等于2的情况下，调节后的功分器中的全部或部分中间端口所对应的输入阻抗和/或输出阻抗不等于功分器的目标源阻抗或者目标负载阻抗，其中，中间端口为功分器中功分器输入端口和功分器输出端口之间的输入端口或者输出端口。
根据本发明的一个实施例，还提供了一种功率分配方法，包括：利用如上述任一实施例所述的功分器进行功率分配。
可选实施方式
本发明实施例提供了一种小型化功分器的设计方法，通过此设计方法可以得到面积至少缩减至原来的三分之一，传输损耗也降低的功率分配器。
图5是本发明可选实施例提供的一种小型化功分器实施流程示意图，如图5所示，本发明实施例所述小型化功分器的方法包括以下步骤：
第一步：首先明确要求一分2 N功分器的源阻抗Z S和负载阻抗Z L，例如预先设置功分器的目标源阻抗和目标负载阻抗，令功分器的输入输出阻抗与源阻抗和负载阻抗共轭匹配。
第二步：实现从输入为Z in1到输出与负载Z L1匹配的一分二功率分配器。
本发明实施例所述功分器的输入端与信号源阻抗Z S匹配，输入阻抗为Z in1＝Zs*，第一级一分二功分器的负载阻抗为Z L1。功分器所用微带线的特性阻抗为Z 01，臂长为l 1。
令第一级一分二功分器的输出阻抗和负载阻抗共轭匹配，以获得良好的传输特性。第一级一分二功分器的两个输出端口之间由隔离阻抗连接，隔离阻抗Z 1可以由电阻R 1和电容C 1并联构成。隔离电阻R 1和电容C 1不仅起到改善隔离度的作用，还调节输出阻抗以实现和负载阻抗的共轭匹配。
第三步：实现从输入阻抗为Z in2到输出与负载Z L2匹配的一分二功分器，与上述第二步设计的功分器级联实现一分四功分器。
本发明实施例所述第二级一分二功分器输入端与第一级一分二功分器输出阻抗Z L1*匹配，输入阻抗为Z in2＝Z L1。功分器所用微带线的特性阻抗为Z 02，臂长为l 2。
令第二级一分二功分器的输出阻抗和负载阻抗共轭匹配，以获得良好的传输特性。第二级一分二功分器的两个输出端口之间由隔离阻抗连接，隔离阻抗Z 2由电阻R 2和电容C 2并联。隔离电阻R 2和电容C 2不仅起到改善隔离度的作用，还调节输出阻抗以实现和负载阻抗的共轭匹配。
第四步：实现从输入阻抗为Z ink到输出与负载Z Lk匹配的一分二功分器，与第三步设计的功分器级联实现一分2 k功分器。其中，k＝2,3,...,N-1。
本发明实施例所述第k级一分二功分器输入端与第(k-1)级一分二功分器输出阻抗Z L(k-1)*匹配，输入阻抗为Z ink＝Z L(k-1)。第k级一分二功分器的负载阻抗分别为Z Lk。Z ink和Z Lk的关系是：
Figure PCTCN2020118315-appb-000002
其中，Z 0k是第k级一分二功分器的特性阻抗，l k是第k级一分二功分器的长度，Z Lk是第k级一分二功分器的负载阻抗，Z ink是第k级一分二功分器的输入阻抗，β＝2π/λ，λ是波长。
第k级一分二功分器的输出阻抗和负载阻抗共轭匹配，以获得良好的传输特性。第k级一分二功分器的两个输出端口之间由隔离阻抗连接，隔离阻抗Z k由电阻R k和电容C k并联。隔离电阻R k和电容C k不仅起到改善隔离度的作用，还可以调节输出阻抗以实现和负载阻抗的共轭匹配。
第五步：实现从输入阻抗为Z inN到输出与负载Z LN匹配的一分二功分器，与第四步设计的功分器级联实现一分2 N功分器。
本发明实施例所述第N级一分二功分器输入端与第(N-1)级一分二功分器输出阻抗Z L(N-1)*匹配，第N级一分二功分器输入端的输入阻抗为Z inN＝Z L(N-1)。第N级一分二功分器的负载阻抗分别为Z LN＝Z L。功分器所用微带线的特性阻抗为Z 0N，臂长为l N。
第N级一分二功分器的输出阻抗和负载阻抗共轭匹配，以获得良好的传输特性。第N级一分二功分器的两个输出端口之间由隔离阻抗连接，隔离阻抗Z N由电阻R N和电容C N并联。隔离电阻R N和电容C N不仅起到改善隔离度的作用，还可以调节输出阻抗以实现和负载阻抗的共轭匹配。
第六步：将上述功分器级联组成一分2 N功分器。
本发明实施例所设计的一分2 N功分器共N级，由2 N-1个功分器连接组成。第一级有一个一分二功分器，第二级有两个一分二功分器，第三级有四个一分二功分器，以此类推，第N级有2 (N-1)个功分器。
第一级一分二功分器的输入端和源阻抗相连，信号从源阻抗传递到第一级一分二功分器的输入端，通过第一级一分二功分器实现了功率的二等分分配。第一级一分二功分器的两个输出端分别接第二级两个一分二功分器的输入端，信号通过第一级和第二级功分器实现了功率的四等分分配。以此类推，第N-1级一分二功分器的两个输出端分别接第N级两个一分二功分器的输入端，信号通过这N级功分器实现了功率的2 N等分分配。
传统的Wilkinson功分器采用四分之一波长的功分器臂长实现输出端口到输入端口的50ohm匹配，本发明实施例中多级一分二功分器通过灵活的阻抗匹配而不需要限制在四分之一波长中，从而达到缩小功分器臂长，减小功分器尺寸的效果。无论是在板级电路或者在芯片电路中，此方法均适用且有效。采用本发明实施例所述的方法，减小了传输损耗，节约了面积，减少了制造成本等。
而基于本发明实施例阐述的理论设计的一分十六功分器有效的解决了上述 传统功分器存在的问题，一分十六功分器的整体结构示意图如附图6所示，图6是附图3中一分2 N功分器的具体实例。
在本发明实施例设计的每级一分二功分器中，输入阻抗Z in和负载阻抗Z L之间的关系是：
Figure PCTCN2020118315-appb-000003
其中
Figure PCTCN2020118315-appb-000004
λ g为信号在微带线介质中的波长，λ为信号在真空中的波长，ε r为微带线中介质的介电常数。
与传统功分器设计不同的是，这里Z in和Z L不是固定的50ohm，而是可以实现的一个中间阻抗值。同样，功分器的臂长l也不是四分之一波长，而是由输入输出阻抗决定的值。
本发明实施例的功分器由微带线组成，信号线为顶层厚金属E1层，底层M1金属作为地平面，工作频段为37GHz～40GHz，四分之一波长约为1200μm，输入输出阻抗为50ohm。
在本发明实施例所涉及一分十六功分器的第一级一分二功分器中，输入阻抗要和50ohm进行匹配，而输出阻抗则不需要和50ohm匹配，因此微带线的长度不需要四分之一波长的长度。设计微带线的特性阻抗为50ohm，输出端口的输出阻抗为56ohm-j25ohm，长度为387μm，是四分之一波长的三分之一。输出端口之间的隔离度通过隔离电阻及电容优化。
在本发明实施例所涉及一分十六功分器的第二级一分二功分器中，设计输入阻抗为56ohm+j25ohm以匹配第一节功分器，同样采用50ohm特性阻抗的微带线实现功率一分二分配的功能。微带线长度为330μm，是四分之一波长的三分之一。输出端口的输出阻抗为40ohm-j40ohm，输出端口之间的隔离度通过隔离电阻及电容优化。
在本发明实施例所涉及一分十六功分器的第三级一分二功分器中，设计输入阻抗为40ohm+j40ohm以匹配第二节功分器，同样采用50ohm特性阻抗的微带线实现功率一分二分配的功能，微带线长度为290μm。输出端口的输出阻抗为30ohm-j42ohm，输出端口之间的隔离度通过隔离电阻及电容优化。
在本发明实施例所涉及一分十六功分器的第四级一分二功分器中，设计输入阻抗为30ohm+j42ohm以匹配第三节功分器，输出阻抗要和50ohm负载匹配。输出端口之间的隔离度通过隔离电阻及电容优化。
将上述第一级一分二功分器、第二级一分二功分器、第三级一分二功分器以及第四级一分二功分器级联，得到十六等分功分器。本发明实施例涉及的一分十六功分器包含一个第一级一分二功分器，两个第二级一分二功分器，四个第三级一分二功分器和八个第四级一分二功分器。传统Wilkinson功分器的每级一分二功分器的长度为四分之一波长，而本发明实施例所设计的功分器中每级一分二功分器的长度均只有传统功分器长度的三分之一。功分器的总面积为1.3mm*1.3mm，与传统的功分器相比，极大的缩小了芯片的面积成本。
另外，由于一分十六功分器长度的缩短，由于微带信号线的寄生而产生的损耗也减小了，因此本发明实施例设计的功分器也降低了传输损耗。
在37GHz～40GHz频段内，所设计的一分十六功分器的损耗小于1dB，多个输出端口的隔离度也均小于-20dB，输入端口的回波损耗S11<-10dB。所设计的一分十六功分器的回波损耗，插入损耗和隔离度曲线如图7所示。
综上，基于本发明实施例提出的一分2 N功分器设计方法设计出一分十六功分器，性能指标良好且面积缩小为传统Wilkinson功分器的三分之一左右，大大节省了电路设计的成本，适宜在电路设计中加以推广。
通过以上的实施方式的描述，上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，也可以通过硬件。本公开的技术方案本质上可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如Read-Only Memory，ROM)/随机存取存储器(Random Access Memory，RAM)、磁碟、光盘)中，包括多个指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本发明实施例所述的方法。
本发明的实施例还提供了一种计算机可读的存储介质，该计算机可读的存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一方法实施例中的步骤。
可选地，在本实施例中，上述计算机可读的存储介质可以被设置为存储用于执行以下步骤的计算机程序：
S1，调节第K级功分单元的输入阻抗以使第K级功分单元的输入阻抗与第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配。
S2，调节第K级功分单元的输出阻抗以使第K级功分单元的输出阻抗与第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数，其中，功分器包括M个功分单元，M个功分单元级联形成N级的级联结构，每个功分单元包括一个输入端口和两个输出端口。
通过上述步骤，由于每级功分单元的输入阻抗与每级功分单元的输入端所 连接的单元的输出阻抗共轭匹配，并且，每级功分单元的输出阻抗与每级功分单元的负载阻抗共轭匹配，即，功分器的级间阻抗不再局限在固定的阻抗值，可以是一个指定的复数阻抗，因此缩短了每级一分二功分器的长度，解决了相关技术中功分器信号线长度较长导致功分器面积较大的问题，实现了功分器整体面积的减少，并且还降低了功分器损耗。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、ROM、RAM、移动硬盘、磁碟或者光盘等多种可以存储计算机程序的介质。
本发明的实施例还提供了一种电子装置，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一方法实施例中的步骤。
可选地，上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
可选地，在本实施例中，上述处理器可以被设置为通过计算机程序执行以下步骤：
S1，调节第K级功分单元的输入阻抗以使第K级功分单元的输入阻抗与第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配。
S2，调节第K级功分单元的输出阻抗以使第K级功分单元的输出阻抗与第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数，其中，功分器包括M个功分单元，M个功分单元级联形成N级的级联结构，每个功分单元包括一个输入端口和两个输出端口。
通过上述步骤，由于每级功分单元的输入阻抗与每级功分单元的输入端所连接的单元的输出阻抗共轭匹配，并且，每级功分单元的输出阻抗与每级功分单元的负载阻抗共轭匹配，即，功分器的级间阻抗不再局限在固定的阻抗值，可以是一个指定的复数阻抗，因此缩短了每级一分二功分器的长度，解决了相关技术中功分器信号线长度较长导致功分器面积较大的问题，实现了功分器整体面积的减少，并且还降低了功分器损耗。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
上述的本公开的多个模块或多个步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在一些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成多个集成电路模块，或者 将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。

Claims (12)

  1. 一种功分器，包括：
    M个功分单元，其中，所述M个功分单元级联形成N级的级联结构，每个功分单元包括一个输入端口和两个输出端口，所述级联结构中的每个第K级功分单元满足以下关系：
    所述第K级功分单元的输入阻抗与所述第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配，并且，所述第K级功分单元的输出阻抗与所述第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数。
  2. 根据权利要求1所述的功分器，其中，在N、M和K均为1的情况下，第1级功分单元的输入阻抗与预先设定的所述功分器的目标源阻抗共轭匹配，并且，所述第1级功分单元的输出阻抗与预先设定的所述功分器的目标负载阻抗共轭匹配；
    在M大于或等于3，N大于或等于2以及K等于1的情况下，第1级功分单元的输入阻抗与预先设定的所述功分器的目标源阻抗共轭匹配，所述第1级功分单元的输出阻抗与所述第1级功分单元的负载阻抗共轭匹配；
    在M大于或等于3，N大于或等于2以及K大于或等于2且小于N的情况下，第K级功分单元的输入阻抗与所述第K级功分单元所连接的第K-1级功分单元的输出阻抗共轭匹配，并且，所述第K级功分单元的输出阻抗与所述第K级功分单元的负载阻抗共轭匹配；
    在M大于或等于3，N大于或等于2并且K等于N的情况下，第K级功分单元的输入阻抗与所述第K级功分单元所连接的第K-1级功分单元的输出阻抗共轭匹配，并且，所述第K级功分单元的输出阻抗与预先设定的所述功分器的目标负载阻抗共轭匹配。
  3. 根据权利要求1所述的功分器，还包括：
    隔离阻抗单元，其中，所述隔离阻抗单元连接在所述功分单元的所述两个输出端口之间，所述隔离阻抗单元设置为调节所述功分单元的输出阻抗以使所述功分单元的所述输出阻抗与所述功分单元的所述负载阻抗共轭匹配。
  4. 根据权利要求3所述的功分器，其中，所述隔离阻抗单元包括并联的电阻和电容。
  5. 根据权利要求1所述的功分器，其中，在M大于或等于3以及N大于或等于2的情况下，所述功分器中的全部或部分中间端口所对应的输入阻抗不等于所述功分器的目标源阻抗，或所述功分器中的全部或部分中间端口所对应的 输出阻抗不等于所述功分器的目标负载阻抗，或所述功分器中的部分中间端口所对应的输入阻抗不等于所述功分器的目标源阻抗且功分器中的部分中间端口所对应的输出阻抗不等于所述功分器的目标负载阻抗，其中，所述中间端口为所述功分器中所述功分器的输入端口和所述功分器的输出端口之间的功分单元的输入端口和功分单元的输出端口中的至少之一。
  6. 一种调节方法，应用于功分器中，包括：
    调节所述功分器的每个第K级功分单元的输入阻抗以使所述每个第K级功分单元的输入阻抗与所述第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配，其中，所述功分器包括M个功分单元，所述M个功分单元级联形成N级的级联结构，每个功分单元包括一个输入端口和两个输出端口；
    调节所述第K级功分单元的输出阻抗以使所述第K级功分单元的输出阻抗与所述第K级功分单元的负载阻抗共轭匹配，其中，N、K和M均为大于或等于1的正整数。
  7. 根据权利要求6所述的调节方法，其中，所述调节所述功分器的每个第K级功分单元的输入阻抗以使所述每个第K级功分单元的输入阻抗与所述第K级功分单元的输入端口所连接的单元的输出阻抗共轭匹配；调节所述第K级功分单元的输出阻抗以使所述第K级功分单元的输出阻抗与所述第K级功分单元的负载阻抗共轭匹配，包括：
    在N、M和K均为1的情况下，调节第1级功分单元的输入阻抗与预先设定的所述功分器的目标源阻抗共轭匹配，并且，调节所述第1级功分单元的输出阻抗与预先设定的所述功分器的目标负载阻抗共轭匹配；
    在M大于或等于3，N大于或等于2以及K等于1的情况下，调节第1级功分单元的输入阻抗与预先设定的所述功分器的目标源阻抗共轭匹配，调节所述第1级功分单元的输出阻抗与所述第1级功分单元的负载阻抗共轭匹配；
    在M大于或等于3，N大于或等于2以及K大于或等于2且小于N的情况下，调节第K级功分单元的输入阻抗与所述第K级功分单元所连接的第K-1级功分单元的输出阻抗共轭匹配，并且，调节所述第K级功分单元的输出阻抗与所述第K级功分单元的负载阻抗共轭匹配；
    在M大于或等于3，N大于或等于2并且K等于N的情况下，调节第K级功分单元的输入阻抗与所述第K级功分单元所连接的第K-1级功分单元的输出阻抗共轭匹配，并且，调节所述第K级功分单元的输出阻抗与预先设定的所述功分器的目标负载阻抗共轭匹配。
  8. 根据权利要求6所述的调节方法，其中，通过以下方式中的至少之一调 节所述第K级功分单元的的输出阻抗：
    调节所述功分单元的特性阻抗和微带线长度中的至少之一；
    利用隔离阻抗单元调节所述功分单元的输出阻抗，其中，所述隔离阻抗单元连接在所述功分单元的所述两个输出端口之间。
  9. 根据权利要求6至8中任一项所述的调节方法，其中，在M大于或等于3以及N大于或等于2的情况下，调节后的所述功分器中的全部或部分中间端口所对应的输入阻抗不等于所述功分器的目标源阻抗，或所述功分器中的全部或部分中间端口所对应的输出阻抗不等于所述功分器的目标源阻抗或者目标负载阻抗，或所述功分器中的部分中间端口所对应的输入阻抗不等于所述功分器的目标源阻抗且功分器中的部分中间端口所对应的输出阻抗不等于所述功分器的目标负载阻抗，其中，所述中间端口为所述功分器中所述功分器的输入端口和所述功分器的输出端口之间的功分单元的输入端口和功分单元的输出端口中的至少之一。
  10. 一种功率分配方法，包括：利用如权利要求1至5中任一项所述的功分器进行功率分配。
  11. 一种计算机可读的存储介质，存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求6至9中任一项所述的调节方法。
  12. 一种电子装置，包括存储器和处理器，其中，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行所述权利要求6至9中任一项所述的调节方法。
PCT/CN2020/118315 2019-09-30 2020-09-28 功分器、调节方法、功率分配方法、存储介质及电子装置 WO2021063302A1 (zh)

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