WO2021051924A1 - 发光二极管封装组件 - Google Patents

发光二极管封装组件 Download PDF

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Publication number
WO2021051924A1
WO2021051924A1 PCT/CN2020/098502 CN2020098502W WO2021051924A1 WO 2021051924 A1 WO2021051924 A1 WO 2021051924A1 CN 2020098502 W CN2020098502 W CN 2020098502W WO 2021051924 A1 WO2021051924 A1 WO 2021051924A1
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WO
WIPO (PCT)
Prior art keywords
light
layer
package assembly
emitting diode
diode package
Prior art date
Application number
PCT/CN2020/098502
Other languages
English (en)
French (fr)
Inventor
辛舒宁
林振端
廖燕秋
时军朋
曹爱华
余长治
徐宸科
廖启维
李佳恩
吴政
Original Assignee
泉州三安半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201921554474.5U external-priority patent/CN210403768U/zh
Priority claimed from CN201921554475.XU external-priority patent/CN210403726U/zh
Priority claimed from CN202020278177.9U external-priority patent/CN211743151U/zh
Application filed by 泉州三安半导体科技有限公司 filed Critical 泉州三安半导体科技有限公司
Priority to KR1020217021342A priority Critical patent/KR20210096270A/ko
Priority to JP2021542363A priority patent/JP2022536436A/ja
Priority to EP20866760.0A priority patent/EP4033547A4/en
Publication of WO2021051924A1 publication Critical patent/WO2021051924A1/zh
Priority to US17/691,638 priority patent/US20220199592A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention relates to packaging components, in particular to a light-emitting diode packaging component, and a light-emitting device including the light-emitting diode packaging component.
  • LED Light-emitting diode
  • PDA Personal Digital Assistant
  • Reducing the size of the LED device can increase the resolution of the display, thereby expanding the application areas of the LED display, such as mobile phones, car panels, TVs, computers, video conferences, etc.
  • the package sizes of mainstream display screens are 2121 and 1010. With the development of technology, 0808 or even smaller package sizes have appeared on the market.
  • An object of the present invention is to provide a light emitting diode (LED) package assembly with an ultra-fine pitch.
  • the LED package assembly includes a plurality of pixel regions PX arranged in an m ⁇ n matrix, where m and n are integers greater than 1, and each pixel region PX may be referred to as a pixel.
  • the LED package assembly includes: a plurality of light emitting units arranged in an m ⁇ n matrix, where m and n are integers and m ⁇ n ⁇ 4, and each light emitting unit includes a first LED chip, A second LED chip and a third LED chip; each LED chip includes an opposite first surface, a second surface, a side surface connected between the first surface and the second surface, and is formed on An electrode group on the second surface, the electrode group includes a first electrode and a second electrode, the first surface is a light-emitting surface; an encapsulation layer, filling the gap between the LED chips, and covering the LED The sidewall of the chip; the wiring layer is formed on the second surface of the plurality of LED chips.
  • the LED chips of each light-emitting unit are arranged in a row according to the first direction, and the first and second electrodes of each LED chip are arranged in parallel according to the second direction.
  • the first electrode of the first, second, and third LED chips of two or more light-emitting units that are adjacent to each other in parallel from the third direction of the wiring layer is connected in parallel from the fourth direction.
  • the packaging component does not have a packaging substrate for carrying the LED chip, and the LED chip is fixed in position by the packaging layer.
  • the distance D1 between adjacent light-emitting units is preferably 0.8 mm or less, where N can be an integer greater than 4, such as 4, 6. , 8, 9, 16, 32, or 64, etc., when the value of N is larger, the value of D1 is smaller.
  • N can be 4-9
  • D1 can be 0.4-0.8
  • N when N is more than 8 , Then D can be 0.1 ⁇ 0.4.
  • the package assembly further includes pads for external connection, and the number P of the pads is n + m ⁇ a, where a is the number of LED chips in each light-emitting unit, where n ⁇ m.
  • the LED package assembly includes: a plurality of light emitting units arranged in an m ⁇ n matrix, where m and n are integers and m ⁇ n ⁇ 2, and each light emitting unit includes a first LED chip, A second LED chip and a third LED chip; each LED chip includes an opposite first surface, a second surface, a side surface connected between the first surface and the second surface, and is formed on An electrode group on the second surface, the electrode group includes a first electrode and a second electrode, the first surface is a light-emitting surface, each LED chip of each light-emitting unit is arranged in a row according to a first direction, each The first and second electrodes of the LED chip are arranged side by side in the second direction, and the positions of the first electrode and the second electrode of the LED chips in two adjacent columns are opposite; the encapsulation layer fills the gap between the LED chips and covers The sidewall of the LED chip; the wiring layer is formed on the second surface of the plurality of LED chips, and the plurality of light-e
  • the wiring layer connects the first electrodes of the first, second, and third LED chips of two or more adjacent light-emitting units in parallel from the first direction, and connects the two adjacent first electrodes in parallel from the second direction.
  • the second electrodes of the first, second and third LED chips of one or more light-emitting units are electrically connected to form an all-in-one light-emitting module.
  • the effect of the present invention is: the present invention adopts a substrate-less packaging form, the LED chips of a plurality of light-emitting units are fixed by the packaging layer, and a multilayer wiring layer is formed on the back of the multi-layer light-emitting unit to connect the LEDs of the multiple light-emitting units in series and parallel. Chips, where the first wiring layer connects LED chips in multiple pixel areas in series and parallel, and rewiring through the via layer and the second wiring layer to form an integrated thin and small-pitch light-emitting diode package assembly.
  • the number of external pads of the package can be reduced, thereby reducing the difficulty of application-side patching, and at the same time improving the reliability of the product; furthermore, the number of wiring layers is not more than not high.
  • the thickness of the product can be guaranteed to be lighter and thin, which is beneficial to the lighter and thinner of the end product.
  • Another object of the present invention is to provide a highly reliable small-pitch light-emitting diode package assembly.
  • the light-emitting diode package assembly includes: a plurality of LED chips spaced apart from each other, each LED chip includes a first surface, a second surface opposite to each other, a side surface connected between the first surface and the second surface, and formed on the An electrode group on the second surface, the electrode group including a first electrode and a second electrode, the first surface is a light-emitting surface; an encapsulation layer, filling the gap between the LED chips, and covering the The side wall of the LED chip exposes the first electrode and the second electrode of the LED chip; the wiring layer is formed on the second surface of the LED chip.
  • the wiring layer includes multiple layers of conductive lines, wherein the first layer of conductive lines is connected to the electrode group of the LED chip, and the minimum line width W of each layer of lines and the thickness T of the layer have the following relationship: W ⁇ T ⁇ 2W.
  • the packaging assembly does not have a packaging substrate for carrying the LED chip, and the LED chip is fixed in position by the packaging layer, and the wiring layer and the packaging layer provide sufficient physical support Therefore, the design of the thickness T and the minimum line width W of the conductive lines of each layer of the wiring layer directly determines the reliability of the package assembly.
  • the size of the package components and the spacing between the chips determine the minimum line width W of the conductive lines.
  • the minimum line width W of each layer of conductive lines is not exactly the same. Therefore, by designing the minimum line width W of each layer of lines and the layer
  • the relationship of the thickness T is W ⁇ T ⁇ 2W. On the one hand, it can meet the requirement of the overall package circuit thickness and provide sufficient mechanical strength for the device. On the other hand, it can take into account the exposure of the conductive circuit and the yield of thick electrode coating.
  • the thickness of each layer of the multilayer conductive circuit is different.
  • the thickness of at least one layer of the multilayer conductive circuit is 50 ⁇ m or less, and the thickness of at least one layer is 60 ⁇ m or more.
  • the melting point of the multilayer conductive circuit is above 400°C.
  • the multilayer conductive circuit can be made of a metal element with good conductivity, such as Ag, Cu, Ni, Al and other materials.
  • the aforementioned metal materials can form metal bonds with the electrodes of the LED chip through processes such as electroplating, electroless plating, and printing.
  • At least one surface of the multilayer conductive circuit has a protective layer.
  • the protective layer one is a very thin material with good stability at high temperatures, preferably a material with resistance to electromigration, corrosion and oxidation, and the thickness of the protective layer is 50 to 200 nm.
  • the minimum line width W of each layer of the multilayer conductive circuit is 10 ⁇ m or more, for example, it may be 10-60 ⁇ m.
  • the encapsulation layer adopts a colored material layer, and its light transmittance is preferably not higher than 30%. It fills the gaps between the plurality of LED chips and covers the sidewalls of the LED chips, which can prevent the LED chips from being disturbed. Optical interference between. Further, a transparent or semi-transparent light-transmitting layer can be formed on the light-emitting surface of the multiple LED chips, which can protect the light-emitting surface of the LED chip on the one hand, and can be used as a light-scattering transparent layer on the other hand to produce a light-scattering effect. When the final LED package assembly is applied to a display panel, it can effectively reduce the dazzling sensation.
  • the light-transmitting layer may include light-dispersing materials, such as scattering particles.
  • the transmittance of the light-transmitting layer can be adjusted according to different needs, so as to achieve the best display effect.
  • a translucent material can be selected as the light-transmitting layer, and its transmittance is preferably between 40% and 80%, which can further reduce the sense of vertigo; when applied to outdoor display, select the transmittance Preferably, it is a transparent layer of 70% or more.
  • the thickness of the light-transmitting layer is preferably 20 ⁇ m or less, more preferably 10 ⁇ m or less, such as 10 ⁇ m, and the light emitting surface of each LED chip is basically at the same height (height difference is less than 10 ⁇ m), so that the package assembly greatly increases the number of pixels. In the area, it is beneficial to unify the light-emitting surface and reduce the influence of light crosstalk between the side walls.
  • the packaging component further includes an insulating layer formed on the packaging layer and covering one or more conductive lines of the wiring layer.
  • the insulating layer includes one or more layers, wherein the hardness of at least one layer is greater than the hardness of the conductive circuit.
  • the plurality of LED chips form a plurality of light-emitting units arranged in an m ⁇ n matrix to form an N-in-one light-emitting module, where n and m are integers greater than 1, and each light-emitting unit includes a first One LED chip, one second LED chip and one third LED chip, and the distance between each light-emitting unit is less than 1 mm.
  • the distance D1 between adjacent light-emitting units is more preferably 0.8mm or less, where N can be an integer greater than 4, such as 4, 6, 8, 9, 16, 32, or 64.
  • N can be an integer greater than 4, such as 4, 6, 8, 9, 16, 32, or 64.
  • the package assembly further includes pads for external connection, and the number P of the pads is n + m ⁇ a, where a is the number of LED chips in each light-emitting unit, where n ⁇ m.
  • Fig. 1 is a perspective view illustrating the structure of a light emitting diode (LED) package assembly according to an embodiment of the present invention
  • FIG. 2 is a schematic side sectional view illustrating the structure of an LED package assembly according to an embodiment of the present invention
  • FIG. 3 is a schematic top view illustrating the arrangement of the LED chips of the LED package assembly of an embodiment of the present invention
  • FIG. 4 is a schematic side sectional view illustrating that the LED chip of the LED package assembly of this embodiment is a conventional LED chip
  • FIG. 5 is a schematic side sectional view illustrating the LED chip bonding method of the LED package assembly of this embodiment
  • Fig. 6 is a schematic side sectional view illustrating the first wiring layer of the LED package assembly of this embodiment
  • FIG. 7 is a schematic top view illustrating the first wiring layer of the LED package assembly of this embodiment.
  • FIG. 8 is a schematic side sectional view illustrating the through hole layer of the LED package assembly of this embodiment.
  • FIG. 9 is a schematic top view illustrating the through hole layer of the light emitting diode package assembly of the present invention.
  • FIG. 10 is a schematic side sectional view illustrating the second wiring layer of the LED package assembly of this embodiment.
  • FIG. 11 is a schematic top view illustrating the second wiring layer of the LED package assembly of this embodiment.
  • FIG. 12 is a schematic top view illustrating the first wiring layer, the via layer and the second wiring layer of the LED package assembly of this embodiment
  • FIG. 13 is a circuit diagram illustrating the circuit connection of the LED package assembly of this embodiment.
  • FIG. 14 is a schematic top view illustrating the arrangement of LED chips and the first wiring layer of the LED package assembly of an embodiment of the present invention
  • 15 is a schematic top view illustrating the second wiring layer of the LED package assembly of the embodiment of the present invention.
  • 16 is a schematic top view illustrating the first wiring layer, the via layer and the second wiring layer of the LED package assembly of this embodiment of the present invention.
  • FIG. 17 is a circuit diagram illustrating the circuit connection of the LED package assembly of this embodiment.
  • FIG. 18 is a schematic diagram of circuit connection, illustrating the wiring connection of the LED package assembly of another embodiment of the present invention.
  • 19 is a schematic diagram of circuit connection, illustrating the wiring connection of the LED package assembly according to another embodiment of the present invention.
  • FIG. 20 is a schematic top view illustrating the first wiring layer of the LED package assembly according to still another embodiment of the present invention.
  • 21 is a schematic top view illustrating the second wiring layer of the LED package assembly of the embodiment of the present invention.
  • 22 is a schematic top view illustrating the third wiring layer of the LED package assembly of the embodiment of the present invention.
  • FIG. 23 is a schematic side sectional view illustrating the structure of an LED package assembly according to an embodiment of the present invention.
  • FIG. 24 is a schematic side sectional view illustrating the structure of the LED package assembly of an embodiment of the present invention.
  • FIG. 25 is a schematic side sectional view illustrating the structure of the LED package assembly according to an embodiment of the present invention.
  • FIG. 2 which is an embodiment of a light emitting diode (LED) packaging component of the present invention, which is a substrate-less LED packaging component, and the LED packaging component may include multiple arrays arranged in an m ⁇ n matrix.
  • Light-emitting units where m and n are integers greater than 1.
  • Each light-emitting unit includes several LED chips 100 with different wavelengths.
  • the chip (including the wavelength conversion layer) forms an RGBW combination, which can improve the brightness of the display screen, which is very beneficial for outdoor display.
  • Each light-emitting unit is equivalent to a pixel area PX, which can also be called a pixel.
  • the LED package assembly includes 2 ⁇ 2 pixel regions.
  • Each pixel area PX has a plurality of LED chips 100 spaced apart from each other and having a light-emitting surface S21, the package assembly further includes an encapsulation layer 200 that fixes and fills the gaps between the plurality of LED chips 100, and is located on the encapsulation layer
  • the multilayer wiring layer includes a first wiring layer 310, a via layer 320, and a second wiring layer 330, and each layer is electrically isolated by the insulating layer 500.
  • the first wiring layer 310 is formed on the lower surface of the plurality of LED chips to connect a plurality of LED chips in parallel and/or in series.
  • the via layer 320 is formed on the first wiring layer 310 and is connected to the The first wiring layer 310 forms an electrical connection; the second wiring layer 330 is formed on the via layer 320 and forms an electrical connection with the via layer 320.
  • Figure 3 simply illustrates the arrangement of the LED chips of the package assembly.
  • the package assembly has four pixel regions PX1 to PX4, and each pixel region PX includes a plurality of LED chips 100, such as a first LED chip 100L1, a second LED chip 100L2, and a third LED chip 100L3.
  • each pixel area may also include only two LED chips or more than three LED chips, for example, four LED chips.
  • the three LED chips 100L1, 100L2, and 100L3 can emit light of different wavelengths, for example, can emit red light, green light, and blue light, respectively.
  • each of the above-mentioned LED chips 100L1-100L3 has a pair of electrodes 110 on the same side, and has a first surface S21 and a second surface S22 opposite to each other. And a side surface S24 connecting the first surface S21, the second surface S22, and the electrode surface S23.
  • the first surface S21 is a light-emitting surface S21
  • the second surface S22 is provided with the pair of electrodes 110.
  • the LED chip includes a substrate 101, a first type semiconductor layer 121, a light emitting layer 122, and a second type semiconductor layer 123.
  • the first type semiconductor layer 121 and the second type semiconductor layer 123 may be a p-type semiconductor layer and an n-type semiconductor layer, respectively.
  • the LED chip also includes a transparent substrate 101 disposed on the first type semiconductor layer 121.
  • the electrode group 110 of the LED chip includes a first electrode 111 electrically connected to the first type semiconductor layer 121 and a second electrode 112 electrically connected to the second type semiconductor layer 123.
  • the electrode group 110 of each LED chip may further include a thickened layer made of conductive material. The thickened layers are respectively disposed between the first electrode 111 and the first wiring layer and between the second electrode 112 and the first wiring layer 310, and can be formed by electroplating, electroless plating, or printing.
  • the material is It can be Cu, Cu x W or other conductive metal materials.
  • the thickness of the electrode is 5 to 200 ⁇ m, for example, it can be 5 ⁇ m to 30 ⁇ m, 30 ⁇ m to 50 ⁇ m, or 80 ⁇ m to 120 ⁇ m, depending on specific requirements.
  • the LED chip 100 can be a conventional-sized LED chip (generally refers to a chip with a single side size exceeding 200 ⁇ m), a Mini LED chip (generally refers to a chip size between 100 and 200 ⁇ m), or a Micro LED chip (generally refers to a chip The size does not exceed 100 ⁇ m), this embodiment is preferably a Mini LED chip or a micro LED chip.
  • the first, second, and third chips LED-100L1 to 100-L3 in each pixel area PX in the package assembly are arranged in a "one" shape, specifically each LED of each light-emitting unit
  • the chips are arranged in a row in a first direction, and the first and second electrodes of each LED chip are arranged side by side in a second direction, wherein the first and second directions are substantially vertical.
  • the first electrode 111 and the second electrode 112 are arranged on the left and right, and the electrode polarities of the LED chips in two adjacent columns are opposite, that is, the chip electrodes in the adjacent columns are symmetrical, which can facilitate wiring arrangement, thereby Reduce the spacing between chips.
  • the electrode polarities of the three LED chips 100L1 to 100L3 in the first pixel area PX1 are opposite to the electrode polarities of the three LED chips 100L1 to L3 in the second pixel area PX2.
  • Each pixel area is regarded as one pixel, and the dot pitch D1 of each pixel is preferably 1 mm, more preferably, 0.8 mm or less, for example, it may be 0.1 to 0.3 mm, 0.3 to 0.5 mm, or 0.5 to 0.8 mm.
  • the spacing D2 between the chips in the same pixel area PX is preferably 100 ⁇ m or less, for example, 50-100 ⁇ m, or less than 50 ⁇ m.
  • the distance between LED chips in the same pixel area is preferably 50 ⁇ m.
  • the periphery of the plurality of first, second, and third LED chips 100L1 ⁇ L3 is filled with the first packaging layer 200.
  • the light transmittance of the packaging layer 200 is less than 30%; more preferably, The light transmittance of the encapsulation layer 200 is 5%-20%; optionally, the encapsulation layer 200 is opaque and opaque, and specifically includes a light-absorbing component (not shown in the figure), and the light-absorbing component is at least arranged on the sidewall of the LED chip Around or between adjacent LED chips, or further at least around the LED semiconductor light-emitting stack or adjacent semiconductor light-emitting stacks.
  • the light-absorbing component may specifically be light-absorbing particles dispersed in epoxy resin or silica gel used in the encapsulation layer, such as black particles, carbon powder, or the light-absorbing component is black resin.
  • the light absorption component of the encapsulation layer 200 is arranged at least around the LED side wall to prevent the side of the LED chip from emitting light, thereby realizing that the light output of the LED chip is mainly concentrated on the light emitting surface of the LED chip or all concentrated on the light emitting surface of the LED chip, reducing different LEDs.
  • the encapsulation layer 200 may be epoxy resin or silica gel with black colorant added, so that the entire LED encapsulation assembly is black except for the light-emitting surface S21 of the LED chip 100, which helps to enhance the display panel. At the same time, the LED chips 100 are isolated by the black packaging material, which can reduce the optical interference between the LED chips.
  • the hardness of the encapsulation layer 200 is preferably D60 or higher, more preferably D85 or higher.
  • a transparent or semi-transparent material layer can be formed on the packaging layer 200 as another packaging layer 400 to cover the first surface S21 of the plurality of first, second, and third LED chips, so that the LED chips can be avoided exposed.
  • the packaging layer 400 can be used as a light scattering lens to produce a light scattering effect. When the final LED packaging component is applied to a display panel, it can effectively reduce the vertigo.
  • the packaging layer 400 shown can include a light scattering material, such as scattering Particles.
  • the thickness of the encapsulation layer 400 is preferably between 5-20 ⁇ m, such as 10 ⁇ m.
  • the light-emitting surface of the LED chip can be protected, and on the other hand, the encapsulation layer 200 made of light-absorbing material can reduce the optical interference between the LED chips.
  • the light transmittance is preferably 40% or more.
  • the LED packaging component is applied to indoor displays.
  • the packaging layer 400 is preferably a semi-transparent layer, and its light transmittance is preferably 40% to 80%, more preferably 70 to 80%, which can reduce the LED The brightness of the chip, thereby reducing the dizziness of the light.
  • the packaging component is applied to outdoor displays.
  • the packaging layer 400 is preferably a transparent layer, and its light transmittance is preferably above 80%.
  • the plurality of first, second, and third LED chips 100L1 to L3 may first use the light-emitting surface S21 of the LED chip 100 as the bonding surface, and temporarily adhere to a support 800 such as tape. At this time, the electrode surface S23 faces upward, and then the fluid insulating material is filled between the chips and cured as the encapsulation layer 200, and the electrode surface S23 of the LED chip is exposed, as shown in FIG. 5. In this embodiment, it is preferable to control the thickness of the adhesive material 810 of the tape 800 to 5-20 ⁇ m.
  • the first surface S21 of the chips 100L1 ⁇ L3 is basically on the same horizontal plane, and the height difference is basically kept below 10 ⁇ m, so that when the package assembly greatly increases the pixel area, it is beneficial to unify the light emitting surface and reduce the light crosstalk between the side walls. influences.
  • the wiring layer is formed on the second surface of the plurality of LED chips 100 and includes multiple conductive circuits.
  • the multilayer conductive circuit specifically includes a first wiring layer 310, a via layer 320, and a second wiring layer 330.
  • the first wiring layer 310 is connected to the electrode 110 of the LED chip, and the via layer 320 is formed On the first wiring layer 310, the second wiring layer 330 is formed on the via layer 320 and is electrically connected to the first wiring layer 310 through the via layer 320.
  • the multilayer conductive circuit preferably uses metal materials with a melting point higher than 400°C, such as Ag, Cu, Ni, Al, etc.
  • the materials of each layer can be the same or different, and can be formed by electroplating, electroless plating, or printing processes.
  • each layer is preferably 100 ⁇ m or less, and may be, for example, 20 to 80 ⁇ m.
  • the LED package assembly does not have a package substrate for carrying the LED chip.
  • the LED chip 100 is fixed in position by the package layer 200, and the wiring layer 300 and the package layer provide sufficient physical support.
  • the wiring layer 300 needs to have a sufficient thickness for providing mechanical strength. By increasing the thickness of any layer of conductive lines, the mechanical strength of the wiring layer can be increased. However, considering the need for exposure of the lines and the yield of thick electrode coatings, the thickness of each layer of conductive lines should not be large enough.
  • the relationship between the thickness T of each layer of the conductive line of the wiring layer and the minimum line width W of the layer of the conductive line can be set to ensure the reliability of the wiring layer.
  • the minimum line width W depends on the size of the package component and the spacing between the chips, which is preferably not less than 30 ⁇ m.
  • the minimum line width W of each layer of circuit design and the thickness T of the layer are related to W ⁇ T ⁇ 2W.
  • the thickness of a conductive line is not less than the minimum line width of the layer, which can satisfy that the layered line 300 has sufficient thickness to provide mechanical strength for the device.
  • the first wiring layer 310 is formed on the surface of the packaging layer 200 and is electrically connected to the electrodes 110 of the plurality of LED chips.
  • the gap between the lines of the first wiring layer 310 is filled with an insulating layer 510, and the surface S310 of the first wiring layer 310 away from the LED chip is exposed.
  • the material of the insulating layer 510 may be the same as or different from the material of the encapsulation layer 200. When the same material is used, the insulating layer 510 and the encapsulation layer 200 are combined into one layer, which is difficult to distinguish.
  • the LED package assembly is applied to a display device, and the insulating layer 510 and the encapsulation layer 200 are epoxy resin or silica gel with coloring agent added.
  • the hardness of the insulating layer 510 is not lower than the hardness of the first wiring layer 310, for example, D60 or more, more preferably, D85 or more, so that it is convenient to expose the surface S310 of the first wiring layer 310 by grinding.
  • the first wiring layer 310 includes a plurality of first wirings and at least two common wirings, thereby electrically connecting the LED chips in the multi-point pixel area PX to form an n-in-one pixel area.
  • FIG. 7 shows an example of a four-in-one package, that is, LED chips in four pixel areas are connected in series and parallel. In other embodiments, it is not limited to the four-in-one structure, and can also be nine-in-one, sixteen-in-one, and so on.
  • the first wiring layer 310 includes two common wirings 314a, 314d and ten first wirings. The first wirings 311a to 311d are respectively connected to the first chip 100- of each pixel area PX.
  • the first electrode 111 of L1, the wiring 313a ⁇ 313d are respectively connected to the first electrode 111 of the third chip 100-L3 of each PX, the wiring 312a is connected to the first electrode of the second LED chip 100-L2 of PX1 and PX4, the wiring 312b is connected to the first electrode of the second LED chip 100-L2 of PX2 and PX3, the common wiring 314a is connected to the second electrode 112 of the first, second, and third LED chips of PX1 and PX2, and the common wiring 314d is connected to PX3 and PX4 The second electrode 112 of the first, second, and third LED chips.
  • the thickness T310 of the first wiring layer 310 is preferably 1 to 2 times the minimum line width W1 of the first wiring layer, preferably 1.2 to 1.8 times.
  • the through hole layer 320 is located on the surface S310 of the first wiring layer 310 to form a series of through holes 320 in an insulating layer 520.
  • the number and positions of the through holes correspond to each of the first wiring layer.
  • the material of the insulating layer 520 can refer to the insulating layer 510.
  • the thickness T320 of the through hole layer 320 is preferably 100 ⁇ m or less, preferably 1 to 2 times the minimum line width W2 of the through hole layer, for example, 1 to 1.2 times, or 1.2 to 1.5 times can be selected according to different requirements, or 1.5 ⁇ 2 times.
  • the diameter of the through hole of the layer is the minimum line width W2 of the layer, and the diameter of the through hole is preferably 20-60 ⁇ m.
  • the package component has a relatively thin structure.
  • the through-hole layer is preferably 20-50 ⁇ m, for example, 25-30 ⁇ m. This can prevent the through-hole layer from being too thick and the stress is too large, and the thermal resistance Too large, while ensuring the strength of the package structure, makes the total thickness of the package structure thinner, and ultimately makes the application product lighter and thinner.
  • the thickness of the via layer is 50-80 ⁇ m, for example, 60 ⁇ m, so as to appropriately increase the thickness of the package component to facilitate picking up from the sidewall of the device.
  • the second wiring layer 330 is located on the via layer 320, and is electrically connected to the first wiring layer 310 through the through holes of the via layer 320.
  • the gap is filled with an insulating layer 530, and the surface S330 of the second wiring layer 330 away from the LED chip is exposed.
  • the material of the insulating layer 530 can be designed with reference to the insulating layer 510.
  • the circuit of the third wiring layer 330 includes a plurality of wires 331ac, 331bd, 333ac, 333bd and a plurality of connecting portions 331a, 331b, 332a, 332b, 333c, 333d, 334a, and 334d.
  • the wire 331ac is connected to the first electrode 111 of the first LED chip 100-L1 of PX1 and PX3
  • the wire 333ac is connected to the third LED chip 100 of PX1 and PX3.
  • the connecting part can be used as an external electrode pad for connecting to a power source.
  • the pad 600 may be fabricated in the area corresponding to the connecting portion, and the area outside the pad may be covered with ink, epoxy resin or other insulating materials to protect the lines of the second wiring layer 330.
  • the connecting portion of the second wiring layer 330 completely covers each through hole of the through hole layer, which increases the contact area between the second wiring layer and the through hole.
  • the through hole layer and The second wiring layer can form conductive materials in the same process at the same time, saving a process of forming conductive materials and grinding, which can effectively save costs and improve product stability.
  • the thickness T330 of the third wiring layer 330 is preferably 1 to 2 times the minimum line width W3 of the third wiring layer, preferably 1.2 to 1.8 times.
  • the insulating layers 510 to 530 can be made of the same material or different materials.
  • the specific material can be epoxy resin, silica gel, polyimide, benzocyclobutene, or PBO.
  • the insulating layers 510-530 are combined into a layer 500, which is difficult to distinguish.
  • the insulating layers 510-530 are made of opaque or low-transmittance materials, such as epoxy resin or silica gel mixed with black colorants, which can prevent or reduce the light emitted by the LED chip from exiting from the rewiring layer. , Causing crosstalk.
  • the metal pattern pattern in the wiring layer can be formed first, then the insulating layer is filled, and finally the surface of the metal circuit in the wiring layer is exposed by grinding.
  • the insulating layers 510 to 530 may be partially or entirely light-transmitting materials, so the transmittance is higher than that of the encapsulation layer 200. rate.
  • the light-transmitting layer does not need to add colorants or light-absorbing materials, such as carbon powder or dyes.
  • a photosensitive material is used for curing to form an insulating layer, which can simplify the process.
  • the periphery of the chip and the non-metallic part of the electrode surface are covered with a light-absorbing material as the encapsulation layer 200 to prevent crosstalk of light on the chip side.
  • FIG. 12 shows the connection relationship of the three wiring layers
  • FIG. 13 is an equivalent circuit diagram of the four-in-one light-emitting unit.
  • the four-in-one light-emitting unit is output by eight connecting parts 331a, 331b, 332a, 332b, 333c, 333d, 334a, and 334d.
  • the first electrode of the first LED chip 100-L1 is output by the connecting parts 331a, 331b.
  • the first electrode of the second LED chip 100-L2 is output by the connection parts 332a, 332b
  • the first electrode of the third LED chip 100-L3 is output by the connection parts 333c, 333d
  • the connection parts 334a and 334d are used as common electrodes, respectively connected to PX1 ⁇
  • the LED chips in each PX are arranged in a shape of "one". Specifically, the LED chips of each light-emitting unit are arranged in a row in the first direction, and each LED chip The first and second electrodes are arranged side by side in the second direction, where the first and second directions are substantially vertical, and the electrodes of the two adjacent columns of LED chips have opposite polarities.
  • the first wiring layer 310 there are two adjacent PXs on the left and right.
  • the common pole of the LED chip is connected to a common pole, and the two PX second LED chips 100-L2 (located in the middle of the three chips) adjacent to each other are connected in parallel (that is, the first electrodes of the second LED chips of PX1 and PX3) In parallel, the first electrodes of the second LED chips of PX1 and PX4 are connected in parallel), the first LED chip 100-L1 and the third LED chip 100-L3 of PX1 ⁇ PX4 are separately leaded, so that the four-in-one light-emitting unit
  • the number of electrode terminals is reduced to 10; in the second wiring layer, the first and second LED chips of two PX adjacent to each other are connected in parallel respectively (that is, the first electrodes of the first LED chips of PX1 and PX3 are connected in parallel
  • An electrode terminal 331a is formed.
  • the first electrodes of the first LED chip of PX2 and PX4 are connected in parallel to form an electrode terminal 331b.
  • the first electrodes of the third LED chip of PX1 and PX3 are connected in parallel to form an electrode terminal 334c.
  • the first electrode of the LED chip is connected in parallel to form an electrode terminal 334d), and a total of 8 electrode terminals (that is, 8 connection parts) are output, which effectively reduces the number of electrode pads of the package assembly, thereby bringing convenience to the patch.
  • the packaging assembly according to the above example embodiments does not have a packaging substrate or a support for carrying the LED chips, and the light-emitting units arranged in an m ⁇ n matrix are mainly fixed by insulating material layers (including 200, 400, and 500) and wiring layers And support, the thickness T of the package component mainly depends on the thickness T A of the LED chip and the thickness T C of the wiring layer.
  • a mini-type LED chip is used, the chip thickness TA is between 40 ⁇ 150 ⁇ m, the thickness TC of the multilayer wiring layer is between 30 ⁇ 200 ⁇ m, more preferably the thickness TC of the wiring layer is between 50 ⁇ 150 ⁇ m ,
  • the T and TA satisfy the relational expression: 1.4 ⁇ T/TA ⁇ 10, which can prevent the circuit layer from being too thick, stress, and thermal resistance too large. While ensuring the strength of the package structure, the total thickness of the package assembly is reduced. thin.
  • the thickness TA of the LED chip is about 80 ⁇ m, and the package component may have a thickness of 120 ⁇ m to 500 ⁇ m, such as 120 to 200 ⁇ m.
  • the thickness of each wiring layer sublayer may be 10 to 50 ⁇ m, with a ratio of 40 ⁇ m.
  • the thickness T of the package component can be appropriately increased. , So that the sidewall of the package component has a larger area for the gripping device to contact and grab.
  • the thickness of the package component can be 150 ⁇ 500 ⁇ m, for example, 180 ⁇ 360 ⁇ m, which can be achieved by increasing the thickness of the LED chip and/ Or the thickness of the wiring layer to increase the thickness of the package assembly, for example, the electrode thickness of the LED chip can be increased, and the thickness of each wiring layer can be appropriately increased.
  • the thickness of the via layer is preferably 30 ⁇ 80 ⁇ m, and the thickness of other wiring layers is preferably It is 50 ⁇ 100 ⁇ m.
  • a micro-type LED chip is used, the chip thickness TA is between 5-10 ⁇ m, and the thickness TC of the multilayer wiring layer is between 20 and 200 ⁇ m. More preferably, the thickness TC of the wiring layer is between 50 and 150 ⁇ m.
  • the T and TA satisfy the relationship: 10 ⁇ T/TA ⁇ 60, for example, the thickness of the package component may be 50-100 ⁇ m, or 100-200 ⁇ m.
  • Figures 14-17 show another embodiment of the LED package assembly of the present invention. Please refer to FIG. 14.
  • the package assembly also includes a plurality of pixel regions PX1 to PX4 arranged in an m ⁇ n matrix.
  • the difference from the package assembly shown in FIG. 3 is that the LED chip electrode direction of each pixel region is the same. It is helpful to improve the efficiency and accuracy of chip arrangement.
  • the first wiring layer includes first wirings 311a, 313c and common wirings 314a, 314d, where 311a connects the first LED chips 100-L1 of two adjacent pixel regions PX1 and PX2, and 313c connects
  • 311a connects the first LED chips 100-L1 of two adjacent pixel regions PX1 and PX2
  • 313c connects
  • the third LED chips 100-L3 of the two horizontally adjacent pixel regions PX3 and PX4, 314a are commonly connected to all the LED chips of the vertically adjacent pixel regions PX1 and PX4, and 314d is commonly connected to the vertically adjacent pixel regions All LED chips of PX2 and PX3.
  • the second wiring layer includes connecting portions 331a, 331c, 332b, 332c, 333b, 333c, 334a, 334d and wiring 331cd, 332ab, 332cd, 333ab, where 331cd connects horizontally adjacent pixel regions
  • the first LED chips 100-L1, 332ab of PX3 and PX4 are connected to the second LED chips 100-L2 of laterally adjacent pixel regions PX1 and PX2, and 332ab is connected to the second LED chips 100- of laterally adjacent pixel regions PX1 and PX2.
  • FIG. 17 shows the equivalent circuit diagram of the four-in-one package assembly, where 334a and 334d are connected vertically to the same All the LED chips of the light-emitting units of the column, 331a, 331c, 332b, 332c, 333b, and 333c, are respectively connected to the same type of LED chips of the light-emitting units located in the same row from the lateral direction.
  • Fig. 18 is another embodiment of the LED package assembly of the present invention.
  • the LED device also includes four pixel regions PX1 to PX4, arranged in a 2 ⁇ 2 matrix, each pixel region corresponds to a light-emitting unit, and the LED chips in each pixel region are arranged in the same electrode direction.
  • the first wiring layer 330 includes conductive lines 314a and 314b, which respectively connect the second electrodes 112 of all LED chips in the same column, and the second wiring layer includes The conductive lines 331a ⁇ 333a, 331b ⁇ 333b are respectively connected to the first electrodes 111 of the same type of LED chips in the same row.
  • the line 331a is connected to the first electrodes 111-L1 of the first type of LED chips in the first row.
  • the line 332a is connected to the first electrode 111-L2 of the second type of LED chip in the first row, and the line 331b is connected to the first electrode 111-L1 of the first type of LED chip in the second row.
  • the insulating layer between the first wiring layer and the second wiring layer is isolated and electrically connected through the via layer. The route connection mode of the first wiring layer and the second wiring layer can be reversed.
  • Fig. 19 is another embodiment of the LED package assembly of the present invention.
  • the LED device also includes four pixel areas PX1 to PX4, arranged in a 4 ⁇ 1 matrix.
  • the LED packaging component is rectangular or approximately rectangular, which is convenient for assembly when applied to a display device, and the minimum number of external pads can be achieved through wiring design.
  • the first wiring layer includes lines 314a to 314d, which respectively connect the second electrodes of the respective light-emitting units in the pixel regions PX1 to PX4 in parallel from the vertical direction, and form four external electrode terminals;
  • the second wiring layer includes 331a to 333a , Respectively connect the same first, second and third LED chips in the pixel regions PX1 to PX4, and form three external electrode terminals, so that the pixel regions PX1 to PX4 can form a four-in-one light emitting module.
  • the number of pads can reduce the size of the package assembly, and at the same time facilitate wiring, facilitate the application of the patch, and reduce the risk of short circuit.
  • Figures 20-22 are still another embodiment of the LED package assembly of the present invention.
  • Figure 20 shows the arrangement of the LED chips of the LED package assembly and the first wiring layer.
  • the LED device also includes 16 pixel areas PX1 to PX4 arranged in a 4 ⁇ 4 matrix.
  • the distance D1 between each light-emitting unit is preferably 0.1-0.5 mm, for example, it may be 0.2-0.5 mm.
  • the LED chips of each light-emitting unit are arranged in a row according to the first direction, and the first and second electrodes of each LED chip are arranged side by side according to the second direction. Upward, connect the second electrodes of all the LED chips in the same column in parallel.
  • the first wiring layer includes common wirings 314a to 314d, which are respectively commonly connected to the second electrodes of the LED chips of the Nx1 to Nx4 columns of light-emitting units.
  • the first wiring includes 311 to 313, of which 311 is connected to the Nx2 and Nx3 columns.
  • the first electrode of the first LED chip L1 in the same row, 312 is connected to the first electrode of the second LED chip L2 in the same row in the Nx2 and Nx3 columns, and the 313 is connected to the third LED in the same row in the Nx2 and Nx3 columns
  • the first line further includes lines 311a to 313a, which are respectively connected to the first electrodes of the first, second, and third LED chips in the Nx1 and Nx4th rows.
  • FIG. 21 shows the pattern of the via layer, which has a series of vias.
  • the via 324 is connected to the common wiring 314a ⁇ d of the first wiring layer, and the vias 321 to 323 are respectively connected to the first circuit of the first wiring layer. .
  • Figure 22 shows the pattern of the second wiring layer, which includes wires 331 to 333 and connecting portions 331a to 333, 334.
  • the wire 331 is connected in parallel to the first electrode of the first LED chip in the same row, and the wire 332 is located in parallel in The first electrode of the second LED chip in the same row (for example, rows N Y1 ⁇ N Y4 ), the connection 333 is connected in parallel to the first electrode of the third LED chip in the same row, and the connection part is used as an external connection terminal, of which 331a ⁇ 333a are Connect with lines 331 ⁇ 333, 334 and 324 respectively.
  • a pad can be made in the area corresponding to the connecting portion, and the area outside the pad can be covered with ink, epoxy resin or other insulating materials to protect the lines of the second wiring layer.
  • the wiring of the wiring layer can be simplified, and the reliability of the product can be improved at the same time; furthermore, the number of wiring layers is no more than no more than Four groups (including the external pad layer) can ensure the thickness of the product is light and thin, which is conducive to the lightness and thinness of the end product.
  • Figure 23 shows a substrate-less LED package assembly. Different from the package assembly shown in FIG. 2, the package layer 200 simultaneously covers the side wall of the LED chip and the side wall S311 of the first wiring layer 310.
  • the encapsulation layer 200 is preferably opaque or low in light transmission, for example, the light transmittance is less than 30%, for example, 5 to 20%, and more preferably, the encapsulation layer is made of black material, such as epoxy resin or silica gel with black coloring agent. .
  • the insulating layers 520 and 530 can be made of light-transmissive or opaque materials.
  • the LED package assembly of the present invention uses the package layer to fix and package the pixel points arranged in a matrix, and design a multilayer wiring layer to connect the LED chips of each pixel in series. Therefore, the present invention does not require wire bonding and precise wiring circuit boards, which improves reliability and contrast.
  • the electrode assembly of the LED chip does not need to be soldered to the circuit board with solder paste, which avoids the problem of poor chip soldering, and can improve the integration of the LED and the electronic components, so it can indeed achieve the purpose of the invention.
  • Fig. 24 is a structure of an LED package assembly according to another embodiment of the present invention.
  • a metal protective layer 700 is formed on the surface of one or more of the conductive lines of the wiring layer.
  • the thickness of the protective layer is 20 ⁇ 500nm, and its material can be selected from titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo ), cobalt (Co) and platinum (Pt), etc.
  • Fig. 25 is a structure of an LED package assembly according to still another embodiment of the present invention.
  • the protective layer 700 simultaneously covers the surface and the sidewall of the conductive circuit.
  • the protective layer can not only better protect the conductive lines, but also increase the adhesion between the layered wires and the insulating layer 500.

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Abstract

一种发光二极管LED封装组件，该LED封装组件，包含：以m×n矩阵布置的多个发光单元，其中m，n为整数且m×n≥4，每个该发光单元包括一第一LED芯片，一第二LED芯片和一第三LED芯片；每一LED芯片（100）包含相反的一第一表面、一第二表面、一连接于该第一表面和该第二表面之间的侧表面，及形成于所述第二表面上的一电极组（110），该电极组（110）包括第一电极（111）及第二电极（112），所述第一表面为出光面；封装层（200），填充所述LED芯片（100）之间的间隙，并覆盖所述LED芯片（100）的侧壁；布线层，形成于所述多个LED芯片（100）的第二表面之上。

Description

发光二极管封装组件
相关申请：优先权：中国实用新型专利申请号201921554474.5，标题为“发光二极管封装组件”，于2019年9月18日提交；中国实用新型专利申请号201921554475.X，标题为“发光二极管封装组件”，于2019年9月18日提交；以及中国实用新型专利申请号202020278177.9，标题为“发光二极管封装组件”，于2020年3月9日提交，上述申请的全部内容通过引用结合在本申请中。
技术领域
本发明系关于封装组件，特别是指一种发光二极管封装组件，及包含发光二极管封装组件的发光装置。
 背景技术
发光二极管（LED）是当今最热门的光源技术之一，可用于照明装置的光源，而且也用于各种电子产品的光源，如被广泛地用作于诸如TV、蜂窝电话、PC、笔记本PC、个人数字助理(PDA)等的各种显示设备的光源。缩小LED装置的尺寸可以提升显示的分辨率，从而扩大LED显示屏的应用领域，如手机，车载面板，电视，计算机，视频会议等。目前主流显示屏采用的封装尺寸为2121和1010，随着技术的发展，市场上已经出现0808甚至更小的封装尺寸。
 技术解决方案
本发明的一个目的在于：提供一种超小间距的发光二极管（light emitting diode，LED）封装组件。该LED封装组件包含以m×n矩阵布置的多个像素区域PX，其中m和n是大于1的整数，每个像素区域PX可以被称为像素。
在一些实施例中，该LED封装组件，包含：以m×n矩阵布置的多个发光单元，其中m ，n为整数且m×n≥4，每个该发光单元包括一第一LED芯片，一第二LED芯片和一第三LED芯片；每一LED芯片包含相反的一第一表面、一第二表面、一连接于该第一表面和该第二表面之间的侧表面，及形成于所述第二表面上的一电极组，该电极组包括第一电极及第二电极，所述第一表面为出光面；封装层，填充所述LED芯片之间的间隙，并覆盖所述LED芯片的侧壁；布线层，形成于所述多个LED芯片的第二表面之上。
在一些实施例中，每个发光单元的各个LED芯片按照第一方向排成一列，每个LED芯片的第一、第二电极按照第二方向并列布置。
在一些实施例中，所述布线层从第三方向并联相邻的两个或者多个发光单元的第一、第二和第三LED芯片的第一电极，从第四方向并联相邻的两个或者多个发光单元的第一、第二和第三LED芯片的第二电极，从而将该多个发光单元电连接形成一多合一的发光模块，其中第三方向第一方向相同，第四方向与第二方向相同，或者第三方向与第二方向相同，第四方向与第一方向相同。
在一些实施例中，该封装组件不具有用于承载所述LED芯片的封装基板，所述LED芯片由所述封装层固定位置。
进一步的，该具有N合一的发光模块的封装组件，其中N=m×n，相邻发光单元之间的间距D1优选为0.8mm以下，其中N可以取4以上的整数，例如4、6、8、9、16、32或者64等，当N的取值越大，而D1的取值越小，例如当N为4~9时，D1可以为0.4~0.8，当N为8以上时，则D可以为0.1~0.4。
在一些实施例中，该封装组件还包括用于外接的焊盘，所述焊盘的数量P为n + m × a，其中a为每个所述发光单元的LED芯片的数量，其中n ≥ m。通过如此设计，可以尽可能的减少封装组件的焊盘数量，一方面方便进行布线，另一方面利于应用端的贴片，降低短路的风险。
在一些实施例中，该LED封装组件，包含：以m×n矩阵布置的多个发光单元，其中m，n为整数且m×n≥2，每个该发光单元包括一第一LED芯片，一第二LED芯片和一第三LED芯片；每一LED芯片包含相反的一第一表面、一第二表面、一连接于该第一表面和该第二表面之间的侧表面，及形成于所述第二表面上的一电极组，该电极组包括第一电极及第二电极，所述第一表面为出光面，每个发光单元的各个LED芯片按照第一方向排成一列，每个LED芯片的第一、第二电极按照第二方向并列布置，相邻两列的LED芯片的第一电极和第二电极的位置相反；封装层，填充所述LED芯片之间的间隙，并覆盖所述LED芯片的侧壁；布线层，形成于所述多个LED芯片的第二表面之上，将该多个发光单元电连接形成一多合一的发光模块。
在一些实施例中，所述布线层从第一方向并联相邻的两个或者多个发光单元的第一、第二和第三LED芯片的第一电极，从第二方向并联相邻的两个或者多个发光单元的第一、第二和第三LED芯片的第二电极，从而将该多个发光单元电连接形成一多合一的发光模块。
本发明之功效在于：本发明采用无基板的封装形式，由封装层固定多个发光单元的LED芯片，并在该多层发光单元的背面形成多层布线层串并联该多个发光单元的LED芯片，其中第一布线层将多个像素区域的LED芯片进行串、并联，并透过通孔层和第二布线层，进行重新布线，形成集成式的薄型小间距的发光二极管封装组件，其次通过合理的布线层设计，一方面可以减少封装组件的外接焊盘的数量，从而降低了应用端的贴片难度，同时提高了产品的可靠性；再者使得布线层的层数不多于不高于四组，可以保证产品的厚度轻薄化，有利于终端产品的轻薄化。
本发明的再一个目的在于提供一种高可靠性的小间距发光二极管封装组件。
所述发光二极管封装组件包括：彼此间隔的多个LED芯片，每一LED芯片包含相反的第一表面、第二表面、连接该第一表面和该第二表面之间的侧面，及形成于所述第二表面上的一电极组，该电极组包括一第一电极及一第二电极，所述第一表面为出光面；封装层，填充所述LED芯片之间的间隙，并覆盖所述LED芯片的侧壁，裸露出所述LED芯片的第一电极和第二电极；布线层，形成在所述LED芯片的第二表面之上。
所述布线层包括多层导电线路，其中第一层导电线路与所述LED芯片的电极组连接，每层线路的最小线宽W和该层的厚度T的关系如下：W≤T≤2W。
在上述发光二极管封装组件，该封装组件不具有用于承载所述LED芯片的封装基板，所述LED芯片由所述封装层固定位置，并由所述布线层和封装层提供足够强度的物理支撑，因此所述布线层的各层导电线路的厚度T及最小线宽W的设计直接决定该封装组件的可靠性。其中封装组件的尺寸及芯片之间的间距决定了导电线路的最小线宽W，通常每层导电线路的最小线宽W不完全一样，因此通过设计每层线路的最小线宽W和该层的厚度T的关系为W≤T≤2W，一方面可以满足整体封装要求线路厚度，为器件提供足够的机械强度，另一方面兼顾导电线路的曝光和厚电极镀膜的良率。
优选地，所述多层导电线路的各层的厚度不一样。在一些实施例中，该多层导电线路的至少一层的厚度为50μm以下，至少一层的厚度为60μm以上。
优选地，所述多层导电线路的熔点为400℃以上。较佳的，该多层导电线路可以采用导电性好的金属单质，如Ag，Cu，Ni，Al等材料。在一些实施，前述金属材料可以通过电镀、化镀、印刷等工艺和LED芯片的电极形成金属键结。
在一些实施例中，所述多层导电线路的至少一层表面具有保护层。该保护层一为很薄且高温下稳定性好的材料，优选采用具有抗电迁移、抗腐蚀和氧化的材料，所述保护层的厚度为50~200nm。
优选地，所述多层导电线路的各层最小线宽W为10μm以上，例如可以为10~60μm。
在一些实施例中，所述封装层采用有色材料层，其透光率优选不高于30%，填充于该多个LED芯片之间的间隙并覆盖LED芯片的侧壁，可以防止LED芯片之间的光学干扰。进一步地，可以在该多个LED芯片的出光面形成一透明或者半透明的透光层，一方面可以保护LED芯片的出光面，另一方面可以作为一个光散射透层，产生光散射效果，最终LED封装组件运用于显示面板时，可有效降低眩晕感，进一步的所述透光层中可以包括有光散色材料，如散射颗粒。可以根据不同的需求调整透光层的透射率，从而达到最佳显示效果。例如应用于户内显示时，可以选择半透明的材料作为透光层，其透射率优选为40%~80%之间，此时可以进一步降低眩晕感；应用于户外显示时，可以选择透射率优选为70%以上的透明层。该透光层的厚度优选为20μm以下，更佳的为10μm以下，例如10μm，并配合各个LED芯片的出光面基本位于同一高度（高低差为10μm以下），使得该封装组件在大幅度增加像素区域时，有利于统一出光面，减少侧壁之间的光串扰的影响。
进一步地，该封装组件还包括绝缘层，形成于所述封装层之上，并覆盖所述布线层的一层或者多层的导电线路。优选地，所述绝缘层包括一层或者多层，其中至少一层的硬度大于所述导电线路的硬度。
在一些实施例，所述多个LED芯片组成以m×n矩阵布置的多个发光单元构成一N合一的发光模块，其中n，m为大于1 的整数，每个该发光单元包括一第一LED芯片，一第二LED芯片和一第三LED芯片，每个发光单元之间的间距为1mm以下。相邻发光单元之间的间距D1更优选为0.8mm以下，其中N可以取4以上的整数，例如4、6、8、9、16、32或者64等，当N的取值越大，而D1的取值越小，例如当N为4~9时，D1可以为0.4~0.8，当N为8以上时，则D可以为0.1~0.4。
进一步地，该封装组件还包括用于外接的焊盘，所述焊盘的数量P为n + m × a，其中a为每个所述发光单元的LED芯片的数量，其中n ≥ m。通过如此设计，可以尽可能的减少封装组件的焊盘数量，一方面方便进行布线，使得封装组件的厚度轻薄化，另一方面利于应用端的贴片，同时提高了产品的可靠性。
 有益效果
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
 附图说明
本发明之其他的特征及功效，将于参照图式的实施方式中清楚地呈现，其中：
图1是一个立体图，说明本发明的一个实施例的发光二极管（LED）封装组件的结构；
图2是一个侧面剖视示意图，说明本发明的一个实施例的LED封装组件的结构；
图3是一个俯视示意图，说明本发明的一个实施例的LED封装组件的LED芯片的布置方式；
图4是一个侧面剖视示意图，说明该实施例的LED封装组件的LED芯片是一种常规的LED芯片；
图5是一个侧面剖视示意图，说明该实施例的LED封装组件的LED芯片固晶方式；
图6是一个侧面剖视示意图，说明该实施例的LED封装组件的第一布线层；
图7是一个俯视示意图，说明该实施例的LED封装组件的第一布线层；
图8是一个侧面剖视示意图，说明该实施例的LED封装组件的通孔层；
图9是一个俯视示意图，说明本发明发光二极管封装组件的通孔层；
图10是一个侧面剖视示意图，说明该实施例的LED封装组件的第二布线层；
图11是一个俯视示意图，说明该实施例的LED封装组件的第二布线层；
图12是一个俯视示意图，说明该实施例的LED封装组件的第一布线层、通孔层和第二布线层；
图13是一个电路图，说明该实施例的LED封装组件的电路连接；
图14是一个俯视示意图，说明本发明的一个实施例的LED封装组件的LED芯片布置及第一布线层；
图15是一个俯视示意图，说明本发明的该实施例的LED封装组件的第二布线层；
图16是一个俯视示意图，说明本发明的该实施例的LED封装组件的第一布线层、通孔层和第二布线层；
图17是一个电路图，说明该实施例的LED封装组件的电路连接；
图18是一个电路连接示意图，说明本发明的再一个实施例的LED封装组件的布线连接；
图19是一个电路连接示意图，说明本发明的再一个实施例的LED封装组件的布线连接；
图20是一个俯视示意图，说明本发明的再一个实施例的LED封装组件的第一布线层；
图21是一个俯视示意图，说明本发明的该实施例的LED封装组件的第二布线层；
图22是一个俯视示意图，说明本发明的该实施例的LED封装组件的第三布线层；
图23是一个侧面剖视示意图，说明本发明的一个实施例的LED封装组件的结构；
图24是一个侧面剖视示意图，说明本发明的一个实施例的LED封装组件的结构；
图25是一个侧面剖视示意图，说明本发明的一个实施例的LED封装组件的结构。
 本发明的实施方式
在本发明被详细描述之前，应当注意在以下的说明内容中，类似的组件是以相同的编号来表示。
参阅图1和图2，为本发明发光二极管（light emitting diode，LED）封装组件的一个实施例，为一种无基板的LED封装组件，该LED封装组件可以包含以m×n矩阵布置的多个发光单元，其中m和n是大于1的整数。每个发光单元包括若干个不同波长的LED芯片100，优选地，比如至少三颗LED芯片分别发射红光（R）、绿光（G）、蓝光（B），还可以是包括发出白光的LED芯片（含波长转换层），即形成RGBW组合，如此可以提升显屏的亮度，对于户外显示非常有利。每个发光单元相当于一个像素区域PX，也可以被称为像素。在一个具体实施例中，该LED封装组件包含2×2个像素区域。每个像素区域PX具有多个彼此间隔且具有一出光面S21的LED芯片100，该封装组件还包括固定并填充多个LED芯片100之间的间隙的封装层200、及位于该封装层之上的多层布线层。该多层布线层包含第一布线层310、通孔层320和第二布线层330，每层之间借助绝缘层500进行电性隔离。其中第一布线层310形成于所述多个LED芯片的下表面之上，连接并联和/或串联多个LED芯片，该通孔层320形成于所述第一布线层310之上，与所述第一布线层310形成电性连接；第二布线层330形成于所述通孔层320之上，与所述通孔层320形成电性连接。
图3简单示意了该封装组件的LED芯片排列方式。参阅图3，该封装组件具有四个像素区域PX1~PX4，每个像素区域PX包含多个LED芯片100，例如第一LED芯片100L1、第二LED芯片100L2和第三LED芯片100L3。在另一些实施例中，每个像素区域也可仅包括两个LED 芯片或者三个以上的LED芯片，例如四个LED芯片。该三个LED芯片100L1、100L2和100L3可以发射不同波长的光，例如可以分别发射红光、绿光和蓝光。
再配合参阅图4为其中一个上述的LED芯片100L1~100L3，每一个上述LED芯片100L1~100L3具有一对位于同侧的电极110，具有相反的一第一表面S21、和一第二表面S22，以及一连接该第一表面S21、该第二表面S22的一侧表面S24及电极表面S23。其中，该第一表面S21为出光面S21，该第二表面S22上设置有该一对电极110。进一步的，该LED芯片包括一衬底101、第一类型半导体层121、一发光层122和一第二类型半导体层123。该第一类型半导体层121和该第二类型半导体层123可分别为p型半导体层和n型半导体层。该LED芯片还包括一设置于该第一类型半导体层121上的透明基板101。该LED芯片的电极组110包括与该第一类型半导体层121电性连接的第一电极111，及一与该第二类型半导体层123电性连接的第二电极112。在另一些实施例中，每一LED芯片的电极组110还可以包括由导电材料构成的加厚层。该等加厚层分别设置于该第一电极111与第一布线层之间及该第二电极112与该第一布线层310之间，可以通过电镀、化镀或者印刷等方式形成，其材料可以是Cu、Cu xW或者其他导电金属材料。通过增加电极的厚度，可以增加所述LED芯片的侧面S24与该封装层200接触的面积，从而增加所述LED芯片与该封装层200之间的黏着力。较佳地，每一LED芯片的电极组厚度为5~200μm，例如可以为5μm~30μm，30μm~50μm，或80μm~120μm，根据具体需求进行选择。所述LED芯片100可以是常规尺寸的LED芯片（一般指芯片单边尺寸超过200μm），也可以是Mini LED芯片（一般指芯片尺寸介于100~200μm），或是Micro LED芯片（一般指芯片尺寸不超过100μm），本实施例优选Mini LED芯片或者micro LED芯片。
再参阅图3，该封装组件内的每个像素区域PX内的第一、第二和第三芯片LED-100L1 ~100-L3呈“一”字型排列，具体为每个发光单元的各个LED芯片按照第一方向排成一列，每个LED芯片的第一、第二电极按照第二方向并列布置，其中第一、第二方向基本垂直。在本实施例中，第一电极111、第二电极112呈左、右布置，相邻两列LED芯片的电极极性相反，即相邻列的芯片电极呈对称性，可以便于布线设置，从而缩小芯片之间的间距。以图3所示封装组件以例，第一个像素区域PX1的三个LED芯片100L1~100L3的电极极性与第二个像素区域PX2的三个LED芯片100L1~L3的电极极性相反。每个像素区域视为一个像素，则每个像素的点间距D1优选为1mm，更佳地，为0.8mm以下，例如可以为0.1~0.3mm，0.3~0.5mm，或者0.5~0.8mm。同一个像素区域PX内的芯片之间的间距D2优选为100μm以下，例如可以为50~100μm，或者50μm以下，在一些显示面板的应用中，同一像素区域的LED芯片之间的间距优选为50μm以下，例如40~50μm，或者30~40μm，或者20~30μm，或者10~20μm。间距越小，越有利于缩小该LED封装组件的尺寸，从而提升显示面板的分辨率。
再参阅图2，该多个第一、第二、第三LED芯片100L1~L3的周边填充第一封装层200，较佳地，该封装层200的透光率小于30%；更佳地，该封装层200的透光率为5%~20%；可选择地，该封装层200不透光且不透明，具体的包括吸光成分（图中未示意），吸光成分至少设置在LED芯片侧壁周围或者相邻的LED芯片之间，或进一步的至少在LED半导体发光叠层周围或者相邻半导体发光叠层周围。吸光成分具体可以是封装层使用的环氧树脂或硅胶内分散的吸光颗粒，如黑色颗粒、碳粉，或者所述的吸光成分为黑色树脂。该封装层200的吸光成分设置至少在LED侧壁周围可以防止LED芯片的侧面出光，由此实现LED芯片的出光主要集中在LED芯片的出光面或全部集中在LED芯片的出光面，减少不同LED芯片之间的光在侧面方向的串光或混光现象。在一个具体实施例中，该封装层200可为加入黑色着色剂的环氧树脂或硅胶，如此整个LED封装组件除了LED芯片100的出光面S21，其余区域均为黑色，有助于提升显示面板的对比度，同时各个LED芯片100之间通过该黑色封装材料进行隔离，可以减少各个LED芯片之间的光学干扰。在一些实施例中，该封装层200的硬度优选为D60以上，更佳的为D85以上。
进一步的，在封装层200上可以形成透明或者半透明的材料层作为另一封装层400，覆盖该多个第一、第二、第三LED芯片的第一表面S21，如此可以避免了LED芯片裸露。该封装层400可以作为一个光散射透镜，产生光散射效果，最终LED封装组件运用于显示面板时，可有效降低眩晕感，进一步的所示封装层400中可以包括有光散色材料，如散射颗粒。该封装层400的厚度优选为介于5~20μm，例如10μm，如此一方面可以保护LED芯片的出光表面，另一方面配合采用吸光材料的封装层200，可以减少各个LED芯片之间的光学干扰。优选透光率为优选40%以上。在一些实施例中，该LED封装组件应用于室内显示，此时该封装层400优选为半透明层，其透光率优选为40%~80%，更佳为70~80%，可以降低LED芯片的亮度，从而降低出光的眩晕效果。在一些实施例中，该封装组件应用于户外显示，此时该封装层400优选为透明层，其透光率优选为80%以上。
在本实施例中，该多个第一、第二、第三LED芯片100L1~L3可以先以LED芯片100的出光面S21作为固晶面，临时性地粘附于一诸如胶带的支撑体800上，此时电极面S23朝上，然后在芯片间填充流动性绝缘材料并固化作为封装层200，裸露出LED芯片的电极面S23，如图5所示。在本实施例中，优选控制胶带800的胶材810厚度为5~20μm，一方面可以保证LED芯片不会在填充封装层时发生位移，另一方面可以确保第一、第二、第三LED芯片100L1~L3的第一表面S21基本位于同一水平面，其高度差基本保持在10μm以下，使得该封装组件在大幅度增加像素区域时，有利于统一出光面，减少侧壁之间的光串扰的影响。
布线层形成于该多个LED芯片100的第二表面之上，包括多层导电线路。在本实施例中，该多层导电线路具体包含了第一布线层310、通孔层320和第二布线层330，其中第一布线层310与LED芯片的电极110连接，通孔层320形成于该第一布线层310上，第二布线层330形成在通孔层320上，并通过通孔层320电连接至第一布线层310。该多层导电线路优选选用熔点高于400℃的金属材料，例如Ag，Cu，Ni，Al等，各层的材料可以相同，也可以不同，可以采用电镀、化镀或者印刷等工艺形成。每一层的厚度优选为100μm以下，例如可以为20~80μm。在本实施例中，该LED封装组件不具有用于承载所述LED芯片的封装基板，LED芯片100由封装层200固定位置，并由布线层300和封装层提供足够强度的物理支撑，因此该布线层300需要具有足够的厚度用于提供机械强度。通过增加任一层导电线路的厚度可以增加该布线层的机械强度，但是考虑线路需曝光和厚电极镀膜的良率，因此每一层导电线路的厚度不宜够大。在本实施例中，可以通过设定布线层的各层导电线路的厚度T与该层导电线路的最小线宽W的关系，从而保证该布线层的可靠性。其中最小线宽W取决于封装组件的尺寸及芯片之间的间距，其优选不低于30μm，设计每层线路的最小线宽W和该层的厚度T的关系为W≤T≤2W，每一导电线路的厚度不低于该层的最小线宽，可以满足该布层线300具有足够的厚度为器件提供机械强度，同时要求任一层导电线路的厚度T≤2W，使得任一层导电线路不会因厚度过大而导致良率下降。
请参看图6，第一布线层310形成在封装层200的表面上，并与该多个LED芯片的电极110形成电性连接。在第一布线层310的线路之间的间隙内填充有绝缘层510，裸露出第一布线层310之远离LED芯片的表面S310。该绝缘层510的材料可以与封装层200的材料相同，也可以不同。当采用相同的材料所构成时，该绝缘层510与封装层200合为一层体，较难于进行区分，例如在一个实施例中，该LED封装组件应用于显示装置，绝缘层510与封装层200均为添加着色剂的环氧树脂或硅胶。优选地，该绝缘层510的硬度不低于第一布线层310的硬度，例如为D60以上，更佳的，为D85以上，如此方便采用研磨的方式裸露出第一布线层310的表面S310。
第一布线层310包括多个第一布线和至少两个公共布线，从而将多点像素区域PX内的LED芯片进行电性连接，构成一个n合一的像素区域。请参看图7，该图示范例为一四合一的封装组件，即四个像素区域的LED芯片进行串并联。在其他实施例中，并不局限于四合一的结构，也可以是九合一、十六合一等。在图7所示的封装组件，该第一布线层310包括两个公共布线314a、314d和十个第一布线，其中第一布线311a~311d分别连接到各个像素区域PX的第一芯片100-L1的第一电极111，布线313a~313d分别连接到各PX的第三芯片100-L3的第一电极111，布线312a连接到PX1和PX4的第二LED芯片100-L2的第一电极，布线312b连接到PX2和PX3的第二LED芯片100-L2的第一电极，公共布线314a连接PX1和PX2的第一、第二、第三LED芯片的第二电极112，公共布线314d连接PX3和PX4的第一、第二、第三LED芯片的第二电极112。该第一布线层310的厚度T310优先为该第一布线层的最小线宽W1的1~2倍，较佳为1.2~1.8倍。
请参阅图8和9，通孔层320位于第一布线层310的表面S310上，为在一绝缘层520形成一系列的通孔320，通孔的数量和位置对应于第一布线层的各个布线，其中图9的实斜线填充的图案即为通孔，其尽可能的远离各个LED芯片。其中绝缘层520的材料可以参考绝缘层510。该通孔层320的厚度T320优选为100μm以下，以优先为该通孔层的最小线宽W2的1~2倍，例如可以根据不同的需求选择1~1.2倍，或者1.2~1.5倍，或者1.5~2倍，在本实施例中，该层的通孔直径为该层的最小线宽W2，该通孔的直径优选为20~60μm。在一些实施例中，该封装组件为较薄结构，此时该通孔层的较佳的为20~50μm，例如可以为25~30μm，如此可以避免通孔层太厚应力过大，热阻过大，在保证封装结构体强度的同时，使得封装结构体的总厚度减薄，最终使得应用产品更轻薄。在另一些实施例中，该通孔层的厚度为50~80μm，例如60μm，从而适当增加封装组件的厚度，从而方便从器件的侧壁进行拾取。
请参阅图10，第二布线层330位于通孔层320上，并通过通孔层320的各个通孔与第一布线层310形成电连接，在该第三布线层330的各个线路之间的间隙内填充有绝缘层530，并裸露出第二布线层330之远离LED芯片的表面S330。绝缘层530的材料可以参考绝缘层510进行设计。
请参阅图11，第三布线层330的线路包括了多个连线331ac、331bd、333ac、333bd和多个连接部331a、331b、332a、332b、333c、333d 、334a和334d，其中连线用于连接相同类型的LED芯片的相同极性电极，例如连线331ac连接了PX1和PX3的第一LED芯片100-L1的第一电极111，连线333ac连接了PX1和PX3的第三LED芯片100-L3的第一电极111，连接部可作为外接电极焊盘，用于连接电源。在一个较佳实施例中，可以在连接部对应区域制作焊盘600，并在焊盘外的区域覆盖油墨、或者环氧树脂或者其他绝缘性材料，保护第二布线层330的线路。在一个较佳实施例中，该第二布线层330的连接部完全覆盖通孔层的各个通孔，增加了第二布线层与通孔的接触面积，同时在工艺流程中，通孔层和第二布线层可以同时在同一道工艺形成导电材料，节省了一道形成导电材料及研磨的工艺，可以有效节省成本，并提高产品稳定性。该第三布线层330的厚度T330优先为该第三布线层的最小线宽W3的1~2倍，较佳为1.2~1.8倍。
绝缘层510~530可以选用相同的材料，也可以选用不同的材料，具体材料可以为环氧树脂、硅胶、聚酰亚胺、苯并环丁烯或者PBO。当以相同的材料构成时，该绝缘层510-530合为一层体500，较难于进行区分。在一些具体实施例中，绝缘层510~530选用不透光或者低透射率的材料，例如掺有黑色着色剂的环氧树脂或硅胶，可以防止或减少LED芯片发出的光线从重新布线层射出，造成串扰。采用不透光或者低透光的材料作为绝缘层时，可以先形成布线层中的金属线图图案，然后再填充绝缘层，最后采用磨研的方式裸露出布线层中的金属线路的表面。在另一些实施例中，当封装层200采用低透光率或者不透光的材料时，绝缘层510~530可以部分或者全部为透光性材料，因此透射率高于封装层200的透光率。该透光层可以不用添加着色剂或者吸光材料，例如碳粉或者染料，较佳的为一硅胶或环氧树脂材料层，未含有微米级颗粒（通常是指颗粒的直径为1微米以上的颗粒，例如C粉颗粒），避免添加着色剂带来的可能的不均匀、界面等缺陷而导致可靠性下降（例如绝缘性能下降），可以保证绝缘层对布线层包覆的可靠性。在另一些实施例中，采用光敏型材料固化形成绝缘层，可以简化工艺，同时芯片周围以及电极面非金属部分覆盖有吸光材料作为封装层200，防止芯片侧光的串扰。
请参阅图12和13，其中图12显示了三层布线层的连接关系，图13为该四合一的发光单元的等效电路图。该四合一发光单元由331a、331b、332a、332b、333c、333d、334a和334d这八个连接部输出，其中第一LED芯片100-L1的第一电极由连接部331a、331b输出，第二LED芯片100-L2的第一电极由连接部332a、332b输出，第三LED芯片100-L3的第一电极由连接部333c、333d输出，连接部334a和334d作为公共极，分别连接了PX1~PX4的所有LED芯片的第二电极112。
在本实施例中，首先在LED芯片的布置上，每个PX内的LED芯片按“一”字形排列，具体为每个发光单元的各个LED芯片按照第一方向排成一列，每个LED芯片的第一、第二电极按照第二方向并列布置，其中第一、第二方向基本垂直，相邻两列LED芯片的电极极性相反，在第一布线层310中，左右两个相邻PX的LED芯片的公共极连接成一个公共极，上下相邻的两个PX的第二LED芯片100-L2(位于三颗芯片的中间)并联（即PX1和PX3的第二LED芯片的第一电极并联，PX1 和PX4的第二LED芯片的第一电极并联），PX1~PX4的第一LED芯片100-L1、第三LED芯片100-L3分别单独引线，如此将该四合一发光单元的的电极端子减少为10个；在第二布线层中，上下相邻的两个PX的第一、第二LED芯片分别再通过连线并联（即PX1和PX3的第一LED芯片的第一电极并联形成一个电极端子331a，PX2和PX4的第一LED芯片的第一电极并联形成一个电极端子331b，PX1和PX3的第三LED芯片的第一电极并联形成一个电极端子334c，PX2和PX4的第三LED芯片的第一电极并联形成一个电极端子334d），共输出8个电极端子（即8个连接部），如此有效缩减了该封装组件的电极焊盘的数量，从而为贴片带来便利。
根据以上示例实施例的封装组件不具有用于承载所述LED芯片的封装基板或者支架，该m×n矩阵布置的发光单元主要由绝缘材料层（包括200、400和500）及布线层进行固定和支撑，该封装组件的厚度T主要取决于LED芯片的厚度T A和布线层的厚度T C。在一些具体实施例中，采用mini型LED芯片，芯片厚度TA介于 40~150μm，多层布线层的厚度TC介于30~200μm，更优选地所述布线层的厚度TC介于50~150μm，所述T、TA满足关系式：1.4≤T/TA≤10，如此可以避免电路层太厚应力过大，热阻过大，在保证封装结构体强度的同时，使得封装组件的总厚度减薄。例如在一个实施例，LED芯片的厚度TA约为80μm，所述封装组件厚度可以为120μm~500μm，例如120~200μm，此时每个布线层的子层的厚度可以10~50μm，比例40μm。例如在另一个实施例，该封装组件的尺寸较小时（例如为0.4mm×0.4mm或者更小尺寸），不便于从封装组件的上表面进行抓取，此时可以适当增加封装组件的厚度T，使得封装组件的侧壁具有较大的面积供抓取设备接触并进行抓取，此时优选的，封装组件的厚度可以为150~500μm，例如180~360μm，可以通过增加LED芯片厚度和/或者布线层的厚度进而增加封装组件的厚度，例如可以增加LED芯片的电极厚度，并适当增加每个布线层的厚度，此时通孔层的厚度优选为30~80μm，其他布线层的厚度优选为50~100μm。在一些具体实施例中，采用micro型LED芯片，芯片厚度TA介于5~10μm，多层布线层的厚度TC介于20~200μm，更优选地所述布线层的厚度TC介于50~150μm，所述T、TA满足关系式：10≤T/TA≤60，例如封装组件的厚度可以为50~100μm，或者100~200μm。
图14~图17为本发明LED封装组件的另一个实施例。请参看附图14，该封装组件同样包括了以m×n矩阵布置的多个像素区域PX1~PX4，与图3所示封装组件不同的是，每个像素区域的LED芯片电极方向均相同，有利于提高芯片排列的效率及精度。在该实施例中，第一布线层包括了第一布线311a、313c和公共布线314a、314d，其中311a连接横向相邻的两个像素区域PX1和PX2的第一LED芯片100-L1，313c连接横向相邻的两个像素区域PX3和PX4的第三LED芯片100-L3，314a公共的连接到纵向相邻的像素区域PX1和PX4的所有LED芯片，314d公共的连接到纵向相邻的像素区域PX2和PX3的所有LED芯片。请参看附图15和16，第二布线层包括连接部331a、331c、332b、332c、333b、333c、334a、334d和连线331cd、332ab、332cd、333ab，其中331cd连接横向相邻的像素区域PX3和PX4的第一LED芯片100-L1，332ab连接横向相邻的像素区域PX1和PX2的第二LED芯片100-L2，332ab连接横向相邻的像素区域PX1和PX2的第二LED芯片100-L2，333cd横向相邻的像素区域PX3和PX4的第三LED芯片100-L3，图17显示了该四合一的封装组件的等效电路图，其中，334a和334d分别从纵向上连接到位于同一列的发光单元的所有LED芯片，331a、331c、332b、332c、333b、333c分别从横向上连接到位于同一行的发光单元的同一类型的LED芯片。
图18为本发明LED封装组件的再一个实施例。该LED器件同样包括了四个像素区域PX1~PX4，以2×2的矩阵布置，每个像素区域对应一个发光单元，每个像素区域的LED芯片按照相同的电极方向排列。与图14~17所示的LED封装组件不同的是，第一布线层330包括了导电路线314a和314b，其分别连接了位于同一列所有LED芯片的第二电极112，第二布线层包括了导电路线331a~333a、331b~333b，分别连接了位于同一行的相同类型的LED芯片的第一电极111，例如，线路331a连接了第一行的第一种LED芯片的第一电极111-L1，线路332a连接了第一行的第二种LED芯片的第一电极111-L2，线路331b连接了第二行的第一种LED芯片的第一电极111-L1。第一布线层与第二布线层之间绝缘层进行隔离，并通过通孔层进行电性连接。第一布线层和第二布线层的路线连接方式可以进行对调。
图19为本发明LED封装组件的再一个实施例。该LED器件同样包括了四个像素区域PX1~PX4，以4×1的矩阵布置。首先该LED封装组件呈长方形或近似长方形，应用于显示装置时方便进行组装，且通过布线设计可以实现最小的外接焊盘数量。具体的，第一布线层包括线路314a~314d，分别各自从纵向并联连接像素区域PX1~PX4的各个发光单元的第二电极，并形成四个外接电极端子；第二布线层包括了331a~333a，分别连接像素区域PX1~PX4相同的第一、第二和第三LED芯片，并形成三个外接电极端子，如此可以将该像素区域PX1~PX4形成一个四合一的发光模组。
在本实施例中，该四合一LED封装组件，变改发光单元的排列方式，采用4×1的方式，其外接焊盘的数量P=4+a，其中a为单个发光单元中的芯片数量，在一个具体实施例中，每个发光单元红光LED芯片100-L1、绿光LED芯片100-L2和蓝光LED芯片100-L3三个芯片，则仅需要7个焊盘，可以达到最小的焊盘数量，可以缩小封装组件的尺寸，同时有利于布线，便于应用端的贴片，降低短路的风险。
图20~22为本发明LED封装组件的再一个实施例。图20显示了该LED封装组件的LED芯片的排列方式及第一布线层，该LED器件同样包括了16个像素区域PX1~PX4，以4×4的矩阵布置。该16合一的LED封装组件，各个发光单元之间的间距D1优选为0.1~0.5 mm，例如可以为0.2~0.5mm。首先将每个发光单元的各个LED芯片按照第一方向排成一列，每个LED芯片的第一、第二电极按照第二方向并列布置，其中第一、第二方向基本垂直，在第一方向上，将位于同一列的所有的LED芯片的第二电极进行并联，在第二方向上，位于同一行的同一类型的LED芯片的第一电极并联，同时相邻列的LED芯片的第一电极和第二电极的位置相反，方便将位于同一行的相同LED芯片的第一电极进行并联，从而简化布线层的线路。具体的，第一布线层包括公共布线314a~314d，分别公共的连接到Nx1~Nx4列的发光单元的LED芯片的第二电极，第一线路包括311~313，其中311连接第Nx2和Nx3列位于同一行的第一LED芯片L1的第一电极，312连接第Nx2和第Nx3列位于同一行的第二LED芯片L2的第一电极，313连接第Nx2和Nx3列位于同一排的第三LED芯片L3的第一电极。第一线路还包括线路311a~313a，其分别与第Nx1和第Nx4行的第一、第二和第三LED芯片的第一电极连接。图21显示了通孔层的图案，具有一系列的孔通，其中通孔324与第一布线层的公共布线314a~d连接，通孔321~323分别与第一布线层的第一线路连接。图22显示了第二布线层的图案，包括了连线331~333和连接部331a~333、334，其中连线331并联位于同一行的第一LED芯片的第一电极，连线332并联位于同一行（例如N Y1~ N Y4行）的第二 LED芯片的第一电极，连线333并联位于同一行的第三LED芯片的第一电极，连接部作为外部连接端子，其中331a~333a为分别与连线331~333连接，334与324连接。在一个较佳实施例中，可以在连接部对应区域制作焊盘，并在焊盘外的区域覆盖油墨、或者环氧树脂或者其他绝缘性材料，保护第二布线层的线路。
在本实施例中，通过合理的LED芯片的排列及布线层设计，一方面可以简化布线层的线路连接，同时提高了产品的可靠性；再者使得布线层的层数不多于不高于四组（包括外接焊盘层），可以保证产品的厚度轻薄化，有利于终端产品的轻薄化。
图23为一种无基板的LED封装组件。与图2所示封装组件不同的是，封装层200同时覆盖了LED芯片的侧壁和第一布线层310的侧壁S311。其中封装层200优选不透光或者低透光，例如透光率低于30%，例如可以5~20%，更佳的，该封装层选用黑色材料，例如黑色着色剂的环氧树脂或硅胶。绝缘层520和530可以选用透光或者不透光的材料。
上所述，本发明LED封装组件利用该封装层固定并封装呈矩阵布置的像素点，并设计多层布线层进行串联各个像素的LED芯片。因此，本发明不需焊线及精密布线的电路板，提升了可靠性以及对比度。此外，所述LED芯片之电极组无需以锡膏焊接于该电路板，避免了芯片焊接不良的问题，并可改善LED与电子组件的整合性，故确实能达成本发明之目的。
图24是本发明的另一个实施例的LED封装组件的结构。与图2所示封装组件不同的是，在本实施例中，在布线层的其中一层或者多层导电线路的表面形成一金属保护层700，一方面可以防止导电线路的金属扩散，另一方面具有抗腐蚀和氧化的作用。优选的，该保护层的厚度为20~500nm，其材料可以选自钛（Ti）、氮化钛（TiN）、钨（W）、钽（Ta）、氮化钽（TaN）、钼（Mo）、钴（Co）和铂（Pt）等。
图25是本发明的再一个实施例的LED封装组件的结构。与图14所示封装组件不同的是，在本实施例所示的封装器件中，保护层700同时覆盖导电线路的表面及侧壁。在本实施例中，该保护层除了可以更好的保护导电线路，同时可以增加布层线与绝缘层500的粘附力。
惟以上所述者，仅为本发明之实施例而已，当不能以此限定本发明实施之范围，凡是依本发明申请专利范围及专利说明书内容所作之简单的等效变化与修饰，皆仍属本发明专利涵盖之范围内。

Claims (56)

  1. 一种发光二极管封装组件，其特征在于，包含：
    以m×n矩阵布置的多个发光单元，其中m，n为整数且m×n≥4，每个该发光单元包括一第一LED芯片，一第二LED芯片和一第三LED芯片；每一LED芯片包含相反的一第一表面、一第二表面、一连接于该第一表面和该第二表面之间的侧表面，及形成于所述第二表面上的一电极组，该电极组包括第一电极及第二电极，所述第一表面为出光面，每个发光单元的各个LED芯片按照第一方向排成一列，每个LED芯片的第一、第二电极按照第二方向并列布置；
    封装层，填充所述LED芯片之间的间隙，并覆盖所述LED芯片的侧壁；
    布线层，形成于所述多个LED芯片的第二表面之上，从第三方向并联相邻的两个或者多个发光单元的第一、第二和第三LED芯片的第一电极，从第四方向并联相邻的两个或者多个发光单元的第一、第二和第三LED芯片的第二电极，从而将该多个发光单元电连接形成一多合一的发光模块，其中第三方向第一方向相同，第四方向与第二方向相同，或者第三方向与第二方向相同，第四方向与第一方向相同。
  2. 根据权利要求1所述的发光二极管封装组件，其特征在于：相邻发光单元之间的间距为0.8mm以下。
  3. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述封装组件的总厚度为100~500μm之间。
  4. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述封装组件的总厚度介于120~200μm之间或者320~500μm之间。
  5. 根据权利要求1所述的发光二极管封装组件，其特征在于：定义所述LED芯片的厚度为T A，所述封装层的厚度为T B，所述封装组件的总厚度为T，则T、T A、T B满足关系式：T B/T A≥1，10≥T/T A≥1.4，120μm≥T A≥50μm。
  6. 根据权利要求1所述的发光二极管封装组件，其特征在于：定义所述LED芯片的厚度为T A，所述封装层的厚度为T B，所述封装组件的总厚度为T，则T、T A、T B满足关系式：T B/T A≥1，60≥T/T A≥10，10μm≥T A≥5μm。
  7. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述各组发光单元的多个LED芯片的第一表面的高度差为10μm以下。
  8. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述封装层为有色层，在所述发光单元的第一表面上覆盖有一透光层，其透射率大于所述封装层的透射率。
  9. 根据权利要求8所述的发光二极管封装组件，其特征在于：所述透光层的厚度为20 μm以下。
  10. 根据权利要求8所述的发光二极管封装组件，其特征在于：所述透光层的透光率为40~80%。
  11. 根据权利要求8所述的发光二极管封装组件，其特征在于：所述透光层的透光率为70以上。
  12. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述封装层的透光率为0~30%。
  13. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述发光单元相邻并排放置，其中第一个发光单元的多个LED芯片的第一电极邻近所述第二发光单元的多个LED芯片的第一电极。
  14. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述布线层包括第一布线层、通孔层和第二布线层，其中所述第一布线层形成于所述多个LED芯片的第二表面之上，连接所述多个LED芯片的第一电极和第二电极，所述通孔层形成于所述第一布线层之上，与所述第一布线层形成电性连接，所述第二布线层形成于所述通孔层之上，与所述通孔层形成电性连接。
  15. 根据权利要求14所述的发光二极管封装组件，其特征在于：所述第一布线层连接至位于同一行的两个或者多个发光相同类型的LED芯片的第一电极，第二布线层连接至位于同一列的两个或者多个发光单元的第一、第二和第三LED芯片的第二电极。
  16. 根据权利要求14所述的发光二极管封装组件，其特征在于：所述第一布线层包括公共布线和第一布线，所述公共布线公共连接到第二方向上相邻的两组发光单元的多个LED芯片；第一布线将第一方向上相邻的两组发光单元的第一LED芯片并联，所述第二布线层分别将第二方向上相邻的两组发光单元的第二、第三LED芯片并联。
  17. 根据权利要求14所述的发光二极管封装组件，其特征在于：所述第一布线层包括公共布线和第一布线，所述公共布线公共连接到第二方向上相邻的两组发光单元的多个LED芯片；所述多个发光单元分为两部分，第一布线分别并联第一部分的发光单元的第一LED芯片和第二部分的发光单元的第三LED芯片，所述第二将第一方向上相邻的两组发光单元的第一LED芯片并联，所述第二布线层分别并联第二方向上相邻的发光单元的相同类型的LED芯片，使得第一方向上相邻的发光单元的相同类型的LED芯片分别并联。
  18. 根据权利要求14所述的发光二极管封装组件，其特征在于：第二布线层包括连线和连接部，所述连线将不同发光单元的同一类型的LED芯片并联，所述连接部作为外部连接输入电极。
  19. 根据权利要求18所述的发光二极管封装组件，其特征在于：所述连接部的数量为n+m×a，其中a为每个所述发光单元的LED芯片的数量，其中n ≥ m。
  20. 根据权利要求14所述的发光二极管封装组件，其特征在于：所述通孔层的厚度为20 ~ 80μm。
  21. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述布线层包含多层彼此电性隔离的导电线路，该导电线路的层数为四层以下。
  22. 根据权利要求21所述的发光二极管封装组件，其特征在于：该多层导电线路的至少一层的厚度为50μm以下。
  23. 根据权利要求21所述的发光二极管封装组件，其特征在于：该多层导电线路的至少一层的厚度为60μm以上。
  24. 根据权利要求1所述的发光二极管封装组件，其特征在于：还包括形成于所述封装层的表面上的绝缘层，该绝缘层封覆盖所述布线层。
  25. 根据权利要求24所述的发光二极管封装组件，其特征在于：所述绝缘层包括一层或多层结构，其中至少一层的硬度大于所述布线层的硬度。
  26. 权利要求要求24所述的发光二极管封装组件，其特征在于：所述绝缘层包括一层或多层结构，其中至少一层的硬度为D60以上。
  27. 根据权利要求24所述的发光二极管封装组件，其特征在于：所述绝缘层包括一层或多层结构，其中至少一层与所述第一封装层采用相同的材料。
  28. 根据权利要求24所述的发光二极管封装组件，其特征在于：所述绝缘层为一层或者多层结构，其中至少一层由光敏材料固化而成。
  29. 根据权利要求1所述的发光二极管封装组件，其特征在于：所述绝缘层为包括一层或多层结构，其中至少一层为透明层。
  30. 根据权利要求1所述的发光二极管封装组件，其特征在于：还包括焊盘，所述焊盘的数量P为n+m×a，其中a为每个所述发光单元的 LED芯片的数量，其中n ≥ m。
  31. 一种发光二极管封装组件，其特征在于，包含：
    以m×n矩阵布置的多个发光单元，其中m，n为整数且m×n≥2，每个该发光单元包括一第一LED芯片，一第二LED芯片和一第三LED芯片；每一LED芯片包含相反的一第一表面、一第二表面、一连接于该第一表面和该第二表面之间的侧表面，及形成于所述第二表面上的一电极组，该电极组包括第一电极及第二电极，所述第一表面为出光面，每个发光单元的各个LED芯片按照第一方向排成一列，每个LED芯片的第一、第二电极按照第二方向并列布置，相邻两列的LED芯片的第一电极和第二电极的位置相反；
    封装层，填充所述LED芯片之间的间隙，并覆盖所述LED芯片的侧壁；
    布线层，形成于所述多个LED芯片的第二表面之上，将该多个发光单元电连接形成一多合一的发光模块。
  32. 根据权利要求31所述的发光二极管封装组件，其特征在于：相邻发光单元之间的间距为0.8mm以下。
  33. 根据权利要求31所述的发光二极管封装组件，其特征在于：所述封装组件的总厚度介于120~200μm之间或者320~500μm之间。
  34. 根据权利要求31所述的发光二极管封装组件，其特征在于：所述各组发光单元的多个LED芯片的第一表面的高度差为10μm以下。
  35. 根据权利要求31所述的发光二极管封装组件，其特征在于：所述封装层为有色层，在所述发光单元的第一表面上覆盖有一透光层，该透光层的厚度为20μm以下。
  36. 根据权利要求31所述的发光二极管封装组件，其特征在于：所述封装层的透光率为0~30%。
  37. 根据权利要求31所述的发光二极管封装组件，其特征在于：所述布线层包括第一布线层、通孔层和第二布线层，其中所述第一布线层形成于所述多个LED芯片的第二表面之上，连接所述多个LED芯片的第一电极和第二电极，所述通孔层形成于所述第一布线层之上，与所述第一布线层形成电性连接，所述第二布线层形成于所述通孔层之上，与所述通孔层形成电性连接。
  38. 根据权利要求37所述的发光二极管封装组件，其特征在于：该多个发光单元以2×2矩阵布置，所述第一布线层包括公共布线和第一布线，所述公共布线公共连接到第二方向上相邻的两组发光单元的多个LED芯片，第一布线连接第一方向上相邻的两组发光单元的第二LED芯片，所述第二布线层分别连接第一方向上相邻的两组发光单元的第一、第三LED芯片并联。
  39. 根据权利要求37所述的发光二极管封装组件，其特征在于：所述第一布线层包括公共布线和第一布线，其中所述公共布线公共连接到第一方向上相邻的多组发光单元的多个LED芯片，第一布线从第二方向至少将相邻两列的同一行的第一、第二、第三LED芯片分别连接，第二布线层从第二方向将位于同一行的第一、第二和第三LED芯片分别连接。
  40. 根据权利要求37所述的发光二极管封装组件，其特征在于：第二布线层包括连线和连接部，所述连线将不同发光单元的同一类型的LED芯片并联，所述连接部作为外部连接输入电极。
  41. 根据权利要求40所述的发光二极管封装组件，其特征在于：所述连接部的数量为n+m×a，其中a为每个所述发光单元的LED芯片的数量，其中n ≥ m。
  42. 根据权利要求37所述的发光二极管封装组件，其特征在于：所述通孔层的厚度为20~ 80μm。
  43. 根据权利要求31所述的发光二极管封装组件，其特征在于：所述布线层包含多层彼此电性隔离的导电线路，该导电线路的层数为四层以下。
  44. 根据权利要求43所述的发光二极管封装组件，其特征在于：该多层导电线路的至少一层的厚度为50μm以下。
  45. 根据权利要求43所述的发光二极管封装组件，其特征在于：该多层导电线路的至少一层的厚度为60μm以上。
  46. 根据权利要求31所述的发光二极管封装组件，其特征在于：还包括形成于所述封装层的表面上的绝缘层，该绝缘层封覆盖所述布线层。
  47. 根据权利要求46所述的发光二极管封装组件，其特征在于：所述绝缘层包括一层或多层结构，其中至少一层的硬度大于所述布线层的硬度。
  48. 权利要求要求46所述的发光二极管封装组件，其特征在于：所述绝缘层包括一层或多层结构，其中至少一层的硬度为D60以上。
  49. 根据权利要求46所述的发光二极管封装组件，其特征在于：所述绝缘层包括一层或多层结构，其中至少一层的与所述第一封装层采用相同的材料。
  50. 根据权利要求46所述的发光二极管封装组件，其特征在于：所述绝缘层为一层或者多层结构，其中至少一层由光敏材料固化而成。
  51. 利要求31所述的发光二极管封装组件，其特征在于：所述绝缘层为包括一层或多层结构，其中至少一层为透明层。
  52. 根据权利要求1或者31所述的发光二极管封装组件，其特征在于：还包括焊盘，所述焊盘的数量P为n + m×a，其中a为每个所述发光单元的LED芯片的数量，其中n≥m。
  53. 根据权利要求31所述的发光二极管封装组件，其特征在于：所述布线层包括多层导电线路，其中第一层导电线路与所述LED芯片的电极组连接，每层导电线路的最小线宽W和该层导电线层的厚度T的关系如下：W≤T≤2W。
  54. 根据权利要求53所述的发光二极管封装组件，其特征在于：所述多层导电线路的至少一层表面具有保护层。
  55. 根据权利要求53所述的发光二极管封装组件，其特征在于：所述保护层的厚度为50~200nm。
  56. 根据权利要求53所述的发光二极管封装组件，其特征在于：所述多层导电线路的各层最小线宽W为10μm以上。
PCT/CN2020/098502 2019-09-18 2020-06-28 发光二极管封装组件 WO2021051924A1 (zh)

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