WO2021051548A1 - 忆阻器的读写电路及读写方法 - Google Patents

忆阻器的读写电路及读写方法 Download PDF

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Publication number
WO2021051548A1
WO2021051548A1 PCT/CN2019/117419 CN2019117419W WO2021051548A1 WO 2021051548 A1 WO2021051548 A1 WO 2021051548A1 CN 2019117419 W CN2019117419 W CN 2019117419W WO 2021051548 A1 WO2021051548 A1 WO 2021051548A1
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voltage
read
circuit
memristor
write
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PCT/CN2019/117419
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English (en)
French (fr)
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王兴晟
黄恩铭
缪向水
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华中科技大学
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Priority to US17/049,024 priority Critical patent/US11238928B2/en
Publication of WO2021051548A1 publication Critical patent/WO2021051548A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0057—Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the invention belongs to the field of memristor read-write circuits, and more specifically, relates to a memristor read-write circuit and a read-write method.
  • a memory material based on a memristive material can be switched between high resistance and low resistance by applying an appropriate voltage to the memristive material.
  • the low-resistance state is the state formed by the conductive path, which has a low resistance value
  • the high-resistance state is the state where the conductive path is disconnected, and has a high resistance value.
  • the memristive material forms a variety of different responses to different excitations.
  • the resistance state is used to store or read data.
  • the storage and read operations of the memristor include a variety of voltages with different amplitudes.
  • the most basic operations in the read and write operations of the memristor are set (write 1) and reset (write 0) operations, which correspond to multi-resistance
  • the operation of the state memristor is to add multiple corresponding set or reset pulse widths to reach the corresponding resistance state.
  • the resistance state of the memristor changes rapidly with the application of various operating voltages. Therefore, the applied write voltage must have a good value. It is stable and does not drift and change with the change of the resistance of the memristor. Otherwise, it is easy to cause write failure or over-operation, which causes greater random fluctuations in the resistance distribution and leads to errors in reading data.
  • a memristor read-write circuit that meets fast and stable is proposed, which can provide high-speed and stable read-write voltage, and the random fluctuations of the memristor are considered in the design of the readout circuit. , Improve the stability of the memristor circuit.
  • a memristor read-write circuit which is characterized in that it includes a voltage follower circuit for the read-write loop voltage applied to the memristor memory cell, and the voltage follower circuit According to a control signal, a selection voltage or a conduction voltage corresponding to the selection voltage to form a read-write operation loop for the memristor memory cell is used to realize a switch function on the read-write loop in this way.
  • the voltage follower circuit includes a voltage selector, the input terminal of the voltage selector is connected to the closed loop voltage, the other input terminal of the voltage selector is connected to an amplifier, and the other input terminal of the amplifier is connected to Into the conduction voltage of the operating loop, the output terminal of the amplifier is connected to a feedback tube, and the voltage selector is also connected to the feedback tube to form a voltage follower loop.
  • the read-write circuit is applied to a bipolar memristor, between the first voltage selector electrically connected to one pole of the memristor storage unit, and between the other pole of the memristor storage unit and electrically connected to the other pole of the memristor storage unit.
  • the above two electrical connections or one of the electrical connections sets the voltage follower circuit, and the first voltage selector and the second voltage selector are used to select the selection voltage to be input to the Voltage follower circuit.
  • the read circuit includes a differential amplifier that outputs read data, wherein the first branch of the differential amplifier comes from the read signal of the memristor storage unit;
  • the read circuit further includes a variable resistance selector, which selects a corresponding reference resistance value resistor according to the control signal to connect to the reference read voltage loop to form a second branch read signal input to the differential amplifier.
  • the reference read voltage loop includes a third voltage follower circuit
  • the third voltage follower circuit includes a third amplifier, and a third feedback tube, wherein one input of the third amplifier is connected to the variable resistance selector The output of, forms a voltage follower loop with the third feedback tube and the third amplifier at the same time, and the other input terminal of the third amplifier is connected to the read voltage signal.
  • the invention also discloses a writing operation method of the memristor read-write circuit, which is characterized in that the above-mentioned method includes the following steps:
  • the write voltage loop is turned on through the second control signal, and the voltage follower circuit at the write end maintains a stable voltage input.
  • the invention also discloses a read operation method of the memristor read-write circuit, which is characterized in that the above-mentioned method includes the following steps:
  • the reading voltage loop is connected through the second control signal, the voltage follower circuit at the reading input terminal maintains a stable voltage input, and the signal is read.
  • the read operation method further includes the following steps:
  • the differential amplifier outputs the read data according to the first read signal and the first reference signal.
  • the fourth control signal is a control signal generated by comparing the first readout signal with a reference signal, or the control signal selector randomly selects a variable resistor for access, and adjusts the control signal selection after the readout fails. After the device selects other resistors, the reading operation is continued until the reading is completed. If the reading failure reaches the preset number of times, it is judged that the current memristor memory cell is invalid.
  • turning on the write voltage loop by the second control signal includes the following steps:
  • the memristor storage unit forms the turn-on voltage of the operating loop.
  • the read-write circuit implemented according to the present invention is set by the selector in the voltage follower circuit, and the loop conduction signal is also used as a receiving input of the selector, which can realize the conduction of the read-write loop under the action of the control signal. Through, it has achieved the technical effect of simplifying the circuit while providing stable reading and writing voltage;
  • the readout circuit is designed with differential output, and a variable reference resistance readout method is proposed for the reference voltage to solve the problem of readout circuit drift caused by the memristor resistance difference of the readout circuit.
  • Fig. 1 is a schematic diagram of a memory cell used in a memristor read-write circuit implemented in accordance with the present invention
  • FIG. 2 is a schematic diagram of the basic storage structure of a storage unit applied to a memristor read-write circuit implemented in accordance with the present invention
  • FIG. 3 is a schematic diagram of a memory array structure corresponding to a memory cell used in a memristor read-write circuit implemented in accordance with the present invention
  • Fig. 4 is a schematic structural frame diagram of one of the implementation modes of a high-speed read-write circuit for a memristor memory cell implemented in accordance with the present invention
  • FIG. 5 is a schematic diagram of a specific circuit structure of one embodiment of a high-speed read-write circuit for a memristor memory cell implemented according to the present invention
  • FIG. 6 is a schematic flow chart of a writing method for a high-speed reading and writing circuit of a memristor memory cell implemented in accordance with the present invention
  • FIG. 7 is a schematic flowchart of one embodiment of a reading method for a high-speed read-write circuit of a memristor memory cell implemented in accordance with the present invention.
  • FIG. 8 is a schematic flowchart of another embodiment of a reading method for a high-speed reading and writing circuit of a memristor memory cell implemented according to the present invention.
  • Vforming represents the forward voltage of the forming operation
  • Vset represents the forward voltage required for the Set operation
  • Vread represents the forward voltage required for the read operation
  • Vtest represents the test voltage applied in the forward direction
  • To the input voltage group, Vreset is the reverse voltage of the reset operation
  • Vtest is the reverse input test voltage.
  • Memristor unit in 1T1R structure 12 Bit line selection transistor in memory array 13: Word line transistor in 1T1R structure
  • the first voltage follower circuit 22 The second voltage follower circuit 31: The first voltage selector (4 out of 4 selectors for forward voltage, the control signal of the forward input voltage 4 out of 4 selector 21) 32: Second Voltage selector (2 out of 2 selectors for reverse voltage, reverse input voltage selector control signal)
  • the first amplifier 212 The first feedback tube 213: The third voltage selector (2 out of 2 selectors for forward voltage)
  • Second amplifier high gain amplifier
  • Second feedback tube 223: Fourth voltage selector
  • the first current-voltage conversion circuit (the diode is connected to the PMOS tube 212 to convert current into voltage) 42: the current feedback circuit 43: the second current-voltage conversion circuit 44: the third voltage follower circuit 45: the variable resistance selector ( Reference resistor's 4 out of 1 selector) 46: Variable resistor 47: Sensitive differential amplifier
  • Figure 1 shows an embodiment of a memory cell used in a memristor read-write circuit implemented in accordance with the present invention. Its structure includes three parts, an upper electrode 111, a functional layer 110, and a lower electrode 112.
  • the electrode material of the upper electrode and the lower electrode can be Ti, Ta, TiN, TaN, and the material of the functional layer is HfOx.
  • the material of the upper electrode of the memristor memory cell is TiN
  • the material of the functional layer is HfOx
  • the material of the lower electrode is Ti.
  • the memristor is When a certain positive voltage is applied to the upper electrode of the memory cell, and the lower electrode is connected to 0 voltage, the Set operation will be executed. At this time, the memristive memory cell is placed in a low resistance state (called positive voltage). When a certain amount is applied to the lower electrode When the upper electrode is connected to 0 voltage, the Reset operation will be performed to put the memristor in a high resistance state (called reverse voltage).
  • the scope of application of the read-write circuit of the present invention is not limited to the embodiment of the above-mentioned bipolar memory structure, and the electrode and functional layer materials are not strictly limited.
  • the design of the read-write circuit and method of the present invention is mainly A read-write circuit and a read-write method for a memristor applying a read-write voltage.
  • FIG. 2 is a schematic diagram of the basic storage structure of the memory cell used in the bipolar memristor read-write circuit implemented according to one of the embodiments of the present invention, which is a traditional 1T1R structure, that is, 1 transistor and 1 memristor unit .
  • the gate of the word line transistor 13 is connected to the word line control signal, the drain is connected to the lower electrode 112 of the memristor, and the upper electrode 111 is connected to the source of the selection transistor 12.
  • FIG. 3 is a schematic diagram of the memory array structure corresponding to the memory cell used in the memristor read-write circuit implemented according to the present invention.
  • the drain of the bit selection transistor 12 is connected to the upper electrode of a column of memory cells, and the word selection transistors 13 share the same gate in the same row, thus forming an N ⁇ M memory array.
  • the Yth bit transistor is selected At this time, only the memristor memory cell in row X and column Y will be selected.
  • FIG. 4 is a schematic structural diagram of one embodiment of a high-speed read-write circuit for a memristor memory cell implemented in accordance with the present invention.
  • the memristor read-write circuit implemented in accordance with the present invention mainly includes two parts, one It is the reading circuit module and the other is the writing circuit module.
  • the reading circuit module includes a first voltage follower circuit 21 electrically connected to the first electrode of the memristor memory array 1 and a first voltage selector 31 electrically connected to the first voltage follower circuit 21.
  • the reading and writing circuit module also Comprising a second voltage follower circuit 22 electrically connected to the second electrode of the memristor storage array 1 and a second voltage selector 32 electrically connected to the second voltage follower circuit 22;
  • the first voltage selector 31 is used to select the corresponding voltage for the Forming, Set, Read, and Test operations, and it receives an external control signal to select the corresponding voltage to be applied to the first voltage follower circuit 21, and the first voltage follower circuit 21
  • the output of is connected to the source of the bit selection transistor 12 connected to the upper electrode 111 of the memory cell;
  • the second voltage selector 32 is used to select the corresponding voltage for the Reset and Test operations of the second pole, and it receives an external control signal to select the corresponding voltage to be applied to the second voltage follower circuit 22, and the output of the second voltage follower circuit 22 Connected to the source of the word selection transistor 13 connected to the lower electrode 112 of the memory cell;
  • the improvement measures are mainly in the first voltage follower circuit 21 and the second voltage follower circuit 21.
  • the arrangement of the voltage follower circuit 22 and the arrangement of the above two circuit modules enable the output voltage of the first voltage follower circuit 21 to stably output the voltage selected by the selector and apply to the selected memristor storage unit;
  • the first voltage follower circuit 21 includes a first amplifier 211, a first MOS feedback tube 212, and a third voltage selector 213.
  • the input terminal of the first amplifier 211 is connected to the output of the first voltage selector 31, and the output of the first amplifier Connected to the gate of the first MOS feedback tube 212, where the other input terminal of the first amplifier 211 and the ground signal serve as the voltage selection terminal of the third voltage selector 213, and the output terminal of the third voltage selector 213 is connected to the bit selection transistor 12, wherein the output terminal of the third voltage selector 213 is also connected to the drain of the first MOS feedback tube 212, and the drain of the first MOS feedback tube 212 is connected to the source of the selection transistor 12;
  • the second voltage follower circuit 22 includes a second amplifier 221, a second MOS feedback tube 222, and a fourth voltage selector 223.
  • the input end of the second amplifier 221 is connected to the output of the second voltage selector 32, and the second amplifier 221
  • the output is connected to the gate of the second MOS feedback tube 222, where the other input terminal of the second amplifier 221 and the ground signal serve as the voltage selection terminal of the fourth voltage selector 223, and the output terminal of the fourth voltage selector 223 is connected to the word selection
  • the source of the transistor 13, the output of the fourth voltage selector 223 is also connected to the source of the second MOS feedback tube 222, the source of the second MOS feedback tube 222 is connected to the source of the selection transistor 13, and the second MOS feedback
  • the drain of the tube 222 is connected to a reference voltage;
  • the reading circuit 4 mainly includes a first current-voltage conversion circuit 41.
  • the input terminal of the first current-voltage conversion circuit is connected to the source of the first MOS feedback tube 212, and the output terminal is connected to the current feedback circuit 42 of the next stage on the one hand.
  • the sensitive differential amplifier 47 is also connected to the first current feedback circuit 42.
  • the first current feedback circuit 42 is used as a control signal and is input to the control terminal of the variable resistance selector 45.
  • variable resistance selector 45 The input terminal of the variable resistance selector 45 is connected to an optional multi
  • the output terminal of the variable resistance selector 45 is connected to the third voltage follower circuit 44, the third voltage follower circuit 44 is connected to the second current-to-voltage conversion circuit 43, and the output terminal of the second current-to-voltage conversion circuit 43 is connected to the sensitive differential amplifier 47. Finally, the data is read through the output of the sensitive differential amplifier 47;
  • the circuit structure of the third voltage follower circuit 44 includes a third amplifier 441 and a third MOS feedback tube 442.
  • One input of the third amplifier 441 is connected to the output of the variable resistance selector 45, and the other input is connected to the output of the variable resistance selector 45.
  • Vread signal the output terminal of the third amplifier 441 is connected to the gate of the third MOS feedback tube 442, an input terminal of the third amplifier 441 is also connected to the source of the third MOS feedback tube 442, and the drain of the third MOS feedback tube 442 Connect the second current-voltage conversion circuit 43.
  • the current feedback module 42 is composed of multiple comparators, which can generate a control signal to the variable resistance selector 45 based on the comparison of the read voltage, and select the corresponding resistance value of the variable resistance according to the control signal, so as to be able to accurately read Find the resistance of the memristor.
  • the working principle of the current feedback module 42 is to generate a control signal according to the read voltage signal collected by the read circuit.
  • This control signal can select the resistance of the variable resistor to be connected to realize the output of the read voltage reference terminal.
  • an implementation is composed of multiple comparators.
  • the collected reading voltage signal is input to three comparators, and the other input of the three comparators is three reference voltage signals (for example, Corresponding to high-resistance, low-resistance, intermediate resistance states, etc.), so as to generate three-bit logic digital control signals through comparison to realize the selection control of the variable resistance selector 45.
  • the comparators can be set to multiple, and multiple The reference voltage signal is compared to achieve a more precise voltage adjustment control so that the readout accuracy of the voltage drift is improved.
  • the above setting method is a digital feedback setting method.
  • the setting method of an analog circuit can be used to realize different current and voltage corresponding to different resistance access.
  • the conduction mode of the circuit realizes the selection of variable resistance.
  • the first current-voltage conversion circuit 41 and the current feedback module 42 are generally controlled by logic output in the digital realization mode.
  • the magnitude of the voltage and current signal is mainly used to turn on the resistance of the corresponding variable resistor loop, so that the signal at the reference voltage terminal can be read as the resistance of the memristor circuit drifts.
  • the reference signal can also be adjusted accordingly.
  • the present invention also proposes a memristor read-write method, which includes the following steps:
  • the main steps are as follows:
  • the write voltage circuit is turned on by the second control signal, and the voltage follower circuit maintains a stable voltage input to the write terminal;
  • the integration simplifies the writing circuit, for the bipolar memristor, further, the other end of the writing terminal of the memory cell is grounded through the third control signal to realize the writing voltage circuit of the corresponding pole of the memristor memory cell Conduction.
  • the first polarity write voltage is selected by the first voltage selector 31, and the control terminal of the third voltage selector 213 gates the feedback terminal of the first amplifier 211 to form a loop to apply a forward voltage to the memory cell, and at the same time, the fourth The control terminal of the voltage selector 223 gates the ground input terminal of the fourth voltage selector 223 to form a first-pole write loop (to form a write or erase operation);
  • the second polarity write voltage is selected by the second voltage selector 32, and the control terminal of the fourth voltage selector 223 gates the feedback terminal of the second amplifier 221 to form a loop to apply a reverse voltage to the memory cell while the third voltage
  • the control terminal of the selector 213 gates the ground input terminal of the third voltage selector 213 to form a second-pole write loop (to form a write or erase operation).
  • the main steps of the reading method of the memristor implemented according to the present invention are:
  • the differential amplifier outputs the read data according to the first read signal and the first reference voltage signal.
  • the reference loop is formed by the voltage follower circuit applying a read voltage at the variable resistance end.
  • Generate the control signal of the variable resistance selector 45 select the resistance value of the variable resistance, apply the same read voltage to the variable resistance, collect the read voltage signal and input it into the other end of the sensitive differential amplifier 47.
  • the output of the sensitive differential amplifier 47 is To read the data.
  • the generation of the control signal of the variable resistance selector 45 implemented according to the present invention can collect the first voltage follower circuit 21
  • the voltage signal at the upper end is formed by the current feedback module 42 as a control signal to select the variable resistor. It can also be directly formed by the external control terminal of the variable resistor selector 45 to directly form a random resistance selection control signal. If the reading fails, then select other ones in turn. The resistance value of is connected until it can be read, otherwise it is determined that the corresponding memory cell is invalid.
  • one of the implementations of the current feedback module 42 is a comparator, and its working mode is to collect the readout signal of the actual storage unit and compare it with the reference signal to realize the control of the variable resistance.
  • the resistance difference of the memristive unit can be considered in the generation of the selection signal to realize smooth reading and avoid reading failure caused by the resistance difference.
  • FIG. 5 is a schematic diagram of the specific connection circuit structure of one of the implementations of the high-speed read-write circuit for the memristor memory cell implemented according to the present invention, where the dashed box represents the N ⁇ M memory array, and the following will be from Forming, Set, The four operation modes of Reset and Read will describe the specific implementation process of the above-mentioned read-write circuit and read-write method.
  • the memristor read-write circuit implemented in accordance with the embodiment of the present invention can quickly and stably write and read with consideration of the difference in resistance value. ,among them:
  • Forming operation After the storage chip leaves the factory, initialize the storage unit to 1;
  • Reset operation the process of applying a reverse voltage to the memory cell to set the memristor to high resistance
  • Read operation the process of adding a small voltage in the positive direction to read the resistance state of the memristor.
  • the working process of the above-mentioned high-speed read-write circuit is as follows:
  • Forming is to add a certain forward voltage to the memristor storage unit selected by the control signal (here Vforming is used to represent the forward voltage), and initialize the selected memristor unit to a low resistance state.
  • the first voltage selector 31 is a four-to-one selector for forward voltage, selects the forming voltage to be input to the first amplifier 211, and the third voltage selector 213 is a two-to-one selector for forward voltage, and selects the output terminal to be connected.
  • the first feedback tube 212 is a PMOS tube, which will form a feedback loop to stabilize the output terminal of the 2 out of 1 selector of the forward voltage to the forming voltage.
  • the fourth voltage selector 223 is a two-to-one selector for reverse voltage, and connects the selection ground terminal.
  • the upper part of the entire memory array module (the drain of the bit line selection transistor 12) will be applied with a stable follower voltage Vforming, and the lower part of the array (the source of the word line selection transistor 13) will be grounded.
  • the positive voltage Vforming is applied to the upper end of the corresponding memory cell selected from the N ⁇ M array to realize the forming operation.
  • the first voltage selector 31 (4 out of 4 selectors for forward voltage) selects the Vset voltage, and the first feedback tube 212 (PMOS feedback tube) acts as a voltage follower.
  • the entire memory array module The part (the drain of the bit line selection transistor 12) will be applied with a stable follower voltage Vset, and the lower part of the array (the source of the word line selection transistor 13) will be grounded. Then the bit line transistor switch signal 121 and the word line transistor switch signal 131 select the memory cell and apply the Vset voltage to the upper end of the corresponding memory cell to implement the Set operation.
  • Reset is to add a certain reverse voltage to the selected memristor unit (here represented by Vreset), and put the selected memristor unit in a high resistance state.
  • the second voltage selector 32 (two-to-one selector for reverse voltage) selects the Vreset voltage to input into the second amplifier 221, and the fourth voltage selector 223 (two-to-one selector for reverse voltage) selects the output terminal to be connected.
  • the second feedback tube 222 (PMOS feedback tube) will form a feedback loop to stabilize the output terminal of the fourth voltage selector 223 (two-to-one selector for reverse voltage) to the Vreset voltage.
  • the 2 out of 1 selector 213, which controls the forward voltage connects the selective ground terminal.
  • the lower part of the dashed frame (the entire memory array module) (the source of the word line selection transistor 13) will be applied with a stable follow-up voltage Vreset, and the upper part of the array (the drain of the bit line selection transistor 12) will be grounded.
  • a reverse voltage Vreset is applied to the upper end of a memory cell selected from the N ⁇ M array to realize the Reset operation.
  • Read operation is mainly to select the Vread voltage through the first voltage selector 31 (4 out of 4 selectors for forward voltage), and the third voltage selector 213 and the first amplifier 211 apply the Vread voltage to the storage device. The upper end of the array.
  • the fourth voltage selector 223 (two out of two selectors for reverse voltage) will ground the lower end of the memory array. Then, a Vread voltage is applied to the selected memory cell through the bit line transistor switch signal 121 and the word line transistor switch signal 131. At this time, a read current will be generated on the entire branch;
  • the first current-to-voltage conversion circuit (the diode is connected to the PMOS tube 212 for converting current into voltage) will generate a voltage at one end of the sensitive amplifier 47.
  • the voltage passing through the current feedback circuit 42 will generate a control signal and act on the variable resistance selector 45.
  • the external selector control signal and the control signal generated by the current feedback circuit 42 simultaneously act on the variable resistance selector 45 to select the corresponding reference resistance.
  • the third amplifier 441 and the third feedback tube 442 add the Vread voltage to the reference resistor. Then, the branch current of the reference resistor is converted into a voltage by the second current-voltage conversion circuit 43 and applied to the other end of the sensitive amplifier 47. The voltage comparison is performed by differential amplification by the sensitive amplifier 47 to obtain the stored data.
  • both the low resistance state resistance value and the high resistance state resistance value of the memristor will drift (including random fluctuations), then the reference resistance The selection will also change.
  • the variable reference resistance according to the signal of the current feedback module 42 (the feedback module can be composed of multiple comparators), select the best reference resistance; or when writing and reading once After failure, the reference resistor is selected by the external control signal, and the read operation is performed again. If the read fails, the next reference resistor will be selected until all reference resistors have been selected and the read fails, then the memory cell is judged to be invalid and can be enabled Spare storage unit.
  • the read and write circuits are integrated, which not only simplifies the circuit, but also achieves rapid and stable voltage supply by the amplifier voltage follower circuit after the voltage is selected by the selector.
  • the read circuit module of the present invention can be combined with other write circuit modules, or the write circuit module of the present invention can be combined with other write circuit modules.
  • Other combinations of reading circuit modules, especially the reading and writing circuit of the present invention, are also suitable for reading and writing multi-value memristor memory.
  • some circuits restrict the feedback tube to PMOS, but this is not strictly limited. Choose different MOS tubes according to the conduction mode in the circuit, and modify the selection for the loop conduction connection setting of the gate source and the drain. .
  • the current feedback circuit that generates the control signal in the present invention mainly realizes the logical selection of the actual read signal and the reference signal that can be multiple or single to form a control signal to select the resistance value of the variable resistance.
  • analog and digital design methods in the realization form There are analog and digital design methods in the realization form.
  • the appropriate resistance value is selected according to the comparison of different drift conditions when resistance drift may occur, and the selection of the read reference resistance value is performed.
  • One embodiment is to select the corresponding resistance access circuit through a selector.
  • the circuit design modification of the above analog and digital design methods can achieve the purpose of controlling the variable resistance.
  • the high-resistance and low-resistance settings correspond to the forward and reverse voltages applied by various operations such as writing, erasing, and reading, and the corresponding read-write circuit settings.
  • Symmetrical circuit structures can be set according to the material properties of the memory cells That is to say, the memristor involved in the above embodiment is a bipolar memristor, but the same for a unipolar memristor, or the corresponding setting of other materials makes the voltage setting of the read-write terminal change .
  • the modules of the read-write circuit and read-write method involved in the present invention can also be implemented in simple modification, that is, it is suitable for unipolar memristors, and for binary and multi-value storage units, the read-write circuit is equally applicable and can correspond Adjustment.
  • various control signals need to be generated by the controller to realize the selection and read-write control of the memory cell array.
  • the above-mentioned various control signals need to have the overall control from the memristor chip.
  • this The selector and comparator circuit structures mentioned in the embodiments are also available in the prior art, and the specific structure forms are not repeated here.

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Abstract

本发明公开了一种忆阻器的读写电路及读写方法，其中上述读写电路主要包括读电路和写电路，其中写电路包括：与忆阻器存储阵列电连接的第一电压跟随电路及与第一电压选择器，读写电路还包括有与忆阻器存储阵列电连接的第二电压跟随电路及第二电压选择器，通过上述选择器来选择双极写入时的电压稳定跟随，同时在读电路上设置了可变电阻选择接入的方式，将实际读出电压和在相同读电压下的经参考电阻的输出电压输入差分放大器获得读出数据，按照本发明实现的读写电路及读写方法，简化了读写电路，能够提供高速稳定的读写电压，并在读出电路的设计中考虑了忆阻器随机涨落，提高了忆阻器电路的稳定性，其中读电路同样适用于二值与多值忆阻器。

Description

忆阻器的读写电路及读写方法 [技术领域]
本发明属于忆阻器读写电路领域，更具体地，涉及一种忆阻器的读写电路及读写方法。
[背景技术]
以忆阻材料为基底的存储器材料，例如以HfOx为基底的材料或类似的材料，可通过对其施加适当的电压，来使忆阻材料在高阻，低阻设置多阻之间进行转换。一般来说低阻态是导电通路形成的状态，具有低阻值，高阻态则是导电通路断开的状态，具有高阻值，通过忆阻材料这种对不同激励的响应形成多种不同的阻态来实现储存或读取数据。
忆阻器的存储和读取操作包括多种幅值大小不同的电压，例如忆阻器读写操作中最基本的操作为set(写1)和reset(写0)操作，而对应于多阻态忆阻器的操作则是加多个相应的set或者reset脉宽来达到相应的电阻态。对于上述的各种操作，需要快速准确地在忆阻器电极端加上电压，同时忆阻器的阻值状态随着各种操作电压地施加发生快速转变，因此施加的写电压必须有较好的稳定性并且不随忆组器阻值的改变而发生漂移改变，否则容易导致写失败或者过操作，使得阻值分布出现更大的随机涨落，导致读出数据出错。
[发明内容]
针对现有技术的以上缺陷或改进需求，提出一种满足快速稳定的忆阻器读写电路，能够提供高速稳定的读写电压，并在读出电路的设计中考虑了忆阻器随机涨落，提高了忆阻器电路的稳定性。
为实现上述目的，按照本发明，提供了一种忆阻器读写电路，其特征在于，其包括对施加于忆阻器存储单元的读写回路电压，设置电压跟随电路，所述电压跟随电路依据控制信号接选择电压或与所述选择电压对应的对所述忆阻器存储单元形成读写操作回路的导通电压，以此方式对所述读写回路实现开关作用。
进一步地，所述电压跟随电路包括电压选择器，所述电压选择器输入一端接入所述接通回路关闭电压，所述电压选择器另外输入一端接放大器，所述放大器 的另外一输入端接入所述操作回路的导通电压，所述放大器输出端连接反馈管，所述电压选择器也接入反馈管以此形成电压跟随回路。
进一步地，所述读写电路应用于双极型忆阻器，与忆阻器存储单元一极电连接的第一电压选择器之间及与忆阻器存储单元另一极和其电连接的第二电压选择器之间，以上两个电连接或其中一个电连接设置所述电压跟随电路，所述第一电压选择器及所述第二电压选择器用于选择所述选择电压输入至所述电压跟随电路。
进一步地，读电路包括输出读出数据的差分放大器，其中所述差分放大器第一支路来自所述忆阻器存储单元的读出信号；
所述读电路还包括可变电阻选择器，所述可变电阻选择器依据控制信号选择相应参考阻值电阻接入参考读电压回路形成第二支路读出信号输入至所述差分放大器。
进一步地，所述参考读电压回路包括第三电压跟随电路，所述第三电压跟随电路包括第三放大器，第三反馈管，其中所述第三放大器一输入端接所述可变电阻选择器的输出，同时与所述第三反馈管及所述第三放大器形成电压跟随回路，所述第三放大器另一输入端接读电压信号。
本发明还公开了一种忆阻器读写电路的写操作方法，其特征在于，上述方法包括如下步骤：
通过第一控制信号将所述选择电压确定为写电压；
通过第二控制信号接通写电压回路，写入端的电压跟随电路保持稳定电压输入。
本发明还公开了一种忆阻器读写电路的读操作方法，其特征在于，上述方法包括如下步骤：
通过第一控制信号将所述选择电压确定为读电压；
通过第二控制信号接通读电压回路，读入端的电压跟随电路保持稳定电压输入，读取信号。
进一步地，所述读操作方法还包括如下步骤：
采集所述忆阻器存储单元的第一路读出信号输入至差分放大器；
生成第四控制信号控制可变选择电阻接入参考读电压回路；
将所述参考读电压回路的读出电压作为第一路参考信号输入至差分放大器(47)；
所述差分放大器依据第一路读出信号及第一路参考信号输出读出数据。
进一步地，所述第四控制信号为由第一路读出信号与参考信号比较生成的控制信号，或者由控制信号选择器随机选择可变电阻接入，读出失败后调整所述控制信号选择器选择其它电阻后继续读操作，直到完成读出，若达到预设次数的读出失败，则判断当前忆阻器存储单元失效。
进一步地，所述第二控制信号接通写电压回路包括如下步骤：
控制所述忆阻器存储单元第一端的所述电压跟随电路接通选择电压；控制所述忆阻器存储单元第二端的所述电压跟随电路接通与所述选择电压对应的与所述忆阻器存储单元形成操作回路的导通电压。
总体而言，通过本发明所构思的以上技术方案与现有技术相比，具有以下有益效果：
(1)按照本发明实现的读写电路，通过电压跟随电路中的选择器设置，并通过回路导通信号也作为选择器的一个接收输入，能够在控制信号的作用下实现读写回路的导通，在提供稳定读写电压的同时达到了简化电路的技术效果；
(2)通过选择器选择电压后，对选择好的各类读写电压设置放大器电压跟随电路，达到了快速稳定提供电压的技术效果，并在读写电路的各个需要稳定电压的施加端都进行了放大器电压跟随电路设置；
(3)将读出电路进行了差分的输出设计，并且对参考电压提出了可变参考电阻的读出方式，解决读出电路由于忆阻器电阻差异性引起的读出电路漂移的问题。
[附图说明]
图1为按照本发明实现的忆阻器读写电路所应用的存储单元示意图；
图2为按照本发明实现的忆阻器读写电路所应用的存储单元的存储基本架构示意图；
图3为按照本发明实现的忆阻器读写电路所应用的存储单元所对应的存储阵列构架示意图；
图4为按照本发明实现的针对忆阻器存储单元的高速读写电路其中一种实 施方式的结构框架示意图；
图5为按照本发明实现的针对忆阻器存储单元的高速读写电路其中一种实施方式的具体电路结构示意图；
图6为按照本发明实现的针对忆阻器存储单元的高速读写电路的写方法流程示意图；
图7为按照本发明实现的针对忆阻器存储单元的高速读写电路的读方法其中一种实施例的流程示意图；
图8为按照本发明实现的针对忆阻器存储单元的高速读写电路的读方法另外一种实施例的流程示意图。
所有视图中，同一个附图标记表示相同的结构，其中：
正向输入的电压组，Vforming表示forming操作的正向电压；Vset表示Set操作所需加的正向电压；Vread表示读操作所需要加的正向电压；Vtest表示正向加的测试电压；反向输入电压组，Vreset为reset操作反向电压；Vtest为反向输入测试电压。
11：1T1R结构中的忆阻器单元 12：存储阵列中的位线选择晶体管 13：1T1R结构中的字线晶体管
111：忆阻器上电极 110：忆阻器功能层 112：忆阻器下电极132：1T1R结构中的晶体管源极 121：位线晶体管开关信号 131：字线晶体管开关信号
21：第一电压跟随电路 22：第二电压跟随电路 31：第一电压选择器(正向电压的4选1选择器，正向输入电压4选1选择器21的控制信号) 32：第二电压选择器(反向电压的2选1选择器，反向输入电压选择器控制信号)
211：第一放大器 212：第一反馈管 213：第三电压选择器(正向电压的2选1选择器)
221：第二放大器(高增益放大器) 222：第二反馈管 223：第四电压选择器
41：第一电流电压转化电路(二极管连接PMOS管212用于将电流转换为电压) 42：电流反馈电路 43：第二电流电压转化电路 44：第三电压跟随电路 45：可变电阻选择器(参考电阻的4选1选择器) 46：可变电阻 47： 灵敏差分放大器
441：第三放大器 442：第三反馈管
[具体实施方式]
图1所示为按照本发明实现的忆阻器读写电路所应用的存储单元的其中一种实施例，其结构包含三个部分，上电极111，功能层110，下电极112，为一种典型的三明治结构，上电极和下电极的电极材料可以为Ti，Ta，TiN，TaN，功能层材料为HfOx。
在本发明所涉及的一种具体实施方式中，忆阻器存储单元的上电极材料为TiN，功能层材料为HfOx，下电极材料为Ti，在这种材料的设置下，对于上述忆阻器存储单元当在上电极加一定的正电压，下电极接0电压时，将执行Set操作，此时将忆阻存储单元置于低阻状态(称为加正向电压)，当在下电极加一定的正电压，上电极接0电压时，将执行Reset操作，将忆阻器至于高阻状态(称为加反向电压)。
当然本发明的读写电路的适用范围并不限定为上述的双极型存储结构的实施例，电极及功能层材料也并不严格限定，本发明的读写电路和读写方法的设计主要是针对施加读写电压的忆阻器的读写电路及读写方法。
图2为按照本发明的其中一种实施例实现的双极型忆阻器读写电路所应用的存储单元的存储基本架构示意图，为传统的1T1R构架，即1个晶体管1个忆阻器单元。其中字线晶体管13的栅极接字线控制信号，漏极接忆阻器的下电极112，上电极111接位选择晶体管12源极。
图3为按照本发明实现的忆阻器读写电路所应用的存储单元所对应的存储阵列构架示意图。位选择晶体管12漏极接一列存储单元的上电极，字选择晶体管13同一行共栅极，由此构成一个N×M的存储阵列，当第X个字选择晶体选中，第Y个位晶体管选中时，将只选中第X行Y列的忆阻器存储单元。
图4为按照本发明实现的针对忆阻器存储单元的高速读写电路其中一种实施方式的结构框架示意图，其中，按照本发明实现的忆阻器读写电路，主要包括两个部分，一个是读电路模块，一个是写电路模块。
其中，读电路模块包括有与忆阻器存储阵列1第一极电极电连接的第一电压跟随电路21及与第一电压跟随电路21电连接的第一电压选择器31，读写电路 模块还包括有与忆阻器存储阵列1第二极电极电连接的第二电压跟随电路22及与第二电压跟随电路22电连接的第二电压选择器32；
其中第一电压选择器31，用于针对Forming，Set，Read，Test操作选择相应的电压，其接受外部的控制信号来选择相应的电压施加于第一电压跟随电路21，第一电压跟随电路21的输出接与存储单元上电极111相连的位选择晶体管12的源极；
第二电压选择器32，用于针对第二极的Reset，Test操作选择相应的电压，其接受外部的控制信号选择相应的电压施加于第二电压跟随电路22，第二电压跟随电路22的输出接与存储单元下电极112相连的字选择晶体管13的源极；
其中，作为本发明能够解决保持输入电压稳定性的问题，并且不随忆阻器存储单元阻值的在读写过程中发生快速转变而发生漂移，改进措施主要在于第一电压跟随电路21及第二电压跟随电路22的设置，上述两个电路模块的设置，使得第一电压跟随电路21的输出电压能够稳定输出选择器所选择的电压并施加于选择出的忆阻器存储单元；
其中第一电压跟随电路21包括第一放大器211，第一MOS反馈管212及第三电压选择器213，其中第一放大器211的输入一端接第一电压选择器31的输出，第一放大器的输出接第一MOS反馈管212的栅极，其中，第一放大器211的另外一个输入端与接地信号作为第三电压选择器213的电压选择端，第三电压选择器213的输出端接位选择晶体管12的源极，其中第三电压选择器213的输出端还接第一MOS反馈管212的漏极，第一MOS反馈管212的漏极接位选择晶体管12的源极；
其中第二电压跟随电路22包括第二放大器221，第二MOS反馈管222及第四电压选择器223，其中第二放大器221的输入一端接第二电压选择器32的输出，第二放大器221的输出接第二MOS反馈管222的栅极，其中，第二放大器221的另外一个输入端与接地信号作为第四电压选择器223的电压选择端，第四电压选择器223的输出端接字选择晶体管13的源极，其中第四电压选择器223的输出端还接第二MOS反馈管222的源极，第二MOS反馈管222的源极接字选择晶体管13的源极，第二MOS反馈管222的漏极接一参考电压；
其中读电路4主要包括第一电流电压转化电路41，其中第一电流电压转化 电路的输入端接第一MOS反馈管212的源极，输出端一方面接下一级的电流反馈电路42，输出端另一方面还接灵敏差分放大器47，其中第一电流反馈电路42作为一路控制信号，输入可变电阻选择器45的控制端，可变电阻选择器45的输入端接可选择接入的多个电阻值，可变电阻选择器45的输出端接第三电压跟随电路44，第三电压跟随电路44接第二电流电压转化电路43，第二电流电压转化电路43的输出端接灵敏差分放大器47，最后经灵敏差分放大器47的输出读出数据；
进一步地，其中第三电压跟随电路44的电路结构形式包括第三放大器441，第三MOS反馈管442，其中第三放大器441一输入端接可变电阻选择器45的输出，另外一输入端接Vread信号，第三放大器441的输出端接第三MOS反馈管442的栅极，第三放大器441一输入端还接第三MOS反馈管442的源极，其中第三MOS反馈管442的漏极接第二电流电压转化电路43。
进一步地，其中电流反馈模块42为多个比较器组成，可以依据读出电压比较来生成控制信号予可变电阻选择器45，依据控制信号选择相应的可变电阻的阻值，从而能准确读出忆阻器阻值。
电流反馈模块42的工作原理是依据读电路采集的读电压信号来生成一个控制信号，这个控制信号能够选择可变电阻的阻值的接入，实现读电压参考端的输出。其中，对上述电流反馈模块42举出了一种实施方式为多个比较器组成，例如采集的读电压信号输入三个比较器，三个比较器的另外一个输入为三个参考电压信号(例如对应高阻、低阻、中间阻态等)，从而通过比较生成三位的逻辑数字控制信号，实现对可变电阻选择器45的选择控制，当然，比较器可以设置为多个，与多个参考电压信号进行比较，实现更为精准的电压调节控制从而使得电压漂移的读出精度提高。
另外，对于在依据读电压信号生成控制信号的技术方案设计上，以上设置方式为数字化的反馈设置方式，在其它的实施方式中可使用模拟电路的设置方法来实现不同电流电压对应不同电阻接入电路的导通方式来实现可变电阻的选择，在模拟信号反馈控制的实现方式下，第一电流电压转化电路41及电流反馈模块42总体在数字式的实现方式中是利用逻辑输出的控制方式，但在模拟信号的方式中，主要是利用电压电流本身信号的大小来导通相应的可变电阻的阻值的回路， 从而使得参考电压端的信号能够随着忆阻器电路阻值的漂移读出参考信号也能相应调整。
基于上述的忆阻器读写电路，本发明也提出了一种忆阻器的读写方法，其中包括如下步骤：
对于写方法而言，如图6中忆阻器存储单元的读写电路的写方法流程示意图所示，主要包括如下主要步骤：
通过第一控制信号选择写电压；
通过第二控制信号导通写电压电路，电压跟随电路保持稳定电压输入到写入端；
进一步地，由于整合简化了写电路，对于双极型忆阻器而言，进一步地，通过第三控制信号使得存储器单元写入端的另外一端接地从而实现忆阻器存储单元相应极的写电压电路导通。
具体来说：通过第一电压选择器31选择第一极性写电压，第三电压选择器213控制端选通第一放大器211的反馈端形成回路，为存储单元加正向电压，同时第四电压选择器223控制端选通第四电压选择器223接地输入端，形成第一极写回路(形成写或擦操作)；
同样的，通过第二电压选择器32选择第二极性写电压，第四电压选择器223控制端选通第二放大器221的反馈端形成回路，为存储单元加反向电压，同时第三电压选择器213控制端选通第三电压选择器213接地输入端，形成第二极写回路(形成写或擦操作)。
如图7中忆阻器存储单元的读写电路的读方法的其中一种实施方式所示，为按照本发明实现的忆阻器的读方法操作主要步骤：
通过第一控制信号选择读电压；
通过第二控制信号导通存储单元的读回路；
采集第一路读出信号输入至差分放大器；
采集第二路读出信号生成控制信号，该控制信号选择合适参考电阻接入参考信号的回路生成第一路参考电压信号；
差分放大器依据第一路读出信号及第一路参考电压信号输出读出数据。
其中，更进一步地，参考回路由电压跟随电路在可变电阻端施加读电压而形 成。
具体来说，对于上述的读方法的操作而言：对存储单元施加读电压；读取第一电压跟随电路21上端的电压信号输入灵敏差分放大器47的一端；
生成可变电阻选择器45控制信号，选择可变电阻阻值，在可变电阻上施加同样的读电压，采集读出的电压信号输入灵敏差分放大器47的另外一端，灵敏差分放大器47的输出即为读出数据。
如图8中的忆阻器存储单元的读写电路的读方法的另外一种实施方式所示，按照本发明实现的可变电阻选择器45控制信号的生成，可采集第一电压跟随电路21上端的电压信号，通过电流反馈模块42形成一控制信号选择可变电阻，也可直接由可变电阻选择器45的外部控制端直接形成随机的电阻选择控制信号，如果读出失败再依次选择其它的电阻值接入，直到能够读出，否则判定相应存储单元失效。
其中，如前述在读出电路的介绍中所述，电流反馈模块42的其中一种实施方式为比较器，其工作方式是采集实际存储单元读出信号与参考信号进行比较从而实现对可变电阻的选择信号的生成，以此方式，能够考虑忆阻单元的电阻差异，实现顺利的读出，避免因为电阻差异引起的读出失败。
图5为按照本发明实现的针对忆阻器存储单元的高速读写电路的其中一种实施方式的具体连接电路结构示意图，其中虚线框表示N×M的存储阵列，下面将从Forming，Set，Reset，Read四个操作实施方式进行说明上述读写电路及读写方法的具体实施过程，按照本发明的实施方式实现的忆阻器读写电路，能够快速稳定地写与考虑阻值差异的读，其中：
Forming操作：存储芯片出厂后，将存储单元初始化置1过程；
Set操作：往存储单元加正向电压，将忆阻器置位到低阻的过程；
Reset操作：往存储单元加反向电压，将忆阻器置位到高阻的过程；
Read操作：正向加小电压，读取忆阻器阻值状态的过程。
在本发明的一种实施方式中，为了说明上述读写电路的工作原理，上述高速读写电路的工作过程如下：
(1)Forming操作过程：Forming是将通过控制信号选中的忆阻器存储单元加一定的正向电压(这里用Vforming表示正向电压)，将选中的忆阻器单元初始 化到低阻状态。
第一电压选择器31为正向电压的4选1选择器，选择Vforming电压输入第一放大器211，第三电压选择器213为正向电压的2选1选择器，选择输出端接入。此时通过第一反馈管212为一PMOS管，将构成一个反馈回路将正向电压的2选1选择器输出端稳定到Vforming电压，
同时第四电压选择器223为反向电压的2选1选择器，将选择接地端连入。整个存储阵列模组上部分(位线选择晶体管12的漏极)将加上稳定的跟随电压Vforming，而阵列下部分(字线选择晶体管13的源极)将接地。此时通过位线晶体管开关信号121和字线晶体管开关信号131，将从N×M的阵列中选择相应存储单元上端施加正向电压Vforming，实现Forming操作。
(2)Set操作过程，第一电压选择器31(正向电压的4选1选择器)选择Vset电压，经第一反馈管212(PMOS反馈管)做电压跟随作用，整个存储阵列模组上部分(位线选择晶体管12的漏极)将加上稳定的跟随电压Vset，而阵列下部分(字线选择晶体管13的源极)将接地。然后位线晶体管开关信号121和字线晶体管开关信号131选择存储单元相应存储单元上端施加Vset电压，实现Set操作。
(3)Reset操作过程：Reset是将选中的忆阻器单元加一定的反向电压(这里用Vreset表示)，将选中的忆阻器单元置于高阻状态。
首先第二电压选择器32(反向电压的2选1选择器)选择Vreset电压输入第二放大器221，第四电压选择器223(反向电压的2选1选择器)选择输出端接入。
此时通过第二反馈管222(PMOS反馈管)将构成一个反馈回路将第四电压选择器223(反向电压的2选1选择器)输出端稳定到Vreset电压。同时控制正向电压的2选1选择器213将选择接地端连入。
虚线框(整个存储阵列模组)下部分(字线选择晶体管13的源极)将加上稳定的跟随电压Vreset，而阵列上部分(位线选择晶体管12的漏极)将接地。此时通过位线晶体管开关信号121和字线晶体管开关信号131，将从N×M的阵列中选择一个存储单元上端施加反向电压Vreset，实现Reset操作。
(4)Read操作过程：Read操作主要是通过第一电压选择器31(正向电压 的4选1选择器)选择Vread电压，第三电压选择器213与第一放大器211将Vread电压施加在存储阵列的上端。而第四电压选择器223(反向电压的2选1选择器)将使存储阵列下端接地。再通过位线晶体管开关信号121和字线晶体管开关信号131将再选择的存储单元上施加一个Vread电压。此时将在整条支路上产生一个读电流；
第一电流电压转化电路(二极管连接PMOS管212用于将电流转换为电压)将在灵敏放大器47一端产生一个电压。同时该电压经过电流反馈电路42将产生一个控制信号，作用于可变电阻选择器45。外部选择器控制信号与电流反馈电路42产生的控制信号同时作用于可变电阻选择器45，选择相应的参考电阻。
第三放大器441与第三反馈管442将Vread电压加到参考电阻上。然后参考电阻的支路电流通过第二电流电压转化电路43转化为电压加到灵敏放大器47另一端。通过灵敏放大器47差分放大进行电压比较，得出存储的数据。
总之，按照本发明实现的忆阻器读写方法，随着操作次数的增加，忆阻器的低阻状态阻值与高阻状态阻值均会发生漂移(包括随机涨落)，那么参考电阻的选择也会发生变化，通过可变参考电阻的选择方式，根据电流反馈模块42的信号(反馈模块可以由多个比较器构成)，选择最佳的参考电阻；或当一次写入并读出失败后，由外部控制信号选择参考电阻，并再次执行读操作，若读出失败，将再选择下一个参考电阻直至所有参考电阻都选择过并还是读出失败，则判断存储单元失效，可启用备用存储单元。
按照本发明实现的读写电路及读写方法，将读与写电路整合到一起，不仅简化了电路，并通过选择器选择电压后放大器电压跟随电路达到了快速稳定提供电压。
值得注意的是，上述实施案例只是举出具体的实施方式，在本发明的其它实施案例中，可以将本发明的读电路模块与其它写电路模块组合，或者是采用本发明的写电路模块与其它读电路模块组合，尤其本发明的读写电路同样适用于多值忆阻器存储器读写。
本实施方式中一些电路限定反馈管为PMOS，但这并不严格限定，依据在电路中的导通方式选择不同的MOS管，针对栅源漏极的回路导通连接设置进行改型选择即可。
另外，作为本发明中的产生控制信号的电流反馈电路，主要是实现实际读出信号与可以是多个或单个的参考信号进行逻辑选择形成控制信号来进行可变电阻阻值的选择，在电路的实现形式上有模拟和数字设计方式。
对于可变电阻选择接入电路的选择电路，其在本技术方案的设计中是依据可能发生电阻漂移的情况下依据不同漂移情况的比较来选择合适的阻值进行读出参考阻值的选择，一种实施方式是通过选择器来进行选择相应阻值接入电路，另外也可通过模拟电路的设计方式来依据读出电压的数值选择导通相应的电路实现参考电阻选择，对于本领域技术人员来说，以上模拟和数字设计的方式的电路设计改型均可实现控制可变电阻的目的。
对于不同的存储单元，高阻和低阻的设置对应写、擦、读等各种操作所施加的正反向电压及对应的读写电路设置，可依据存储单元材料性质设置对称的电路结构形式，也即是说，上述实施例中所涉及的忆阻器为双极性的忆阻器，但是同样对于单极性的忆阻器，或者是其它材料的对应设置使得读写端的电压设置改变，本发明所涉及的读写电路和读写方法各模块也可简单改型实现，即适用于单极性忆阻器，同时针对二值与多值存储单元，读写电路同样适用并可以相应调整。
按照本发明实现的读写电路，需要由控制器进行各类控制信号的产生实现存储单元阵列的选择及读写控制，上述各类控制信号需要有来自忆阻器芯片的整体控制，另外，本实施方式中所举出的选择器、比较器电路结构也为现有技术能够获得，在此不再赘述其具体结构形式。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种忆阻器读写电路，其特征在于，其包括对施加于忆阻器存储单元的读写回路电压，设置电压跟随电路，所述电压跟随电路依据控制信号接选择电压或与所述选择电压对应的对所述忆阻器存储单元形成读写操作回路的导通电压，以此方式对所述读写回路实现开关作用。
  2. 如权利要求1所述的忆阻器读写电路，其特征在于，所述电压跟随电路包括电压选择器，所述电压选择器输入一端接入所述操作回路的导通电压，所述电压选择器另外输入一端接放大器，所述放大器的另外一输入端接入所述选择电压，所述放大器输出端连接反馈管，所述电压选择器也接入反馈管以此形成电压跟随回路。
  3. 如权利要求1或2中的忆阻器读写电路，其特征在于，所述读写电路应用于双极型忆阻器，与忆阻器存储单元一极电连接的第一电压选择器(31)之间及与忆阻器存储单元另一极和其电连接的第二电压选择器(32)之间，以上两个电连接或其中一个电连接设置所述电压跟随电路，所述第一电压选择器(31)及所述第二电压选择器(32)用于选择所述选择电压输入至所述电压跟随电路。
  4. 如权利要求1-3中所述的忆阻器读写电路，其特征在于，读电路(4)包括输出读出数据的差分放大器(47)，其中所述差分放大器(47)第一支路来自所述忆阻器存储单元的读出信号；
    所述读电路(4)还包括可变电阻选择器(45)，所述可变电阻选择器(45)依据控制信号选择相应参考阻值电阻接入参考读电压回路(43，44)形成第二支路读出信号输入至所述差分放大器(47)。
  5. 如权利要求4中所述的忆阻器读写电路，其特征在于，所述参考读电压回路(43，44)包括第三电压跟随电路(44)，所述第三电压跟随电路(44)包括第三放大器(441)，第三反馈管(442)，其中所述第三放大器(441)一输入端接所述可变电阻选择器(45)的输出，同时与所述第三反馈管(442)及所述第三放大器(441)形成电压跟随回路，所述第三放大器(441)另一输入端接读电压信号。
  6. 一种如权利要求1-5中任一项所述的忆阻器读写电路的写操作方法，其特征在于，上述方法包括如下步骤：
    通过第一控制信号将所述选择电压确定为写电压；
    通过第二控制信号接通写电压回路，写入端的电压跟随电路保持稳定电压输入。
  7. 一种如权利要求1-5中任一项所述忆阻器读写电路的读操作方法，其特征在于，上述方法包括如下步骤：
    通过第一控制信号将所述选择电压确定为读电压；
    通过第二控制信号接通读电压回路，读入端的电压跟随电路保持稳定电压输入，读取信号。
  8. 如权利要求7中所述的忆阻器读写电路的读操作方法，其特征在于，所述读操作方法还包括如下步骤：
    采集所述忆阻器存储单元的第一路读出信号输入至差分放大器(47)；
    生成第四控制信号控制可变选择电阻接入参考读电压回路；
    将所述参考读电压回路的读出电压作为第一路参考信号输入至差分放大器(47)；
    所述差分放大器依据第一路读出信号及第一路参考信号输出读出数据。
  9. 如权利要求8中的读操作方法，其特征在于，所述第四控制信号为由第一路读出信号与参考信号比较生成的控制信号，或者由控制信号选择器随机选择可变电阻接入，读出失败后调整所述控制信号选择器选择其它电阻后继续读操作，直到完成读出，若达到预设次数的读出失败，则判断当前忆阻器存储单元失效。
  10. 如权利要求6中的写操作方法，其特征在于，所述第二控制信号接通写电压回路包括如下步骤：
    控制所述忆阻器存储单元第一端的所述电压跟随电路接通选择电压；控制所述忆阻器存储单元第二端的所述电压跟随电路接通与所述选择电压对应的与所述忆阻器存储单元形成操作回路的导通电压。
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