WO2021047071A1 - Goa 电路 - Google Patents

Goa 电路 Download PDF

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Publication number
WO2021047071A1
WO2021047071A1 PCT/CN2019/122957 CN2019122957W WO2021047071A1 WO 2021047071 A1 WO2021047071 A1 WO 2021047071A1 CN 2019122957 W CN2019122957 W CN 2019122957W WO 2021047071 A1 WO2021047071 A1 WO 2021047071A1
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WO
WIPO (PCT)
Prior art keywords
electrically connected
film transistor
thin film
drain
source
Prior art date
Application number
PCT/CN2019/122957
Other languages
English (en)
French (fr)
Inventor
薛炎
韩佰祥
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/621,732 priority Critical patent/US11151943B1/en
Publication of WO2021047071A1 publication Critical patent/WO2021047071A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technology, in particular to a GOA circuit.
  • the horizontal scanning line of the Active-matrix organic light-emitting diode (AMOLED) display panel is driven by an external integrated circuit, which can control the scanning lines at all levels.
  • AMOLED Active-matrix organic light-emitting diode
  • GOA array substrate gate drive
  • TFT Thin Film Transistor
  • the LCD array process manufactures the gate scanning driving circuit on the thin film transistor array substrate to realize the progressive scanning driving mode, which has the advantages of reducing production costs and realizing the narrow frame design of the panel. It is used by a variety of displays. use. Therefore, the GOA technology can integrate the line scan driving circuit on the array substrate of the display panel, which significantly reduces the usage of external ICs, thereby reducing the production cost and power consumption of the display panel, and can realize the narrow frame of the display device.
  • the existing oxide semiconductor array substrate gate drive (IGZO-GOA) circuit is relatively complicated, and each level of the circuit contains multiple working modules.
  • ITZO-GOA oxide semiconductor array substrate gate drive
  • large-size display panels have become the main trend in the development of the industry.
  • the increase in the panel size and the number of gate drive rows results in a larger layout area for each level of GOA circuit, which is not conducive to achieving a narrow frame of the display device.
  • an increase in load will also increase the power consumption of the GOA module.
  • the present invention provides a GOA circuit.
  • a GOA circuit including: cascaded multi-level GOA circuit sharing units, each level of GOA circuit sharing unit includes: feedback module, pull-up control module, pull-up module, bootstrap capacitor module, first and second pull-down sustain Module and first and second pull-down modules;
  • the pull-up control module, the bootstrap capacitor module, the pull-up module, the first and second pull-down maintenance modules, and the first and second pull-down modules are all electrically connected to the first node Q; so The feedback module is electrically connected to the second node N;
  • the pull-up module accesses the M+2 and M+3th clock signals CK (M+2) and CK (M+3), and uses the M+2 and M+3th clock signals CK (M+2), CK (M+3) output the nth and n+1th stage transmission signals (Cout(n), Cout(n+1)) and the nth and n+1th scan signals (G (n), G(n+1));
  • the pull-up control module accesses the Mth clock signal CK(M) and the n-2th level transmission signal Cout(n-2) output by the upper two-level n-2th level GOA circuit sharing unit, and uses all The n-2th stage transmission signal Cout(n-2) charges the first node Q;
  • the first pull-down module is connected to at least the n+3 and n+4th level transmission signals output by the lower three-level n+3-level GOA circuit sharing unit and the lower four-level n+4th level GOA circuit sharing unit (Cout(n+3), Cout(n+4)) and the first negative potential (VGL1);
  • the second pull-down module is connected to at least the n+th output of the next four-level n+4th GOA circuit sharing unit 4 level transmission signals Cout (n+4) and the second negative potential (VGL2);
  • the first pull-down maintenance module is connected to at least a first negative potential (VGL1), a high potential (VGH), and a node QB; the second pull-down maintenance module is connected to at least a node QB;
  • the feedback module is connected to at least the M+2 and M+3th clock signals CK (M+2), CK (M+3), and the nth and n+1th stage transmission signals (Cout(n) , Cout(n+1));
  • nth-level GOA circuit sharing unit in addition to the first-level and second-level GOA circuit sharing unit:
  • the pull-up control module includes: an eleventh thin film transistor, the gate of the eleventh thin film transistor is connected to the n-2th stage transmission signal Cout( n-2), the source is connected to the M-th clock signal CK(M), and the drain is electrically connected to the second node N; and
  • the twelfth thin film transistor, the gate of the twelfth thin film transistor is connected to the n-2th level transmission signal Cout(n-2) output by the upper two-level n-2th level GOA circuit sharing unit, and the source electrode Is electrically connected to the second node N, and the drain is electrically connected to the first node Q;
  • the pull-up module includes:
  • the twenty-first thin film transistor, the gate of the twenty-first thin film transistor is electrically connected to the first node Q, the source is connected to the M+3th clock signal CK (M+3), and the drain is electrically connected to The n+1th scan signal G(n+1) output by the next-stage n+1th-stage GOA circuit sharing unit;
  • the twenty-second thin film transistor The gate of the twenty-second thin film transistor is electrically connected to the first node Q, the source is connected to the M+2th clock signal CK (M+2), and the drain is electrically connected to The nth scan signal G(n);
  • the twenty-third thin film transistor, the gate of the twenty-third thin film transistor is electrically connected to the first node Q, the source is connected to the M+3th clock signal CK (M+3), and the drain is electrically connected to The n+1th stage transmission signal Cout(n+1) output by the next stage n+1th stage GOA circuit sharing unit;
  • the gate of the twenty-fourth thin film transistor is electrically connected to the first node Q, the source is connected to the M+2th clock signal CK (M+2), and the drain is electrically connected The signal Cout(n) is transmitted at the nth level.
  • the second pull-down module includes: a thirty-first thin film transistor, and the gate of the thirty-first thin film transistor is electrically connected to the lower four-level n+4th GOA circuit
  • the n+4th level transmission signal Cout(n+4) output by the sharing unit, the source is electrically connected to the n+1th scan signal G(n+1) output by the next level n+1th GOA circuit sharing unit ), the drain is electrically connected to the second negative potential (VGL2).
  • the first pull-down module includes: a thirty-second thin film transistor, and the gate of the thirty-second thin film transistor is electrically connected to the next three levels of n+3th GOA
  • the source is electrically connected to the nth scanning signal G(n)
  • the drain is electrically connected to the second negative potential (VGL2);
  • the thirty-third thin film transistor, the gate of the thirty-third thin film transistor is electrically connected to the n+4th level transmission signal Cout(n+4) output by the lower four-level n+4th level GOA circuit sharing unit,
  • the source is electrically connected to the first node Q, and the drain is electrically connected to the second node N;
  • the gate of the thirty-fourth thin film transistor is electrically connected to the n+4th stage transmission signal Cout(n+4) output by the lower four-stage n+4th GOA circuit sharing unit ,
  • the source is electrically connected to the second node N, and the drain is electrically connected to the first negative potential (VGL1).
  • the first pull-down sustaining module includes: a forty-third thin film transistor, a forty-fourth thin film transistor, a forty-fifth thin film transistor, a forty-sixth thin film transistor, and a fourth thin film transistor. Fifty-first thin-film transistor, fifty-second thin-film transistor, fifty-third thin-film transistor, and fifty-fourth thin-film transistor;
  • the gate of the forty-third thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the n+1th stage transmission signal Cout(n+ 1)
  • the drain is electrically connected to the second negative potential (VGL2)
  • the gate of the forty-fourth thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the first output of the n-th GOA circuit sharing unit n level transmission signals Cout(n)
  • the drain is electrically connected to the second negative potential (VGL2)
  • the gate of the forty-fifth thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the second node N, the drain is electrically connected to the first negative potential (VGL1)
  • the gate of the forty-sixth thin film transistor is electrically connected to the third node QB, the source is electrically connected to the first node Q, and the drain is electrically connected to the second Two node N;
  • the fifty-first thin film transistor and the fifty-second thin film transistor are first double-gate transistors, and the fifty-third thin film transistor and the fifty-fourth thin film transistor are second double-gate transistors;
  • the first double-gate transistor includes a source transistor and a drain transistor, and the source transistor and the drain transistor have a gate, a source, and a drain, respectively.
  • the source of the source transistor And the gate is electrically connected to a high potential (VGH)
  • the drain of the source transistor is electrically connected to the source of the drain transistor
  • the gate of the drain transistor is electrically connected to the first node Q
  • the The drain of the drain transistor is electrically connected to the first negative potential (VGL1);
  • the second double-gate transistor includes a source transistor and a drain transistor, and the source transistor and the drain transistor respectively have a gate, a source, and a drain.
  • the gate of the source transistor The drain of the source transistor of the first double-gate transistor is electrically connected, the source of the source transistor is electrically connected to a high potential (VGH), and the drain of the source transistor is electrically connected to the The source of the drain transistor is electrically connected to the third node QB, the gate of the drain transistor is electrically connected to the first node Q, and the drain of the drain transistor is electrically connected to the first negative potential (VGL1).
  • the second pull-down sustain module includes: a forty-first thin film transistor and a forty-second thin film transistor;
  • the gate of the forty-first thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the n+1th scan signal G(n+1 ), the drain is electrically connected to the second negative potential (VGL2); the gate of the forty-second thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the nth output of the nth level GOA circuit sharing unit For the scanning signal G(n), the drain is electrically connected to the second negative potential (VGL2).
  • the feedback module includes a sixty-first thin film transistor and a sixty-second thin film transistor;
  • the gate of the 61st thin film transistor is electrically connected to the M+2th clock signal CK (M+2), and the source is electrically connected to the nth stage transmission signal Cout( n), the drain is electrically connected to the second node N; the gate of the 62nd thin film transistor is electrically connected to the M+3th clock signal CK(M+3), and the source is electrically connected to the second node N , The drain is electrically connected to the n+1th stage transmission signal Cout(n+1) output by the next stage n+1th stage GOA circuit sharing unit.
  • the gates of the eleventh thin film transistor and the twelfth thin film transistor are electrically connected to the start signal of the circuit ( STV).
  • the GOA circuit provided by the embodiment of the present invention includes six clock signals: the first, second, third, fourth, fifth, and sixth clock signals (CK(1), CK(2), CK( 3), CK(4), CK(5), CK(6)); when the Mth clock signal (CK(M)) is the second clock signal (CK(2)), the M+th clock signal Two clock signals (CK(M+2)) are the fourth clock signal (CK(4)), and the M+3 clock signal (CK(M+3)) is the fifth clock signal (CK(5)).
  • the pull-up module is connected to the fourth and fifth clock signals (CK(4), CK(5)), and the pull-up control module is connected to The second clock signal (CK(2)), the feedback module is connected to the fourth and fifth clock signals (CK(4), CK(5)); in the lower two-level GOA circuit sharing unit, the upper The pull control module accesses the M-th clock signal CK (M), where the M-th clock signal is the fourth clock signal.
  • the embodiment of the present invention also provides a GOA circuit, including: cascaded multi-level GOA circuit sharing units, each level of GOA circuit sharing unit includes: a feedback module, a pull-up control module, a pull-up module, a bootstrap capacitor module, First and second pull-down maintenance modules and first and second pull-down modules;
  • the pull-up control module, the bootstrap capacitor module, the pull-up module, the first and second pull-down maintenance modules, and the first and second pull-down modules are all electrically connected to the first node Q; so The feedback module is electrically connected to the second node N;
  • the pull-up module accesses the M+2 and M+3th clock signals CK (M+2) and CK (M+3), and uses the M+2 and M+3th clock signals CK (M+2), CK (M+3) output the nth and n+1th stage transmission signals (Cout(n), Cout(n+1)) and the nth and n+1th scan signals (G (n), G(n+1));
  • the pull-up control module accesses the Mth clock signal CK(M) and the n-2th level transmission signal Cout(n-2) output by the upper two-level n-2th level GOA circuit sharing unit, and uses all The n-2th stage transmission signal Cout(n-2) charges the first node Q;
  • the first pull-down module is connected to at least the n+3 and n+4th level transmission signals output by the lower three-level n+3-level GOA circuit sharing unit and the lower four-level n+4th level GOA circuit sharing unit (Cout(n+3), Cout(n+4)) and the first negative potential (VGL1);
  • the second pull-down module is connected to at least the n+th output of the next four-level n+4th GOA circuit sharing unit 4 level transmission signals Cout (n+4) and the second negative potential (VGL2);
  • the first pull-down maintenance module is connected to at least a first negative potential (VGL1), a high potential (VGH), and a node QB; the second pull-down maintenance module is connected to at least a node QB;
  • the feedback module is connected to at least the M+2 and M+3th clock signals CK (M+2), CK (M+3), and the nth and n+1th stage transmission signals (Cout(n) , Cout(n+1)).
  • the nth-stage GOA circuit sharing unit in addition to the first-stage and second-stage GOA circuit sharing units, in the nth-stage GOA circuit sharing unit:
  • the pull-up control module includes: an eleventh thin film transistor, the gate of the eleventh thin film transistor is connected to the n-2th stage transmission signal Cout( n-2), the source is connected to the M-th clock signal CK(M), and the drain is electrically connected to the second node N; and
  • the twelfth thin film transistor, the gate of the twelfth thin film transistor is connected to the n-2th level transmission signal Cout(n-2) output by the upper two-level n-2th level GOA circuit sharing unit, and the source electrode
  • the drain is electrically connected to the second node N, and the drain is electrically connected to the first node Q.
  • the pull-up module includes:
  • the twenty-first thin film transistor, the gate of the twenty-first thin film transistor is electrically connected to the first node Q, the source is connected to the M+3th clock signal CK (M+3), and the drain is electrically connected to The n+1th scan signal G(n+1) output by the next-stage n+1th-stage GOA circuit sharing unit;
  • the twenty-second thin film transistor The gate of the twenty-second thin film transistor is electrically connected to the first node Q, the source is connected to the M+2th clock signal CK (M+2), and the drain is electrically connected to The nth scan signal G(n);
  • the twenty-third thin film transistor, the gate of the twenty-third thin film transistor is electrically connected to the first node Q, the source is connected to the M+3th clock signal CK (M+3), and the drain is electrically connected to The n+1th stage transmission signal Cout(n+1) output by the next stage n+1th stage GOA circuit sharing unit;
  • the gate of the twenty-fourth thin film transistor is electrically connected to the first node Q, the source is connected to the M+2th clock signal CK (M+2), and the drain is electrically connected The signal Cout(n) is transmitted at the nth level.
  • the second pull-down module includes: a thirty-first thin film transistor, and the gate of the thirty-first thin film transistor is electrically connected to the lower four-level n+4th GOA circuit
  • the n+4th level transmission signal Cout(n+4) output by the sharing unit, the source is electrically connected to the n+1th scan signal G(n+1) output by the next level n+1th GOA circuit sharing unit ), the drain is electrically connected to the second negative potential (VGL2).
  • the first pull-down module includes: a thirty-second thin film transistor, and the gate of the thirty-second thin film transistor is electrically connected to the next three levels of n+3th GOA
  • the stage transmission signal Cout(n+3) output by the circuit sharing unit, the source is electrically connected to the nth scanning signal G(n), and the drain is electrically connected to the second negative potential (VGL2);
  • the thirty-third thin film transistor, the gate of the thirty-third thin film transistor is electrically connected to the n+4th level transmission signal Cout(n+4) output by the lower four-level n+4th level GOA circuit sharing unit,
  • the source is electrically connected to the first node Q, and the drain is electrically connected to the second node N;
  • the gate of the thirty-fourth thin film transistor is electrically connected to the n+4th stage transmission signal Cout(n+4) output by the lower four-stage n+4th GOA circuit sharing unit ,
  • the source is electrically connected to the second node N, and the drain is electrically connected to the first negative potential (VGL1).
  • the first pull-down sustaining module includes: a forty-third thin film transistor, a forty-fourth thin film transistor, a forty-fifth thin film transistor, a forty-sixth thin film transistor, and a fourth thin film transistor. Fifty-first thin-film transistor, fifty-second thin-film transistor, fifty-third thin-film transistor, and fifty-fourth thin-film transistor;
  • the gate of the forty-third thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the n+1th stage transmission signal Cout(n+ 1)
  • the drain is electrically connected to the second negative potential (VGL2)
  • the gate of the forty-fourth thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the first output of the n-th GOA circuit sharing unit n level transmission signals Cout(n)
  • the drain is electrically connected to the second negative potential (VGL2)
  • the gate of the forty-fifth thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the second node N, the drain is electrically connected to the first negative potential (VGL1)
  • the gate of the forty-sixth thin film transistor is electrically connected to the third node QB, the source is electrically connected to the first node Q, and the drain is electrically connected to the second Two node N;
  • the fifty-first thin film transistor and the fifty-second thin film transistor are first double-gate transistors, and the fifty-third thin film transistor and the fifty-fourth thin film transistor are second double-gate transistors;
  • the first double-gate transistor includes a source transistor and a drain transistor, and the source transistor and the drain transistor have a gate, a source, and a drain, respectively.
  • the source of the source transistor And the gate is electrically connected to a high potential (VGH)
  • the drain of the source transistor is electrically connected to the source of the drain transistor
  • the gate of the drain transistor is electrically connected to the first node Q
  • the The drain of the drain transistor is electrically connected to the first negative potential (VGL1);
  • the second double-gate transistor includes a source transistor and a drain transistor, and the source transistor and the drain transistor respectively have a gate, a source, and a drain.
  • the gate of the source transistor The drain of the source transistor of the first double-gate transistor is electrically connected, the source of the source transistor is electrically connected to a high potential (VGH), and the drain of the source transistor is electrically connected to the The source of the drain transistor is electrically connected to the third node QB, the gate of the drain transistor is electrically connected to the first node Q, and the drain of the drain transistor is electrically connected to the first negative potential (VGL1).
  • the second pull-down sustain module includes: a forty-first thin film transistor and a forty-second thin film transistor;
  • the gate of the forty-first thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the n+1th scan signal G(n+1 ), the drain is electrically connected to the second negative potential (VGL2); the gate of the forty-second thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the nth output of the nth level GOA circuit sharing unit For the scanning signal G(n), the drain is electrically connected to the second negative potential (VGL2).
  • the feedback module includes a sixty-first thin film transistor and a sixty-second thin film transistor;
  • the gate of the 61st thin film transistor is electrically connected to the M+2th clock signal CK (M+2), and the source is electrically connected to the nth stage transmission signal Cout( n), the drain is electrically connected to the second node N; the gate of the 62nd thin film transistor is electrically connected to the M+3th clock signal CK(M+3), and the source is electrically connected to the second node N , The drain is electrically connected to the n+1th stage transmission signal Cout(n+1) output by the next stage n+1th stage GOA circuit sharing unit.
  • the gates of the eleventh thin film transistor and the twelfth thin film transistor are electrically connected to the start signal of the circuit ( STV).
  • the GOA circuit provided by the embodiment of the present invention includes six clock signals: the first, second, third, fourth, fifth, and sixth clock signals (CK(1), CK(2), CK( 3), CK(4), CK(5), CK(6)); when the Mth clock signal (CK(M)) is the second clock signal (CK(2)), the M+th clock signal Two clock signals (CK(M+2)) are the fourth clock signal (CK(4)), and the M+3 clock signal (CK(M+3)) is the fifth clock signal (CK(5)).
  • the pull-up module is connected to the fourth and fifth clock signals (CK(4), CK(5)), and the pull-up control module is connected to The second clock signal (CK(2)), the feedback module is connected to the fourth and fifth clock signals (CK(4), CK(5)); in the lower two-level GOA circuit sharing unit, the upper The pull control module accesses the M-th clock signal CK (M), where the M-th clock signal is the fourth clock signal.
  • the present invention provides a GOA circuit.
  • the GOA circuit designs the circuit structure to form a GOA sharing unit with two adjacent two-pole GOA units in the traditional GOA circuit.
  • the new GOA circuit can realize every two-stage GOA output signal Sharing a single-stage GOA circuit, the new GOA circuit can reduce the number of thin film transistors in the GOA circuit and reduce the wiring design, which is conducive to reducing the design space of the GOA circuit to achieve a narrow frame design. At the same time, it can reduce GOA due to the simplified GOA circuit The power consumption of the circuit.
  • FIG. 1 is a structural diagram of a single-stage GOA circuit provided by an embodiment of the present invention.
  • FIG. 2 is a timing diagram of a GOA circuit provided by an embodiment of the present invention.
  • FIG. 3 is a timing signal waveform diagram of the GOA circuit provided by an embodiment of the present invention.
  • FIG. 4 is a signal waveform diagram of the first-stage and second-stage GOA circuits of the GOA circuit provided by the embodiment of the present invention.
  • the present invention provides a GOA circuit, including: cascaded multi-level GOA circuit sharing units, each level of GOA circuit sharing unit includes: a feedback module 101, a pull-up control module 102, a bootstrap capacitor module 103, a pull-up module 104, The first and second pull-down maintenance modules 105, 107 and the first and second pull-down modules 106, 108;
  • the pull-up control module 102, the bootstrap capacitor module 103, the pull-up module 104, the first and second pull-down maintenance modules 105, 107, and the first and second pull-down modules 106, 108 are all Is electrically connected to the first node Q; the feedback module 101 is electrically connected to the second node N;
  • the pull-up module 104 accesses the M+2 and M+3th clock signals CK (M+2) and CK (M+3), and uses the M+2 and M+3th clock signals CK (M+2), CK (M+3) output the nth and n+1th stage transmission signals (Cout(n), Cout(n+1)) and the nth and n+1th scan signals ( G(n), G(n+1));
  • the pull-up control module 102 accesses the M-th clock signal CK(M) and the n-2th stage transmission signal Cout(n-2) output by the upper two-stage n-2th stage GOA circuit sharing unit, and uses The n-2th stage transmission signal Cout(n-2) charges the first node Q;
  • the first pull-down module 106 is connected to at least the n+3 and n+4th levels output by the lower three-level n+3th level GOA circuit sharing unit and the lower four-level n+4th level GOA circuit sharing unit.
  • the second pull-down module 108 is connected to at least the fourth level output of the n+4th level GOA circuit sharing unit n+4 level transmission signals Cout (n+4) and the second negative potential (VGL2);
  • the first pull-down maintenance module 105 is connected to at least a first negative potential (VGL1), a high potential (VGH), and a third node QB; the second pull-down maintenance module 107 is connected to at least a third node QB;
  • the feedback module 101 is connected to at least the M+2 and M+3th clock signals CK(M+2), CK(M+3), and the nth and n+1th stage transmission signals (Cout(n ), Cout(n+1)).
  • FIG. 1 is a diagram of an embodiment of the GOA circuit of the present invention. Assume that M and n are both positive integers.
  • the In the level GOA circuit sharing unit except for the first-stage and second-stage GOA circuit sharing units, the In the level GOA circuit sharing unit:
  • the pull-up control module 102 of this embodiment is composed of two thin film transistors, and its function is to raise the potential of the first node Q and control the opening time of the pull-up circuit.
  • the pull-up control module 102 includes: an eleventh thin film transistor T11, and the gate of the eleventh thin film transistor T11 is connected to the n-2th stage output of the upper two stages of the n-2th stage GOA circuit sharing unit.
  • the source is connected to the M-th clock signal CK(M), and the drain is electrically connected to the second node N; and
  • the twelfth thin film transistor T12, the gate of the twelfth thin film transistor T12 is connected to the n-2th stage transmission signal Cout(n-2) output by the upper two-stage n-2th stage GOA circuit sharing unit, and the source
  • the pole is electrically connected to the second node N
  • the drain is electrically connected to the first node Q.
  • the pull-up module 104 of this embodiment is mainly responsible for transforming clock signals into graded transmission signals (Cout(n), Cout(n+1)) and output scan signals (G(n), G(n+1)) .
  • the pull-up module 104 includes: a twenty-first thin film transistor T21, the gate of the twenty-first thin film transistor T21 is electrically connected to the first node Q, and the source is connected to the M+3th clock signal CK (M +3) The drain is electrically connected to the n+1th scan signal G(n+1) output by the GOA circuit sharing unit of the next stage (n+1);
  • the twenty-second thin film transistor T22, the gate of the twenty-second thin film transistor T22 is electrically connected to the first node Q, the source is connected to the M+2th clock signal CK (M+2), and the drain is electrically connected Connected to the nth scan signal G(n);
  • the twenty-third thin film transistor T23, the gate of the twenty-third thin film transistor T23 is electrically connected to the first node Q, the source is connected to the M+3th clock signal CK (M+3), and the drain is electrically connected Connected to the n+1th stage transmission signal Cout(n+1) output by the next stage n+1th stage GOA circuit sharing unit;
  • the gate of the twenty-fourth thin film transistor T24 is electrically connected to the first node Q, the source is connected to the M+2th clock signal CK (M+2), and the drain is electrically connected It is connected to the nth level transmission signal Cout(n).
  • the pull-down module of this embodiment mainly includes: a first pull-down module 106 and a second pull-down module 108.
  • the pull-down module is responsible for combining the first node Q potential with the output scan signal (G(n), G(n) at the first time. +1)) Pull down to a low level.
  • the first pull-down module 106 includes: a thirty-second thin film transistor T32, the gate of the thirty-second thin film transistor T32 is electrically connected to the stage transmission signal output by the next three stage n+3 stage GOA circuit sharing unit Cout(n+3), the source is electrically connected to the nth scanning signal G(n), and the drain is electrically connected to the second negative potential (VGL2);
  • the thirty-third thin film transistor T33, the gate of the thirty-third thin film transistor T33 is electrically connected to the n+4th level transmission signal Cout(n+4 ), the source is electrically connected to the first node Q, and the drain is electrically connected to the second node N;
  • the gate of the thirty-fourth thin film transistor T34 is electrically connected to the n+4th level transmission signal Cout(n+ 4)
  • the source is electrically connected to the second node N, and the drain is electrically connected to the first negative potential (VGL1).
  • the second pull-down module 108 includes: a thirty-first thin film transistor T31, the gate of the thirty-first thin film transistor T31 is electrically connected to the n+4th output of the lower four-level n+4th GOA circuit sharing unit
  • the source of the transmission signal Cout(n+4) is electrically connected to the n+1 scan signal G(n+1) output by the GOA circuit sharing unit of the next stage (n+1), and the drain is electrically connected to the first scan signal G(n+1).
  • Two negative potentials (VGL2) Two negative potentials
  • the pull-down maintenance module of this embodiment mainly includes: a first pull-down maintenance module 105 and a second pull-down maintenance module 107.
  • the pull-down maintenance module is responsible for maintaining and pulling down the first node Q, the level transmission signal (Cout(n), Cout( n+1)) and the potential of the scan signal (G(n), G(n+1)).
  • the first pull-down maintenance module 105 includes: a forty-third thin film transistor T43, a forty-fourth thin film transistor T44, a forty-fifth thin film transistor T45, a forty-sixth thin film transistor T46, and a fifty-first thin film transistor T51 , Fifty-second thin film transistor T52, fifty-third thin film transistor T53, and fifty-fourth thin film transistor T54;
  • the gate of the forty-third thin film transistor T43 is electrically connected to the third node QB, and the source is electrically connected to the n+1th stage transmission signal Cout(n +1), the drain is electrically connected to the second negative potential (VGL2); the gate of the forty-fourth T44 thin film transistor is electrically connected to the third node QB, and the source is electrically connected to the output of the n-th GOA circuit sharing unit
  • the n-th level transmission signal Cout(n) of, the drain is electrically connected to the second negative potential (VGL2);
  • the gate of the forty-fifth thin film transistor T45 is electrically connected to the third node QB, and the source is electrically connected
  • the fifty-first thin film transistor T51 and the fifty-second thin film transistor T52 are first double-gate transistors, and the fifty-third thin film transistor T53 and the fifty-fourth thin film transistor T54 are second double-gate transistors.
  • the first double-gate transistor includes a source transistor (the fifty-first thin film transistor T51) and a drain transistor (the fifty-second thin film transistor T52), and the source transistor (the fifty-second thin film transistor T52)
  • the fifty-first thin film transistor T51) and the drain transistor (the fifty-second thin film transistor T52) respectively have a gate, a source and a drain, and the source transistor (the fifty-first thin film transistor
  • the source and gate of T51) are electrically connected to a high potential (VGH), and the drain of the source transistor (the fifty-first thin film transistor T51) is electrically connected to the drain transistor (the fifty-first thin film transistor T51).
  • the source of the second thin film transistor T52), the gate of the drain transistor (the fifty-second thin film transistor T52) is electrically connected to the first node Q, and the drain transistor (the fifty-second thin film transistor The drain of T52) is electrically connected to the first negative potential (VGL1);
  • the second double-gate transistor includes a source transistor (the fifty-third thin film transistor T53) and a drain transistor (the fifty-fourth thin film transistor T54), and the source transistor (the fifty-fourth thin film transistor T54)
  • the fifty-third thin film transistor T53) and the drain transistor (the fifty-fourth thin film transistor T54) respectively have a gate, a source and a drain, and the source transistor (the fifty-third thin film transistor)
  • the gate of T53) is electrically connected to the drain of the source transistor (the fifty-first thin film transistor T51) of the first double-gate transistor, and the source transistor (the fifty-third thin film transistor
  • the source of T53) is electrically connected to a high potential (VGH), and the drain of the source transistor (the fifty-third thin film transistor T53) is electrically connected to the drain transistor (the fifty-fourth thin film transistor
  • the source of T54) is electrically connected to the third node QB, the gate of the drain transistor (the fifty-fourth thin film transistor T54)
  • the second pull-down maintenance module 107 includes: a forty-first thin film transistor T41 and a forty-second thin film transistor T42;
  • the gate of the forty-first thin film transistor T41 is electrically connected to the third node QB, and the source is electrically connected to the n+1th scan signal G(n+ 1)
  • the drain is electrically connected to the second negative potential (VGL2)
  • the gate of the forty-second thin film transistor T42 is electrically connected to the third node QB, and the source is electrically connected to the output of the n-th stage GOA circuit sharing unit
  • the nth scan signal G(n) is electrically connected to the second negative potential (VGL2).
  • the feedback module 101 of this embodiment is responsible for raising the potential of the second node N, which is beneficial to suppress the leakage of the first node Q and maintain the potential of the first node Q.
  • the feedback module 101 includes a sixty-first thin film transistor T61 and a sixty-second thin film transistor T62;
  • the gate of the 61st thin film transistor T61 is electrically connected to the M+2th clock signal CK (M+2), and the source is electrically connected to the nth stage transmission signal Cout output by the nth stage GOA circuit sharing unit (n), the drain is electrically connected to the second node N; the gate of the 62nd thin film transistor T62 is electrically connected to the M+3th clock signal CK (M+3), and the source is electrically connected to the second The node N, the drain is electrically connected to the n+1th stage transmission signal Cout(n+1) output by the next stage n+1th stage GOA circuit sharing unit.
  • the function of the bootstrap capacitor module 103 in this embodiment is to be responsible for the secondary raising of the potential of the first node Q, which is beneficial to the output of the scan signal G(n).
  • the bootstrap capacitor module 103 includes a capacitor (Cbt), one end of the capacitor (Cbt) is electrically connected to the first node Q, and the other end is electrically connected to the n-th stage transmission signal Cout(n).
  • the gates of the eleventh thin film transistor T11 and the twelfth thin film transistor T12 are electrically connected to the start signal STV of the circuit.
  • the GOA circuit includes six clock signals: the first, second, third, fourth, fifth, and sixth clock signals (CK(1), CK (2), CK(3), CK(4), CK(5), CK(6)); when the Mth clock signal (CK(M)) is the second clock signal (CK(2) ), the M+2 clock signal (CK(M+2)) is the fourth clock signal (CK(4)), the M+3 clock signal (CK(M+3)) is the fifth Clock signal (CK(5)); when the Mth clock signal (CK(M)) is the fourth clock signal (CK(4)), the M+2th clock signal (CK(M+2) )) is the sixth clock signal (CK(6)), the M+3 clock signal (CK(M+3)) is the first clock signal (CK(1)); when the Mth clock signal When the signal (CK(M)) is the sixth clock signal (CK(6)), the M+2 clock signal (CK(M+2)) is the second clock signal (CK(2)). M+3 clock signals (CK(M+3))
  • the pull-up module 104 accesses the fourth and fifth clock signals (CK(4), CK(5)), and the pull-up control module 102
  • the second clock signal (CK(2)) is connected, and the feedback module 101 is connected to the fourth and fifth clock signals (CK(4), CK(5));
  • the pull-up control module 102 accesses the M-th clock signal CK(M), where the M-th clock signal is the fourth clock signal.
  • the second, fourth, and fifth clock signals (CK(2), CK(4), CK(5)) are AC power sources, and the high potential and the first negative potential (VGL1) and the second negative potential (VGL2) are DC power supplies.
  • this embodiment takes the first-level and second-level GOA shared circuit as an example to illustrate the working process of the circuit:
  • the eleventh thin film transistor T11 and the twelfth thin film transistor T12 are turned on, and the high potential is transmitted to the first node Q, the first node Q is at a high potential, while the twenty-first thin film transistor T21, the twenty-second thin film transistor T22, the twenty-third thin film transistor T23, and the twenty-fourth thin film transistor T24 are turned on, because the first node Q and
  • the inverter structure (the fifty-first thin film transistor T51-the fifty-fourth thin film transistor T54) is connected between the third node QB, and the potential between them is opposite.
  • the third node QB is at a low potential.
  • the thin film transistor T41, the forty-second thin film transistor T42, the forty-third thin film transistor T43, the forty-fourth thin film transistor T44, the forty-fifth thin film transistor T45, and the forty-sixth thin film transistor T46 are all turned off.
  • the fourth-level transmission signal Cout(4) and the fifth-level transmission signal Cout(5) are at low potential, the thirty-first thin film transistor T31, the thirty-second thin film transistor T32, and the thirty-third thin film transistor T33 And the thirty-fourth thin film transistor T34 is turned off, the fourth clock signal CK (4) and the fifth clock signal CK (5) are at low potential, and the first stage transmission signal Cout (1) is output, and the second stage transmission signal Cout (1) is output.
  • the signal Cout(2), the first scan signal G(1) and the second scan signal G(2) are low.
  • the fourth clock signal CK (4) rises to a high potential, and the eleventh thin film transistor T11 and the twelfth thin film transistor T12 are turned off.
  • the first node Q is subjected to the capacitive coupling effect and is raised to a higher potential
  • the third node QB maintains a low potential, the thirty-first thin film transistor T31, the thirty-second thin film transistor T32, the thirty-third thin film transistor T33, the thirty-fourth thin film transistor T34, the forty-first thin film transistor T41, and the Forty-two thin film transistors T42, forty-third thin film transistors T43, forty-fourth thin film transistors T44, forty-fifth thin-film transistors T45, and forty-sixth thin-film transistors T46 continue to be turned off.
  • the first stage transmission signal Cout (1) and the first scanning signal G(1) are high.
  • the 61st thin film transistor T61 is turned on, and the second node N is at a high potential, which reduces the leakage current of the twelfth thin film transistor T12, the 46th thin film transistor T46, and the 33rd thin film transistor T33. .
  • the fifth clock signal CK(5) rises to a high potential
  • the first node Q maintains a high potential
  • the thin film transistor T46 continues to be turned off.
  • the second level transmission signal Cout(2) and the second scan signal G(2) are at a high potential
  • the second node N is at a high potential.
  • the fourth clock signal CK (4) drops to a low level, due to the eleventh thin film transistor T11, the twelfth thin film transistor T12, the forty-fifth thin film transistor T45, the forty-sixth thin film transistor T46, and the thirty The three thin film transistors T33 and the thirty-fourth thin film transistor T34 are turned off, and the first node Q is maintained at a high potential.
  • the thirty-two thin film transistor T32 is turned on, and the first-stage transmission signal Cout(1) and the first scanning signal G are output. (1) Falling to a low potential, and the second node N maintains a high potential.
  • the fifth clock signal CK(5) drops to a low level
  • the 33rd thin film transistor T33 and the 34th thin film transistor T34 are turned on
  • the first node Q drops to a low level.
  • the twenty-first thin film transistor T21, the first The twenty-two thin film transistor T22, the twenty-third thin film transistor T23, and the twenty-fourth thin film transistor T24 are turned off.
  • the third node QB is pulled up to a high potential, the 41st thin film transistor T41, the 45th thin film transistor T45 and the 46th thin film transistor T46 are turned on, and the second stage transmits signals.
  • Cout(2) and the second scan signal G(2) are pulled to a low level.
  • the fifth-level transmission signal Cout(5) rises to a high level, the thirty-first thin-film transistor T31 is turned on, and the thirty-first thin-film transistor T31 and the forty-first thin-film transistor T41 simultaneously pull down the second-level transmission signal Cout. (2) and the potential of the second scanning signal G(2).
  • the present invention provides a GOA circuit.
  • the GOA circuit designs the circuit structure to form a GOA shared unit between two adjacent GOA units in the traditional GOA circuit.
  • the new GOA circuit can realize each The two-stage GOA output signal shares the single-stage GOA circuit.
  • the new GOA circuit can reduce the number of thin film transistors in the GOA circuit and reduce the wiring design, which is beneficial to reduce the GOA circuit design space to achieve a narrow frame design. At the same time, it simplifies the GOA Circuit, can reduce the power consumption of GOA circuit.

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Abstract

一种GOA电路，通过对电路结构进行设计，将传统的GOA电路中相邻的两级GOA单元构成一个GOA共享单元，新的GOA电路能够实现每两级GOA输出信号共享单级GOA电路，新的GOA电路可以减少GOA电路中薄膜晶体管的数量，并减少布线设计，有利于减小GOA电路设计空间，以实现窄边框设计，简化了GOA电路，可以降低GOA电路的功耗。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
 背景技术
目前有源矩阵有机发光二极体（Active-matrix organic light-emitting diode，简称AMOLED）显示面板的水平扫描线的驱动是由外接集成电路来实现的，外接集成电路可以控制各级行扫描线的逐级充电与放电，而采用阵列基板栅极驱动(Gate Driver on Array, 简称GOA)技术，GOA技术是利用薄膜晶体管 (Thin Film Transistor，简称TFT)液晶显示器阵列制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。因此GOA技术可以将行扫描驱动电路集成在显示面板的阵列基板上，显著的减少外接IC的使用量，从而降低了显示面板的生产成本以及功耗，并且能够实现显示装置的窄边框化。
 技术问题
现有的氧化物半导体阵列基板栅极驱动（IGZO-GOA）的电路较为复杂，每一级电路都包含多个工作模块，目前，大尺寸的显示面板已成为行业内发展的主要趋势，随着面板尺寸和栅极驱动行数的增加，这就导致每一级GOA电路的版图面积较大，不利于实现显示装置的窄边框化，同时负载增大也会使GOA模块功耗增加。
 技术解决方案
为解决上述技术问题，本发明提供一种GOA电路。
一种GOA电路，包括：级联的多级GOA电路共享单元，每一级GOA电路共享单元包括：反馈模块、上拉控制模块、上拉模块、自举电容模块、第一和第二下拉维持模块以及第一和第二下拉模块；
所述上拉控制模块、所述自举电容模块、所述上拉模块所述第一和第二下拉维持模块以及所述第一和第二下拉模块均电性连接于第一节点Q；所述反馈模块电性连接于第二节点N；
在所述GOA电路中，每两级GOA电路共享一级GOA电路；
设M和n为正整数，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
所述上拉模块接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3），并利用所述第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）输出第n、第n+1条级传信号（Cout(n)、Cout(n+1)）和第n、第n+1条扫描信号（G(n)、G(n+1)）；
所述上拉控制模块接入第M条时钟信号CK（M）以及上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，并利用所述第n-2条级传信号Cout(n-2)为第一节点Q充电；
所述第一下拉模块至少接入下三级第n+3级GOA电路共享单元与下四级第n+4级GOA电路共享单元输出的第n+3、第n+4条级传信号（Cout(n+3)、Cout(n+4)）和第一负电位（VGL1）；所述第二下拉模块至少接入下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)和第二负电位（VGL2）；
所述第一下拉维持模块至少接入第一负电位（VGL1）、高电位（VGH）以及节点QB；所述第二下拉维持模块至少接入节点QB；
所述反馈模块至少接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）、以及第n、第n+1条级传信号（Cout(n)、Cout(n+1)）；
其中，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
所述上拉控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极接入第M条时钟信号CK（M），漏极电性连接于第二节点N；以及
第十二薄膜晶体管，所述第十二薄膜晶体管的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极电性连接于第二节点N，漏极电性连接于第一节点Q；
其中，所述上拉模块包括：
第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)；
第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条扫描信号G(n)；
第二十三薄膜晶体管，所述第二十三薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)；
以及第二十四薄膜晶体管，所述第二十四薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条级传信号Cout(n)。
根据本发明实施例所提供的GOA电路，所述第二下拉模块包括：第三十一薄膜晶体管，所述第三十一薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）。
根据本发明实施例所提供的GOA电路，所述第一下拉模块包括：第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接下三级第n+3级GOA电路共享单元输出的级传信号Cout(n+3)，源极电性连接第第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）；
第三十三薄膜晶体管，所述第三十三薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第一节点Q，漏极电性连接第二节点N；
以及第三十四薄膜晶体管，所述第三十四薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）。
根据本发明实施例所提供的GOA电路，所述第一下拉维持模块包括：第四十三薄膜晶体管、第四十四薄膜晶体管、第四十五薄膜晶体管、第四十六薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管以及第五十四薄膜晶体管；
所述第四十三薄膜晶体管的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十四薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二负电位（VGL2）；所述第四十五薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）；所述第四十六薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第一节点Q，漏极电性连接第二节点N；
所述第五十一薄膜晶体管和所述第五十二薄膜晶体管为第一双栅晶体管，所述第五十三薄膜晶体管和所述第五十四薄膜晶体管为第二双栅晶体管；
所述第一双栅晶体管包括有一个源极晶体管和一个漏极晶体管，且所述源极晶体管和所述漏极晶体管分别具有栅极、源极和漏极，所述源极晶体管的源极和栅极电性连接高电位（VGH），所述源极晶体管的漏极电性连接所述漏极晶体管的源极，所述漏极晶体管的栅极电性连接第一节点Q，所述漏极晶体管的漏极电性连接第一负电位（VGL1）；
所述第二双栅晶体管包括有一个源极晶体管和一个漏极晶体管，且所述源极晶体管和所述漏极晶体管分别具有栅极、源极和漏极，所述源极晶体管的栅极电性连接所述第一双栅晶体管的所述源极晶体管的漏极，所述源极晶体管的源极电性连接高电位（VGH），所述源极晶体管的漏极电性连接所述漏极晶体管的源极且电性连接第三节点QB，所述漏极晶体管的栅极电性连接第一节点Q，所述漏极晶体管的漏极电性连接第一负电位（VGL1）。
根据本发明实施例所提供的GOA电路，所述第二下拉维持模块包括：第四十一薄膜晶体管以及第四十二薄膜晶体管；
所述第四十一薄膜晶体管的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十二薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）。
根据本发明实施例所提供的GOA电路，所述反馈模块包括第六十一薄膜晶体管以及第六十二薄膜晶体管；
所述第六十一薄膜晶体管的栅极电性连接第M+2条时钟信号CK（M+2），源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二节点N；所述第六十二薄膜晶体管的栅极电性连接第M+3条时钟信号CK（M+3），源极电性连接第二节点N，漏极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)。
根据本发明实施例所提供的GOA电路，在第一级与第二级GOA电路共享单元中，所述第十一薄膜晶体管与第十二薄膜晶体管的栅极电性连接电路的起始信号（STV）。
根据本发明实施例所提供的GOA电路，包括六条时钟信号：第一、第二、第三、第四、第五、及第六条时钟信号（CK（1）、CK（2）、CK（3）、CK（4）、CK（5）、CK（6））；当所述第M条时钟信号（CK（M））为第二条时钟信号（CK（2））时，第M+2条时钟信号（CK（M+2））为第四条时钟信号（CK（4）），第M+3条时钟信号（CK（M+3））为第五条时钟信号（CK（5））；当所述第M条时钟信号（CK（M））为第四条时钟信号（CK（4））时，第M+2条时钟信号（CK（M+2））为第六条时钟信号（CK（6）），第M+3条时钟信号（CK（M+3））为第一条时钟信号（CK（1））；当所述第M条时钟信号（CK（M））为第六条时钟信号（CK（6））时，第M+2条时钟信号（CK（M+2））为第二条时钟信号（CK（2）），第M+3条时钟信号（CK（M+3））为第三条时钟信号（CK（3））；
其中，第一级与第二级GOA电路共享单元中，所述上拉模块接入第四和第五条时钟信号（CK（4）、CK（5）），所述上拉控制模块接入第二条时钟信号（CK（2）），所述反馈模块接入第四和第五条时钟信号（CK（4）、CK（5））；下两级GOA电路共享单元中，所述上拉控制模块接入第M条时钟信号CK（M），其中第M条时钟信号为第四条时钟信号。
本发明实施例还提供了一种GOA电路，包括：级联的多级GOA电路共享单元，每一级GOA电路共享单元包括：反馈模块、上拉控制模块、上拉模块、自举电容模块、第一和第二下拉维持模块以及第一和第二下拉模块；
所述上拉控制模块、所述自举电容模块、所述上拉模块所述第一和第二下拉维持模块以及所述第一和第二下拉模块均电性连接于第一节点Q；所述反馈模块电性连接于第二节点N；
在所述GOA电路中，每两级GOA电路共享一级GOA电路；
设M和n为正整数，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
所述上拉模块接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3），并利用所述第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）输出第n、第n+1条级传信号（Cout(n)、Cout(n+1)）和第n、第n+1条扫描信号（G(n)、G(n+1)）；
所述上拉控制模块接入第M条时钟信号CK（M）以及上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，并利用所述第n-2条级传信号Cout(n-2)为第一节点Q充电；
所述第一下拉模块至少接入下三级第n+3级GOA电路共享单元与下四级第n+4级GOA电路共享单元输出的第n+3、第n+4条级传信号（Cout(n+3)、Cout(n+4)）和第一负电位（VGL1）；所述第二下拉模块至少接入下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)和第二负电位（VGL2）；
所述第一下拉维持模块至少接入第一负电位（VGL1）、高电位（VGH）以及节点QB；所述第二下拉维持模块至少接入节点QB；
所述反馈模块至少接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）、以及第n、第n+1条级传信号（Cout(n)、Cout(n+1)）。
根据本发明实施例所提供的GOA电路，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
所述上拉控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极接入第M条时钟信号CK（M），漏极电性连接于第二节点N；以及
第十二薄膜晶体管，所述第十二薄膜晶体管的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极电性连接于第二节点N，漏极电性连接于第一节点Q。
根据本发明实施例所提供的GOA电路，所述上拉模块包括：
第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)；
第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条扫描信号G(n)；
第二十三薄膜晶体管，所述第二十三薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)；
以及第二十四薄膜晶体管，所述第二十四薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条级传信号Cout(n)。
根据本发明实施例所提供的GOA电路，所述第二下拉模块包括：第三十一薄膜晶体管，所述第三十一薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）。
根据本发明实施例所提供的GOA电路，所述第一下拉模块包括：第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接下三级第n+3级GOA电路共享单元输出的级传信号Cout(n+3)，源极电性连接第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）；
第三十三薄膜晶体管，所述第三十三薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第一节点Q，漏极电性连接第二节点N；
以及第三十四薄膜晶体管，所述第三十四薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）。
根据本发明实施例所提供的GOA电路，所述第一下拉维持模块包括：第四十三薄膜晶体管、第四十四薄膜晶体管、第四十五薄膜晶体管、第四十六薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管以及第五十四薄膜晶体管；
所述第四十三薄膜晶体管的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十四薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二负电位（VGL2）；所述第四十五薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）；所述第四十六薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第一节点Q，漏极电性连接第二节点N；
所述第五十一薄膜晶体管和所述第五十二薄膜晶体管为第一双栅晶体管，所述第五十三薄膜晶体管和所述第五十四薄膜晶体管为第二双栅晶体管；
所述第一双栅晶体管包括有一个源极晶体管和一个漏极晶体管，且所述源极晶体管和所述漏极晶体管分别具有栅极、源极和漏极，所述源极晶体管的源极和栅极电性连接高电位（VGH），所述源极晶体管的漏极电性连接所述漏极晶体管的源极，所述漏极晶体管的栅极电性连接第一节点Q，所述漏极晶体管的漏极电性连接第一负电位（VGL1）；
所述第二双栅晶体管包括有一个源极晶体管和一个漏极晶体管，且所述源极晶体管和所述漏极晶体管分别具有栅极、源极和漏极，所述源极晶体管的栅极电性连接所述第一双栅晶体管的所述源极晶体管的漏极，所述源极晶体管的源极电性连接高电位（VGH），所述源极晶体管的漏极电性连接所述漏极晶体管的源极且电性连接第三节点QB，所述漏极晶体管的栅极电性连接第一节点Q，所述漏极晶体管的漏极电性连接第一负电位（VGL1）。
根据本发明实施例所提供的GOA电路，所述第二下拉维持模块包括：第四十一薄膜晶体管以及第四十二薄膜晶体管；
所述第四十一薄膜晶体管的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十二薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）。
根据本发明实施例所提供的GOA电路，所述反馈模块包括第六十一薄膜晶体管以及第六十二薄膜晶体管；
所述第六十一薄膜晶体管的栅极电性连接第M+2条时钟信号CK（M+2），源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二节点N；所述第六十二薄膜晶体管的栅极电性连接第M+3条时钟信号CK（M+3），源极电性连接第二节点N，漏极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)。
根据本发明实施例所提供的GOA电路，在第一级与第二级GOA电路共享单元中，所述第十一薄膜晶体管与第十二薄膜晶体管的栅极电性连接电路的起始信号（STV）。
根据本发明实施例所提供的GOA电路，包括六条时钟信号：第一、第二、第三、第四、第五、及第六条时钟信号（CK（1）、CK（2）、CK（3）、CK（4）、CK（5）、CK（6））；当所述第M条时钟信号（CK（M））为第二条时钟信号（CK（2））时，第M+2条时钟信号（CK（M+2））为第四条时钟信号（CK（4）），第M+3条时钟信号（CK（M+3））为第五条时钟信号（CK（5））；当所述第M条时钟信号（CK（M））为第四条时钟信号（CK（4））时，第M+2条时钟信号（CK（M+2））为第六条时钟信号（CK（6）），第M+3条时钟信号（CK（M+3））为第一条时钟信号（CK（1））；当所述第M条时钟信号（CK（M））为第六条时钟信号（CK（6））时，第M+2条时钟信号（CK（M+2））为第二条时钟信号（CK（2）），第M+3条时钟信号（CK（M+3））为第三条时钟信号（CK（3））；
其中，第一级与第二级GOA电路共享单元中，所述上拉模块接入第四和第五条时钟信号（CK（4）、CK（5）），所述上拉控制模块接入第二条时钟信号（CK（2）），所述反馈模块接入第四和第五条时钟信号（CK（4）、CK（5））；下两级GOA电路共享单元中，所述上拉控制模块接入第M条时钟信号CK（M），其中第M条时钟信号为第四条时钟信号。
 有益效果
本发明提供了一种GOA电路，所述GOA电路通过对电路结构进行设计，将传统的GOA电路中相邻的两极GOA单元构成一个GOA共享单元，新的GOA电路能够实现每两级GOA输出信号共享单级GOA电路，新的GOA电路可以减少GOA电路中薄膜晶体管的数量，并减少布线设计，有利于减小GOA电路设计空间，以实现窄边框设计，同时由于简化了GOA电路，可以降低GOA电路的功耗。
 附图说明
图1为本发明实施例所提供的单级GOA电路结构图。
图2为本发明实施例所提供的GOA电路的时序图。
图3为本发明实施例所提供的GOA电路的时序信号波形图。
图4为本发明实施例所提供的GOA电路的第一级与第二级GOA电路的信号波形图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的实施例及其附图进行详细描述。在图中，结构相似的单元是以相同标号表示。
本发明提供一种GOA电路，包括：级联的多级GOA电路共享单元，每一级GOA电路共享单元包括：反馈模块101、上拉控制模块102、自举电容模块103、上拉模块104、第一和第二下拉维持模块105、107以及第一和第二下拉模块106、108；
所述上拉控制模块102、所述自举电容模块103、所述上拉模块104、所述第一和第二下拉维持模105、107以及所述第一和第二下拉模块106、108均电性连接于第一节点Q；所述反馈模块101电性连接于第二节点N；
在所述GOA电路中，每两级GOA电路共享一级GOA电路；
设M和n为正整数，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
所述上拉模块104接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3），并利用所述第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）输出第n、第n+1条级传信号（Cout(n)、Cout(n+1)）和第n、第n+1条扫描信号（G(n)、G(n+1)）；
所述上拉控制模块102接入第M条时钟信号CK（M）以及上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，并利用所述第n-2条级传信号Cout(n-2)为第一节点Q充电；
所述第一下拉模块106至少接入下三级第n+3级GOA电路共享单元与下四级第n+4级GOA电路共享单元输出的第n+3、第n+4条级传信号（Cout(n+3)、Cout(n+4)）和第一负电位（VGL1）；所述第二下拉模块108至少接入下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)和第二负电位（VGL2）；
所述第一下拉维持模块105至少接入第一负电位（VGL1）、高电位（VGH）以及第三节点QB；所述第二下拉维持模块107至少接入第三节点QB；
所述反馈模块101至少接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）、以及第n、第n+1条级传信号（Cout(n)、Cout(n+1)）。
请参阅图1，为本发明的GOA电路的实施例图，设M和n均为正整数，在本发明的实施例中，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
本实施例的所述上拉控制模块102，由两个薄膜晶体管构成，其功能是拉升第一节点Q电位并控制上拉电路的打开时间。
所述上拉控制模块102包括：第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极接入第M条时钟信号CK（M），漏极电性连接于第二节点N；以及
第十二薄膜晶体管T12，所述第十二薄膜晶体管T12的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极电性连接于第二节点N，漏极电性连接于第一节点Q。
本实施例的所述上拉模块104主要负责将时钟信号转变为级传信号(Cout(n)、Cout(n+1))与输出扫描信号(G(n)、G(n+1))。
所述上拉模块104包括：第二十一薄膜晶体管T21，所述第二十一薄膜晶体管T21的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)；
第二十二薄膜晶体管T22，所述第二十二薄膜晶体管T22的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条扫描信号G(n)；
第二十三薄膜晶体管T23，所述第二十三薄膜晶体管T23的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)；
以及第二十四薄膜晶体管T24，所述第二十四薄膜晶体管T24的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条级传信号Cout(n)。
本实施例的下拉模块主要包括：第一下拉模块106和第二下拉模块108，所述下拉模块负责在第一时间将第一节点Q电位与输出扫描信号(G(n) 、G(n+1))拉低为低电位。
所述第一下拉模块106包括：第三十二薄膜晶体管T32，所述第三十二薄膜晶体管T32的栅极电性连接下三级第n+3级GOA电路共享单元输出的级传信号Cout(n+3)，源极电性连接第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）；
第三十三薄膜晶体管T33，所述第三十三薄膜晶体管T33的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第一节点Q，漏极电性连接第二节点N；
以及第三十四薄膜晶体管T34，所述第三十四薄膜晶体管T34的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）。
所述第二下拉模块108包括：第三十一薄膜晶体管T31，所述第三十一薄膜晶体管T31的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）。
本实施例的下拉维持模块主要包括：第一下拉维持模块105和第二下拉维持模块107，所述下拉维持模块负责维持与下拉第一节点Q、级传信号（Cout(n) 、Cout(n+1)）以及扫描信号（G(n) 、G(n+1)）的电位。
所述第一下拉维持模块105包括：第四十三薄膜晶体管T43、第四十四薄膜晶体管T44、第四十五薄膜晶体管T45、第四十六薄膜晶体管T46、第五十一薄膜晶体管T51、第五十二薄膜晶体管T52、第五十三薄膜晶体管T53以及第五十四薄膜晶体管T54；
所述第四十三薄膜晶体管T43的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十四T44薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二负电位（VGL2）；所述第四十五薄膜晶体管T45的栅极电性连接第三节点QB，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）；所述第四十六薄膜晶体管T46的栅极电性连接第三节点QB，源极电性连接第一节点Q，漏极电性连接第二节点N；
所述第五十一薄膜晶体管T51和所述第五十二薄膜晶体管T52为第一双栅晶体管，所述第五十三薄膜晶体管T53和所述第五十四薄膜晶体管T54为第二双栅晶体管；
所述第一双栅晶体管包括有一个源极晶体管（所述第五十一薄膜晶体管T51）和一个漏极晶体管（所述第五十二薄膜晶体管T52），且所述源极晶体管（所述第五十一薄膜晶体管T51）和所述漏极晶体管（所述第五十二薄膜晶体管T52）分别具有栅极、源极和漏极，所述源极晶体管（所述第五十一薄膜晶体管T51）的源极和栅极电性连接高电位（VGH），所述源极晶体管（所述第五十一薄膜晶体管T51）的漏极电性连接所述漏极晶体管（所述第五十二薄膜晶体管T52）的源极，所述漏极晶体管（所述第五十二薄膜晶体管T52）的栅极电性连接第一节点Q，所述漏极晶体管（所述第五十二薄膜晶体管T52）的漏极电性连接第一负电位（VGL1）；
所述第二双栅晶体管包括有一个源极晶体管（所述第五十三薄膜晶体管T53）和一个漏极晶体管（所述第五十四薄膜晶体管T54），且所述源极晶体管（所述第五十三薄膜晶体管T53）和所述漏极晶体管（所述第五十四薄膜晶体管T54）分别具有栅极、源极和漏极，所述源极晶体管（所述第五十三薄膜晶体管T53）的栅极电性连接所述第一双栅晶体管的所述源极晶体管（所述第五十一薄膜晶体管T51）的漏极，所述源极晶体管（所述第五十三薄膜晶体管T53）的源极电性连接高电位（VGH），所述源极晶体管（所述第五十三薄膜晶体管T53）的漏极电性连接所述漏极晶体管（所述第五十四薄膜晶体管T54）的源极且电性连接第三节点QB，所述漏极晶体管（所述第五十四薄膜晶体管T54）的栅极电性连接第一节点Q，所述漏极晶体管（所述第五十四薄膜晶体管T54）的漏极电性连接第一负电位（VGL1）。
所述第二下拉维持模块107包括：第四十一薄膜晶体管T41以及第四十二薄膜晶体管T42；
所述第四十一薄膜晶体管T41的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十二薄膜晶体管T42的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）。
本实施例的反馈模块101负责抬升第二节点N电位，有利于抑制第一节点Q漏电，维持第一节点Q电位。
所述反馈模块101包括第六十一薄膜晶体管T61以及第六十二薄膜晶体管T62；
所述第六十一薄膜晶体管T61的栅极电性连接第M+2条时钟信号CK（M+2），源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二节点N；所述第六十二薄膜晶体管T62的栅极电性连接第M+3条时钟信号CK（M+3），源极电性连接第二节点N，漏极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)。
本实施例的自举电容模块103的作用是负责第一节点Q电位的二次抬升，这有利于扫描信号G(n)的输出。
所述自举电容模块103包括一个电容器（Cbt），所述电容器（Cbt）的一端电性连接第一节点Q，另一端电性连接第n条级传信号Cout(n)。
具体地，在第一级与第二级GOA电路共享单元中，所述第十一薄膜晶体管T11与第十二薄膜晶体管T12的栅极电性连接电路的起始信号STV。
需要说明的是，如图2和图3所示，上述GOA电路包括六条时钟信号：第一、第二、第三、第四、第五、及第六条时钟信号（CK（1）、CK（2）、CK（3）、CK（4）、CK（5）、CK（6））；当所述第M条时钟信号（CK（M））为第二条时钟信号（CK（2））时，第M+2条时钟信号（CK（M+2））为第四条时钟信号（CK（4）），第M+3条时钟信号（CK（M+3））为第五条时钟信号（CK（5））；当所述第M条时钟信号（CK（M））为第四条时钟信号（CK（4））时，第M+2条时钟信号（CK（M+2））为第六条时钟信号（CK（6）），第M+3条时钟信号（CK（M+3））为第一条时钟信号（CK（1））；当所述第M条时钟信号（CK（M））为第六条时钟信号（CK（6））时，第M+2条时钟信号（CK（M+2））为第二条时钟信号（CK（2）），第M+3条时钟信号（CK（M+3））为第三条时钟信号（CK（3））；
其中，第一级与第二级GOA电路共享单元中，所述上拉模块104接入第四和第五条时钟信号（CK（4）、CK（5）），所述上拉控制模块102接入第二条时钟信号（CK（2）），所述反馈模块101接入第四和第五条时钟信号（CK（4）、CK（5））；下两级GOA电路共享单元中，所述上拉控制模块102接入第M条时钟信号CK（M），其中第M条时钟信号为第四条时钟信号。
具体地，其中所述第二、第四以及第五条时钟信号（CK（2）、CK（4）、CK（5））为交流电源，而其中所述高电位、所述第一负电位（VGL1）以及第二负电位（VGL2）为直流电源。
将图3中的仿真波形图带入到电路中，进行模拟仿真，得到了非常好的信号输出,如图4所示。
具体地，结合图4，本实施例以第一级与第二级GOA共享电路为例来说明电路的工作过程：
首先，当起始信号（STV）为高电位时，第二条时钟信号（CK2）同时处于高电位，第十一薄膜晶体管T11和第十二薄膜晶体管T12打开，高电位传入到第一节点Q，第一节点Q为高电位，同时第二十一薄膜晶体管T21、第二十二薄膜晶体管T22、第二十三薄膜晶体管T23与第二十四薄膜晶体管T24打开，由于第一节点Q与第三节点QB之间连接反相器结构（第五十一薄膜晶体管T51-第五十四薄膜晶体管T54），它们之间的电位相反，因此，第三节点QB处于低电位，第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、第四十四薄膜晶体管T44、第四十五薄膜晶体管T45与第四十六薄膜晶体管T46均关闭。同时，第4条级传信号Cout(4)与第5条级传信号Cout(5)处于低电位，第三十一薄膜晶体管T31、第三十二薄膜晶体管T32、第三十三薄膜晶体管T33和第三十四薄膜晶体管T34关闭，第4条时钟信号CK（4）与第5条时钟信号CK（5）处于低电位，输出第1条级传信号Cout(1),第2条级传信号Cout(2),第1条扫描信号G(1)与第2条扫描信号G(2)为低电位。
然后，第四条时钟信号CK（4）升为高电位，第十一薄膜晶体管T11与第十二薄膜晶体管T12关闭，此时，第一节点Q受到电容耦合效应，被抬到更高的电位，第三节点QB维持低电位，第三十一薄膜晶体管T31、第三十二薄膜晶体管T32、第三十三薄膜晶体管T33、第三十四薄膜晶体管T34、第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、第四十四薄膜晶体管T44、第四十五薄膜晶体管T45与第四十六薄膜晶体管T46继续关闭，此时第1条级传信号Cout(1)与第1条扫描信号G(1)为高电位。此时，第六十一薄膜晶体管T61打开，第二节点N处于高电位，该电位降低了第十二薄膜晶体管T12、第四十六薄膜晶体管T46与第三十三薄膜晶体管T33管的漏电流。
然后，第五条时钟信号CK（5）升为高电位，第一节点Q维持高电位，第三十一薄膜晶体管T31、第三十二薄膜晶体管T32、第三十三薄膜晶体管T33、第三十四薄膜晶体管T34、第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、第四十四薄膜晶体管T44、第四十五薄膜晶体管T45与第四十六薄膜晶体管T46继续关闭，此时第2条级传信号Cout(2)与第2条扫描信号G(2)为高电位，第二节点N处于高电位。
随后，第四条时钟信号CK（4）降为低电位，由于第十一薄膜晶体管T11，第十二薄膜晶体管T12，第四十五薄膜晶体管T45，第四十六薄膜晶体管T46，第三十三薄膜晶体管T33，第三十四薄膜晶体管T34关闭，第一节点Q维持高电位，同时，滴三十二薄膜晶体管T32管打开，输出第一级传信号Cout(1)与第一扫描信号G(1)降为低电位，第二节点N维持高电位。
最后第五条时钟信号CK（5）降为低电位，第三十三薄膜晶体管T33与第三十四薄膜晶体管T34打开，第一节点Q降为低电位，第二十一薄膜晶体管T21，第二十二薄膜晶体管T22，第二十三薄膜晶体管T23，第二十四薄膜晶体管T24关闭。此时由于反相器的存在，第三节点QB被拉升至高电位，第四十一薄膜晶体管T41，第四十五薄膜晶体管T45与第四十六薄膜晶体管T46打开，第2条级传信号Cout(2)与第2条扫描信号G(2)被拉至低电位。第5条级传信号Cout(5)升为高电位，第三十一薄膜晶体管T31打开，第三十一薄膜晶体管T31与第四十一薄膜晶体管T41管同时拉低第2条级传信号Cout(2)与第2条扫描信号G(2)的电位。
综上所述，本发明提供了一种GOA电路，所述GOA电路通过对电路结构进行设计，将传统的GOA电路中相邻的两极GOA单元构成一个GOA共享单元，新的GOA电路能够实现每两级GOA输出信号共享单级GOA电路，新的GOA电路可以减少GOA电路中薄膜晶体管的数量，并减少布线设计，有利于减小GOA电路设计空间，以实现窄边框设计，同时由于简化了GOA电路，可以降低GOA电路的功耗。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (18)

  1. 一种GOA电路，包括：级联的多级GOA电路共享单元，每一级GOA电路共享单元包括：反馈模块、上拉控制模块、上拉模块、自举电容模块、第一和第二下拉维持模块以及第一和第二下拉模块；
    所述上拉控制模块、所述自举电容模块、所述上拉模块所述第一和第二下拉维持模块以及所述第一和第二下拉模块均电性连接于第一节点Q；所述反馈模块电性连接于第二节点N；
    在所述GOA电路中，每两级GOA电路共享一级GOA电路；
    设M和n为正整数，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
    所述上拉模块接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3），并利用所述第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）输出第n、第n+1条级传信号（Cout(n)、Cout(n+1)）和第n、第n+1条扫描信号（G(n)、G(n+1)）；
    所述上拉控制模块接入第M条时钟信号CK（M）以及上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，并利用所述第n-2条级传信号Cout(n-2)为第一节点Q充电；
    所述第一下拉模块至少接入下三级第n+3级GOA电路共享单元与下四级第n+4级GOA电路共享单元输出的第n+3、第n+4条级传信号（Cout(n+3)、Cout(n+4)）和第一负电位（VGL1）；所述第二下拉模块至少接入下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)和第二负电位（VGL2）；
    所述第一下拉维持模块至少接入第一负电位（VGL1）、高电位（VGH）以及节点QB；所述第二下拉维持模块至少接入节点QB；
    所述反馈模块至少接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）、以及第n、第n+1条级传信号（Cout(n)、Cout(n+1)）；
    其中，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
    所述上拉控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极接入第M条时钟信号CK（M），漏极电性连接于第二节点N；以及
    第十二薄膜晶体管，所述第十二薄膜晶体管的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极电性连接于第二节点N，漏极电性连接于第一节点Q；
    其中，所述上拉模块包括：
    第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)；
    第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条扫描信号G(n)；
    第二十三薄膜晶体管，所述第二十三薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)；
    以及第二十四薄膜晶体管，所述第二十四薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条级传信号Cout(n)。
  2. 根据权利要求1所述的GOA电路，其中所述第二下拉模块包括：第三十一薄膜晶体管，所述第三十一薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）。
  3. 根据权利要求1所述的GOA电路，其中所述第一下拉模块包括：第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接下三级第n+3级GOA电路共享单元输出的级传信号Cout(n+3)，源极电性连接第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）；
    第三十三薄膜晶体管，所述第三十三薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第一节点Q，漏极电性连接第二节点N；
    以及第三十四薄膜晶体管，所述第三十四薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）。
  4. 根据权利要求1所述的GOA电路，其中所述第一下拉维持模块包括：第四十三薄膜晶体管、第四十四薄膜晶体管、第四十五薄膜晶体管、第四十六薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管以及第五十四薄膜晶体管；
    所述第四十三薄膜晶体管的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十四薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二负电位（VGL2）；所述第四十五薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）；所述第四十六薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第一节点Q，漏极电性连接第二节点N；
    所述第五十一薄膜晶体管和所述第五十二薄膜晶体管为第一双栅晶体管，所述第五十三薄膜晶体管和所述第五十四薄膜晶体管为第二双栅晶体管；
    所述第一双栅晶体管包括有一个源极晶体管和一个漏极晶体管，且所述源极晶体管和所述漏极晶体管分别具有栅极、源极和漏极，所述源极晶体管的源极和栅极电性连接高电位（VGH），所述源极晶体管的漏极电性连接所述漏极晶体管的源极，所述漏极晶体管的栅极电性连接第一节点Q，所述漏极晶体管的漏极电性连接第一负电位（VGL1）；
    所述第二双栅晶体管包括有一个源极晶体管和一个漏极晶体管，且所述源极晶体管和所述漏极晶体管分别具有栅极、源极和漏极，所述源极晶体管的栅极电性连接所述第一双栅晶体管的所述源极晶体管的漏极，所述源极晶体管的源极电性连接高电位（VGH），所述源极晶体管的漏极电性连接所述漏极晶体管的源极且电性连接第三节点QB，所述漏极晶体管的栅极电性连接第一节点Q，所述漏极晶体管的漏极电性连接第一负电位（VGL1）。
  5. 根据权利要求1所述的GOA电路，其中所述第二下拉维持模块包括：第四十一薄膜晶体管以及第四十二薄膜晶体管；
    所述第四十一薄膜晶体管的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十二薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）。
  6. 根据权利要求1所述的GOA电路，其中所述反馈模块包括第六十一薄膜晶体管以及第六十二薄膜晶体管；
    所述第六十一薄膜晶体管的栅极电性连接第M+2条时钟信号CK（M+2），源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二节点N；所述第六十二薄膜晶体管的栅极电性连接第M+3条时钟信号CK（M+3），源极电性连接第二节点N，漏极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)。
  7. 根据权利要求1所述的GOA电路，其中在第一级与第二级GOA电路共享单元中，所述第十一薄膜晶体管与第十二薄膜晶体管的栅极电性连接电路的起始信号（STV）。
  8. 根据权利要求1所述的GOA电路，其中包括六条时钟信号：第一、第二、第三、第四、第五、及第六条时钟信号（CK（1）、CK（2）、CK（3）、CK（4）、CK（5）、CK（6））；当所述第M条时钟信号（CK（M））为第二条时钟信号（CK（2））时，第M+2条时钟信号（CK（M+2））为第四条时钟信号（CK（4）），第M+3条时钟信号（CK（M+3））为第五条时钟信号（CK（5））；当所述第M条时钟信号（CK（M））为第四条时钟信号（CK（4））时，第M+2条时钟信号（CK（M+2））为第六条时钟信号（CK（6）），第M+3条时钟信号（CK（M+3））为第一条时钟信号（CK（1））；当所述第M条时钟信号（CK（M））为第六条时钟信号（CK（6））时，第M+2条时钟信号（CK（M+2））为第二条时钟信号（CK（2）），第M+3条时钟信号（CK（M+3））为第三条时钟信号（CK（3））；
    其中，第一级与第二级GOA电路共享单元中，所述上拉模块接入第四和第五条时钟信号（CK（4）、CK（5）），所述上拉控制模块接入第二条时钟信号（CK（2）），所述反馈模块接入第四和第五条时钟信号（CK（4）、CK（5））；下两级GOA电路共享单元中，所述上拉控制模块接入第M条时钟信号CK（M），其中第M条时钟信号为第四条时钟信号。
  9. 一种GOA电路，包括：级联的多级GOA电路共享单元，每一级GOA电路共享单元包括：反馈模块、上拉控制模块、上拉模块、自举电容模块、第一和第二下拉维持模块以及第一和第二下拉模块；
    所述上拉控制模块、所述自举电容模块、所述上拉模块所述第一和第二下拉维持模块以及所述第一和第二下拉模块均电性连接于第一节点Q；所述反馈模块电性连接于第二节点N；
    在所述GOA电路中，每两级GOA电路共享一级GOA电路；
    设M和n为正整数，除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
    所述上拉模块接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3），并利用所述第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）输出第n、第n+1条级传信号（Cout(n)、Cout(n+1)）和第n、第n+1条扫描信号（G(n)、G(n+1)）；
    所述上拉控制模块接入第M条时钟信号CK（M）以及上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，并利用所述第n-2条级传信号Cout(n-2)为第一节点Q充电；
    所述第一下拉模块至少接入下三级第n+3级GOA电路共享单元与下四级第n+4级GOA电路共享单元输出的第n+3、第n+4条级传信号（Cout(n+3)、Cout(n+4)）和第一负电位（VGL1）；所述第二下拉模块至少接入下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)和第二负电位（VGL2）；
    所述第一下拉维持模块至少接入第一负电位（VGL1）、高电位（VGH）以及节点QB；所述第二下拉维持模块至少接入节点QB；
    所述反馈模块至少接入第M+2和第M+3条时钟信号CK（M+2）、CK（M+3）、以及第n、第n+1条级传信号（Cout(n)、Cout(n+1)）。
  10. 根据权利要求9所述的GOA电路，其中除第一级与第二级GOA电路共享单元外，在第n级GOA电路共享单元中：
    所述上拉控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极接入第M条时钟信号CK（M），漏极电性连接于第二节点N；以及
    第十二薄膜晶体管，所述第十二薄膜晶体管的栅极接入上两级第n-2级GOA电路共享单元输出的第n-2条级传信号Cout(n-2)，源极电性连接于第二节点N，漏极电性连接于第一节点Q。
  11. 根据权利要求9所述的GOA电路，其中所述上拉模块包括：
    第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)；
    第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条扫描信号G(n)；
    第二十三薄膜晶体管，所述第二十三薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+3条时钟信号CK（M+3），漏极电性连接于下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)；
    以及第二十四薄膜晶体管，所述第二十四薄膜晶体管的栅极电性连接第一节点Q，源极接入第M+2条时钟信号CK（M+2），漏极电性连接于第n条级传信号Cout(n)。
  12. 根据权利要求9所述的GOA电路，其中所述第二下拉模块包括：第三十一薄膜晶体管，所述第三十一薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）。
  13. 根据权利要求9所述的GOA电路，其中所述第一下拉模块包括：第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接下三级第n+3级GOA电路共享单元输出的级传信号Cout(n+3)，源极电性连接第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）；
    第三十三薄膜晶体管，所述第三十三薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第一节点Q，漏极电性连接第二节点N；
    以及第三十四薄膜晶体管，所述第三十四薄膜晶体管的栅极电性连接下四级第n+4级GOA电路共享单元输出的第n+4条级传信号Cout(n+4)，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）。
  14. 根据权利要求9所述的GOA电路，其中所述第一下拉维持模块包括：第四十三薄膜晶体管、第四十四薄膜晶体管、第四十五薄膜晶体管、第四十六薄膜晶体管、第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管以及第五十四薄膜晶体管；
    所述第四十三薄膜晶体管的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十四薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二负电位（VGL2）；所述第四十五薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第二节点N，漏极电性连接第一负电位（VGL1）；所述第四十六薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第一节点Q，漏极电性连接第二节点N；
    所述第五十一薄膜晶体管和所述第五十二薄膜晶体管为第一双栅晶体管，所述第五十三薄膜晶体管和所述第五十四薄膜晶体管为第二双栅晶体管；
    所述第一双栅晶体管包括有一个源极晶体管和一个漏极晶体管，且所述源极晶体管和所述漏极晶体管分别具有栅极、源极和漏极，所述源极晶体管的源极和栅极电性连接高电位（VGH），所述源极晶体管的漏极电性连接所述漏极晶体管的源极，所述漏极晶体管的栅极电性连接第一节点Q，所述漏极晶体管的漏极电性连接第一负电位（VGL1）；
    所述第二双栅晶体管包括有一个源极晶体管和一个漏极晶体管，且所述源极晶体管和所述漏极晶体管分别具有栅极、源极和漏极，所述源极晶体管的栅极电性连接所述第一双栅晶体管的所述源极晶体管的漏极，所述源极晶体管的源极电性连接高电位（VGH），所述源极晶体管的漏极电性连接所述漏极晶体管的源极且电性连接第三节点QB，所述漏极晶体管的栅极电性连接第一节点Q，所述漏极晶体管的漏极电性连接第一负电位（VGL1）。
  15. 根据权利要求9所述的GOA电路，其中所述第二下拉维持模块包括：第四十一薄膜晶体管以及第四十二薄膜晶体管；
    所述第四十一薄膜晶体管的栅极电性连接第三节点QB，源极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条扫描信号G(n+1)，漏极电性连接第二负电位（VGL2）；所述第四十二薄膜晶体管的栅极电性连接第三节点QB，源极电性连接第n级GOA电路共享单元输出的第n条扫描信号G(n)，漏极电性连接第二负电位（VGL2）。
  16. 根据权利要求9所述的GOA电路，其中所述反馈模块包括第六十一薄膜晶体管以及第六十二薄膜晶体管；
    所述第六十一薄膜晶体管的栅极电性连接第M+2条时钟信号CK（M+2），源极电性连接第n级GOA电路共享单元输出的第n条级传信号Cout(n)，漏极电性连接第二节点N；所述第六十二薄膜晶体管的栅极电性连接第M+3条时钟信号CK（M+3），源极电性连接第二节点N，漏极电性连接下一级第n+1级GOA电路共享单元输出的第n+1条级传信号Cout(n+1)。
  17. 根据权利要求10所述的GOA电路，其中在第一级与第二级GOA电路共享单元中，所述第十一薄膜晶体管与第十二薄膜晶体管的栅极电性连接电路的起始信号（STV）。
  18. 根据权利要求9所述的GOA电路，其中包括六条时钟信号：第一、第二、第三、第四、第五、及第六条时钟信号（CK（1）、CK（2）、CK（3）、CK（4）、CK（5）、CK（6））；当所述第M条时钟信号（CK（M））为第二条时钟信号（CK（2））时，第M+2条时钟信号（CK（M+2））为第四条时钟信号（CK（4）），第M+3条时钟信号（CK（M+3））为第五条时钟信号（CK（5））；当所述第M条时钟信号（CK（M））为第四条时钟信号（CK（4））时，第M+2条时钟信号（CK（M+2））为第六条时钟信号（CK（6）），第M+3条时钟信号（CK（M+3））为第一条时钟信号（CK（1））；当所述第M条时钟信号（CK（M））为第六条时钟信号（CK（6））时，第M+2条时钟信号（CK（M+2））为第二条时钟信号（CK（2）），第M+3条时钟信号（CK（M+3））为第三条时钟信号（CK（3））；
    其中，第一级与第二级GOA电路共享单元中，所述上拉模块接入第四和第五条时钟信号（CK（4）、CK（5）），所述上拉控制模块接入第二条时钟信号（CK（2）），所述反馈模块接入第四和第五条时钟信号（CK（4）、CK（5））；下两级GOA电路共享单元中，所述上拉控制模块接入第M条时钟信号CK（M），其中第M条时钟信号为第四条时钟信号。
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