WO2021035873A1 - 一种图像传感器及图像采集系统 - Google Patents

一种图像传感器及图像采集系统 Download PDF

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Publication number
WO2021035873A1
WO2021035873A1 PCT/CN2019/109334 CN2019109334W WO2021035873A1 WO 2021035873 A1 WO2021035873 A1 WO 2021035873A1 CN 2019109334 W CN2019109334 W CN 2019109334W WO 2021035873 A1 WO2021035873 A1 WO 2021035873A1
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pixel
trigger
acquisition circuit
boundary
pixel acquisition
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PCT/CN2019/109334
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English (en)
French (fr)
Inventor
陈守顺
郭梦晗
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上海芯仑光电科技有限公司
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Priority to JP2022512780A priority Critical patent/JP7456087B2/ja
Priority to EP19943291.5A priority patent/EP4024849B1/en
Publication of WO2021035873A1 publication Critical patent/WO2021035873A1/zh
Priority to US17/680,446 priority patent/US11509853B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/44—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/47—Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/74—Circuitry for scanning or addressing the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/767—Horizontal readout lines, multiplexers or registers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to the technical field of image acquisition, in particular to an image sensor and an image acquisition system.
  • the dynamic vision image sensor (hereinafter referred to as the dynamic vision sensor) only responds to the dynamic information in the field of view, and directly captures the light intensity change in the field of view, so it is particularly suitable for applications in machine vision and other fields.
  • each pixel acquisition circuit works independently and asynchronously, and is responsible for sensing the light intensity change in the field of view. When the corresponding light intensity change is sensed, the pixel acquisition circuit outputs an event.
  • the external readout circuit is responsible for managing the entire array of pixel acquisition circuits, and read out the information of the generated events.
  • the dynamic vision sensor Since the dynamic vision sensor only responds to the dynamic information in the field of view, it saves a lot of bandwidth compared to the traditional fixed frame rate output image sensor, and has a faster response speed.
  • the pixel acquisition circuit array will generate a large number of events in a short time. Since the readout circuit has to scan and read each event one by one, the advantage of the low bandwidth of the dynamic vision sensor will not be obvious.
  • the readout of each event requires a certain amount of time, which will cause blockage of the readout channel. A large number of events generated by the pixel acquisition circuit array need to be queued for readout, which causes a large readout delay. The output delay causes the deviation of the event time information, and also has an adverse effect on the back-end application.
  • the present invention provides an image sensor and an image acquisition system to try to solve or at least alleviate at least one of the above problems.
  • an image sensor including: a pixel collection circuit array composed of a plurality of pixel collection circuits, the pixel collection circuit is adapted to monitor changes in light intensity in a field of view, and when the light intensity changes meet a certain It enters the trigger state when the conditions are met; the boundary trigger pixel judgment array is suitable for determining the trigger pixel acquisition circuit at the boundary from the pixel acquisition circuit in the trigger state; the readout unit is suitable for responding to the trigger pixel acquisition circuit at the boundary, and Output its corresponding address information.
  • the boundary-triggered pixel decision array is further adapted to generate a readout request signal and a flag bit based on the column request signal from the pixel collection circuit array, wherein the flag bit indicates the corresponding pixel collection circuit Location type.
  • the edge-triggered pixel decision array includes a plurality of edge-triggered pixel decision units, wherein the number of edge-triggered pixel decision units is the number of columns of pixel collection circuits in the pixel collection circuit array.
  • the boundary-triggered pixel decision unit includes: a readout request signal generation module adapted to generate data from the pixel acquisition circuit in the column corresponding to the boundary-triggered pixel decision unit and its adjacent columns The column request signal generates a readout request signal; the flag bit generation module is adapted to generate a flag bit based on the column request signal from the pixel acquisition circuit of the column corresponding to the boundary trigger pixel decision unit and at least one adjacent column.
  • the readout unit includes: a row selection module, adapted to respond to a row request signal from the pixel acquisition circuit array, and also adapted to output row address information for obtaining a row response;
  • the selection module is adapted to scan the corresponding pixel acquisition circuit according to the readout request signal from the boundary trigger pixel judgment array, and scan and output its corresponding column address information and flag bit; and the readout control module is adapted to control the row address Output of information and column address information.
  • the readout request signal generation module includes: a NAND gate, the input of which is coupled to the pixel acquisition circuit array, and receives two columns of pixels adjacent to the current boundary trigger pixel decision unit
  • the output terminal of the column request signal of the acquisition circuit is coupled to the input terminal of the AND gate;
  • the input terminal of the AND gate is coupled to the pixel acquisition circuit array, and receives the output of the NAND gate and the pixel determination unit corresponding to the boundary trigger.
  • the flag generation module includes: a NOT gate, the input of which is coupled to the pixel acquisition circuit array, and receives the column of the pixel acquisition circuit adjacent to the current boundary trigger pixel decision unit.
  • the output terminal of the request signal is coupled to the input terminal of the AND gate; the input terminal of the AND gate is coupled to the pixel acquisition circuit array, and receives the output of the NOT gate and the column of the pixel acquisition circuit corresponding to the boundary trigger pixel decision unit.
  • Request signal is
  • the flag generating module includes: a NOR gate, the input end of which is coupled to the pixel acquisition circuit array, and receives the pixel acquisition circuits in the left and right adjacent columns of the pixel decision unit that triggers the current boundary
  • the output terminal of the column request signal is coupled to the input terminal of the AND gate;
  • the input terminal of the AND gate is coupled to the pixel acquisition circuit array to receive the output of the NOR gate and the pixel acquisition of the corresponding column of the pixel decision unit corresponding to the boundary trigger Column request signal of the circuit.
  • the image sensor according to the present invention further includes: a global control unit, adapted to reset the pixel acquisition circuit array when the image sensor is powered on, and also adapted to release the pixel acquisition circuit array when the pixel acquisition circuit array maintains a stable initial state Reset, so that the pixel acquisition circuit array starts to work.
  • a global control unit adapted to reset the pixel acquisition circuit array when the image sensor is powered on, and also adapted to release the pixel acquisition circuit array when the pixel acquisition circuit array maintains a stable initial state Reset, so that the pixel acquisition circuit array starts to work.
  • the flag bit includes one of a head flag bit, a tail flag bit, and an isolated flag bit.
  • the pixel collection circuit includes: a photodetection module, which is suitable for real-time monitoring of the light signal irradiated thereon, and outputs a corresponding electrical signal; a trigger generation module, the first input terminal of which is Is coupled to the photoelectric detection module, the first output terminal of which is coupled to the readout interface module, and the trigger generation module is adapted to generate a trigger generation signal to the readout interface module when the electrical signal meets a predetermined trigger condition; and
  • the output interface module is coupled to the trigger generation module, and is adapted to communicate with the readout unit through a row request line, a row selection line, a column request line, and a column selection line.
  • the trigger generation module includes: a filter and amplifying module, the input of which is coupled to the output of the photodetection module, and is suitable for filtering and amplifying electrical signals; a threshold comparison module, which The input terminal is coupled to the output terminal of the filtering and amplifying module, and is suitable for receiving the electric signal from the filtering and amplifying module, and when the electric signal meets a predetermined condition, a trigger generation signal is generated.
  • an image acquisition system including: the image sensor as described above; an image processor, coupled to the image sensor, adapted to trigger the pixel acquisition circuit based on the received boundary
  • the address information determines the address information of all pixel acquisition circuits in the trigger state in the image sensor.
  • the image sensor is adapted to output the address information and corresponding flag bits of the trigger pixel acquisition circuit at the boundary to the image processor; the image processor is also adapted to be based on the trigger at the boundary The address information of the pixel acquisition circuit and the corresponding flag bit determine the address information of all the pixel acquisition circuits in the trigger state in the image sensor.
  • the pixel acquisition circuit at the boundary is determined from all the pixel acquisition circuits in the trigger state, and then the event (ie, the row and column address information of the pixel acquisition circuit in the trigger state is read out in the readout unit). ), it only scans and reads the pixel acquisition circuit and its flag bit at the boundary, instead of reading the pixel acquisition circuit with multiple continuous trigger states.
  • the event ie, the row and column address information of the pixel acquisition circuit in the trigger state is read out in the readout unit.
  • FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present invention
  • Figure 2 shows a schematic diagram of three flag bits according to an embodiment of the present invention
  • FIG. 3 shows a schematic structural diagram of a boundary-triggered pixel decision array 120 according to an embodiment of the present invention
  • 4A to 4C respectively show circuit diagrams of the boundary-triggered pixel decision unit 122 according to some embodiments of the present invention.
  • FIG. 5 shows a schematic diagram of a readout scene of an image sensor according to an embodiment of the present invention.
  • Fig. 6 shows a schematic diagram of an image acquisition system 600 according to an embodiment of the present invention.
  • FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present invention.
  • the image sensor 100 can be applied to detect scenes of high-speed moving objects to output event data streams related to motion events.
  • the image sensor 100 is coupled to an external image processor, and transmits the output event data stream to the external image processor for the next calculation and application.
  • the embodiment of the present invention does not limit this.
  • the image sensor 100 includes a pixel acquisition circuit array 110, a boundary trigger pixel judgment array 120 and a readout unit 130.
  • the pixel acquisition circuit array 110 as the core part of the image sensor 100, is composed of a plurality of pixel acquisition circuits 112 uniformly distributed in the row and column direction ( Figure 1 shows a 3 ⁇ 3 pixel acquisition circuit array, which is not limited to this).
  • the boundary trigger pixel decision array 120 is respectively coupled to the pixel acquisition circuit array 110 and the readout unit 130, and the readout unit 130 is also coupled to the pixel acquisition circuit array 110.
  • the image sensor 100 also includes a global control unit 140.
  • the global control unit 140 is coupled to the pixel collection circuit array 110 to control the working state of each pixel collection circuit 112.
  • the global control unit 140 is responsible for resetting the entire pixel collection circuit array 110 when the image sensor 100 is powered on to ensure that each pixel collection circuit 112 maintains a stable initial state. Subsequently, the global control unit 140 releases the reset, and the pixel collection circuit array 110 starts to work normally.
  • the image sensor only responds to changes in the light intensity in the field of view, and its function is mainly realized by each pixel collection circuit 112.
  • the pixel collection circuit array 110 After the reset of the global control unit 140 is released, the pixel collection circuit array 110 starts to respond to changes in external light intensity. Specifically, the pixel collection circuit array 110 monitors the light intensity change in the field of view, and meets certain conditions when the light intensity changes (optionally, the condition here can be set as the light intensity change exceeds a set threshold, which is not limited to this)
  • the pixel acquisition circuit that enters the trigger state is also referred to as a triggered pixel event or event).
  • the boundary-triggered pixel decision array 120 includes a plurality of boundary-triggered pixel decision units 122, wherein the number of the boundary-triggered pixel decision units 122 is the number of columns of pixel collection circuits in the pixel collection circuit array 110 (as shown in FIG. 1, a total of 3 boundaries are included). Trigger the pixel decision unit 122).
  • each boundary trigger pixel determination unit 122 corresponds to each column of pixel acquisition circuits, and is used to receive signals from the column of pixel acquisition circuits.
  • the boundary trigger pixel determination array 120 determines the trigger pixel acquisition circuit at the boundary from the pixel acquisition circuit 112 in the triggered state. According to an embodiment of the present invention, when a pixel acquisition circuit A in a trigger state has an adjacent pixel acquisition circuit B that is not in a trigger state on the left or right side, the pixel acquisition circuit A is the triggered pixel acquisition circuit at the boundary. Circuit. Conversely, when the condition is not met, the pixel acquisition circuit A is an internal trigger pixel acquisition circuit.
  • each boundary trigger pixel decision unit 122 For each boundary trigger pixel decision unit 122, it receives a signal from a column of pixel acquisition circuits corresponding to it, and accordingly confirms which pixel acquisition circuits in the column of pixel acquisition circuits are in the trigger state; further, the boundary trigger pixel The decision array 120 then determines from these pixel acquisition circuits in the trigger state which pixel acquisition circuits are the trigger pixel acquisition circuits in the boundary.
  • the readout unit 130 is mainly responsible for managing events generated by the pixel collection circuit array 110 (that is, the pixel collection circuit in the trigger state). In an embodiment, the readout unit 130 responds to the trigger pixel acquisition circuit at the boundary and outputs its corresponding address information.
  • the address information includes row address information and column address information where the pixel acquisition circuit is located.
  • the readout unit 130 outputs the address information to an external image processor, which processes the event stream data generated by the image sensor 100, and finally generates an image frame that characterizes the movement changes in the field of view.
  • each pixel acquisition circuit 112 generally includes the following modules: a photodetection module, a trigger generation module, and a readout interface module.
  • the photoelectric detection module monitors the light signal irradiated on it in real time, and outputs the corresponding electric signal.
  • the first input end of the trigger generation module is coupled to the photodetection module, and the first output end of the trigger generation module is coupled to the readout interface module.
  • the trigger generation module generates a trigger generation signal to the readout interface module when the electrical signal meets a predetermined trigger condition.
  • the readout interface module is coupled to the trigger generation module, and communicates with the readout unit 130 through a row request line, a row selection line, a column request line, and a column selection line.
  • the trigger generation module further includes a filter amplification module and a threshold comparison module.
  • the input end of the filter amplification module is coupled with the output end of the photodetection module, and the electric signal output by the photodetection module is filtered and amplified.
  • the input terminal of the threshold value comparison module is coupled with the output terminal of the filtering and amplifying module to receive the electrical signal from the filtering and amplifying module (ie, the electrical signal after filtering and amplifying processing), and when the electrical signal meets the predetermined condition, it generates a trigger generation signal.
  • the pixel collection circuit of the dynamic vision sensor belongs to the prior art in this field, and the embodiment of the present invention does not make too many restrictions on the pixel collection circuit. Therefore, the specific structure and function of each module will not be repeated here.
  • the readout unit 130 includes a row selection module 132, a column selection module 134 and a readout control module 136.
  • the row selection module 132 manages the entire pixel collection circuit array 110 in the row direction.
  • the column selection module 134 is coupled to the boundary trigger pixel decision array 120 to manage the entire pixel acquisition circuit array 110 in the column direction through the boundary trigger pixel decision array 120.
  • the read control module 136 is respectively coupled to the row selection module 132 and the column selection module 134 to coordinate the row selection module 132 and the column selection module 134.
  • a certain pixel acquisition circuit 112 when a certain pixel acquisition circuit 112 enters the trigger state, it will set the row request line of the corresponding row to be valid.
  • the row selection module 132 in the readout unit 130 manages all row request lines in the pixel acquisition circuit array 110, and responds to a valid row request by setting the corresponding row selection line to be valid. At the same time, the address information of the selected row is output after being encoded by the row selection module 132. When the row selection line is valid, the pixel acquisition circuit 112 triggered in the row will set the corresponding column request line to be valid.
  • the boundary trigger pixel decision unit 122 corresponding to the column in the boundary trigger pixel array 120 receives the column request signal.
  • the boundary trigger pixel array 120 determines the trigger pixel acquisition circuit at the boundary according to the received column request signal, that is, the pixel acquisition circuit that really needs to be read out, and generates a corresponding readout request signal.
  • corresponding flag bits are generated for these trigger pixel acquisition circuits at the boundary, and the flag bits are used to indicate the position type of the corresponding pixel acquisition circuit, that is, the position type to which the trigger pixel acquisition circuit at the boundary belongs.
  • the position type may be a head, a tail, or an isolated position in the middle, and the corresponding flag bit is one of the head flag, the tail flag, and the isolated flag.
  • each boundary trigger pixel decision unit 122 converts the column request signal sent by the pixel acquisition circuit array 110 into a readout request signal, generates a corresponding flag bit, and outputs it to the corresponding column selection module 134.
  • the column selection module 134 receives the read request signal and the flag bit. In one embodiment, the column selection module 134 scans the corresponding pixel acquisition circuit according to the readout request signal, and scans and outputs the corresponding column address information and flag bit, so that the image processor at the back end can restore the corresponding pixel acquisition circuit according to the flag bit. Other pixel acquisition circuits in the trigger state in this row.
  • the readout control module 136 controls the output of row address information and column address information. In one embodiment, when all the pixel acquisition circuits in the trigger state of the row have been read out, the readout control module 136 notifies the row selection module 132 to perform a row change operation. The row selection module 132 cancels the row selection signal of the current row and selects the next row. The response of the row selection module 132 to the valid row request signal can be either randomly or in a fixed order, as long as it can ensure that the valid row request signal can be responded fairly. Similarly, the column selection module 134 can also scan for valid read request signals randomly or in a fixed order.
  • the image sensor 100 outputs an asynchronous event stream, where each event stream contains the row address X, column address Y, and time information T of the event (time information T means that the event is Read out, that is, the time received by the back-end image processor) and flag bit F, that is, the output event format is denoted as (X, Y, T, F).
  • FIG. 2 shows a schematic diagram of three types of identification bits according to some embodiments of the present invention.
  • the following describes the process of generating flag bits from the perspective of the above three flag bits.
  • the pixel acquisition circuits filled with "/" indicate that they are in the trigger state, that is, the second and fourth to the 9th
  • the pixel acquisition circuit enters the trigger state.
  • the left side (and right side) of the second pixel acquisition circuit, the left side of the fourth pixel acquisition circuit, and the right side of the ninth pixel acquisition circuit are all non-triggered pixel acquisition circuits.
  • the boundary trigger pixel decision array 120 can be determined that the second, fourth, and ninth three pixel acquisition circuits are the trigger pixel acquisition circuits at the boundary. On this basis, the boundary trigger pixel decision array 120 is the three A trigger pixel acquisition circuit on the boundary adds a flag bit.
  • the header flag indicates that the trigger pixel acquisition circuit at the boundary is the beginning of some continuous trigger pixel acquisition circuits. The judgment is based on whether the left side adjacent to the boundary trigger pixel acquisition circuit is the pixel acquisition circuit in the trigger state. If it is not the pixel acquisition circuit in the trigger state, the head mark position of the trigger pixel acquisition circuit at the boundary is 1; otherwise, it is set to 0. As shown in Figure 2, the header flag bits of the second, fourth, and ninth trigger pixel acquisition circuits at the boundary are 1, 1, and 0 respectively.
  • the tail flag indicates that the trigger pixel acquisition circuit at the boundary is the end of some continuous trigger pixel acquisition circuits.
  • the judgment basis is whether the right side adjacent to the trigger pixel acquisition circuit at the boundary is the pixel acquisition circuit in the trigger state. If the pixel acquisition circuit is not in the triggered state, then the tail flag position of the trigger pixel acquisition circuit at the boundary is set to 1; otherwise, it is set to 0.
  • the tail flags of the second, fourth, and ninth trigger pixel acquisition circuits at the boundary are 1, 0, and 1, respectively.
  • the isolated flag indicates that the trigger pixel acquisition circuit at the boundary is an isolated trigger pixel acquisition circuit.
  • the judgment basis is whether the left and right sides adjacent to the trigger pixel acquisition circuit at the boundary are the pixel acquisition circuits in the trigger state. If none of the pixel acquisition circuits are in the trigger state, then the isolated flag position of the trigger pixel acquisition circuit at the boundary is set to 1; otherwise, it is set to 0.
  • the isolated flag bits of the second, fourth, and ninth trigger pixel acquisition circuits at the boundary are 1, 0, and 0, respectively.
  • FIG. 3 shows a schematic structural diagram of the boundary-triggered pixel decision array 120 according to an embodiment of the present invention.
  • the boundary-triggered pixel decision array 120 is composed of N identical boundary-triggered pixel decision units 122, which are respectively denoted as: boundary-triggered pixel decision unit ⁇ 1>, boundary-triggered pixel decision unit ⁇ 2>, and boundary-triggered pixel The decision unit ⁇ 3>, ..., the boundary trigger pixel decision unit ⁇ N>.
  • N is the number of columns of the pixel collection circuit array 110.
  • Each boundary trigger pixel decision unit 122 further includes a readout request signal generation module and a flag bit generation module (not shown in FIG. 3).
  • the readout request signal generation module generates the readout request signal based on the column request signal from the pixel acquisition circuit of the column corresponding to the boundary trigger pixel decision unit 122 and the adjacent column.
  • the flag bit generation module generates flag bits based on the column request signal from the pixel acquisition circuit in the column corresponding to the boundary trigger pixel decision unit 122 and at least one adjacent column.
  • each of the other boundary-triggered pixel decision units 122 receives three column request signals, which are respectively denoted as REQ_IN, REQ_L, and REQ_R, where REQ_IN is the current column.
  • REQ_L is the column request signal of the adjacent column to the left of the current column
  • REQ_R is the column request signal of the adjacent column to the right of the current column.
  • the boundary trigger pixel decision unit ⁇ 2> its input signal is the column request signal ⁇ 2> (REQ_IN) and its left column request signal ⁇ 1> (REQ_L) and the right column request signal ⁇ 3 > (REQ_R), according to the three column request signals, the boundary trigger pixel decision unit ⁇ 2> generates a read request signal ⁇ 2> (READ_REQ) and a flag bit ⁇ 2> (FLAG) to the column selection module 134.
  • the two boundary trigger pixel decision units 122 at the beginning and the end in an embodiment according to the present invention, as long as it is determined that the corresponding pixel acquisition circuit enters the trigger state, it can be considered to be at the boundary.
  • the pixel acquisition circuit is triggered, and then the readout request signal is asserted.
  • the input signal is the column request signal ⁇ 1> (REQ_IN) and the column request signal ⁇ 2> (REQ_R) on the right side, and REQ_L is 0 by default.
  • the input signal is the column request signal ⁇ N> (REQ_IN) and the column request signal ⁇ N-1> (REQ_L) on the left, and REQ_R is 0 by default. Then, the flag bit is calculated based on this, which will not be repeated here.
  • the readout request signal generation module 1222 determines whether the corresponding pixel acquisition circuit is the trigger pixel acquisition circuit at the boundary. If the readout request signal generation module 1222 confirms that the corresponding pixel acquisition circuit is the trigger pixel acquisition circuit at the boundary, then the readout request signal is set It is valid, and the corresponding flag bit is generated by the flag bit generation module 1224. If the readout request signal generation module 1222 confirms that the corresponding pixel acquisition circuit is not a trigger pixel acquisition circuit at the boundary, then the readout request signal is invalidated.
  • These functions can be implemented by logic circuits.
  • 4A to 4C respectively show circuit diagrams of the boundary-triggered pixel decision unit 122 according to some embodiments of the present invention.
  • Figures 4A to 4C respectively show a circuit diagram for generating a head flag bit, a tail flag bit, and an isolated flag bit.
  • the read request signal generating module 1222 is composed of a NAND gate and an AND gate.
  • the input terminal of the NAND gate is coupled to the pixel acquisition circuit array, and receives column request signals (denoted as REQ_L and REQ_R, respectively) of the pixel acquisition circuits in two columns adjacent to the current boundary trigger pixel judgment unit 122.
  • the output terminal of the NAND gate is coupled to an input terminal of the AND gate, and the other input terminal of the AND gate is coupled to the pixel acquisition array, and receives the column request signal (marked by the pixel acquisition circuit) of the pixel acquisition circuit corresponding to the column of the pixel decision unit that triggers the boundary.
  • REQ_IN column request signal
  • the input of the AND gate is REQ_IN and the output of the NAND gate, and the output of the AND gate is the read request signal (denoted as READ_REQ). If and only if REQ_IN is 1 (that is, the current pixel acquisition circuit is in the trigger state) and REQ_L and REQ_R are not all 1 (that is, the pixel acquisition circuits adjacent to both sides of the current pixel acquisition circuit are not all in the trigger state), READ_REQ is 1. The read request signal is valid.
  • the flag generation module 1224 is composed of a NOT gate and an AND gate. Wherein, the input end of the NOT gate is coupled to the pixel acquisition circuit array, and receives the column request signal of the pixel acquisition circuit in a column adjacent to the current boundary trigger pixel judgment unit. Taking the header flag bit as an example, as shown in FIG. 4A, the input terminal of the NOT gate receives the column request signal (denoted as REQ_L) of the pixel acquisition circuit adjacent to the left side of the current corresponding pixel acquisition circuit.
  • REQ_L column request signal
  • the output terminal of the NOT gate is coupled to one input terminal of the AND gate, and the other input terminal of the AND gate is coupled to the pixel acquisition circuit array, and receives the column request signal (marked by the pixel acquisition circuit) of the pixel acquisition circuit corresponding to the column of the pixel decision unit that triggers the boundary.
  • REQ_IN the input of the AND gate is the output of REQ_IN and the NOT gate, and the output of the AND gate is the flag bit (denoted as FLAG). If and only if REQ_L is 0 (that is, the left pixel acquisition circuit is not in the trigger state) and REQ_IN is 1 (that is, the current pixel acquisition circuit is in the trigger state), FLAG is 1.
  • the read request signal generating module 1222 is exactly the same as that in FIG. 4A, and will not be repeated here.
  • the flag bit generation module 1224 takes the generation of the tail flag bit as an example, which is also composed of a NOT gate and an AND gate.
  • the input terminal of the NOT gate receives the column request signal (denoted as REQ_R) of the pixel acquisition circuit adjacent to the right side of the current corresponding pixel acquisition circuit.
  • the output terminal of the NOT gate is coupled to one input terminal of the AND gate, and the other input terminal of the AND gate is coupled to the pixel acquisition circuit array, and receives the column request signal (marked by the pixel acquisition circuit) of the pixel acquisition circuit corresponding to the column of the pixel decision unit that triggers the boundary.
  • REQ_IN the column request signal
  • the input of the AND gate is the output of REQ_IN and the NOT gate, and the output of the AND gate is the flag bit (denoted as FLAG). If and only if REQ_IN is 1 (that is, the current pixel acquisition circuit is in the triggered state) and REQ_R is 0 (that is, the right adjacent pixel acquisition circuit of the current pixel acquisition circuit is not in the trigger state), FLAG is 1.
  • the read request signal generating module 1222 is still the same as that in FIG. 4A, and will not be repeated here.
  • the flag bit generation module 1224 takes the generation of an isolated flag bit as an example, and is composed of a NOR gate and an AND gate.
  • the input terminal of the NOR gate is coupled to the pixel acquisition circuit array, and receives column request signals (denoted as REQ_L and REQ_R) of the pixel acquisition circuits adjacent to the current boundary trigger pixel judgment unit 122.
  • the output terminal of the NOR gate is coupled to one input terminal of the AND gate, and the other input terminal of the AND gate is coupled to the pixel acquisition circuit array, and receives the column request signal of the pixel acquisition circuit in the column corresponding to the boundary trigger pixel decision unit 122 (Denoted as REQ_IN).
  • the input of the AND gate is the output of REQ_IN and the NOR gate, and the output of the AND gate is the flag bit (denoted as FLAG).
  • REQ_IN is 1 (that is, the current pixel acquisition circuit is in the trigger state)
  • REQ_L and REQ_R are both 0 (that is, the two adjacent pixel acquisition circuits on the left and right of the current pixel acquisition circuit are not in the trigger state)
  • FLAG is 1.
  • circuit diagram of the boundary trigger pixel decision unit 122 is shown here only as an example, and the embodiment of the present invention is not limited to this. Based on the description of the related embodiments of the present invention, any logic circuit that generates the corresponding readout request signal and flag bit according to the column request signal of the pixel acquisition circuit array is within the protection scope of the present invention.
  • FIG. 5 shows a schematic diagram of a readout scene of an image sensor.
  • This scene is a scene with more dynamic information in the field of view, so the triggered pixel acquisition circuit accounts for a large proportion of the entire pixel acquisition circuit array.
  • the pixel acquisition circuit array consists of 4 rows and 10 columns. A square is used to represent a pixel acquisition circuit.
  • the triggered pixel acquisition circuit is filled with "/" to indicate.
  • the traditional dynamic vision sensor when a certain pixel acquisition circuit enters the trigger state, it will set the corresponding row request line to be valid.
  • the row selection module in the readout unit responds to a valid row request by setting its corresponding row selection line to be valid.
  • the address information of the selected row is output after being encoded by the row selection module.
  • the pixel acquisition circuit triggered in the row When the row selection line is valid, the pixel acquisition circuit triggered in the row will set the corresponding column request line to be valid.
  • the column selection module manages all column requests in the column direction. It scans all valid column request lines in the row one by one. , And output the corresponding column address after encoding. After all the triggered pixel acquisition circuits of the row have been read out, the readout control module informs the row selection unit to perform a row change operation.
  • the readout unit must read out all the pixel acquisition circuits in the trigger state in the pixel acquisition circuit array one by one, and output their row and column addresses and time information in the format of (X, Y, T).
  • the unit of time T is the time required for the dynamic vision sensor to read a pixel acquisition circuit.
  • it is set to 1 here, and it is assumed that no time is needed for line feed.
  • both the row selection module and the column selection module scan in an ascending manner.
  • the row selection module selects the first row, and then the column selection module reads out all the pixel acquisition circuits in the trigger state in the row in order from smallest to largest, and the untriggered pixel acquisition circuits are automatically ignored, that is, the output event stream For (1,2,1), (1,4,2), (1,5,3), (1,6,4), (1,7,5), (1,8,6), ( 1,9,7). Then the first line is all read, and the read control module informs the line selection module to wrap. The row selection module cancels the first row and selects the second row.
  • the column selection module reads out all the pixel acquisition circuits in the trigger state in the row from smallest to largest, that is, the output event stream is (2, 3, 8 ), (2,4,9), (2,5,10), (2,6,11), (2,8,12), (2,9,13), (2,10,14). Subsequently, the row selection module selects the third row and the fourth row successively, and the output event stream is (3,1,15), (3,2,16), (3,3,17), (3,4,18 ), (3,8,19), (3,9,20), (3,10,21), (4,3,22), (4,4,23), (4,5,24), (4,6,25).
  • the dynamic vision sensor reads a total of 25 events, which consumes 25 reading time units. Since the pixel acquisition circuit array contains a total of 40 pixel acquisition circuits, the bandwidth that the dynamic vision sensor can save in this readout method is very limited. Compared with the scanning mode in which each pixel acquisition circuit (no matter whether it is triggered or not) reads out, this readout can only save about 40% of the bandwidth. More importantly, since the entire readout consumes 25 time units, for the last pixel acquisition circuit to be read out, the time information given by the dynamic vision sensor is 25 later than its real trigger time. Time unit, resulting in the inaccuracy of time information, and bringing greater error to the back-end application of the time information.
  • the pixel acquisition circuits excited by the same moving object are closely spaced. Therefore, according to the image sensor 100 proposed by the embodiment of the present invention, when an event is read, for those pixel acquisition circuits in a continuous trigger state in the address space, only the trigger pixel acquisition circuit located at the boundary is read out instead of reading. Take the internal trigger pixel acquisition circuit, thereby reducing the data of the pixel acquisition circuit that needs to be read out, and reducing the output bandwidth and readout delay of the dynamic vision sensor.
  • the row selection module selects the first row, there are a total of 7 pixel acquisition circuits in the trigger state in the row, which are respectively in the second column and the fourth to ninth columns. Since there is no pixel acquisition circuit in the trigger state on the left and right sides of the pixel acquisition circuit in the second column (neither the first column nor the third column is triggered), the pixel acquisition circuit in the second column is the trigger pixel acquisition circuit at the boundary. Is read out. For the pixel acquisition circuits in the 4th to 9th columns, this is the 6 pixel acquisition circuits in the trigger state arranged continuously in the row direction.
  • the trigger pixel acquisition circuits at the boundary are the pixel acquisition circuits in the 4th and 9th columns, and the rest are the pixel acquisition circuits in the 4th and 9th columns. 4 are all internal pixel acquisition circuits.
  • the back-end image processor is notified through the flag bit that these two pixel acquisition circuits are on the boundary Location. Then, after the image processor receives the two pixel acquisition circuits at the boundary, it can restore the pixel acquisition circuit in the middle trigger state, thereby ensuring that the dynamic vision sensor reads out events without reducing the amount of events. Loss of valid event information.
  • the image sensor 100 no longer scans each triggered pixel acquisition circuit one by one, but first extracts the pixel acquisition circuit at the boundary, and then reads out the event (that is, the trigger state in the readout unit).
  • the row and column address information of the pixel acquisition circuit only the pixel acquisition circuit at the boundary and its flag bit are scanned and read, instead of reading the pixel acquisition circuit in a plurality of continuous trigger states.
  • Fig. 6 shows a schematic diagram of an image acquisition system 600 according to an embodiment of the present invention.
  • the image acquisition system 600 includes an image sensor 100 and an image processor 610.
  • the image processor 610 is coupled to the image sensor 100.
  • the image sensor 100 when the image sensor 100 detects that the light intensity change in the field of view satisfies a certain condition, it outputs an event data stream about the trigger event.
  • the event data stream includes the address information and corresponding flag bits of the pixel acquisition circuit at the boundary (it should be noted that the event data stream may also include time information, which is not limited to this).
  • the image sensor 100 outputs the above-mentioned event data stream to the image processor 610.
  • the image processor 610 determines the address information of all pixel acquisition circuits in the trigger state in the image sensor 100 based on the received address information and corresponding flag bits of the triggered pixel acquisition circuits in the boundary.
  • FIG. 2 Take the three kinds of flag bits as an example to illustrate the above process.
  • the image processor 610 After the image processor 610 receives the address information of the second, fourth, and ninth boundary trigger pixel acquisition circuits and the corresponding header flag bit, the image processor 610 restores all the pixel acquisition circuits in the trigger state.
  • the head flag of the second pixel acquisition circuit is 1, which means that it is at the boundary of the head to trigger the pixel acquisition circuit
  • the head flag of the fourth pixel acquisition circuit is 1, which is also at the boundary of the head.
  • the pixel acquisition circuit is triggered, which indicates that there is no pixel acquisition circuit in the trigger state on the left and right sides of the second pixel acquisition circuit.
  • the head flag bit of the 9th pixel acquisition circuit is 0, indicating that it is not at the boundary of the head to trigger the pixel acquisition circuit, and the previous 4th pixel acquisition circuit is at the boundary of the head to trigger the pixel acquisition circuit, then it indicates that the pixel acquisition circuit is triggered at the boundary of the head.
  • Columns 4 to 9 are all pixel acquisition circuits in the trigger state. In this way, it is finally determined that all the pixel acquisition circuits in the trigger state in the row are the second, fourth to ninth pixel acquisition circuits.
  • the image processor 610 After the image processor 610 receives the address information of the second, fourth, and ninth boundary trigger pixel acquisition circuits and the corresponding tail flag bit, the image processor 610 restores all the pixel acquisition circuits in the trigger state of the row. Specifically, the tail flag bit of the second pixel acquisition circuit is 1, indicating that it is the boundary trigger pixel acquisition circuit at the tail. Since this pixel acquisition circuit is the first boundary pixel acquisition circuit output by the row, then the second pixel acquisition circuit can be determined The first and third pixel acquisition circuits are not trigger state pixel acquisition circuits.
  • the tail flag bit of the fourth pixel acquisition circuit is 0, indicating that it is not the boundary trigger pixel acquisition circuit at the tail
  • the tail flag bit of the ninth pixel acquisition circuit is 1, indicating that it is the boundary trigger pixel at the tail.
  • Acquisition circuit then it indicates that the 4th to 9th columns are all pixel acquisition circuits in the trigger state. In this way, it is finally determined that all the pixel acquisition circuits in the trigger state in the row are the second, fourth to ninth pixel acquisition circuits.
  • the image processor 610 After the image processor 610 receives the address information of the second, fourth, and ninth boundary trigger pixel acquisition circuits and the corresponding isolated flag bit, the image processor 610 restores all the pixel acquisition circuits in the trigger state of the row.
  • the isolated flag bit of the second pixel acquisition circuit is 1, indicating that it is a pixel acquisition circuit in an isolated trigger state.
  • the isolated flags of the 4th pixel acquisition circuit and the 9th pixel acquisition circuit are both 0, indicating that they are not isolated trigger state pixel acquisition circuits.
  • the fourth pixel acquisition circuit is some continuous trigger state pixels. The beginning of the acquisition circuit, and the 9th pixel acquisition circuit is the end of some continuous trigger state pixel acquisition circuit.
  • the image acquisition system 600 can collect the motion information of high-speed moving objects in the field of view, and perform subsequent optical flow calculations, so as to be applied to the scenes of target detection and target tracking of high-speed moving objects, and it is not limited to this. .
  • modules or units or components of the device in the example disclosed herein can be arranged in the device as described in this embodiment, or alternatively can be positioned differently from the device in this example Of one or more devices.
  • the modules in the foregoing examples can be combined into one module or, in addition, can be divided into multiple sub-modules.
  • modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and/or processes or units are mutually exclusive, any combination can be used to compare all the features disclosed in this specification (including the accompanying claims, abstract and drawings) and any method or methods disclosed in this manner or All the processes or units of the equipment are combined. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

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Abstract

一种图像传感器（100）及图像采集系统。其中，图像传感器（100）包括：由多个像素采集电路（112）组成的像素采集电路阵列（110），像素采集电路（112）适于监测视场中的光强变化，并在光强变化满足一定条件时进入触发状态；边界触发像素判决阵列（120），适于从处于触发状态的像素采集电路中，确定出处于边界的触发像素采集电路；读出单元（130），适于响应处于边界的触发像素采集电路，并输出其对应的地址信息。

Description

一种图像传感器及图像采集系统 技术领域
本发明涉及图像采集技术领域，尤其涉及一种图像传感器及图像采集系统。
背景技术
在图像传感器的诸多应用领域之中，对运动物体的检测是其中的一个重要的方面。在该应用领域，相对于传统的图像传感器(如有源像素传感器)，动态视觉图像传感器因其独特的优势而逐渐受到人们的重视。
动态视觉图像传感器(以下简称为，动态视觉传感器)仅响应视场中的动态信息，直接捕捉视场中的光强变化，因而特别适合应用于机器视觉等领域。在动态视觉传感器中，每个像素采集电路独立异步地工作，负责感知视场中本区域的光强变化，当感知到相应的光强变化时，像素采集电路输出一个事件。外部的读出电路负责管理整个像素采集电路的阵列，将所生成的事件的信息读出。
由于动态视觉传感器仅响应视场中的动态信息，这相比于传统的固定帧率输出的图像传感器节省了大量带宽，并且具有更快的响应速度。然而，当视场中存在大量的动态信息时，例如是检测一个视场中较近的快速运动物体，像素采集电路阵列在较短的时间内会产生大量的事件。由于读出电路要逐一扫描读取每一个事件，这样动态视觉传感器低带宽的优势将不明显。此外，每个事件的读出都需要一定的时间，这样会造成读出通道的阻塞，像素采集电路阵列生成的大量事件就需要排队读出，从而造成了很大的读出延时，这个读出延时引起了事件时间信息的偏差，对后端的应用也会造成不利影响。
基于上述描述，需要一种新的图像传感器，来解决上述问题。
发明内容
本发明提供了一种图像传感器及图像采集系统，以力图解决或至少缓解上面存在的至少一个问题。
根据本发明的一个方面，提供了一种图像传感器，包括：由多个像素采集电路组成的像素采集电路阵列，像素采集电路适于监测视场中的光强变化，并在光强变化满足一定条 件时进入触发状态；边界触发像素判决阵列，适于从处于触发状态的像素采集电路中，确定出处于边界的触发像素采集电路；读出单元，适于响应处于边界的触发像素采集电路，并输出其对应的地址信息。
可选地，在根据本发明的图像传感器中，边界触发像素判决阵列还适于基于来自像素采集电路阵列的列请求信号，生成读出请求信号和标志位，其中标志位指示对应像素采集电路的位置类型。
可选地，在根据本发明的图像传感器中，边界触发像素判决阵列包括多个边界触发像素判决单元，其中边界触发像素判决单元的数目为像素采集电路阵列中像素采集电路的列数。
可选地，在根据本发明的图像传感器中，边界触发像素判决单元包括：读出请求信号生成模块，适于基于来自与该边界触发像素判决单元对应列及其相邻列的像素采集电路的列请求信号，生成读出请求信号；标志位生成模块，适于基于来自与该边界触发像素判决单元对应列及至少一个相邻列的像素采集电路的列请求信号，生成标志位。
可选地，在根据本发明的图像传感器中，读出单元包括：行选择模块，适于对来自像素采集电路阵列的行请求信号进行响应，还适于输出得到行响应的行地址信息；列选择模块，适于根据来自边界触发像素判决阵列的读出请求信号，来扫描对应的像素采集电路，并扫描输出其对应的列地址信息和标志位；以及读出控制模块，适于控制行地址信息和列地址信息的输出。
可选地，在根据本发明的图像传感器中，读出请求信号生成模块包括：与非门，其输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元相邻两列的像素采集电路的列请求信号，其输出端耦接到与门的输入端；与门，其输入端耦接到像素采集电路阵列，接收与非门的输出和与该边界触发像素判决单元对应列的像素采集电路的列请求信号。
可选地，在根据本发明的图像传感器中，标志位生成模块包括：非门，其输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元相邻一列的像素采集电路的列请求信号，其输出端耦接到与门的输入端；与门，其输入端耦接到像素采集电路阵列，接收非门的输出和与该边界触发像素判决单元对应列的像素采集电路的列请求信号。
可选地，在根据本发明的图像传感器中，标志位生成模块包括：或非门，其输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元左右相邻列的像素采集电路的列请求信号，其输出端耦接到与门的输入端；与门，其输入端耦接到像素采集电路阵列，接收或非门的输出和与该边界触发像素判决单元对应列的像素采集电路的列请求信号。
可选地，根据本发明的图像传感器还包括：全局控制单元，适于在图像传感器上电时，复位像素采集电路阵列，以及，还适于在像素采集电路阵列保持稳定的初始状态时，解除复位，使得像素采集电路阵列开始工作。
可选地，在根据本发明的图像传感器中，标志位包括头部标志位、尾部标志位、孤立标志位中的一种。
可选地，在根据本发明的图像传感器中，像素采集电路包括：光电探测模块，适于实时监测照射在其上的光信号，并输出相应的电信号；触发生成模块，其第一输入端耦接到所述光电探测模块，其第一输出端耦接到读出接口模块，触发生成模块适于在所述电信号满足预定触发条件时，生成触发生成信号给读出接口模块；以及读出接口模块，耦接到触发生成模块，适于通过行请求线、行选择线、列请求线和列选择线与读出单元进行通信。
可选地，在根据本发明的图像传感器中，触发生成模块包括：滤波放大模块，其输入端与光电探测模块的输出端耦接，适于对电信号进行滤波放大处理；阈值比较模块，其输入端与滤波放大模块的输出端耦接，适于接收来自滤波放大模块的电信号，且在该电信号满足预定条件时，生成触发生成信号。
根据本发明的又一个方面，提供了一种图像采集系统，包括：如上所述的图像传感器；图像处理器，耦接到图像传感器，适于基于所接收到的处于边界的触发像素采集电路的地址信息，确定出图像传感器中所有处于触发状态的像素采集电路的地址信息。
可选地，在根据本发明的图像采集系统中，图像传感器适于将处于边界的触发像素采集电路的地址信息及对应标志位输出给图像处理器；图像处理器还适于基于处于边界的触发像素采集电路的地址信息及对应标志位，确定出图像传感器中所有处于触发状态的像素采集电路的地址信息。
根据本发明的图像传感器，先从所有处于触发状态的像素采集电路中，确定出处于边界的像素采集电路，随后在读出单元读出事件(即，处于触发状态的像素采集电路的行列地址信息)时，仅仅扫描读出处于边界的像素采集电路及其标志位，而不用去读取连续的多个触发状态的像素采集电路。由此，不仅减少了图像传感器需要读出的事件的数据量，保证了在高动态信息场景下，动态视觉传感器低带宽的特性；而且加快了数据读取速度，降低了读出通道的阻塞，减小了读出延时。
附图说明
为了实现上述以及相关目的，本文结合下面的描述和附图来描述某些说明性方面，这些方面指示了可以实践本文所公开的原理的各种方式，并且所有方面及其等效方面旨在落 入所要求保护的主题的范围内。通过结合附图阅读下面的详细描述，本公开的上述以及其它目的、特征和优势将变得更加明显。遍及本公开，相同的附图标记通常指代相同的部件或元素。
图1示出了根据本发明一些实施例的图像传感器100的示意图；
图2示出了根据本发明一种实施例的三种标志位的示意图；
图3示出了根据本发明一个实施例的边界触发像素判决阵列120的结构示意图；
图4A至图4C分别示出了根据本发明一些实施例的边界触发像素判决单元122的电路图；
图5示出了根据本发明实施例的图像传感器的读出场景示意图；以及
图6示出了根据本发明一个实施例的图像采集系统600的示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
图1示出了根据本发明一些实施例的图像传感器100的示意图。该图像传感器100能够应用于检测高速运动物体的场景，以输出与运动事件相关的事件数据流。根据一种实现方式，该图像传感器100与外部的图像处理器相耦接，将输出的事件数据流传送给外部的图像处理器，以进行下一步的计算和应用。本发明的实施例对此不作限制。
如图1所示，图像传感器100包括像素采集电路阵列110、边界触发像素判决阵列120和读出单元130。其中，像素采集电路阵列110作为图像传感器100的核心部分，由在行列方向上均匀分布的多个像素采集电路112组成(如图1示出了一个3×3大小的像素采集电路阵列，不限于此)。边界触发像素判决阵列120分别与像素采集电路阵列110和读出单元130相耦接，读出单元130还与像素采集电路阵列110相耦接。
除此之外，图像传感器100还包括全局控制单元140。全局控制单元140耦接到像素采集电路阵列110，用来控制各像素采集电路112的工作状态。一般来说，全局控制单元140负责在图像传感器100上电时，复位整个像素采集电路阵列110，以确保每个像素采集电路112均保持稳定的初始状态。随后，全局控制单元140解除复位，像素采集电路阵列110开始正常工作。
根据本发明的实施方式，图像传感器仅响应视场中的光强变化，其功能主要是通过各像素采集电路112来实现的。当全局控制单元140的复位解除后，像素采集电路阵列110开始响应外界光强变化。具体地，像素采集电路阵列110监测视场中的光强变化，并在光强变化满足一定条件(可选地，此处的条件可以设置为光强变化超出设定的阈值，不限于此)时进入触发状态(在一种实施例中，进入触发状态的像素采集电路，或称之为触发像素事件或事件)。
边界触发像素判决阵列120包括多个边界触发像素判决单元122，其中边界触发像素判决单元122的数目为像素采集电路阵列110中像素采集电路的列数(如图1所示，共包含3个边界触发像素判决单元122)。换句话说，每个边界触发像素判决单元122与每一列像素采集电路相对应，用以接收来自该列像素采集电路的信号。
在一种实施例中，边界触发像素判决阵列120从处于触发状态的像素采集电路112中，确定出处于边界的触发像素采集电路。根据本发明的实施例，当一个处于触发状态的像素采集电路A的左侧或者右侧有一个不处于触发状态的相邻像素采集电路B时，该像素采集电路A就是处于边界的触发像素采集电路。反之，当该条件不满足时，该像素采集电路A就是处于内部的触发像素采集电路。
对于每个边界触发像素判决单元122，其接收来自与之对应的一列像素采集电路的信号，并据此确认在该列像素采集电路中，哪些像素采集电路处于触发状态；进一步地，边界触发像素判决阵列120再从这些处于触发状态的像素采集电路中，确定出哪些像素采集电路是处于边界的触发像素采集电路。
读出单元130作为像素采集电路阵列110的外围模块，主要负责管理像素采集电路阵列110所产生的事件(即，触发状态的像素采集电路)。在一种实施例中，读出单元130响应处于边界的触发像素采集电路，并输出其对应的地址信息，地址信息包括该像素采集电路所在的行地址信息和列地址信息。
在一种实施例中，读出单元130输出地址信息至外部的图像处理器，由其对图像传感器100所产生的事件流数据进行处理，最终生成表征视场内运动变化的图像帧。
以下将结合图1，对图像传感器100中各部分进行进一步说明。
为实现光强变化的实时检测、以及与外界读出电路通信等功能，每个像素采集电路112一般包含以下几个模块：光电探测模块、触发生成模块和读出接口模块。
其中，光电探测模块实时监测照射在其上的光信号，并输出相应的电信号。触发生成模块的第一输入端耦接到光电探测模块，其第一输出端耦接到读出接口模块，触发生成模块在电信号满足预定触发条件时，生成触发生成信号给读出接口模块。读出接口模块耦接 到触发生成模块，通过行请求线、行选择线、列请求线和列选择线与读出单元130进行通信。
进一步地，触发生成模块又包括滤波放大模块和阈值比较模块。滤波放大模块的输入端与光电探测模块的输出端耦接，对经光电探测模块输出的电信号进行滤波放大处理。阈值比较模块的输入端与滤波放大模块的输出端耦接，接收来自滤波放大模块的电信号(即，经滤波放大处理后的电信号)，且在该电信号满足预定条件时，生成触发生成信号。
需要说明的是，动态视觉传感器的像素采集电路属于本领域现有技术，本发明实施例对像素采集电路不做过多限制。故对各模块的具体结构和功能，此处不再赘述。
继续如图1，读出单元130包括行选择模块132、列选择模块134和读出控制模块136。其中，行选择模块132在行方向上管理整个像素采集电路阵列110。列选择模块134耦接到边界触发像素判决阵列120，以通过边界触发像素判决阵列120，在列方向上管理整个像素采集电路阵列110。读出控制模块136分别耦接到行选择模块132与列选择模块134，来协调行选择模块132与列选择模块134。
在一种实施例中，当某个像素采集电路112进入触发状态后，它会将所属行的行请求线置为有效。读出单元130中的行选择模块132管理像素采集电路阵列110中的所有行请求线，并通过将其对应的行选择线置为有效来响应一个有效的行请求。同时，被选中行的地址信息经过行选择模块132编码后输出。当行选择线有效后，该行中触发的像素采集电路112会将相应的列请求线置为有效。
此时，边界触发像素阵列120中对应该列的边界触发像素判决单元122接收该列请求信号。首先，边界触发像素阵列120根据接收到的列请求信号，确定出处于边界的触发像素采集电路，即，真正需要被读出的像素采集电路，生成相应的读出请求信号。其次，为这些处于边界的触发像素采集电路生成相应的标志位，标志位用来指示对应像素采集电路的位置类型，即处于边界的触发像素采集电路所属的位置类型。在根据本发明的实施例中，位置类型可以是头部、尾部或中间孤立位置，对应的标志位就是头部标志位、尾部标志位、孤立标志位中的一种。
综上，每个边界触发像素判决单元122将像素采集电路阵列110发出的列请求信号转换为读出请求信号，并生成相应的标志位，一并输出给对应的列选择模块134。
列选择模块134接收读出请求信号和标志位。在一种实施例中，列选择模块134根据读出请求信号来扫描对应的像素采集电路，并扫描输出其对应的列地址信息和标志位，以便于后端的图像处理器根据该标志位恢复出该行其他的处于触发状态的像素采集电路。
读出控制模块136控制行地址信息和列地址信息的输出。在一种实施例中，当该行所 有进入触发状态的像素采集电路读出完毕后，读出控制模块136通知行选择模块132进行换行操作。行选择模块132撤销当前行的行选择信号，并选中下一行。行选择模块132对有效行请求信号的响应既可以是随机地，也可以是按照某个固定的顺序进行扫描，只要确保能够公平地响应有效的行请求信号即可。同样地，列选择模块134也可以是随机地、或是按照某个固定的顺序对有效的读出请求信号进行扫描。按照如上所述的读出机制，图像传感器100输出的是异步的事件流，其中每个事件流包含有该事件的行地址X，列地址Y、时间信息T(时间信息T是指该事件被读出、也就是被后端的图像处理器接收到的时间)和标志位F，即，输出的事件格式记作(X,Y,T,F)。
进一步地，图2示出了根据本发明一些实施例的三种标识位的示意图。结合图2，下文分别从上述三种标志位的角度出发，分别描述生成标志位的过程。
假设图2示出的是像素采集电路阵列110中一行像素采集电路，以图2所示的例子，用“/”填充的像素采集电路表示处于触发状态，即，第2、第4-9个像素采集电路进入触发状态。其中，第2个像素采集电路的左侧(以及右侧)、第4个像素采集电路的左侧和第9个像素采集电路的右侧，均为非触发像素采集电路。结合前文所述，边界触发像素判决阵列120就可以确定，第2、4、9三个像素采集电路为处于边界的触发像素采集电路，在此基础之上，边界触发像素判决阵列120为这三个处于边界的触发像素采集电路添加标志位。
需要说明的是，此处所示出的三种标志位及其判断依据仅作为示例。基于本发明实施例的描述，本领域技术人员还可衍生出其他一些描述处于边界的触发像素采集电路的位置类型的方案，均在本发明的保护范围之内，此处不再一一阐述。
实施例1-头部标志位
头部标志位，即表征该处于边界的触发像素采集电路为一些连续触发像素采集电路的开头。其判断依据是与该边界触发像素采集电路相邻的左侧是否为触发状态的像素采集电路，如果不是触发状态的像素采集电路，则将该处于边界的触发像素采集电路的头部标志位置为1；反之，则置为0。如图2，第2、4、9个处于边界的触发像素采集电路的头部标志位分别为1、1、0。
实施例2-尾部标志位
尾部标志位表征该处于边界的触发像素采集电路为一些连续触发像素采集电路的结尾。其判断依据是与该处于边界的触发像素采集电路相邻的右侧是否为触发状态的像素采集电路。如果不是触发状态的像素采集电路，则将该处于边界的触发像素采集电路的尾部标志位置为1；反之，则置为0。如图2，第2、4、9个处于边界的触发像素采集电路的尾 部标志位分别为1、0、1。
实施例3-孤立标志位
孤立标志位表征该处于边界的触发像素采集电路为孤立的触发像素采集电路。其判断依据是与该处于边界的触发像素采集电路相邻的左侧和右侧是否为触发状态的像素采集电路。如果均不是触发状态的像素采集电路，则将该处于边界的触发像素采集电路的孤立标志位置为1；反之，则置为0。如图2，第2、4、9个处于边界的触发像素采集电路的孤立标志位分别为1、0、0。
为进一步说明边界触发像素判决阵列120的工作原理，图3示出了根据本发明一个实施例的边界触发像素判决阵列120的结构示意图。
如图3所示，边界触发像素判决阵列120由N个相同的边界触发像素判决单元122组成，分别记作：边界触发像素判决单元<1>、边界触发像素判决单元<2>、边界触发像素判决单元<3>、……、边界触发像素判决单元<N>。其中，N为像素采集电路阵列110的列数。每个边界触发像素判决单元122又包括读出请求信号生成模块和标志位生成模块(图3中未示出)。根据一种实施例，读出请求信号生成模块基于来自与该边界触发像素判决单元122对应列及其相邻列的像素采集电路的列请求信号，生成读出请求信号。标志位生成模块基于来自与该边界触发像素判决单元122对应列及至少一个相邻列的像素采集电路的列请求信号，生成标志位。也就是说，除了处于头尾的两个边界触发像素判决单元122外，其它每个边界触发像素判决单元122接收到3个列请求信号，分别记作REQ_IN、REQ_L、REQ_R，其中REQ_IN为当前列的列请求信号，REQ_L为当前列左侧相邻列的列请求信号，REQ_R为当前列右侧相邻列的列请求信号。如图3，对于边界触发像素判决单元<2>，其输入信号是列请求信号<2>(REQ_IN)及其左侧的列请求信号<1>(REQ_L)和右侧的列请求信号<3>(REQ_R)，根据这三个列请求信号，边界触发像素判决单元<2>生成读出请求信号<2>(READ_REQ)和标志位<2>(FLAG)至列选择模块134。
需要说明的是，对于处于头尾的两个边界触发像素判决单元122，在根据本发明的一种实施例中，只要确定其对应的像素采集电路进入触发状态，就可以认为其为处于边界的触发像素采集电路，进而将读出请求信号置为有效。例如，对于处于头部的边界触发像素判决单元<1>，其输入信号是列请求信号<1>(REQ_IN)及其右侧的列请求信号<2>(REQ_R)，默认REQ_L为0。对于处于尾部的边界触发像素判决单元<N>，其输入信号是列请求信号<N>(REQ_IN)及其左侧的列请求信号<N-1>(REQ_L)，默认REQ_R为0。而后，据此计算出标志位，此处不再赘述。
根据本发明的实施方式，对于每个边界触发像素判决单元122，如果经读出请求信号生成模块1222确认，其对应的像素采集电路是处于边界的触发像素采集电路，那么将读 出请求信号置为有效、并由标志位生成模块1224生成相应的标志位。如果经读出请求信号生成模块1222确认，其对应的像素采集电路不是处于边界的触发像素采集电路，那么将读出请求信号置为无效。这些功能可以由逻辑电路实现。
图4A至图4C分别示出了根据本发明一些实施例的边界触发像素判决单元122的电路图。
根据生成的标志位的类型不同，图4A至图4C分别给出了生成一种头部标志位、尾部标志位和孤立标志位的电路图。
在图4A中，读出请求信号生成模块1222由一个与非门和一个与门组成。其中与非门的输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元122相邻两列的像素采集电路的列请求信号(分别记作REQ_L和REQ_R)。与非门的输出端耦接到与门的一个输入端，与门的另一个输入端耦接到像素采集阵列，接收与该边界触发像素判决单元对应列的像素采集电路的列请求信号(记作REQ_IN)。这样，与门的输入就是REQ_IN以及与非门的输出，与门的输出就是读出请求信号(记作READ_REQ)。当且仅当REQ_IN为1(即，当前像素采集电路处于触发状态)且REQ_L与REQ_R不全为1(即，当前像素采集电路两侧相邻的像素采集电路不全处于触发状态)时，READ_REQ才为1，读出请求信号有效。
标志位生成模块1224由一个非门和一个与门组成。其中，非门的输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元相邻一列的像素采集电路的列请求信号。以头部标志位为例，如图4A，非门的输入端接收的是与当前对应像素采集电路左侧相邻的像素采集电路的列请求信号(记作REQ_L)。非门的输出端耦接到与门的一个输入端，与门的另一个输入端耦接到像素采集电路阵列，接收与该边界触发像素判决单元对应列的像素采集电路的列请求信号(记作REQ_IN)。这样，与门的输入就是REQ_IN和非门的输出，与门的输出就是标志位(记作FLAG)。当且仅当REQ_L为0(即，左侧像素采集电路不处于触发状态)且REQ_IN为1(即，当前像素采集电路处于触发状态)时，FLAG为1。
在图4B中，读出请求信号生成模块1222与图4A完全相同，此处不再赘述。
标志位生成模块1224以生成尾部标志位为例，也是由一个非门和一个与门组成。其中，非门的输入端接收的是与当前对应像素采集电路右侧相邻的像素采集电路的列请求信号(记作REQ_R)。非门的输出端耦接到与门的一个输入端，与门的另一个输入端耦接到像素采集电路阵列，接收与该边界触发像素判决单元对应列的像素采集电路的列请求信号(记作REQ_IN)。这样，与门的输入就是REQ_IN和非门的输出，与门的输出就是标志位(记作FLAG)。当且仅当REQ_IN为1(即，当前像素采集电路处于触发状态)且REQ_R 为0(即，当前像素采集电路的右侧相邻像素采集电路不处于触发状态)时，FLAG为1。
在图4C中，读出请求信号生成模块1222还是与图4A保持一致，此处不再赘述。
而标志位生成模块1224以生成孤立标志位为例，由一个或非门和一个与门组成。其中，或非门的输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元122左右相邻列的像素采集电路的列请求信号(记作，REQ_L和REQ_R)。或非门的输出端耦接到与门的一个输入端，与门的另一个输入端耦接到像素采集电路阵列，接收与该边界触发像素判决单元122对应列的像素采集电路的列请求信号(记作REQ_IN)。这样，与门的输入就是REQ_IN和或非门的输出，与门的输出就是标志位(记作FLAG)。当REQ_IN为1(即，当前像素采集电路处于触发状态)且REQ_L和REQ_R均为0(即，当前像素采集电路左右相邻两个像素采集电路均不处于触发状态)时，FLAG为1。
当然，此处仅作为示例，示出了边界触发像素判决单元122的电路图，本发明实施例并不局限于此。基于本发明相关实施例的阐述，任何根据像素采集电路阵列的列请求信号，来生成相应的读出请求信号和标志位的逻辑电路，均在本发明的保护范围之内。
为便于比较说明根据本发明实施例的图像传感器100的优势，图5示出了一个图像传感器的读出场景的示意图。
该场景是视场中动态信息较多的一个场景，因而触发的像素采集电路占整个像素采集电路阵列的比重较大。此场景中，像素采集电路阵列由4行10列组成。用一个方块代表一个像素采集电路，为便于区分，已触发的像素采集电路用“/”填充来表示。
先以传统的动态视觉传感器输出事件的过程为例。简而言之，在传统的动态视觉传感器中，当某个像素采集电路进入触发状态后，它会将相应的行请求线置为有效。读出单元中的行选择模块通过将其对应的行选择线置为有效来响应一个有效的行请求。同时，被选中行的地址信息经过行选择模块编码后输出。当行选择线有效后，该行中触发的像素采集电路会将相应的列请求线置为有效，列选择模块在列方向上管理所有的列请求，它逐一扫描该行所有的有效的列请求线，并将其对应的列地址进行编码后输出。当该行所有被触发的像素采集电路读出完毕后，读出控制模块通知行选择单元进行换行操作。
故，读出单元要逐一读出像素采集电路阵列中所有的处于触发状态的像素采集电路，并将它们的行列地址以及时间信息以(X,Y,T)的格式输出。其中，时间T的单位为动态视觉传感器读取一个像素采集电路所需的时间，为了表述的方便，在此取为1，同时假定换行不需要时间。在此，假定行选择模块和列选择模块均是按照从小到大的方式进行扫描。首先，行选择模块选中第一行，然后列选择模块按照从小到大的顺序依次读出该行中所有的处于触发状态的像素采集电路，未触发的像素采集电路自动忽略，即输出的事件流为 (1,2,1)、(1,4,2)、(1,5,3)、(1,6,4)、(1,7,5)、(1,8,6)、(1,9,7)。然后第一行全部读取完毕，读出控制模块通知行选择模块换行。行选择模块撤销第一行并选中第二行，列选择模块按照从小到大的顺序依次读出该行中所有的处于触发状态的像素采集电路，即输出的事件流为(2,3,8)、(2,4,9)、(2,5,10)、(2,6,11)、(2,8,12)、(2,9,13)、(2,10,14)。随后，行选择模块先后选中第三行和第四行，输出的事件流为(3,1,15)、(3,2,16)、(3,3,17)、(3,4,18)、(3,8,19)、(3,9,20)、(3,10,21)、(4,3,22)、(4,4,23)、(4,5,24)、(4,6,25)。
从整个输出的事件流可以看出，动态视觉传感器一共读出了25个事件，耗费了25个读出时间单位。由于像素采集电路阵列一共包含40个像素采集电路，在这种读出方式下，动态视觉传感器所能节省的带宽是非常有限的。相比于每个像素采集电路(不论触发与否)均读出的扫描方式，这种读出仅能节省约40％的带宽。更为重要的是，由于整个读出耗费了25个时间单位，对于最后一个被读出的像素采集电路而言，动态视觉传感器给出的时间信息相比于其真正的被触发时间晚了25个时间单位，从而造成了时间信息的不准确，为后端对该时间信息的应用带来了较大的误差。
而本申请人在研究后发现，当视场中存在较多动态信息时，这些事件在空间上的分布通常具有一定的连续性，这主要是由运动的连续性造成的。在一定的时间内，由同一个运动物体所激发的像素采集电路在空间上是紧密排列的。因此，根据本发明的实施例所提出的图像传感器100，在事件读出时，对于那些地址空间连续的触发状态的像素采集电路，仅仅读出位于边界处的触发像素采集电路，而不去读取内部的触发像素采集电路，从而减小了需要读出的像素采集电路的数据，降低了动态视觉传感器的输出带宽和读出延时。
依旧以图5的例子进行说明，当行选择模块选中第一行时，该行中一共有7个处于触发状态的像素采集电路，分别处于第2列以及第4至9列。由于第2列像素采集电路的左右两侧均没有触发状态的像素采集电路(第1列和第3列均未触发)，因此第2列的像素采集电路为处于边界的触发像素采集电路，会被读出。对于第4至9列的像素采集电路，这是在行方向上连续排列的6个触发状态的像素采集电路，其处于边界的触发像素采集电路为第4列和第9列的像素采集电路，其余4个均为内部像素采集电路。对于这连续的6个触发状态的像素采集电路，只读出边界的第4和第9个像素采集电路，并通过标志位的方式告知后端的图像处理器，这两个像素采集电路是处于边界位置的。那么图像处理器在接收到这两个处于边界的像素采集电路之后，便可恢复出中间的触发状态的像素采集电路，从而确保了在减小动态视觉传感器读出事件量的前提下，又不丢失有效事件信息。
因此，根据本发明的方案，考虑到由于物体运动的连续性，像素采集电路阵列在一定时间内产生的事件在空间上大多也是连续的。事件在空间上存在大量的冗余，如果能够将 这些冗余信息去除，那么就能够在保证不丢失有效事件的前提下减小需要读出的事件量。因此，根据本发明的图像传感器100不再逐一地扫描每个被触发的像素采集电路，而是先提取出处于边界的像素采集电路，随后在读出单元读出事件(即，处于触发状态的像素采集电路的行列地址信息)时，仅仅扫描读出处于边界的像素采集电路及其标志位，而不用去读取连续的多个触发状态的像素采集电路。由此，不仅减少了动态视觉传感器需要读出的事件的数据量，保证了在高动态信息场景下，动态视觉传感器低带宽的特性；而且加快了数据读取速度，降低了读出通道的阻塞，减小了读出延时。
图6示出了根据本发明一个实施例的图像采集系统600的示意图。如图6所示，该图像采集系统600包括图像传感器100和图像处理器610。其中，图像处理器610耦接到图像传感器100。
如前文所述，图像传感器100在检测到视场中的光强变化满足一定条件时，输出关于触发事件的事件数据流。该事件数据流包括处于边界的像素采集电路的地址信息及对应标志位(应当指出，事件数据流中还可以包含时间信息，不限于此)。图像传感器100将上述事件数据流输出给图像处理器610。
图像处理器610基于所接收到的处于边界的触发像素采集电路的地址信息及对应标志位，确定出图像传感器100中所有处于触发状态的像素采集电路的地址信息。
为进一步说明图像处理器610基于处于边界的触发像素采集电路的地址信息及对应标志位，恢复出图像传感器100中所有处于触发状态的像素采集电路的地址信息的过程，还是以图2中示出的三种标志位为例，说明上述过程。
实施例1-头部标志位
图像处理器610在接收到第2、4、9个处于边界的触发像素采集电路的地址信息以及相应的头部标志位后，恢复出所有的触发状态的像素采集电路。具体地，第2个像素采集电路的头部标志位为1，说明其是处于头部的边界触发像素采集电路，第4个像素采集电路的头部标志位是1，也是处于头部的边界触发像素采集电路，这表明第2个像素采集电路的左右两侧都没有触发状态的像素采集电路。第9个像素采集电路的头部标志位是0，说明其不是处于头部的边界触发像素采集电路，而前面的第4个像素采集电路是处于头部的边界触发像素采集电路，那么表明第4至第9列全部是触发状态的像素采集电路。如此，最终确定出该行中所有的触发状态的像素采集电路为第2、第4至第9个像素采集电路。
实施例2-尾部标志位
图像处理器610在接收到第2、4、9个处于边界的触发像素采集电路的地址信息以及相应的尾部标志位后，恢复出该行所有的触发状态的像素采集电路。具体地，第2个像素 采集电路的尾部标志位为1，说明其为处于尾部的边界触发像素采集电路，由于该像素采集电路是该行输出的第一个边界像素采集电路，那么可以确定第1个和第3个像素采集电路不是触发状态的像素采集电路。接着，第4个像素采集电路的尾部标志位是0，说明其不是处于尾部的边界触发像素采集电路，而第9个像素采集电路的尾部标志位是1，说明其是处于尾部的边界触发像素采集电路，那么表明第4至第9列全部是触发状态的像素采集电路。如此，最终确定出该行中所有的触发状态的像素采集电路为第2、第4至第9个像素采集电路。
实施例3-孤立标志位
图像处理器610在接收到第2、4、9个处于边界的触发像素采集电路的地址信息以及相应的孤立标志位后，恢复出该行所有的触发状态的像素采集电路。具体地，第2个像素采集电路的孤立标志位为1，说明其为孤立的触发状态的像素采集电路。第4个像素采集电路和第9个像素采集电路的孤立标志位均为0，说明都不是孤立的触发状态的像素采集电路，可以进一步确定出第4个像素采集电路是一些连续触发状态的像素采集电路的开头，而第9个像素采集电路是一些连续触发状态的像素采集电路的结尾。如此，最终确定出该行中所有的触发状态的像素采集电路为第2、第4至第9个像素采集电路。总之，根据本发明的图像采集系统600能够采集到视场中高速运动物体的运动信息，并进行后续的光流计算，以应用到高速运动物体的目标检测和目标跟踪的场景中，不限于此。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本公开并帮助理解各个发明方面中的一个或多个，在上面对本发明的示例性实施例的描述中，本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多特征。更确切地说，如下面的权利要求书所反映的那样，发明方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本发明的单独实施例。
本领域那些技术人员应当理解在本文所公开的示例中的设备的模块或单元或组件可以布置在如该实施例中所描述的设备中，或者可替换地可以定位在与该示例中的设备不同的一个或多个设备中。前述示例中的模块可以组合为一个模块或者此外可以分成多个子模块。
本领域那些技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变 并且把它们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及此外可以把它们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本发明的范围之内并且形成不同的实施例。例如，在下面的权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
此外，所述实施例中的一些在此被描述成可以由计算机系统的处理器或者由执行所述功能的其它装置实施的方法或方法元素的组合。因此，具有用于实施所述方法或方法元素的必要指令的处理器形成用于实施该方法或方法元素的装置。此外，装置实施例的在此所述的元素是如下装置的例子：该装置用于实施由为了实施该发明的目的的元素所执行的功能。
如在此所使用的那样，除非另行规定，使用序数词“第一”、“第二”、“第三”等等来描述普通对象仅仅表示涉及类似对象的不同实例，并且并不意图暗示这样被描述的对象必须具有时间上、空间上、排序方面或者以任意其它方式的给定顺序。
尽管根据有限数量的实施例描述了本发明，但是受益于上面的描述，本技术领域内的技术人员明白，在由此描述的本发明的范围内，可以设想其它实施例。此外，应当注意，本说明书中使用的语言主要是为了可读性和教导的目的而选择的，而不是为了解释或者限定本发明的主题而选择的。因此，在不偏离所附权利要求书的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。对于本发明的范围，对本发明所做的公开是说明性的，而非限制性的，本发明的范围由所附权利要求书限定。

Claims (14)

  1. 一种图像传感器，包括：
    由多个像素采集电路组成的像素采集电路阵列，所述像素采集电路适于监测视场中的光强变化，并在光强变化满足一定条件时进入触发状态；
    边界触发像素判决阵列，适于从处于触发状态的像素采集电路中，确定出处于边界的触发像素采集电路；
    读出单元，适于响应处于边界的触发像素采集电路，并输出其对应的地址信息。
  2. 如权利要求1所述的图像传感器，其中，
    所述边界触发像素判决阵列还适于基于来自所述像素采集电路阵列的列请求信号，生成读出请求信号和标志位，其中所述标志位指示对应像素采集电路的位置类型。
  3. 如权利要求2所述的图像传感器，其中，
    所述边界触发像素判决阵列包括多个边界触发像素判决单元，其中所述边界触发像素判决单元的数目为所述像素采集电路阵列中像素采集电路的列数。
  4. 如权利要求3所述的图像传感器，其中，所述边界触发像素判决单元包括：
    读出请求信号生成模块，适于基于来自与该边界触发像素判决单元对应列及其相邻列的像素采集电路的列请求信号，生成读出请求信号；
    标志位生成模块，适于基于来自与该边界触发像素判决单元对应列及至少一个相邻列的像素采集电路的列请求信号，生成标志位。
  5. 如权利要求1-4中任一项所述的图像传感器，其中，所述读出单元包括：
    行选择模块，适于对来自所述像素采集电路阵列的行请求信号进行响应，还适于输出得到行响应的行地址信息；
    列选择模块，适于根据来自所述边界触发像素判决阵列的所述读出请求信号，来扫描对应的像素采集电路，并扫描输出其对应的列地址信息和标志位；以及
    读出控制模块，适于控制行地址信息和列地址信息的输出。
  6. 如权利要求4所述的图像传感器，其中，所述读出请求信号生成模块包括：
    与非门，其输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元相邻 两列的像素采集电路的列请求信号，其输出端耦接到与门的输入端；
    与门，其输入端耦接到像素采集电路阵列，接收所述与非门的输出和与该边界触发像素判决单元对应列的像素采集电路的列请求信号。
  7. 如权利要求4所述的图像传感器，其中，所述标志位生成模块包括：
    非门，其输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元相邻一列的像素采集电路的列请求信号，其输出端耦接到与门的输入端；
    与门，其输入端耦接到像素采集电路阵列，接收所述非门的输出和与该边界触发像素判决单元对应列的像素采集电路的列请求信号。
  8. 如权利要求4所述的图像传感器，其中，所述标志位生成模块包括：
    或非门，其输入端耦接到像素采集电路阵列，接收与当前边界触发像素判决单元左右相邻列的像素采集电路的列请求信号，其输出端耦接到与门的输入端；
    与门，其输入端耦接到像素采集电路阵列，接收所述或非门的输出和与该边界触发像素判决单元对应列的像素采集电路的列请求信号。
  9. 如权利要求1-8中任一项所述的图像传感器，还包括：
    全局控制单元，适于在所述图像传感器上电时，复位所述像素采集电路阵列，以及，还适于在像素采集电路阵列保持稳定的初始状态时，解除复位，使得所述像素采集电路阵列开始工作。
  10. 如权利要求2-9中任一项所述的图像传感器，其中，所述标志位包括头部标志位、尾部标志位、孤立标志位中的一种。
  11. 如权利要求1-10中任一项所述的图像传感器，其中，所述像素采集电路包括：
    光电探测模块，适于实时监测照射在其上的光信号，并输出相应的电信号；
    触发生成模块，其第一输入端耦接到所述光电探测模块，其第一输出端耦接到读出接口模块，所述触发生成模块适于在所述电信号满足预定触发条件时，生成触发生成信号给读出接口模块；以及
    读出接口模块，耦接到所述触发生成模块，适于通过行请求线、行选择线、列请求线和列选择线与所述读出单元进行通信。
  12. 如权利要求11所述的图像传感器，其中，所述触发生成模块包括：
    滤波放大模块，其输入端与所述光电探测模块的输出端耦接，适于对所述电信号进行滤波放大处理；
    阈值比较模块，其输入端与所述滤波放大模块的输出端耦接，适于接收来自滤波放大模块的电信号，且在该电信号满足预定条件时，生成触发生成信号。
  13. 一种图像采集系统，包括：
    如权利要求1-12中任一项所述的图像传感器；
    图像处理器，耦接到所述图像传感器，适于基于所接收到的所述处于边界的触发像素采集电路的地址信息，确定出所述图像传感器中所有处于触发状态的像素采集电路的地址信息。
  14. 如权利要求13所述的图像采集系统，其中，
    所述图像传感器适于将所述处于边界的触发像素采集电路的地址信息及对应标志位输出给所述图像处理器；
    所述图像处理器还适于基于所述处于边界的触发像素采集电路的地址信息及对应标志位，确定出所述图像传感器中所有处于触发状态的像素采集电路的地址信息。
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