WO2021027038A1 - 基板管理控制器及其构建方法 - Google Patents

基板管理控制器及其构建方法 Download PDF

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WO2021027038A1
WO2021027038A1 PCT/CN2019/108978 CN2019108978W WO2021027038A1 WO 2021027038 A1 WO2021027038 A1 WO 2021027038A1 CN 2019108978 W CN2019108978 W CN 2019108978W WO 2021027038 A1 WO2021027038 A1 WO 2021027038A1
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openbmc
risc
management controller
baseboard management
processor
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PCT/CN2019/108978
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English (en)
French (fr)
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邹晓峰
刘同强
周玉龙
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苏州浪潮智能科技有限公司
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Priority to JP2021571556A priority Critical patent/JP7145347B2/ja
Publication of WO2021027038A1 publication Critical patent/WO2021027038A1/zh
Priority to US17/595,978 priority patent/US20220237144A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Definitions

  • the invention relates to the technical field of server system management, in particular to a substrate management controller and a construction method thereof.
  • the Baseboard Management Controller is one of the core components of the server, and is usually implemented as an ASIC on the south bridge of the server mainboard, and mainly realizes the management and control function of the whole system of the server.
  • the BMC used in the current server is based on the ARM architecture.
  • the ARM architecture has been granted intellectual property rights, so the existing BMC is not only costly, but also the security cannot be effectively guaranteed.
  • the ARM architecture needs to be authorized to use, so if manufacturers implement technical controls on the ARM architecture, it will have a serious impact on the server and embedded industries.
  • the BMC used by the user is limited by the manufacturer, and the BMC used by the user cannot be fully autonomous and controllable.
  • the present invention provides a substrate management controller and a construction method thereof to solve the problem that the substrate management controller used by the user is limited by the manufacturer and cannot realize the basic management Completely autonomous and controllable issues.
  • the first aspect of the present invention provides a baseboard management controller, which is constructed based on the RISC-V system architecture, wherein the baseboard management controller includes: a processor, a memory, and an external interface connected through an AXI bus;
  • the memory is used to store the OpenBMC system, and the OpenBMC system is obtained by cross-compiling the OpenBMC software framework by the RISC-V tool chain of the RISC-V architecture;
  • the processor is used to execute the OpenBMC system stored in the memory, and the soft core source code of the processor is generated by the RocketChip generator.
  • the external interface includes: a two-wire serial bus interface I2C, a universal serial bus interface USB, a video transmission interface VGA, an Ethernet interface Ethernet, and a high-speed serial computer Expansion bus interface PCIE.
  • the memory includes an SPI memory of the RISC-V system architecture.
  • the startup mode of the OpenBMC system is set to the SPI mode.
  • the startup mode of the OpenBMC system in the SPI mode is obtained by modifying the RISC-V startup firmware of the RISC-V system architecture.
  • Another aspect of the present invention provides a method for constructing a baseboard management controller, including:
  • the OpenBMC system is refreshed to the memory.
  • the refreshing the OpenBMC system to the memory includes:
  • the OpenBMC system is refreshed to the SPI memory of the RISC-V system architecture.
  • the external interfaces include: a two-wire serial bus interface I2C, a universal serial bus interface USB, a video transmission interface VGA, an Ethernet interface Ethernet, and High-speed serial computer expansion bus interface PCIE.
  • the method further includes:
  • the setting the startup mode of the OpenBMC system to the SPI mode includes:
  • the present invention provides a substrate management controller and a construction method thereof.
  • the substrate management controller is constructed based on the open source RISC-V system architecture.
  • the constructed substrate management controller includes: a processor connected via an AXI bus, A memory and an external interface; wherein the memory is used to store the OpenBMC system, which is obtained by cross-compiling the OpenBMC software framework by the RISC-V tool chain of the RISC-V architecture; the processor is used to execute the The OpenBMC system stored in the memory, and the soft core source code of the processor is generated by the RocketChip generator.
  • the baseboard management controller is constructed to replace the construction of the baseboard management controller based on the ARM architecture. Therefore, the baseboard management controller used by the user is no longer limited to the manufacturer, and the baseboard management controller used by the user is completely independent and controllable.
  • FIG. 1 is a schematic structural diagram of a substrate management controller according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a baseboard management controller provided by another embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a hierarchical structure of a baseboard management controller provided by an embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of a method for constructing a substrate management controller according to another embodiment of the present invention.
  • the terms “include”, “include” or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes no Other elements clearly listed, or also include elements inherent to this process, method, article or equipment. If there are no more restrictions, the element defined by the sentence “including a" does not exclude the existence of other same elements in the process, method, article, or equipment including the element.
  • the embodiment of the present invention provides a baseboard management controller constructed based on the RISC-V system architecture, as shown in FIG. 1, including:
  • the processor 101, the memory 102 and the external interface 103 are connected via the AXI bus.
  • the RISC-V system architecture is an open source instruction set architecture designed and released by the University of California, Berkeley. Since the RISC-V system architecture is open source, compared to other patent-protected system architectures, such as ARM architecture, x86 architecture, MIPS architecture, and Alpha architecture, users using the RISC-V system architecture do not need to bear high costs. , And does not require authorization, making innovation easier. Therefore, the substrate management controller provided by the embodiment of the present invention is constructed based on the open source RISC-V system architecture.
  • the memory 102 is used to store the OpenBMC system, and the OpenBMC system is obtained by cross-compiling the OpenBMC software framework by the RISC-V tool chain of the RISC-V architecture.
  • OpenBMC software framework is an open source software framework for building a complete Linux operating system image of the baseboard management controller. Therefore, the operating system of the baseboard management controller can be obtained by compiling the OpenBMC system.
  • cross-compilation can be understood as compared to local compilation.
  • a popular understanding of cross-compilation refers to compiling programs that run on other platforms under the current platform. Because, the OpenBMC system compiled on the local development platform needs to run on the baseboard management controller, not on the local development platform. Therefore, the OpenBMC software framework needs to be cross-compiled on the local development platform to obtain the OpenBMC system that can run on the baseboard management controller.
  • the baseboard management controller of the embodiment of the present invention is constructed based on the RISC-V system architecture, the operating system should be cross-compiled through the RISC-V tool chain. That is, the OpenBMC software framework is cross-compiled through the RISC-V tool chain to obtain the OpenBMC system, and the OpenBMC system is refreshed into the memory 102 of the baseboard management controller.
  • the memory 102 of the baseboard management controller adopts an SPI memory. Therefore, it is specifically to refresh the fully compiled OpenBMC system into the SPI memory of the RISC-V system architecture.
  • the startup mode of the OpenBMC system is set to the SPI mode.
  • the startup mode of the OpenBMC system is set to the SPI mode.
  • the OpenBMC system includes the Linux operating system kernel.
  • the management interface service program, the built-in IPMI management application, system firmware, and the startup loader at each stage and other management protocols and applications are all running on the Linux operating system kernel of the OpenBMC system.
  • the processor 101 of the baseboard management controller is used to execute the OpenBMC system stored in the memory 102, and the soft core source code of the processor 101 is generated by the RocketChip generator.
  • RocketChip generator is a set of processor 101 source code generator based on RISC-V reduced instruction set developed by the University of California, Berkeley, which is written in Chisel language.
  • the RocketChip generator environment is built and the source code provided by the RocketChip generator is modified to perform corresponding configuration, thereby generating the soft core source code of the processor 101 based on the RISC-V reduced instruction set.
  • the baseboard management controller usually has two-wire serial bus interface I2C, universal serial bus interface USB, video transmission interface VGA, Ethernet interface Ethernet, and high-speed serial computer expansion bus interface PCIE and other rich peripheral interfaces . Therefore, the external interface 103 configured by the baseboard management controller in another embodiment of the present invention also includes: a two-wire serial bus interface I2C, a universal serial bus interface USB, a video transmission interface VGA, an Ethernet interface Ethernet, and High-speed serial computer expansion bus interface PCIE.
  • the baseboard management controller in the embodiment of the present invention is provided with the above-mentioned several interfaces, because these external interfaces belong to the more commonly used interfaces in the baseboard management controller.
  • the baseboard management controller is not limited to the above-mentioned external interfaces. It is also possible to set only some of the above-mentioned external interfaces in the baseboard management controller according to actual needs, or set more external interfaces, which all belong to the protection category of the present invention.
  • a two-wire serial bus interface I2C, a universal serial bus interface USB, a video transmission interface VGA, an Ethernet interface Ethernet, and a high-speed serial computer expansion bus interface PCIE are respectively added to the AXI bus of the baseboard management controller. And, at the same time, you need to add drivers for each external interface accordingly.
  • the generated soft core source code of the processor 101 can be mapped to a Field Programmable Gate Array (FPGA) chip to implement the processor 101 of the substrate management controller, and it can be added to the FPGA Two-wire serial bus interface I2C, universal serial bus interface USB, video transmission interface VGA, Ethernet interface Ethernet, and high-speed serial computer expansion bus interface PCIE and other peripheral interfaces.
  • FPGA Field Programmable Gate Array
  • the baseboard management controller may further include a trusted security verification module and firmware.
  • the trusted security verification module is used to verify the legality of the data and protect the safe operation of the baseboard management controller.
  • the baseboard management controller in the embodiment of the present invention from an architectural point of view, specifically includes: a RISC-V system carried on a processor and based on a RISC-V system, and its corresponding firmware , And store the SPI memory of the OpenBMC system, there are two-wire serial bus interface I2C, universal serial bus interface USB, video transmission interface VGA, Ethernet interface Ethernet, and high-speed serial computer expansion bus interface PCIE. In addition, it is also connected to the server's south bridge PCH to manage the service hardware system.
  • the baseboard management controller provided in the embodiment of the present invention can be divided into management protocol and application layer, kernel layer, middleware, firmware layer, The processor 101 hardware layer.
  • the management protocol and application layer include various applications running on the Linux operating system kernel of the OpenBMC system, management interface service programs, and built-in IPMI management applications.
  • the kernel layer mainly includes the Linux operating system kernel of the OpenBMC system and the driver of the external interface 103.
  • the firmware layer mainly includes the startup process management and kernel startup boot chromatography during the startup process of the baseboard management controller, and the built-in trusted security verification module.
  • the hardware layer of the processor 101 mainly includes external modules such as a soft core source code based on the RISC-V system architecture and an external interface 103.
  • An embodiment of the present invention provides a baseboard management controller, which is based on the open source RISC-V system architecture.
  • the constructed baseboard management controller includes: a processor 101, a memory 102, and an external device connected via an AXI bus. Interface 103;
  • the memory 102 is used to store the OpenBMC system
  • the OpenBMC system is obtained by cross-compiling the OpenBMC software framework by the RISC-V tool chain of the RISC-V architecture
  • the processor 101 is used to execute the OpenBMC system stored in the memory 102
  • the soft core source code of the processor 101 is generated by the RocketChip generator.
  • the baseboard management controller used by the user is no longer limited by intellectual property rights, and the baseboard management controller used by the user is completely independent and controllable. In addition, the cost of the baseboard management controller is greatly reduced.
  • Another embodiment of the present invention also provides a method for constructing a baseboard management controller, as shown in FIG. 4, including:
  • the configuration information is configuration information of the processor.
  • the RocketChip generator by building the RocketChip generator operating environment on the local development platform or equipment, and using the RocketChip generator, in the built operating environment, modify the source code and kernel configuration provided by the RocketChip generator and increase the parameter attributes such as multi-core to generate Superscalar out-of-order execution of kernel RTL source code.
  • the generated superscalar out-of-order execution kernel RTL source code is the soft core source code of the processor.
  • S402 Configure an external interface based on the soft core source code of the processor.
  • the external interface is connected to the processor through the AXI bus.
  • the configured external interfaces include: a two-wire serial bus interface I2C, a universal serial bus interface USB, a video transmission interface VGA, an Ethernet interface Ethernet, and a high-speed serial computer expansion bus interface PCIE.
  • the high-speed serial computer expansion bus interface PCIE can be used to connect with the South Bridge PCH of the service to realize the interconnection between the baseboard management controller and the service, so that the baseboard management controller can manage and control the server hardware. Therefore, in the configuration of the external interface, the high-speed serial computer expansion bus interface PCIE is essential.
  • the storage, clock, interface, etc. in the RTL source code generated in step S101 can be mapped to the FPGA chip, and then a two-wire serial bus interface I2C, universal serial bus interface USB, video transmission can be added to the source code of the FPGA chip Interface VGA, Ethernet interface Ethernet, and high-speed serial computer expansion bus interface PCIE and other external interfaces, thereby constructing a system-on-chip of the baseboard management controller.
  • a two-wire serial bus interface I2C, universal serial bus interface USB, video transmission can be added to the source code of the FPGA chip Interface VGA, Ethernet interface Ethernet, and high-speed serial computer expansion bus interface PCIE and other external interfaces, thereby constructing a system-on-chip of the baseboard management controller.
  • the development environment of the OpenBMC software framework is built on the local development platform or equipment, and the OpenBMC software framework is cross-compiled using the RISC-V tool chain of the RISC-V architecture, so that it can be run on the local platform.
  • V system architecture is built on the baseboard management controller.
  • the startup mode of the OpenBMC system can be further set to the SPI mode.
  • the startup mode of the OpenBMC system can be set to SPI mode.
  • step S403 After executing step S403 to obtain the OpenBMC system, refresh the OpenBMC system into the memory of the baseboard management controller.
  • step S404 is specifically: refreshing the OpenBMC system to the SPI memory of the RISC-V system architecture.
  • the baseboard management controller after the baseboard management controller is constructed, it may further include:
  • the high-speed serial computer expansion bus interface PCIE of the baseboard management controller is connected to the serving South Bridge PCH, so that the baseboard management controller is connected to the server for system integration. Then, according to the function of the baseboard management controller, the function of the baseboard management controller is tested through each corresponding external interface. So as to ensure the reliability of the baseboard management controller.
  • the method for constructing a substrate management controller constructs a RocketChip generator operating environment, and uses the RocketChip generator to process configuration information in the constructed operating environment to generate the soft core source code of the processor; wherein, The configuration information is the configuration information of the processor. Then, an external interface is configured based on the soft core source code of the processor. Wherein, the external interface is connected to the processor through the AXI bus.
  • the baseboard management controller used by the user is no longer limited by intellectual property rights, and the baseboard management controller used by the user is completely independent and controllable. In addition, the cost of the baseboard management controller is greatly reduced.

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Abstract

一种基于RISC-V系统架构构建得到的基板管理控制器，其中，所述基板管理控制器包括：通过AXI总线进行连接的处理器（101）、存储器（102）和外接接口（103）；其中，所述存储器用于存储OpenBMC系统，所述OpenBMC系统由所述RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到；所述处理器用于执行所述存储器中存储的OpenBMC系统，且所述处理器的软核源码由RocketChip生成器生成。通过基于开源的RISC-V系统架构，构建基板管理控制器，取代基于需要授权的ARM架构实现基板管理控制器，从而使得用户所使用的基板管理控制器不再受限于生产厂家，实现对自己使用的基板管理控制器的完全自主可控。

Description

基板管理控制器及其构建方法
本申请要求于2019年08月09日提交中国专利局、申请号为201910734857.9、发明名称为“基板管理控制器及其构建方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及服务器系统管理技术领域，特别涉及一种基板管理控制器及其构建方法。
背景技术
基板管理控制器(Baseboard Management Controller，BMC)是服务器核心元器件之一，通常作为ASIC在服务器主板的南桥上实现，主要实现服务器的全系统的管理控制功能。
现在的服务器中所使用的BMC，都是基于ARM架构来实现的。而ARM架构已经被授予了知识产权，所以现有的BMC不但成本高，而且安全性也无法得到有效的保证。而且ARM架构需要授权才能使用，所以如果厂家对ARM架构进行技术管制，则会对服务器以及嵌入式行业造成严重影响。
所以，用户所使用的BMC受限于生产厂家，并无法实现对自己使用的BMC的完全自主可控。
发明内容
基于上述现有技术的不足，本发明提供了一种基板管理控制器及其构建方法，以解决用户所使用的基板管理控制器受限于生产厂家，并无法实现对自己使用的基本管理器的完全自主可控的问题。
为了实现上述目的，本发明提供了以下技术方案：
本发明第一方面提供了一种基板管理控制器，基于RISC-V系统架构构建得到，其中，所述基板管理控制器包括：通过AXI总线进行连接的处理器、存储器和外接接口；
其中，所述存储器用于存储OpenBMC系统，所述OpenBMC系统由 所述RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到；
所述处理器用于执行所述存储器中存储的OpenBMC系统，且所述处理器的软核源码由RocketChip生成器生成。
可选地，在上述基板管理控制器中，所述外接接口，包括：两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE。
可选地，在上述基板管理控制器中，所述存储器，包括所述RISC-V系统架构的SPI存储器。
可选地，在上述基板管理控制器中，所述OpenBMC系统的启动模式设置为SPI模式。
可选地，在上述基板管理控制器中，所述SPI模式的OpenBMC系统的启动模式，由修改RISC-V系统架构的RISC-V启动固件得到。
本发明另一方面提供了一种基板管理控制器的构建方法，包括：
搭建RocketChip生成器的运行环境，并利用所述RocketChip生成器在搭建的运行环境下处理配置信息，生成处理器的软核源码；其中，所述配置信息为所述处理器的配置信息；
基于所述处理器的软核源码配置外接接口；其中，所述外接接口通过AXI总线与所述处理器连接；
搭建OpenBMC软件框架的开发环境，并利用所述RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到OpenBMC系统；
将所述OpenBMC系统刷新到存储器。
可选地，在上述的基板管理控制器的构建方法中，所述将所述OpenBMC系统刷新到存储器，包括：
将所述OpenBMC系统刷新到RISC-V系统架构的SPI存储器。
可选地，在上述的基板管理控制器的构建方法中，所述外接接口，包括：两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE。
可选地，在上述的基板管理控制器的构建方法中，所述利用所述 RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到OpenBMC系统之后，还包括：
设置所述OpenBMC系统的启动模式为SPI模式。
可选地，在上述的基板管理控制器的构建方法中，所述设置所述OpenBMC系统的启动模式为SPI模式，包括：
修改RISC-V系统架构的RISC-V启动固件，使得所述OpenBMC系统的启动模式为SPI模式。
本发明提供的一种基板管理控制器及其构建的方法，基于开源的RISC-V系统架构构建基板管理控制器，所构建的所述基板管理控制器包括：通过AXI总线进行连接的处理器、存储器和外接接口；其中，所述存储器用于存储OpenBMC系统，所述OpenBMC系统由所述RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到；所述处理器用于执行所述存储器中存储的OpenBMC系统，且所述处理器的软核源码由RocketChip生成器生成。基于开源的RISC-V系统架构，构建基板管理控制器，取代基于ARM架构实现基板管理控制器的构建。从而使得用户所使用的基板管理控制器不再受限于生产厂家，实现对自己使用的基板管理控制器的完全自主可控。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例提供的一种基板管理控制器的结构示意图；
图2为本发明另一实施例提供的一种基板管理控制器的结构示意图；
图3为本发明实施例提供的一种基板管理控制器的分层结构示意图；
图4为本发明另一实施例提供的一种基板管理控制器的构建方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本申请中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
本发明实施例提供了一种基于RISC-V系统架构构建得到的基板管理控制器，如图1所示，包括：
通过AXI总线进行连接的处理器101、存储器102和外接接口103。
需要说明的是，RISC-V系统架构是加州大学伯克利分校设计并发布的一种开源指令集架构。由于，RISC-V系统架构是开源的，所以相比于其他受专利保护的系统架构，例如ARM架构、x86架构、MIPS架构、Alpha架构，用户使用RISC-V系统架构不仅不需要承担高昂的成本，并且还不需要授权，更便于创新。所以，本发明实施例所提供的基板管理控制器，是基于开源的RISC-V系统架构来构建的。
其中，存储器102用于存储OpenBMC系统，OpenBMC系统由RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到。
需要说明的是，OpenBMC软件框架是一个开源的软件框架，用于构建一个完整的基板管理控制器的Linux操作系统镜像。所以，可以通过编译OpenBMC系统，得到基板管理控制器的操作系统。
还需要说明的是，交叉编译可以相对比于本地编译来理解。通俗的理解交叉编译指的就是在当前平台下编译出在其他平台下运行的程序。由于，在本地开发平台上所编译的OpenBMC系统，是要运行于基板管理控制器上，并不运行于本地开发平台。所以，需要在本地开发平台上，通过交叉编译工具链对OpenBMC软件框架，以得到能在基板管理控制器上运行的OpenBMC系统。
具体的，由于本发明实施例的基板管理控制器，是基于RISC-V系统架构构建的，所以操作系统应该通过RISC-V工具链进行交叉编译。即通过RISC-V工具链对OpenBMC软件框架进行交叉编译，从而获得OpenBMC系统，并将OpenBMC系统刷新到基板管理控制器的存储器102中。
可选地，在本发明实施例中，基板管理控制器的存储器102采用的是SPI存储器。所以，具体是将完全编译好的OpenBMC系统，刷新到RISC-V系统架构的SPI存储器中。
可选的，本发明另一实施例中，OpenBMC系统的启动模式被设置为SPI模式。具体的，通过修改RISC-V系统架构的RISC-V启动固件，从而将OpenBMC系统的启动模式设置为SPI模式。
具体的，OpenBMC系统中包括Linux操作系统内核。管理接口服务程序、内置的IPMI管理应用、系统固件，各阶段的启动加载程序等管理协议与应用都运行于OpenBMC系统的Linux操作系统内核上。
本发明实施例中，基板管理控制器的处理器101用于执行存储器102中存储的OpenBMC系统，且处理器101的软核源码由RocketChip生成器生成。
其中，RocketChip生成器是加州大学伯克利分校开发的一套基于RISC-V精简指令集的处理器101源码生成器，该生成器采用Chisel语言编写。
所以，本发明实施例中，通过搭建RocketChip生成器环境，并修改RocketChip生成器提供的源码，从而进行相应的配置，从而生成基于RISC-V精简指令集的处理器101的软核源码。
由于，基板管理控制器通常都具备两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE等丰富的外设接口。所以，本发明另一实施例中的基板管理控制器配置的外接接口103，同样包括：两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE。
需要说明的是，本发明实施例中的基板管理控制器设置有上述的几个接口，是因为这几个外接接口属于基板管理控制器中比较常用的接口。但 在基板管理控制器上并不限于仅能设置上述外接接口。也可以根据实际的需求仅在基板管理控制器中设置上述外接接口在中的部分外接接口，或者设置更多的外接接口，这都属于本发明的保护范畴。
具体的，在基板管理控制器的AXI总线上分别添加两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE。并且，同时还需要相应地添加各个外接接口的驱动程序。
可选地，可以将生成的处理器101的软核源码映射到现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)芯片上，实现基板管理控器的处理器101，并且可以在FPGA中添加两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE等外设接口。
可选的，本发明另一实施例中，基板管理控制器还可以包括可信安全验证模块以及固件。可信安全验证模块用于验证数据是否合法，保护基板管理控制器的安全运行。
所以，本发明实施例中的基板管理控制器，如图2所示，从架构上看，具体包括：承载于处理器上，基于RISC-V系统实现的RISC-V系统，及其相应的固件，以及存储有OpenBMC系统的SPI存储器，还有两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE。并且，同样是通过与服务器的南桥PCH相连，从而对服务的硬件系统进行管理。
还需要说明的是，本发明实施例中所提供的基板管理控制器，如图3所示，若按照软件分层机制，可分为管理协议与应用层、内核层、中间件、固件层、处理器101硬件层。其中，管理协议与应用层包含运行于OpenBMC系统的Linux操作系统内核上的各类应用、管理接口服务程序以及内置的IPMI管理应用等。内核层则主要包含OpenBMC系统的Linux操作系统内核以及外接接口103的驱动。固件层主要包含是在基板管理控制器启动过程中的启动流程管理与内核启动引导层析，以及内置的可信安全验证模块等。处理器101硬件层主要包括有基于RISC-V系统架构的软核源码以及外接接口103等外接模块。
本发明实施例提供的一种基板管理控制器，基于开源的RISC-V系统架 构构建基板管理控制器，所构建的基板管理控制器包括：通过AXI总线进行连接的处理器101、存储器102和外接接口103；其中，存储器102用于存储OpenBMC系统，OpenBMC系统由RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到；处理器101用于执行存储器102中存储的OpenBMC系统，且处理器101的软核源码由RocketChip生成器生成。通过基于开源的RISC-V系统架构，构建基板管理控制器，取代基于ARM架构实现基板管理控制器的构建。从而使得用户所使用的基板管理控制器不再受限于知识产权的限制，并实现对自己使用的基板管理控制器的完全自主可控。并且，还极大的较低基板管理控制器的成本。
本发明另一实施例还提供了一种基板管理控制器的构建方法，如图4所示，包括：
S401、搭建RocketChip生成器的运行环境，并利用RocketChip生成器在搭建的运行环境下处理配置信息，生成处理器的软核源码。
其中，所述配置信息为所述处理器的配置信息。
具体的，通过在本地开发平台或设备上搭建RocketChip生成器运行环境，并利用RocketChip生成器，在所搭建的运行环境下，修改RocketChip生成器提供的源码以及内核配置以及增加多核等参数属性，生成超标量乱序执行内核RTL源码。其中，所生成超标量乱序执行内核RTL源码，即为处理器的软核源码。
S402、基于处理器的软核源码配置外接接口。
其中，外接接口通过AXI总线与所述处理器连接。
可选地，配置的外接接口包括：两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE。
其中，高速串行计算机扩展总线接口PCIE，可用于与服务的南桥PCH相连，实现基板管理控制器与服务的互连，从而通过基板管理控制器对服务器的硬件进行管理与控制。所以，在配置的外接接口中，高速串行计算机扩展总线接口PCIE是必不可少的。
具体的，可以将步骤S101生成的RTL源码中的存储、时钟、接口等映射到FPGA芯片，然后在FPGA芯片的源码中增加两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及 高速串行计算机扩展总线接口PCIE等外接接口，从而构建出基板管理控制器的片上系统。
S403、搭建OpenBMC软件框架的开发环境，并利用RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到OpenBMC系统。
具体的，在本地开发平台或设备上搭建OpenBMC软件框架的开发环境，并利用RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译，从而在本地平台上得到可运行于基于RISC-V系统架构构建的基板管理控制器上。
可选地，在编译OpenBMC系统时，还可以进一步将OpenBMC系统的启动模式设置为SPI模式。
具体，可以通过修改RISC-V系统架构的RISC-V启动固件，将OpenBMC系统的启动模式设置SPI模式。
S404、将OpenBMC系统刷新到存储器。
也就是说，在执行步骤S403得到OpenBMC系统后，将OpenBMC系统刷新到基板管理控制器的存储器中。
可选地，本发明实施例中所采用的存储器为SPI存储器。所以步骤S404的具体为：将OpenBMC系统刷新到RISC-V系统架构的SPI存储器。
可选地，本发明另一实施例中，在构建出基板管理控制器后，还可以进一步包括：
将基板管理控制器接入服务器中，进行系统集成，并按照基板管理控制器的功能进行系统测试。
具体的，通过基板管理控制器的高速串行计算机扩展总线接口PCIE，与服务的南桥PCH相连，从而将基板管理控制器接入服务器中，进行系统的集成。然后，按照基板管理控制器的功能，通过各个相应的外接接口，对基板管理控制器的功能进行测试。从而保证基板管理控制器的可靠性。
本发明实施例提供的一种基板管理控制器的构建方法，通过搭建RocketChip生成器的运行环境，并利用RocketChip生成器在搭建的运行环境下处理配置信息，生成处理器的软核源码；其中，配置信息为所述处理器的配置信息。然后，基于所述处理器的软核源码配置外接接口。其中，外接接口通过AXI总线与所述处理器连接。通过搭建OpenBMC软件框架的开发环境，并利用RISC-V架构的RISC-V工具链对OpenBMC软件框架 进行交叉编译得到OpenBMC系统，然后将OpenBMC系统刷新到存储器。从而实现基于开源的RISC-V系统架构，构建基板管理控制器，取代基于ARM架构实现基板管理控制器的构建。从而使得用户所使用的基板管理控制器不再受限于知识产权的限制，并实现对自己使用的基板管理控制器的完全自主可控。并且，还极大的较低基板管理控制器的成本。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种基板管理控制器，其特征在于，基于RISC-V系统架构构建得到，其中，所述基板管理控制器包括：通过AXI总线进行连接的处理器、存储器和外接接口；
    其中，所述存储器用于存储OpenBMC系统，所述OpenBMC系统由所述RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到；
    所述处理器用于执行所述存储器中存储的OpenBMC系统，且所述处理器的软核源码由RocketChip生成器生成。
  2. 根据权利要求1所述的基板管理控制器，其特征在于，所述外接接口，包括：两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE。
  3. 根据权利要求1所述的基板管理控制器，其特征在于，所述存储器，包括所述RISC-V系统架构的SPI存储器。
  4. 根据权利要求1至3中任意一项所述的基板管理控制器，其特征在于，所述OpenBMC系统的启动模式设置为SPI模式。
  5. 根据权利要求4所述的基板管理控制器，其特征在于，所述SPI模式的OpenBMC系统的启动模式，由修改RISC-V系统架构的RISC-V启动固件得到。
  6. 一种基板管理控制器的构建方法，其特征在于，包括：
    搭建RocketChip生成器的运行环境，并利用所述RocketChip生成器在搭建的运行环境下处理配置信息，生成处理器的软核源码；其中，所述配置信息为所述处理器的配置信息；
    基于所述处理器的软核源码配置外接接口；其中，所述外接接口通过AXI总线与所述处理器连接；
    搭建OpenBMC软件框架的开发环境，并利用所述RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到OpenBMC系统；
    将所述OpenBMC系统刷新到存储器。
  7. 根据权利要求6所述的构建方法，其特征在于，所述将所述OpenBMC系统刷新到存储器，包括：
    将所述OpenBMC系统刷新到RISC-V系统架构的SPI存储器。
  8. 根据权利要求6所述的构建方法，其特征在于，所述外接接口，包括：两线式串行总线接口I2C、通用串行总线接口USB、视频传输接口VGA、以太网接口Ethernet、以及高速串行计算机扩展总线接口PCIE。
  9. 根据权利要求6至8中任意一项所述的构建方法，其特征在于，所述利用所述RISC-V架构的RISC-V工具链对OpenBMC软件框架进行交叉编译得到OpenBMC系统之后，还包括：
    设置所述OpenBMC系统的启动模式为SPI模式。
  10. 根据权利要求8所述的构建方法，其特征在于，所述设置所述OpenBMC系统的启动模式为SPI模式，包括：
    修改RISC-V系统架构的RISC-V启动固件，使得所述OpenBMC系统的启动模式为SPI模式。
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