WO2021017118A1 - 像素驱动电路及显示装置 - Google Patents

像素驱动电路及显示装置 Download PDF

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Publication number
WO2021017118A1
WO2021017118A1 PCT/CN2019/106107 CN2019106107W WO2021017118A1 WO 2021017118 A1 WO2021017118 A1 WO 2021017118A1 CN 2019106107 W CN2019106107 W CN 2019106107W WO 2021017118 A1 WO2021017118 A1 WO 2021017118A1
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Prior art keywords
digital signal
pixel
light
transistor
pixel unit
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PCT/CN2019/106107
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English (en)
French (fr)
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聂诚磊
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/617,520 priority Critical patent/US11341899B2/en
Publication of WO2021017118A1 publication Critical patent/WO2021017118A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display device.
  • the pixel drive circuit is divided into time division multiplexing circuit and space multiplexing circuit.
  • the time division multiplexing circuit is mainly based on the pulse width modulation (Pulse Width Modulation, PWM) circuit.
  • PWM pulse width modulation
  • This circuit divides the display time of a row into multiple different time periods and switches the light-emitting area in different time periods.
  • the thin film transistor (TFT) is driven in the linear region, which makes the gray-scale switching frequency too fast, which exceeds the existing driver chip (Integrated Circuit, IC).
  • the switching frequency that can be provided.
  • the spatial multiplexing circuit mainly divides the light emission into areas with a certain proportion, and realizes the switching of gray levels by displaying different light-emitting areas, which occupy a large space.
  • the pixel driving circuit of the prior art has the problems of too fast gray-scale switching frequency and large space occupation.
  • the present application provides a pixel drive circuit and a display device to realize the coordination of spatial multiplexing and time division multiplexing of the pixel drive circuit, thereby improving the problem of too fast grayscale switching frequency of the pixel drive circuit and large space occupation.
  • the embodiments of the present application provide a pixel driving circuit, which includes an address transistor, a driving transistor, a storage capacitor, and a plurality of pixel units connected in parallel; the drain of the address transistor and the The gate of the driving transistor is electrically connected;
  • One end of the storage capacitor is connected to the gate of the driving transistor, and the other end is connected to the drain of the driving transistor;
  • the pixel unit is connected to the drain of the driving transistor, the pixel unit includes at least one digital signal controller, and the digital signal controller is connected in series with anodes of a plurality of light emitting units;
  • the gate of the address selection transistor receives a scan signal, the digital signal controller provides a digital signal, and the scan signal and the digital signal cause the light-emitting unit to emit light periodically to form a preset frame display screen.
  • the source of the driving transistor is connected to the positive voltage of the power source
  • the cathode of the light-emitting unit is connected to the negative voltage of the power source
  • the scan signal, the positive voltage of the power source and the negative voltage of the power source jointly act on the driving transistor , Forming a current signal of the drain of the driving transistor;
  • the digital signal controller provides a digital signal with a preset address period, and both the digital signal and the current signal are transmitted to the anode of the light-emitting unit, so that the current signal exhibits a preset display period, and the light-emitting The unit emits light during the preset display period;
  • the address selection period and the display period jointly form a preset period of a preset frame display screen, so that the light-emitting unit constitutes the preset frame display screen.
  • the address selection transistor when the scan signal is a high pulse, the address selection transistor is turned on, the gate of the address selection transistor receives the scan signal, and the storage capacitor stores the scan signal and converts it into a corresponding current signal;
  • the address transistor When the scan signal is a low pulse, the address transistor is turned off, and the storage capacitor provides a current signal to the gate of the driving transistor. When the current value of the current signal reaches the current threshold of the driving transistor , The driving transistor is turned on, and the light emitting unit emits light.
  • the scanning signal, the digital signal, and the current signal are combined to correspond to one of the preset address selection period and one of the preset display period within a preset period:
  • the scan signal is a high-level pulse, the current signal is a low-level, and the digital signal is a high-level;
  • the scan signal is a low-potential pulse
  • the current signal is a high-potential
  • the digital signal is a low-potential
  • the preset display period is twice the preset address selection period.
  • the plurality of parallel pixel units includes a first pixel unit and a second pixel unit
  • the first pixel unit includes a first digital signal controller and a light emitting unit
  • the first digital signal controller and a The anode of the light-emitting unit is electrically connected
  • the second pixel unit includes a second digital signal controller and two light-emitting units connected in parallel, and the second digital signal controller is electrically connected to the anodes of the two light-emitting units, so that a picture is displayed in a preset frame Inside, the brightness of the second pixel unit is twice the brightness of the first pixel unit.
  • the plurality of parallel connected pixel units further includes at least one third pixel unit, and the third pixel unit is connected in parallel with the second pixel unit;
  • the third pixel unit includes a third digital signal controller, the third digital signal controller is electrically connected to anodes of a preset number of light-emitting units, the preset number of light-emitting units are connected in parallel, and the preset number is An even multiple of the number of light-emitting units in the second pixel unit, so that in a preset frame picture, the brightness of the third pixel unit is an even multiple of the brightness of the second pixel unit.
  • the pixel driving circuit further includes a plurality of vertically arranged data lines and a plurality of horizontally arranged scan lines, the data lines provide data signals to the source of the address transistor, and the scan lines provide the The gate of the address transistor provides a scan signal, so that the drain of the address transistor provides the current signal to the storage capacitor.
  • the digital signal controller is a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor or an amorphous silicon thin film transistor.
  • an embodiment of the present application provides a display device, which includes a pixel drive circuit, the pixel drive circuit includes an address transistor, a drive transistor, a storage capacitor, and a plurality of pixel units connected in parallel; wherein,
  • the drain of the address selection transistor is electrically connected to the gate of the drive transistor
  • One end of the storage capacitor is connected to the gate of the driving transistor, and the other end is connected to the drain of the driving transistor;
  • the pixel unit is connected to the drain of the driving transistor, the pixel unit includes at least one digital signal controller, and the digital signal controller is connected in series with anodes of a plurality of light emitting units;
  • the gate of the address selection transistor receives a scan signal, the digital signal controller provides a digital signal, and the scan signal and the digital signal cause the light-emitting unit to emit light periodically to form a preset frame display screen.
  • the source of the driving transistor is connected to the positive voltage of the power source
  • the cathode of the light-emitting unit is connected to the negative voltage of the power source
  • the scan signal, the positive voltage of the power source and the negative voltage of the power source work together on the driving A transistor, which forms a current signal of the drain of the driving transistor;
  • the digital signal controller provides a digital signal with a preset address period, and both the digital signal and the current signal are transmitted to the anode of the light-emitting unit, so that the current signal exhibits a preset display period, and the light-emitting The unit emits light during the preset display period;
  • the address selection period and the display period jointly form a preset period of a preset frame display screen, so that the light-emitting unit constitutes the preset frame display screen.
  • the address selection transistor when the scan signal is a high pulse, the address selection transistor is turned on, the gate of the address selection transistor receives the scan signal, and the storage capacitor stores the scan signal and converts it into a corresponding current signal;
  • the address transistor When the scan signal is a low pulse, the address transistor is turned off, and the storage capacitor provides a current signal to the gate of the driving transistor. When the current value of the current signal reaches the current threshold of the driving transistor , The driving transistor is turned on, and the light emitting unit emits light.
  • the scanning signal, the digital signal, and the current signal are combined to correspond to one of the preset address selection period and one of the preset display period within a preset period:
  • the scan signal is a high-level pulse, the current signal is a low-level, and the digital signal is a high-level;
  • the scan signal is a low-potential pulse
  • the current signal is a high-potential
  • the digital signal is a low-potential
  • the preset display period is twice the preset address selection period.
  • the plurality of parallel pixel units includes a first pixel unit and a second pixel unit
  • the first pixel unit includes a first digital signal controller and a light emitting unit
  • the first digital signal controller and a The anode of the light-emitting unit is electrically connected
  • the second pixel unit includes a second digital signal controller and two light-emitting units connected in parallel, and the second digital signal controller is electrically connected to the anodes of the two light-emitting units, so that a picture is displayed in a preset frame Inside, the brightness of the second pixel unit is twice the brightness of the first pixel unit.
  • the plurality of parallel connected pixel units further includes at least one third pixel unit, and the third pixel unit is connected in parallel with the second pixel unit;
  • the third pixel unit includes a third digital signal controller, the third digital signal controller is electrically connected to anodes of a preset number of light-emitting units, the preset number of light-emitting units are connected in parallel, and the preset number is An even multiple of the number of light-emitting units in the second pixel unit, so that in a preset frame picture, the brightness of the third pixel unit is an even multiple of the brightness of the second pixel unit.
  • the pixel driving circuit further includes a plurality of vertically arranged data lines and a plurality of horizontally arranged scan lines, the data lines provide data signals to the source of the address transistor, and the scan lines provide the The gate of the address transistor provides a scan signal, so that the drain of the address transistor provides the current signal to the storage capacitor.
  • the digital signal controller is a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor or an amorphous silicon thin film transistor.
  • the beneficial effect of the present application is that, different from the prior art, the pixel drive circuit provided by the present application can control the light-emitting unit to emit light periodically by adding a digital signal controller, so as to achieve the coordination of spatial multiplexing and time-division multiplexing, thereby improving pixels
  • the gray-scale switching frequency of the driving circuit is too fast and takes up a lot of space.
  • FIG. 1 is a schematic circuit diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of another circuit of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of another circuit of a pixel driving circuit provided by an embodiment of the application.
  • the embodiments of the present application provide a pixel driving circuit, which will be described in detail below.
  • FIGS. 1, 3, and 4 are schematic diagrams of the structure of a pixel driving circuit provided by an embodiment of the application.
  • the embodiment of the application provides a pixel driving circuit 10, and the pixel driving circuit 10 includes an address transistor T1. , A driving transistor T2, a storage capacitor Cst, and a plurality of pixel units L connected in parallel; the drain s of the address selection transistor T1 is electrically connected to the gate g of the driving transistor T2;
  • One end of the storage capacitor Cst is connected to the gate g of the driving transistor T2, and the other end is connected to the drain d of the driving transistor T2;
  • the pixel unit L is connected to the drain d of the driving transistor T2, the pixel unit M includes at least one digital signal controller Ctr, and the digital signal controller Ctr is connected in series with the anodes of a plurality of light emitting units M;
  • the gate g of the address transistor T2 receives a scan signal, and the digital signal controller Ctr provides a digital signal DS.
  • the scan signal scan and the digital signal DS cause the light-emitting unit M to emit light periodically to form a preset Set frame display screen.
  • the source s of the driving transistor T2 is connected to the positive power supply voltage Vss, the cathode of the light-emitting unit M is connected to the negative power supply voltage Vdd, the scan signal scan, the positive power supply voltage Vss, and the negative power supply voltage Vdd Acting together on the driving transistor T2 to form a current signal ES of the drain d of the driving transistor T2;
  • FIG. 2 is a schematic diagram of a predetermined period of a pixel driving circuit provided by an embodiment of the application.
  • the digital signal controller Ctr provides a digital signal DS with a predetermined address period TA, and Both the digital signal DS and the current signal ES are transmitted to the anode of the light-emitting unit M, so that the current signal ES assumes a preset display period TL, and the light-emitting unit M emits light during the preset display period TL.
  • the luminous brightness in the preset address selection period TA is weaker than that in the preset display period TL;
  • the address selection period TA and the display period TL together form a preset period T of a preset frame display screen, so that the light-emitting unit M forms the preset frame display screen.
  • the pixel driving circuit 10 further includes a plurality of vertically arranged data lines and a plurality of horizontally arranged scan lines.
  • the data lines provide data signals data to the source s of the address transistor T1.
  • the scan line provides a scan signal scan to the gate g of the address transistor T1, so that the drain d of the address transistor T1 provides the current signal ES to the storage capacitor Cst.
  • the pixel driving circuit 10 provided by the embodiment of the present application, at least one digital signal controller Ctr and a plurality of light-emitting units M are provided at the drain d of the driving transistor T2 of the pixel driving circuit 10, and the digital signal controller Ctr provides light
  • the unit M provides a digital signal DS of the address period TA.
  • the scan signal scan, the positive power supply voltage Vss, and the negative power supply voltage Vdd act together on the driving transistor T2 to form the drain d of the driving transistor T2
  • the current signal ES of the preset display period TL makes the address selection period TA and the display period TL jointly form the preset period T of the preset frame display screen, so that the pixel unit L presents the preset frame display screen. Assuming a period T, the light-emitting unit M emits light periodically.
  • the scan signal scan includes a high pulse and a low pulse, and the scan signal scan changes to control the on and off of the address selection transistor T1;
  • the address transistor T1 When the scan signal scan is a high pulse, the address transistor T1 is turned on, the gate g of the address transistor T1 receives the scan signal scan, and the storage capacitor Cst stores the scan signal scan and converts it into a corresponding ⁇ current signal ES;
  • the address transistor T1 When the scan signal scan is a low pulse, the address transistor T1 is turned off, and the storage capacitor Cst provides a current signal ES to the gate g of the driving transistor T2.
  • the current value of the current signal ES reaches When the current threshold of the driving transistor T2 is described, the driving transistor T2 is turned on, and the light-emitting unit M emits light.
  • the scan signal scan, the digital signal data, and the current signal ES are combined to correspond to one preset address period TA and one preset display period within a preset period T.
  • the scan signal scan is a high-level pulse
  • the current signal ES is a low-level
  • the digital signal DS is a high-level.
  • the light emitting unit M in the pixel driving circuit 10 emits light.
  • the scan signal scan is a low potential pulse
  • the current signal ES is a high potential
  • the digital signal DS is a low potential.
  • the light emitting unit M in the pixel driving circuit 10 emits light.
  • FIG. 3 is another schematic diagram of the pixel driving circuit provided by the embodiment of the application.
  • the pixel driving circuit 11 performs spatial multiplexing on the basis of the pixel driving circuit 10 in FIG. 1, and the details are as follows:
  • the number of the pixel unit L is at least one, and the pixel unit L is arranged in parallel at the drain d of the driving transistor T2;
  • the plurality of parallel-connected pixel units L includes a first pixel unit L1 and a second pixel unit L2, the first pixel unit L1 includes a first digital signal controller Ctr1 and a light emitting unit M1, and the first digital signal controls
  • the device Ctr1 is electrically connected to the anode of one of the light-emitting units M1;
  • the second pixel unit L2 includes a second digital signal controller Ctr2 and two light-emitting units M2 connected in parallel, and the second digital signal controller Ctr2 is electrically connected to the anodes of the two light-emitting units M2, so that one In the preset frame display screen, the brightness of the second pixel unit L2 is twice the brightness of the first pixel unit L1.
  • the preset display period TL is twice the preset address period TA, Therefore, in the pixel driving circuit 11 provided by the embodiment of the present application.
  • the preset display period TL is twice the preset address period TA, so in one pixel unit L, one preset In the period T, the grayscale brightness emitted by the light-emitting unit M in the preset display period TL is twice the brightness emitted by the same period of time when the address selection period TA is turned on.
  • the gray-scale brightness corresponding to the preset address period TA is 1, then the corresponding gray-scale brightness in the preset display period TL is 2; and because the second pixel unit The brightness of L2 is twice the brightness of the first pixel unit L1.
  • the overall gray-scale brightness of the second pixel unit L2 is 2 times the gray-scale brightness of the first pixel unit L1. That is, in the second pixel unit L2, when the gray-scale brightness corresponding to the preset address period TA is 2, the gray-scale brightness corresponding to the preset display period TL is 4.
  • the pixel driving circuit 11 In the pixel driving circuit 11 provided by the embodiment of the present application, only one second pixel unit L2 is adopted, and two parallel light-emitting units M2 in the second pixel unit L2 cooperate with the second digital signal controller Ctr2, A variety of grayscale brightness display of the pixel driving circuit is realized. While reducing the space occupation of the pixel unit L, the pixel driving circuit 11 also reduces the signal switching frequency of the gate of the switching transistor of the original prior art, which reduces the realization The difficulty of multi-gray-scale brightness changes.
  • the number of the pixel unit L is not limited to two pixel units.
  • FIG. 4 is another schematic circuit diagram of the pixel driving circuit provided by the embodiment of the application.
  • the plurality of parallel pixel units L further includes at least one third pixel unit L3, and the third pixel unit L3 is connected in parallel with the second pixel unit L2;
  • the third pixel unit L3 includes a third digital signal controller Ctr3, and the third digital signal controller Ctr3 is electrically connected to anodes of a preset number of light emitting units M3, and the preset number of light emitting units M3 are connected in parallel, so The preset number is an even multiple of the number of light-emitting units M2 in the second pixel unit L2, so that in a preset frame, the brightness of the third pixel unit L3 is equal to that of the second pixel unit L2. Even multiples of brightness.
  • the digital signal controller Ctr is also connected to a timing controller (not shown in the figure) of an external circuit, and the preset addressing period TA of the digital signal and the preset current signal The display period TL is provided by the timing controller.
  • the addressing transistor T1 and the driving transistor T2 are both low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors or amorphous silicon thin film transistors.
  • the digital signal controller Ctr can also be a low-temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor or an amorphous silicon thin film transistor.
  • an embodiment of the present invention provides a display device including the pixel driving circuit provided in any embodiment of the present application.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the beneficial effects are: adding a digital signal controller to the pixel drive circuit to control the light emitting unit to emit light periodically, so as to realize the coordination of space multiplexing and time division multiplexing, and improve the gray scale switching frequency of the pixel drive circuit to be too fast and occupy a large space.
  • the problem adding a digital signal controller to the pixel drive circuit to control the light emitting unit to emit light periodically, so as to realize the coordination of space multiplexing and time division multiplexing, and improve the gray scale switching frequency of the pixel drive circuit to be too fast and occupy a large space.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素驱动电路（10）及显示装置，像素驱动电路（10）包括选址晶体管（T1）、驱动晶体管（T2）、存储电容（Cst）以及多个并联的像素单元（L），像素单元（L）包括一个数字信号控制器（Ctr），数字信号控制器（Ctr）与多个发光单元（M）的阳极串联，选址晶体管（T1）的栅极接收扫描信号（scan），数字信号控制器（Ctr）提供数字信号（DS），扫描信号（scan）与数字信号（DS）使发光单元（M）呈周期性发光，形成预设帧显示画面。

Description

像素驱动电路及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示装置。
背景技术
在主动矩阵显示电路中，像素驱动电路分为时分复用电路和空间复用电路两种电路。
时分复用电路主要以脉冲宽度调制(Pulse Width Modulation，PWM)电路为主，这种电路通过将一行的显示时间划分为多个不同的时间段，通过在不同时间段里切换发光区域的亮暗来实现灰阶的切换，这种电路在工作时，驱动薄膜晶体管(Thin Film Transistor，TFT)工作在线性区，使得灰阶切换的频率过快，超出了现有的驱动芯片(Integrated Circuit，IC)所能提供的切换频率。空间复用电路主要将发光区分为比例一定的区域，通过显示不同发光区域来实现灰阶的切换，该发光区域占用空间较大。
综上所述，现有技术的像素驱动电路存在灰阶切换频率过快、占用空间较大的问题。
技术问题
本申请提供了一种像素驱动电路及显示装置，以实现像素驱动电路的空间复用与时分复用配合，进而改善像素驱动电路灰阶切换频率过快、占用空间较大的问题。
技术解决方案
为了解决上述问题，本申请实施例提供了一种像素驱动电路，该像素驱动电路包括选址晶体管、驱动晶体管、存储电容以及多个并联的像素单元；所述选址晶体管的漏极与所述驱动晶体管的栅极电性连接；
所述存储电容的一端连接所述驱动晶体管的栅极，另一端连接所述驱动晶体管的漏极；
所述像素单元与所述驱动晶体管的漏极连接，所述像素单元包括至少一个数字信号控制器，所述数字信号控制器与多个发光单元的阳极串联；
所述选址晶体管的栅极接收扫描信号，所述数字信号控制器提供数字信号，所述扫描信号与所述数字信号使所述发光单元呈周期性发光，形成预设帧显示画面。
其中，所述驱动晶体管的源极接入电源正电压，所述发光单元的阴极接入电源负电压，所述扫描信号、所述电源正电压与所述电源负电压共同作用于所述驱动晶体管，形成所述驱动晶体管漏极的电流信号；
所述数字信号控制器提供预设选址周期的数字信号，所述数字信号与所述电流信号均传送至所述发光单元的阳极，以使所述电流信号呈预设显示周期，所述发光单元在预设显示周期内发光；
所述选址周期与所述显示周期共同形成预设帧显示画面的预设周期，以使所述发光单元构成所述预设帧显示画面。
其中，在所述扫描信号为高脉冲时，所述选址晶体管开启，所述选址晶体管的栅极接收到扫描信号，所述存储电容存储所述扫描信号并转换成对应的电流信 号；
在所述扫描信号为低脉冲时，所述选址晶体管关闭，所述存储电容向所述驱动晶体管的栅极提供电流信号，当所述电流信号的电流值达到所述驱动晶体管的电流阈值时，所述驱动晶体管开启，所述发光单元发光。
其中，所述扫描信号、数字信号与电流信号相组合，在一个预设周期内先后对应一个所述预设选址周期及一个所述预设显示周期：
在所述选址周期时，所述扫描信号为高电位脉冲，所述电流信号为低电位，所述数字信号为高电平；
在所述显示周期时，所述扫描信号为低电位脉冲，所述电流信号为高电位，所述数字信号为低电平。
其中，一个所述像素单元中，在一个预设周期内，所述预设显示周期是所述预设选址周期的2倍。
其中，所述多个并联的像素单元包括第一像素单元与第二像素单元，所述第一像素单元包括第一数字信号控制器与一个发光单元，所述第一数字信号控制器与一个所述发光单元的阳极电连接；
所述第二像素单元包括第二数字信号控制器与两个并联的发光单元，所述第二数字信号控制器与两个所述发光单元的阳极电连接，以使在一个预设帧显示画面内，所述第二像素单元的亮度为所述第一像素单元的亮度的2倍。
其中，所述多个并联的像素单元还包括至少一个第三像素单元，所述第三像素单元与所述第二像素单元并联；
所述第三像素单元包括第三数字信号控制器，所述第三数字信号控制器与预设数量的发光单元的阳极电连接，所述预设数量的发光单元并联，所述预设数量 为所述第二像素单元中发光单元的数量的偶数倍，以使在一个预设帧画面内，所述第三像素单元的亮度为所述第二像素单元的亮度的偶数倍。
其中，所述像素驱动电路还包括多条竖向排列的数据线与多条横向排列的扫描线，所述数据线给所述选址晶体管的源极提供数据信号，所述扫描线给所述选址晶体管的栅极提供扫描信号，以使所述选址晶体管的漏极给所述存储电容提供所述电流信号。
其中，所述数字信号控制器为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
为了解决上述问题，本申请实施例提供了一种显示装置，该显示装置包括像素驱动电路，所述像素驱动电路包括选址晶体管、驱动晶体管、存储电容以及多个并联的像素单元；其中，
所述选址晶体管的漏极与所述驱动晶体管的栅极电性连接；
所述存储电容的一端连接所述驱动晶体管的栅极，另一端连接所述驱动晶体管的漏极；
所述像素单元与所述驱动晶体管的漏极连接，所述像素单元包括至少一个数字信号控制器，所述数字信号控制器与多个发光单元的阳极串联；
所述选址晶体管的栅极接收扫描信号，所述数字信号控制器提供数字信号，所述扫描信号与所述数字信号使所述发光单元呈周期性发光，形成预设帧显示画面。
其中，所述驱动晶体管的的源极接入电源正电压，所述发光单元的阴极接入电源负电压，所述扫描信号、所述电源正电压与所述电源负电压共同作用于所述驱动晶体管，形成所述驱动晶体管漏极的电流信号；
所述数字信号控制器提供预设选址周期的数字信号，所述数字信号与所述电流信号均传送至所述发光单元的阳极，以使所述电流信号呈预设显示周期，所述发光单元在预设显示周期内发光；
所述选址周期与所述显示周期共同形成预设帧显示画面的预设周期，以使所述发光单元构成所述预设帧显示画面。
其中，在所述扫描信号为高脉冲时，所述选址晶体管开启，所述选址晶体管的栅极接收到扫描信号，所述存储电容存储所述扫描信号并转换成对应的电流信号；
在所述扫描信号为低脉冲时，所述选址晶体管关闭，所述存储电容向所述驱动晶体管的栅极提供电流信号，当所述电流信号的电流值达到所述驱动晶体管的电流阈值时，所述驱动晶体管开启，所述发光单元发光。
其中，所述扫描信号、数字信号与电流信号相组合，在一个预设周期内先后对应一个所述预设选址周期及一个所述预设显示周期：
在所述选址周期时，所述扫描信号为高电位脉冲，所述电流信号为低电位，所述数字信号为高电平；
在所述显示周期时，所述扫描信号为低电位脉冲，所述电流信号为高电位，所述数字信号为低电平。
其中，一个所述像素单元中，在一个预设周期内，所述预设显示周期是所述预设选址周期的2倍。
其中，所述多个并联的像素单元包括第一像素单元与第二像素单元，所述第一像素单元包括第一数字信号控制器与一个发光单元，所述第一数字信号控制器与一个所述发光单元的阳极电连接；
所述第二像素单元包括第二数字信号控制器与两个并联的发光单元，所述第二数字信号控制器与两个所述发光单元的阳极电连接，以使在一个预设帧显示画面内，所述第二像素单元的亮度为所述第一像素单元的亮度的2倍。
其中，所述多个并联的像素单元还包括至少一个第三像素单元，所述第三像素单元与所述第二像素单元并联；
所述第三像素单元包括第三数字信号控制器，所述第三数字信号控制器与预设数量的发光单元的阳极电连接，所述预设数量的发光单元并联，所述预设数量为所述第二像素单元中发光单元的数量的偶数倍，以使在一个预设帧画面内，所述第三像素单元的亮度为所述第二像素单元的亮度的偶数倍。
其中，所述像素驱动电路还包括多条竖向排列的数据线与多条横向排列的扫描线，所述数据线给所述选址晶体管的源极提供数据信号，所述扫描线给所述选址晶体管的栅极提供扫描信号，以使所述选址晶体管的漏极给所述存储电容提供所述电流信号。
其中，所述数字信号控制器为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
有益效果
本申请的有益效果是：区别于现有技术，本申请提供的像素驱动电路，通过增加数字信号控制器，能够控制发光单元周期性发光，以实现空间复用与时分复用配合，进而改善像素驱动电路灰阶切换频率过快、占用空间较大的问题。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的电路示意图。
图2为本申请实施例提供的像素驱动电路的时序示意图。
图3为本申请实施例提供的像素驱动电路的另一电路示意图。
图4为本申请实施例提供的像素驱动电路的另一电路示意图。
本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请实施例提供一种像素驱动电路，以下分别进行详细说明。
请参见图1、图3与图4，该图为本申请实施例所提供的像素驱动电路结构示意图，本申请实施例提供一种像素驱动电路10，所述像素驱动电路10包括选址晶体管T1、驱动晶体管T2、存储电容Cst以及多个并联的像素单元L；所述选址晶体管T1的漏极s与所述驱动晶体管T2的栅极g电性连接；
所述存储电容Cst的一端连接所述驱动晶体管T2的栅极g，另一端连接所述驱动晶体管T2的漏极d；
所述像素单元L与所述驱动晶体管T2的漏极d连接，所述像素单元M包括 至少一个数字信号控制器Ctr，所述数字信号控制器Ctr与多个发光单元M的阳极串联；
所述选址晶体管T2的栅极g接收扫描信号，所述数字信号控制器Ctr提供数字信号DS，所述扫描信号scan与所述数字信号DS使所述发光单元M呈周期性发光，形成预设帧显示画面。
所述驱动晶体管T2的的源极s接入电源正电压Vss，所述发光单元M的阴极接入电源负电压Vdd，所述扫描信号scan、所述电源正电压Vss与所述电源负电压Vdd共同作用于所述驱动晶体管T2，形成所述驱动晶体管T2的漏极d的电流信号ES；
进一步的，请参见图1与图2，图2为本申请实施例提供的像素驱动电路的预设周期示意图，所述数字信号控制器Ctr提供预设选址周期TA的数字信号DS，所述数字信号DS与所述电流信号ES均传送至所述发光单元M的阳极，以使所述电流信号ES呈预设显示周期TL，所述发光单元M在预设显示周期TL内发光，在所述预设选址周期TA内发光亮度相较于预设显示周期TL内较弱；
所述选址周期TA与所述显示周期TL共同形成预设帧显示画面的预设周期T，以使所述发光单元M构成所述预设帧显示画面。
进一步的，所述像素驱动电路10还包括多条竖向排列的数据线与多条横向排列的扫描线，所述数据线给所述选址晶体管T1的源极s提供数据信号data，所述扫描线给所述选址晶体管T1的栅极g提供扫描信号scan，以使所述选址晶体管T1的漏极d给所述存储电容Cst提供所述电流信号ES。
在本申请实施例提供的像素驱动电路10中，通过在像素驱动电路10的驱动晶体管的T2的漏极d提供至少一个数字信号控制器Ctr以及多个发光单元M， 数字信号控制器Ctr给发光单元M提供选址周期TA的数字信号DS，所述扫描信号scan、所述电源正电压Vss与所述电源负电压Vdd共同作用于所述驱动晶体管T2，形成所述驱动晶体管T2的漏极d的预设显示周期TL的电流信号ES，使得所述选址周期TA与所述显示周期TL共同形成预设帧显示画面的预设周期T，使得该像素单元L呈预设帧显示画面的预设周期T，该发光单元M呈周期性发光。
进一步的，该像素驱动电路10的周期性发光的原理如下：
该扫描信号scan包括高脉冲与低脉冲，该扫描信号scan变化进而控制选址晶体管T1的开启与关闭；
在所述扫描信号scan为高脉冲时，所述选址晶体管T1开启，所述选址晶体管T1的栅极g接收到扫描信号scan，所述存储电容Cst存储所述扫描信号scan并转换成对应的电流信号ES；
在所述扫描信号scan为低脉冲时，所述选址晶体管T1关闭，所述存储电容Cst向所述驱动晶体管T2的栅极g提供电流信号ES，当所述电流信号ES的电流值达到所述驱动晶体管T2的电流阈值时，所述驱动晶体管T2开启，所述发光单元M发光。
进一步的，在图2中，所述扫描信号scan、数字信号data与电流信号ES相组合，在一个预设周期T内先后对应一个所述预设选址周期TA及一个所述预设显示周期TL：
在所述选址周期TA时，所述扫描信号scan为高电位脉冲，所述电流信号ES为低电位，所述数字信号DS为高电平。此时像素驱动电路10中的发光单元M发光。
在所述显示周期TL时，所述扫描信号scan为低电位脉冲，所述电流信号ES为高电位，所述数字信号DS为低电平。此时像素驱动电路10中的发光单元M发光。
需要说明的是，上述实施例解释本申请实施例所提供的像素驱动电路10的周期性发光的原理，接下来，将具体的对本像素驱动电路10中时分复用及空间复用原理进行具体说明。
请参见图3，图3为本申请实施例所提供的像素驱动电路的另一电路示意图。该像素驱动电路11在图1中像素驱动电路10的基础上进行空间复用，具体如下：
在该像素驱动电路11中，像素单元L的数量为至少一个以上，且该像素单元L并联设置于该驱动晶体管T2的漏极d；
所述多个并联的像素单元L包括第一像素单元L1与第二像素单元L2，所述第一像素单元L1包括第一数字信号控制器Ctr1与一个发光单元M1，所述第一数字信号控制器Ctr1与一个所述发光单元M1的阳极电连接；
所述第二像素单元L2包括第二数字信号控制器Ctr2与两个并联的发光单元M2，所述第二数字信号控制器Ctr2与两个所述发光单元M2的阳极电连接，以使在一个预设帧显示画面内，所述第二像素单元L2的亮度为所述第一像素单元L1的亮度的2倍。
进一步的，在该图2中的时序图中，当一个所述像素单元L中，在一个预设周期T内，所述预设显示周期TL是所述预设选址周期TA的2倍，因此在本申请实施例提供的像素驱动电路11中。
当只有第一数字信号控制器Ctr1开启，第二数字信号控制器Ctr2关闭时，共可显示2×2＝4种灰阶。而当第一数字信号控制器Ctr1和第二数字信号控制器 Ctr2同时作用时，其第一数字信号控制器Ctr1与第二数字信号控制器Ctr2对应的第一像素单元L1与第二像素单元L2则可显示10个灰阶，具体实现如下表1所示；
Figure PCTCN2019106107-appb-000001
表1
由上述可知，该像素驱动电路11中，在一个预设周期T内，所述预设显示周期TL是所述预设选址周期TA的2倍，因此在一个像素单元L中，一个预设周期T内，预设显示周期TL内发光单元M所发出的灰阶亮度为预设选址周期TA内开启相同时长所发出的亮度的2倍。譬如，假设在第一像素单元L1中，预设选址周期TA对应的灰阶亮度为1时，则在预设显示周期TL内对应的灰阶亮度为2；又因为所述第二像素单元L2的亮度为所述第一像素单元L1的亮度的2 倍，因此在第二像素单元L2中，该第二像素单元L2的整体灰阶亮度为该第一像素单元L1的灰阶亮度的2倍，即在第二像素单元L2中，其预设选址周期TA对应的灰阶亮度为2时，其在预设显示周期TL内对应的灰阶亮度为4。
因此，在该像素驱动电路11中，当该像素驱动电路11的总灰阶亮度呈9时，即该第一数字信号控制器Ctr1与第二数字信号控制器Ctr2同时开启，则该总灰阶亮度为1×1+1×2+1×2+1×4＝9，因此该像素驱动电路11可实现9+1＝10种灰阶亮度。
在本申请实施例提供的像素驱动电路11中，仅仅采取了一个第二像素单元L2，且该第二像素单元L2中的两个并联的发光单元M2与第二数字信号控制器Ctr2相配合，实现了该像素驱动电路的多种灰阶亮度显示，此像素驱动电路11在减少像素单元L空间占用的同时，也减少了原现有技术的开关晶体管的栅极的信号切换频率，降低了实现多灰阶亮度变化的难度。
在一些实施例中，该像素单元L的数量不仅限于两个像素单元，请参见图4，该图为本申请实施例提供的像素驱动电路的另一电路示意图。
在该像素驱动电路12中，所述多个并联的像素单元L还包括至少一个第三像素单元L3，所述第三像素单元L3与所述第二像素单元L2并联；
所述第三像素单元L3包括第三数字信号控制器Ctr3，所述第三数字信号控制器Ctr3与预设数量的发光单元M3的阳极电连接，所述预设数量的发光单元M3并联，所述预设数量为所述第二像素单元L2中发光单元M2的数量的偶数倍，以使在一个预设帧画面内，所述第三像素单元L3的亮度为所述第二像素单元L2的亮度的偶数倍。譬如，假设上述可知，在一个预设周期T内，所述预设显示周期TL是所述预设选址周期TA的2倍时，该第三像素单元L3中的发光单元为4 时，则该第三像素单元L3的灰阶亮度为该第二像素单元L2的灰阶亮度的两倍，其具体实现如下表2所示:
Figure PCTCN2019106107-appb-000002
Figure PCTCN2019106107-appb-000003
表2
当该第一数字信号控制器Ctr1、第二数字信号控制器Ctr2与第三数字信号控制器Ctr3同时开启时，则该总灰阶亮度为1×1+1×2+1×2+1×4+1×4+1×8＝21，因此该像素驱动电路12可实现21+1＝22种灰阶亮度。
在一些申请实施例中，所述数字信号控制器Ctr还与外部电路的时序控制器(图中未示出)连接，所述数字信号的预设选址周期TA与所述电流信号的预设显示周期TL均由所述时序控制器提供。
所述选址晶体管T1与驱动晶体管T2均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。除此之外，该数字信号控制器Ctr也可为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
基于同一申请构思，本发明实施例提供了一种显示装置，该显示装置包括本申请任意实施例提供的像素驱动电路。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有益效果为：在像素驱动电路中增加数字信号控制器，使其控制发光单元周期性发光，以实现空间复用与时分复用配合，改善像素驱动电路灰阶切换频率过 快、占用空间较大的问题。
除上述实施例外，本申请还可以有其他实施方式。凡采用等同替换或等效替换形成的技术方案，均落在本申请要求的保护范围。
综上所述，虽然本申请已将优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种像素驱动电路，其包括选址晶体管、驱动晶体管、存储电容以及多个并联的像素单元；
    所述选址晶体管的漏极与所述驱动晶体管的栅极电性连接；
    所述存储电容的一端连接所述驱动晶体管的栅极，另一端连接所述驱动晶体管的漏极；
    所述像素单元与所述驱动晶体管的漏极连接，所述像素单元包括至少一个数字信号控制器，所述数字信号控制器与多个发光单元的阳极串联；
    所述选址晶体管的栅极接收扫描信号，所述数字信号控制器提供数字信号，所述扫描信号与所述数字信号使所述发光单元呈周期性发光，形成预设帧显示画面。
  2. 根据权利要求1所述的像素驱动电路，其中，所述驱动晶体管的的源极接入电源正电压，所述发光单元的阴极接入电源负电压，所述扫描信号、所述电源正电压与所述电源负电压共同作用于所述驱动晶体管，形成所述驱动晶体管的漏极的电流信号；
    所述数字信号控制器提供预设选址周期的数字信号，所述数字信号与所述电流信号均传送至所述发光单元的阳极，以使所述电流信号呈预设显示周期，所述发光单元在预设显示周期内发光；
    所述选址周期与所述显示周期共同形成预设帧显示画面的预设周期，以使所述发光单元构成所述预设帧显示画面。
  3. 根据权利要求2所述的像素驱动电路，其中，
    在所述扫描信号为高脉冲时，所述选址晶体管开启，所述选址晶体管的栅极 接收到扫描信号，所述存储电容存储所述扫描信号并转换成对应的电流信号；
    在所述扫描信号为低脉冲时，所述选址晶体管关闭，所述存储电容向所述驱动晶体管的栅极提供电流信号，当所述电流信号的电流值达到所述驱动晶体管的电流阈值时，所述驱动晶体管开启，所述发光单元发光。
  4. 根据权利要求2所述的像素驱动电路，其中，所述扫描信号、数字信号与电流信号相组合，在一个预设周期内先后对应一个所述预设选址周期及一个所述预设显示周期：
    在所述选址周期时，所述扫描信号为高电位脉冲，所述电流信号为低电位，所述数字信号为高电平；
    在所述显示周期时，所述扫描信号为低电位脉冲，所述电流信号为高电位，所述数字信号为低电平。
  5. 根据权利要求2所述的像素驱动电路，其中，一个所述像素单元中，在一个预设周期内，所述预设显示周期是所述预设选址周期的2倍。
  6. 根据权利要求1所述的像素驱动电路，其中，所述多个并联的像素单元包括第一像素单元与第二像素单元，所述第一像素单元包括第一数字信号控制器与一个发光单元，所述第一数字信号控制器与一个所述发光单元的阳极电连接；
    所述第二像素单元包括第二数字信号控制器与两个并联的发光单元，所述第二数字信号控制器与两个所述发光单元的阳极电连接，以使在一个预设帧显示画面内，所述第二像素单元的亮度为所述第一像素单元的亮度的2倍。
  7. 根据权利要求6所述的像素驱动电路，其中，所述多个并联的像素单元还包括至少一个第三像素单元，所述第三像素单元与所述第二像素单元并联；
    所述第三像素单元包括第三数字信号控制器，所述第三数字信号控制器与预 设数量的发光单元的阳极电连接，所述预设数量的发光单元并联，所述预设数量为所述第二像素单元中发光单元的数量的偶数倍，以使在一个预设帧画面内，所述第三像素单元的亮度为所述第二像素单元的亮度的偶数倍。
  8. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括多条竖向排列的数据线与多条横向排列的扫描线，所述数据线给所述选址晶体管的源极提供数据信号，所述扫描线给所述选址晶体管的栅极提供扫描信号，以使所述选址晶体管的漏极给所述存储电容提供所述电流信号。
  9. 根据权利要求1所述的像素驱动电路，其中，所述数字信号控制器为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  10. 一种显示装置，其包括像素驱动电路，所述像素驱动电路包括选址晶体管、驱动晶体管、存储电容以及多个并联的像素单元；其中，
    所述选址晶体管的漏极与所述驱动晶体管的栅极电性连接；
    所述存储电容的一端连接所述驱动晶体管的栅极，另一端连接所述驱动晶体管的漏极；
    所述像素单元与所述驱动晶体管的漏极连接，所述像素单元包括至少一个数字信号控制器，所述数字信号控制器与多个发光单元的阳极串联；
    所述选址晶体管的栅极接收扫描信号，所述数字信号控制器提供数字信号，所述扫描信号与所述数字信号使所述发光单元呈周期性发光，形成预设帧显示画面。
  11. 根据权利要求10所述的显示装置，其中，所述驱动晶体管的的源极接入电源正电压，所述发光单元的阴极接入电源负电压，所述扫描信号、所述电源正电压与所述电源负电压共同作用于所述驱动晶体管，形成所述驱动晶体管的漏极 的电流信号；
    所述数字信号控制器提供预设选址周期的数字信号，所述数字信号与所述电流信号均传送至所述发光单元的阳极，以使所述电流信号呈预设显示周期，所述发光单元在预设显示周期内发光；
    所述选址周期与所述显示周期共同形成预设帧显示画面的预设周期，以使所述发光单元构成所述预设帧显示画面。
  12. 根据权利要求11所述的显示装置，其中，
    在所述扫描信号为高脉冲时，所述选址晶体管开启，所述选址晶体管的栅极接收到扫描信号，所述存储电容存储所述扫描信号并转换成对应的电流信号；
    在所述扫描信号为低脉冲时，所述选址晶体管关闭，所述存储电容向所述驱动晶体管的栅极提供电流信号，当所述电流信号的电流值达到所述驱动晶体管的电流阈值时，所述驱动晶体管开启，所述发光单元发光。
  13. 根据权利要求11所述的显示装置，其中，所述扫描信号、数字信号与电流信号相组合，在一个预设周期内先后对应一个所述预设选址周期及一个所述预设显示周期：
    在所述选址周期时，所述扫描信号为高电位脉冲，所述电流信号为低电位，所述数字信号为高电平；
    在所述显示周期时，所述扫描信号为低电位脉冲，所述电流信号为高电位，所述数字信号为低电平。
  14. 根据权利要求11所述的显示装置，其中，一个所述像素单元中，在一个预设周期内，所述预设显示周期是所述预设选址周期的2倍。
  15. 根据权利要求10所述的显示装置，其中，所述多个并联的像素单元包括 第一像素单元与第二像素单元，所述第一像素单元包括第一数字信号控制器与一个发光单元，所述第一数字信号控制器与一个所述发光单元的阳极电连接；
    所述第二像素单元包括第二数字信号控制器与两个并联的发光单元，所述第二数字信号控制器与两个所述发光单元的阳极电连接，以使在一个预设帧显示画面内，所述第二像素单元的亮度为所述第一像素单元的亮度的2倍。
  16. 根据权利要求15所述的显示装置，其中，所述多个并联的像素单元还包括至少一个第三像素单元，所述第三像素单元与所述第二像素单元并联；
    所述第三像素单元包括第三数字信号控制器，所述第三数字信号控制器与预设数量的发光单元的阳极电连接，所述预设数量的发光单元并联，所述预设数量为所述第二像素单元中发光单元的数量的偶数倍，以使在一个预设帧画面内，所述第三像素单元的亮度为所述第二像素单元的亮度的偶数倍。
  17. 根据权利要求10所述的显示装置，其中，所述像素驱动电路还包括多条竖向排列的数据线与多条横向排列的扫描线，所述数据线给所述选址晶体管的源极提供数据信号，所述扫描线给所述选址晶体管的栅极提供扫描信号，以使所述选址晶体管的漏极给所述存储电容提供所述电流信号。
  18. 根据权利要求10所述的显示装置，其中，所述数字信号控制器为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112735341A (zh) * 2020-12-30 2021-04-30 Tcl华星光电技术有限公司 像素驱动电路及显示装置
CN114141195B (zh) * 2021-12-10 2023-05-02 Tcl华星光电技术有限公司 发光器件驱动电路、显示面板及其驱动方法
CN114241976A (zh) * 2021-12-16 2022-03-25 Tcl华星光电技术有限公司 像素电路及显示面板
CN114724516B (zh) * 2022-04-26 2024-02-27 云谷（固安）科技有限公司 显示面板及其控制方法、显示装置
KR20230155635A (ko) * 2022-05-03 2023-11-13 삼성디스플레이 주식회사 표시 장치
CN115240597B (zh) 2022-09-20 2023-01-10 惠科股份有限公司 像素电路、显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1523552A (zh) * 2003-02-17 2004-08-25 友达光电股份有限公司 主动矩阵式显示器的像素结构
CN101355833A (zh) * 2007-07-27 2009-01-28 三星Sdi株式会社 有机发光显示器及其驱动方法
US7688370B2 (en) * 2004-12-06 2010-03-30 Silicon Display Technology Co., Ltd. Active pixel sensor array
CN104599641A (zh) * 2015-03-02 2015-05-06 京东方科技集团股份有限公司 Oled像素单元及其驱动方法、oled显示装置
CN104680973A (zh) * 2013-11-26 2015-06-03 乐金显示有限公司 有机发光显示装置及其驱动方法
CN110033730A (zh) * 2018-04-18 2019-07-19 友达光电股份有限公司 复合式驱动显示面板
CN110047435A (zh) * 2019-04-23 2019-07-23 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板和显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7768487B2 (en) * 2004-12-31 2010-08-03 Lg. Display Co., Ltd. Driving system for an electro-luminescence display device
JP2009109521A (ja) * 2007-10-26 2009-05-21 Sony Corp 表示装置、表示装置の駆動方法および電子機器
CN101540130B (zh) * 2008-03-19 2012-12-26 凌通科技股份有限公司 视觉暂留图像显示装置以及其扫描方法
KR101374443B1 (ko) * 2008-10-10 2014-03-17 엘지디스플레이 주식회사 유기발광다이오드 표시장치
CN103489401B (zh) * 2013-09-03 2016-11-23 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板和显示装置
CN104752468A (zh) * 2013-12-30 2015-07-01 昆山工研院新型平板显示技术中心有限公司 实现高显示密度的像素电路和显示电路
CN105185321B (zh) * 2015-10-27 2018-05-29 深圳市华星光电技术有限公司 Amoled驱动电路、显示面板及显示器
CN107818759B (zh) * 2016-09-14 2023-09-19 合肥鑫晟光电科技有限公司 像素驱动电路及像素驱动方法、阵列基板以及显示装置
CN107170408B (zh) * 2017-06-27 2019-05-24 上海天马微电子有限公司 像素电路、驱动方法、有机电致发光显示面板及显示装置
CN107221557A (zh) * 2017-07-27 2017-09-29 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN108649059B (zh) * 2018-05-14 2020-12-08 京东方科技集团股份有限公司 一种阵列基板、显示装置及其驱动方法
CN110070831B (zh) * 2019-04-19 2021-08-06 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1523552A (zh) * 2003-02-17 2004-08-25 友达光电股份有限公司 主动矩阵式显示器的像素结构
US7688370B2 (en) * 2004-12-06 2010-03-30 Silicon Display Technology Co., Ltd. Active pixel sensor array
CN101355833A (zh) * 2007-07-27 2009-01-28 三星Sdi株式会社 有机发光显示器及其驱动方法
CN104680973A (zh) * 2013-11-26 2015-06-03 乐金显示有限公司 有机发光显示装置及其驱动方法
CN104599641A (zh) * 2015-03-02 2015-05-06 京东方科技集团股份有限公司 Oled像素单元及其驱动方法、oled显示装置
CN110033730A (zh) * 2018-04-18 2019-07-19 友达光电股份有限公司 复合式驱动显示面板
CN110047435A (zh) * 2019-04-23 2019-07-23 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板和显示装置

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