WO2023130222A1 - 显示面板的控制方法及控制装置、显示装置 - Google Patents

显示面板的控制方法及控制装置、显示装置 Download PDF

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Publication number
WO2023130222A1
WO2023130222A1 PCT/CN2022/070150 CN2022070150W WO2023130222A1 WO 2023130222 A1 WO2023130222 A1 WO 2023130222A1 CN 2022070150 W CN2022070150 W CN 2022070150W WO 2023130222 A1 WO2023130222 A1 WO 2023130222A1
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WIPO (PCT)
Prior art keywords
display panel
target refresh
data
refresh frequency
light
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PCT/CN2022/070150
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English (en)
French (fr)
Inventor
吴宝云
赵西玉
赵辉
韩新斌
梁尧
王开民
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/070150 priority Critical patent/WO2023130222A1/zh
Priority to CN202280000002.3A priority patent/CN116710994A/zh
Publication of WO2023130222A1 publication Critical patent/WO2023130222A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • This article relates to but is not limited to the field of display technology, especially a method for controlling a display panel, a control device, and a display device.
  • Organic Light Emitting Diode (OLED, Organic Light Emitting Display) display device has the advantages of self-illumination, high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, light in the use temperature range, simple structure and manufacturing process, etc. characteristics and is considered to be an emerging application technology for next-generation flat-panel displays.
  • Embodiments of the present disclosure provide a control method, a control device, and a display device of a display panel.
  • an embodiment of the present disclosure provides a method for controlling a display panel, including: determining a target refresh frequency of the display panel; determining a data chopping rule adapted to the target refresh frequency according to the first mapping relationship; according to the The data chopping rule provides data signals to the display panel.
  • the data chopping rule includes one of the following: frame inversion and dot inversion.
  • the determining the target refresh frequency of the display panel includes one of the following: determining the target refresh frequency of the display panel according to the received frame rate switching command; by analyzing the received MIPI data, A target refresh rate of the display panel is determined.
  • control method of this embodiment further includes: determining a lighting start signal compensation amount corresponding to the target refresh frequency according to the second mapping relationship.
  • control method of this embodiment further includes: when the display panel is switched to the target refresh rate, using the light emission start signal compensation amount corresponding to the target refresh frequency to adjust the light emission start The signal is compensated.
  • control method of this embodiment further includes: determining a gamma voltage compensation amount corresponding to the target refresh frequency according to a third mapping relationship.
  • control method of this embodiment further includes: when the display panel is switched to the target refresh rate, using the gamma voltage compensation amount corresponding to the target refresh rate to provide the The data voltage of the display panel is compensated.
  • an embodiment of the present disclosure provides a control device for a display panel, including: a frequency determination module configured to determine a target refresh frequency of the display panel; a rule determination module configured to determine the target refresh frequency according to a first mapping relationship Refresh the data chopping rules for frequency adaptation; the control module is configured to provide data signals to the display panel according to the data chopping rules.
  • control device of this embodiment further includes: a first compensation module, configured to determine a lighting start signal compensation amount corresponding to the target refresh frequency according to the second mapping relationship; when the display The panel is switched to the target refresh frequency, and the light-emitting start signal is compensated by using the compensation amount of the light-emitting start signal corresponding to the target refresh frequency.
  • control device of this embodiment further includes: a second compensation module configured to determine a gamma voltage compensation amount corresponding to the target refresh frequency according to a third mapping relationship; when the display panel switch to the target refresh frequency, and use the gamma voltage compensation amount corresponding to the target refresh frequency to compensate the data voltage provided to the display panel.
  • a second compensation module configured to determine a gamma voltage compensation amount corresponding to the target refresh frequency according to a third mapping relationship; when the display panel switch to the target refresh frequency, and use the gamma voltage compensation amount corresponding to the target refresh frequency to compensate the data voltage provided to the display panel.
  • an embodiment of the present disclosure provides a display device, including a display panel and the above-mentioned control device.
  • the display panel includes: a pixel array, the pixel array includes a plurality of sub-pixels, at least one sub-pixel includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light; the pixel circuit includes: a plurality of transistors and at least one capacitor.
  • an embodiment of the present disclosure provides a control device, including: a memory and a processor; the memory is configured to store a computer program, and the processor is configured to execute the computer program to implement the above control method.
  • an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing a computer program, and implementing the above-mentioned control method when the computer program is executed.
  • FIG. 1 is a flowchart of a control method of a display panel in at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a display device according to at least one embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a working timing diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • 5A and 5B are schematic diagrams of the principle of the data chopping function of at least one embodiment of the present disclosure
  • 6A and 6B are schematic diagrams of data chopping rules in at least one embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of ESTV compensation in at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of gamma voltage compensation according to at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a control device of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 10 is another schematic diagram of a control device of a display panel according to at least one embodiment of the present disclosure.
  • Fig. 11 is another schematic diagram of a control device according to at least one embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • the screen refresh rate of the OLED display panel can be reduced to 1 Hertz (Hz) or even lower. Since the brightness change frequency recognizable by the human eye is about 24Hz to 30Hz, for a display panel based on LTPO technology, when performing low-frequency (that is, lower than the conventional 60Hz refresh rate) display, the brightness of the entire screen needs to be kept constant. Low-frequency brightness changes cannot be introduced during the display process.
  • LTPO Low Temperature Polycrystalline Oxide
  • Embodiments of the present disclosure provide a control method, a control device, and a display device for a display panel, which can improve the display effect of the display panel.
  • FIG. 1 is a flowchart of a method for controlling a display panel according to at least one embodiment of the present disclosure. As shown in FIG. 1 , an embodiment of the present disclosure provides a method for controlling a display panel, including:
  • Step S11 determining the target refresh frequency of the display panel
  • Step S12 According to the first mapping relationship, determine a data chopping rule adapted to the target refresh frequency
  • Step S13 according to the data chopping rule, provide the data signal to the display panel.
  • control method of this embodiment can be used to control the display of the OLED display panel.
  • this embodiment does not limit it.
  • the control method of this embodiment may be applied to a display driver integrated circuit (DDIC, Display Driver Integrated Circuit) chip.
  • DDIC Display Driver Integrated Circuit
  • AP Application Processor
  • DDIC chip controls the display panel to perform image processing based on the image data. show.
  • the DDIC chip can output the data signal to the display panel according to the data chopping rule, thereby improving the display effect of the display panel.
  • the data chopping rule may include one of the following: frame flipping, dot flipping. However, this embodiment does not limit it.
  • the data chopping rule may also include: row flipping, column flipping, and the like.
  • control method of this embodiment may further include: determining a lighting start signal compensation amount corresponding to the target refresh frequency according to the second mapping relationship.
  • control method of this embodiment may further include: when the display panel is switched to the target refresh frequency, using the compensation amount of the light start signal corresponding to the target refresh frequency to compensate the light start signal.
  • the control method of this embodiment may further include: when the display panel is switched to the target refresh frequency, using the compensation amount of the light start signal corresponding to the target refresh frequency to compensate the light start signal.
  • control method of this embodiment may further include: determining the gamma voltage compensation amount corresponding to the target refresh frequency according to the third mapping relationship.
  • control method of this embodiment may further include: when the display panel is switched to the target refresh rate, using the gamma voltage compensation amount corresponding to the target refresh rate to compensate the data voltage provided to the display panel .
  • the control method of this embodiment may further include: when the display panel is switched to the target refresh rate, using the gamma voltage compensation amount corresponding to the target refresh rate to compensate the data voltage provided to the display panel .
  • FIG. 2 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device of this exemplary embodiment may include: a display panel and a control device.
  • the control device may include a DDIC chip 10 .
  • the display panel may include: a pixel array 13, a plurality of first signal lines (for example, scanning lines GL1 to GLm, light emission control lines EML1 to EMLo) extending along a first direction, and a plurality of second signal lines extending along a second direction. (eg, data lines DL1 to DLn).
  • the first direction (such as the horizontal direction) intersects with the second direction (such as the vertical direction), for example, the first direction and the second direction may be perpendicular to each other.
  • m, n and o are all integers.
  • the display panel is also provided with a gate driving circuit (eg, including a first gate driving circuit 11 and a second gate driving circuit 12 ).
  • the DDIC chip 10 and the gate driving circuit can be configured to drive the pixel array 13 .
  • the DDIC chip 10 may supply a clock signal, a start signal, etc. suitable for the specification of the first gate driving circuit 11 to the first gate driving circuit 11, and may supply a clock signal suitable for the specification of the second gate driving circuit 12.
  • a clock signal, a start signal, etc. of specifications are supplied to the second gate driving circuit 12 .
  • the first gate driving circuit 11 may generate scan signals supplied to the scan lines GL1 to GLm using a clock signal, a start signal, etc. received from the DDIC chip 10 .
  • the second gate driving circuit 12 may generate light emission control signals supplied to the light emission control lines EML1 to EMLm using a clock signal received from the DDIC chip 10 , a light emission start signal, and the like.
  • the DDIC chip 10 may also be adapted to generate data signals provided to the data lines DL1 to DLn.
  • the first gate driving circuit 11 may sequentially supply scan signals having turn-on level pulses to the scan lines GL1 to GLm.
  • the first gate driving circuit 11 may be configured in the form of a shift register, and may sequentially transmit a start signal provided in the form of a conduction level pulse to a next-stage circuit under the control of a clock signal. Generate scan signal.
  • the second gate driving circuit 12 may sequentially supply light emission control signals having off-level pulses to the light emission control lines EML1 to EMLo.
  • the second gate driving circuit 12 may be configured in the form of a shift register, and may sequentially transmit the light-emitting start signal provided in the form of an off-level pulse to the next-stage circuit under the control of a clock signal. Generate a light control signal.
  • this embodiment does not limit it.
  • the pixel array 13 may include a plurality of sub-pixels PX.
  • One pixel unit may include three sub-pixels. The three sub-pixels are red sub-pixel, green sub-pixel and blue sub-pixel respectively. However, this embodiment does not limit it.
  • one pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.
  • the shape of a sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels can be arranged horizontally, vertically or squarely; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely .
  • this embodiment does not limit it.
  • At least one sub-pixel PX includes: a light emitting element and a pixel circuit for driving the light emitting element to emit light.
  • the light emitting element is electrically connected with the corresponding pixel circuit.
  • the light-emitting element may be an OLED device, including an anode, a cathode, and an organic light-emitting layer between the anode and the cathode.
  • a pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may have a structure such as 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 8T2C. However, this embodiment does not limit it.
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a working timing diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit of this exemplary embodiment has a 7T1C structure. However, this embodiment does not limit it.
  • the pixel circuit of this example includes six switching transistors ( T1 , T2 , T4 to T7 ), one driving transistor T3 and one storage capacitor Cst.
  • the six switch transistors are data writing transistor T4, threshold compensation transistor T2, first light emission control transistor T5, second light emission control transistor T6, first reset transistor T1, and second reset transistor T7.
  • the light emitting element EL includes an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switch transistors may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • the display substrate includes a scan line GL, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second Two initial signal lines INIT2, a first reset control line RST1 and a second reset control line RST2.
  • the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than The second voltage signal VSS.
  • the scan line GL is configured to provide a scan signal SCAN to the pixel circuit
  • the data line DL is configured to provide a data signal DATA to the pixel circuit
  • the light emission control line EML is configured to provide a light emission control signal EM to the pixel circuit
  • the first reset control line RST1 is configured to provide a light emission control signal EM to the pixel circuit.
  • the pixel circuit provides a first reset control signal RESET1
  • the second reset control line RST2 is configured to provide a second reset control signal RESET2 to the pixel circuit.
  • the first reset control line RST1 may be electrically connected to the scan line GL of the n-1th row of pixel circuits, so as to be input with the scan signal SCAN(n-1), that is, the first The reset control signal RESET1(n) is the same as the scan signal SCAN(n-1).
  • the second reset control line RST2 may be electrically connected to the scan line GL of the nth row of pixel circuits to receive the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n).
  • the second reset control line RST2 electrically connected to the pixel circuit in the nth row and the first reset control line RST1 electrically connected to the pixel circuit in the n+1th row have an integral structure. In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • this embodiment does not limit it.
  • the first initial signal line INIT1 is configured to provide the first initial signal to the pixel circuit
  • the second initial signal line INIT2 is configured to provide the second initial signal to the pixel circuit.
  • the first initial signal and the second initial signal may be constant voltage signals whose magnitude may be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto.
  • the driving transistor T3 is electrically connected to the light emitting element EL, and is controlled by signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS. Output driving current to drive the light emitting element EL to emit light.
  • the gate of the data writing transistor T4 is electrically connected to the scanning line GL
  • the first pole of the data writing transistor T4 is electrically connected to the data line DL
  • the second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T3 .
  • the gate of the threshold compensation transistor T2 is electrically connected to the scanning line GL
  • the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3
  • the second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3 .
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML
  • the first pole of the first light emission control transistor T5 is electrically connected to the first power line PL1
  • the second pole of the first light emission control transistor T5 is connected to the driving transistor T3.
  • the first pole is electrically connected.
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML
  • the first pole of the second light emission control transistor T6 is electrically connected to the second pole of the driving transistor T3
  • the second pole of the second light emission control transistor T6 is connected to the light emission control line EML.
  • the anode of the element EL is electrically connected.
  • the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is electrically connected to the anode of the light emitting element EL, and is configured to reset the gate of the light emitting element EL. Anode resets.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first reset transistor T1 is electrically connected to the driving transistor T3.
  • the grid is electrically connected.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first pole of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the second reset transistor T7 is connected to the light emitting element EL. anode electrical connection.
  • the first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T7 and the light emission control transistor T6.
  • the connection point of the element EL is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T
  • the pixel circuit shown in FIG. 3 includes a plurality of transistors that are all P-type transistors as an example for illustration.
  • the working process of the pixel circuit with the first structure includes: a first stage S1 , a second stage S2 and a third stage S3 .
  • the first stage S1 is called the reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal to turn on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1.
  • the first node N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the data is written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second The second light emitting control transistor T6 and the second reset transistor T7 are turned off. At this stage, the light emitting element EL does not emit light.
  • the second stage S2 is called a data writing stage or a threshold compensation stage.
  • the scan signal SCAN provided by the scan line GL is a low level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2 to the second node N2.
  • a node N1 and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the drive transistor T3 is charged into the storage capacitor Cst, and the voltage of the first electrode of the storage capacitor Cst (that is, the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is supplied to the anode of the light-emitting element EL, and the anode of the light-emitting element EL is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization. , to ensure that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal to turn off the first reset transistor T1.
  • the light emission control signal EM provided by the light emission control signal line EML is a high level signal, which turns off the first light emission control transistor T5 and the second light emission control transistor T6.
  • the third stage S3 is called the lighting stage.
  • the emission control signal EM provided by the emission control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light emission control signal EM provided by the light emission control signal line EML is a low-level signal, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned on
  • the first light emission control transistor T5, the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the anode of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 .
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first pole of the driving transistor T3
  • Vth is the driving current of the driving transistor T3.
  • Vdata is the data voltage output from the data line DL
  • VDD is the first voltage signal output from the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • the DDIC chip may at least include: a gamma voltage generation circuit.
  • the gamma voltage generation circuit can generate a plurality of gamma reference voltages by using high voltage and low voltage, and generate a plurality of gamma voltages according to the plurality of gamma reference voltages.
  • the gamma voltage generation circuit can provide data voltages to the display panel through multiple data output channels, so as to improve the driving capability of the data voltages.
  • the data chopping function is introduced in the DDIC chip.
  • 5A and 5B are schematic diagrams of the principle of the data chopping function of at least one embodiment of the present disclosure.
  • the data output channel may include an operational amplifier (for example, operational amplifiers 601 and 602), and the non-inverting input terminal of the operational amplifier may receive the gamma voltage generated by the gamma voltage generating circuit, and the operation The inverting input of the amplifier is electrically connected to the output of the operational amplifier.
  • the operational amplifier 601 Due to the influence of the DDIC chip manufacturing process, there will be differences in operational amplifiers, so that the data output channel will generate an offset voltage (offset).
  • the operational amplifier 601 generates a positive polarity offset voltage ⁇ V.
  • the data voltage Vout1 Vgma+ ⁇ V output from the first output terminal OUT1 .
  • the operational amplifier 602 generates a negative polarity offset voltage ⁇ V.
  • the data voltage Vout2 Vgma ⁇ V output from the second output terminal OUT2 .
  • the data output channels of the DDIC chip are affected by differences in operational amplifiers, and the output data voltages thereof will have different offset voltages.
  • the expected output data voltages (ie, gamma voltages) of multiple data output channels are Vgma1, Vgma2, Vgma3, ... respectively, but due to the influence of the offset voltage brought by the operational amplifier, the multiple data voltage output channels actually The output data voltages will become Vgma1+ ⁇ V1, Vgma2+ ⁇ V2, Vgma3+ ⁇ V3, . . . .
  • the OLED display panel displays a solid-color picture
  • the vertical bar display problem will be caused due to different offset voltages output by different data output channels.
  • the data chopping function is introduced, that is, the data voltages output by different data output channels are equalized in the time domain.
  • different data output channels are made to output Vgma+ ⁇ V or Vgma- ⁇ V at different time points, that is, to output offset voltages of different polarities. In this way, from the perspective of time domain, the output data voltage of the data output channel can be Vgma on average.
  • the data output channel may include: an operational amplifier circuit and a chopper control circuit.
  • the operational amplifier circuit may include a first operational amplifier (such as operational amplifier 601 in FIG. 5A ) and a second operational amplifier (such as operational amplifier 602 in FIG. 5B ).
  • the input terminal of the operational amplifier circuit can be electrically connected with the non-inverting input terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the first operational amplifier is electrically connected with the output terminal of the first operational amplifier, and the second The inverting input terminal of the operational amplifier is electrically connected with the output terminal of the second operational amplifier.
  • the chopper control circuit may be electrically connected to the output terminal of the first operational amplifier and the output terminal of the second operational amplifier, configured to control the output terminal of the first operational amplifier to output a data voltage, or control the output terminal of the second operational amplifier to output a data voltage .
  • this embodiment does not limit it.
  • the display control of the display panel may be performed according to the data chopping rule, so as to improve the display effect of the display panel.
  • the data chopping rule may include at least one of the following: frame inversion, dot inversion.
  • the data chopping rule refers to a rule for the DDIC chip to realize the data chopping function.
  • the DDIC chip can control the polarity of the offset voltage carried by the data voltage according to the data chopping rule.
  • FIG. 6A and 6B are schematic diagrams of data chopping rules according to at least one embodiment of the present disclosure.
  • FIG. 6A is a schematic diagram of a frame flipping rule
  • FIG. 6B is a schematic diagram of a dot flipping rule.
  • Frame inversion refers to the polarity transformation of the offset voltage of the data signal between two consecutive frames
  • point inversion refers to the polarity transformation of the offset voltage of the data signal between two adjacent points of each frame, and the phase There is also a polarity change of the offset voltage between two adjacent frames.
  • "+" means generating a positive polarity offset voltage. For example, as shown in FIG.
  • Vout1 Vgma+ ⁇ V
  • ⁇ V represents an offset voltage.
  • "-" indicates that a negative polarity offset voltage is generated.
  • the left figure shows the offset voltage polarity in the current i-th frame
  • the middle figure shows the offset voltage polarity in the i+1-th frame
  • the right figure shows the i+1-th frame 2 frames of offset voltage polarity.
  • the polarities of the offset voltages corresponding to the subpixels of the current i-th frame are the same, for example, they are all positive
  • the polarities of the offset voltages corresponding to the subpixels of the i+1th frame are all opposite to those of the previous frame, for example They are all negative
  • the polarities of the offset voltages corresponding to the sub-pixels in the i+2th frame are all opposite to those of the previous frame, for example, they are all positive.
  • the polarity of the offset voltage corresponding to each sub-pixel in the current i-th frame is opposite to the polarity of the offset voltage corresponding to the sub-pixels adjacent up, down, left, and right. For example, a certain sub-pixel in the i-th frame If the polarity of the corresponding offset voltage is positive, then the polarities of the offset voltages corresponding to the four adjacent sub-pixels up, down, left, and right of the sub-pixel are all negative. Similarly, the polarity of the offset voltage corresponding to the subpixels in the i+1th frame and the i+2th frame has a similar rule to the polarity of the offset voltage corresponding to the subpixels in the ith frame.
  • the polarity of the offset voltage corresponding to the sub-pixels in the subsequent frame is opposite to that in the previous frame.
  • the data chopping rule may also include: row flipping, column flipping, and the like.
  • the offset voltage polarities corresponding to the subpixels in the same column in the current frame are the same, and the offset voltage polarities corresponding to the subpixels in the left and right adjacent columns are opposite, which is called column inversion.
  • the offset voltages corresponding to the sub-pixels in the same row in the current frame have the same polarity, and the offset voltages corresponding to the sub-pixels in the upper and lower adjacent rows have opposite polarities, which is called row inversion.
  • the polarities of the offset voltages corresponding to the sub-pixels in the same two rows in the current frame are the same, and the polarities of the offset voltages corresponding to the sub-pixels in the two adjacent rows up and down are opposite.
  • the DDIC chip can determine the target refresh rate to which the display panel is to be switched.
  • the frame rate switching command may carry a target refresh rate to which the display panel is to be switched.
  • the AP can send MIPI (Mobile Industry Processor Interface) data, and the DDIC chip can determine the target refresh frequency to be switched to after receiving and analyzing the MIPI data.
  • MIPI Mobile Industry Processor Interface
  • the DDIC chip pre-stores a first mapping relationship, and a data chopping rule adapted to the target refresh frequency can be determined according to the first mapping relationship.
  • the first mapping relationship pre-stored in the DDIC chip may include: a column of refresh frequencies and a corresponding column of data chopping rules, and there is a one-to-one correspondence between the refresh frequencies and the data chopping rules.
  • the refresh frequencies in Table 1 may range from about 0 Hz to 120 Hz.
  • the refresh frequency 1 is 60 Hz
  • the corresponding data chopping rule 1 may be point inversion
  • the refresh frequency 2 is 70 Hz
  • the corresponding data chopping rule 2 may be frame inversion.
  • this embodiment does not limit it.
  • the DDIC chip of this embodiment can automatically switch the data chopping rule according to the target refresh frequency of the display panel.
  • the data chopping rule can be determined as frame flipping, thereby saving power consumption; when the target refresh frequency of the display panel is a low-frequency refresh rate, then the data chopping rule can be determined as Dot flip, thereby improving the flickering effect under low frequency display, and further improving the display effect.
  • the data chopping rule can be dynamically changed according to the target refresh frequency of the display panel, so as to ensure the display effect.
  • the second gate drive circuit may include a plurality of cascaded light emission control circuits. Generally, the light emission control circuits control the conduction of multiple transistors in the circuit through clock signals, high-level signals, and low-level signals.
  • the light emission control signal EM output by the light emission control circuit can be provided to the pixel circuit through the light emission control line for controlling the light emitting element to emit light. That is, the duty cycle of the light emission control signal EM can determine the duty cycle of the bright state in the display brightness waveform of the light emitting element. Therefore, when the light emission brightness of the light emitting element is not within the predetermined brightness range, it can be adjusted by adjusting the light emission control signal EM.
  • the duty cycle is to adjust the duty cycle of the bright state in the display brightness waveform of the light-emitting element, so as to realize the control of the light-emitting brightness of the light-emitting element.
  • the lighting start signal ESTV is input from the input terminal, and the lighting control signal EM is output at the output terminal.
  • the lighting control circuit can generate the lighting control signal EM according to the lighting starting signal ESTV. Therefore, the lighting start The duty cycle of the signal ESTV determines the duty cycle of the lighting control signal EM.
  • the duty cycle of the light-emitting control signal EM can be adjusted by adjusting the duty cycle of the light-emitting start signal ESTV, and then the duty cycle of the light-emitting element in the bright state in the display brightness waveform can be adjusted. Ratio, so as to realize the control of the light-emitting brightness of the light-emitting element.
  • the DDIC chip pre-stores a second mapping relationship, and the compensation amount of the lighting start signal corresponding to the target refresh frequency can be determined according to the second mapping relationship.
  • the second mapping relationship pre-stored in the DDIC chip may include: a column of refresh frequencies and a corresponding column of lighting start signal compensation amounts, and there is a one-to-one correspondence between the refresh frequencies and the lighting start signal compensation amounts.
  • Table 2 may record the refresh frequency corresponding to the ESTV compensation amount of 0, and the ESTV compensation amounts corresponding to other refresh frequencies.
  • the ESTV compensation amount in Table 2 may be greater than zero.
  • this embodiment does not limit it.
  • the ESTV compensation amount in Table 2 may be less than zero.
  • a repetition duration of the light emission start signal ESTV is composed of a high level and a low level.
  • the duty cycle of ESTV is the ratio of the duration of the high level to the total duration within a repeated duration.
  • FIG. 7 is a schematic diagram of ESTV compensation according to at least one embodiment of the present disclosure.
  • the low level duration of ESTV in a frame can effectively control the brightness of the display screen of this frame as an example.
  • the original refresh frequency of the display panel is Q1, and the target refresh frequency is Q2.
  • Q1 may be greater than Q2.
  • the high-level duration of ESTV is a; under the target refresh frequency Q2, the high-level duration of ESTV is b+c.
  • c is the ESTV compensation amount determined according to the second mapping relationship.
  • the DDIC chip can The relationship determines the ESTV compensation amount c corresponding to the target refresh rate, and prolongs the high level of the ESTV at a low refresh rate for a duration of c, thereby increasing the brightness of the display screen so that the brightness of the display screen remains consistent.
  • the luminance curve of the dotted line in FIG. 7 shows the luminance curve after ESTV compensation.
  • the DDIC chip can determine the ESTV compensation amount corresponding to the target refresh rate according to the second mapping relationship, and set the high refresh rate
  • the high level of ESTV under the frequency shortens the duration of c, so that the brightness of the display screen remains consistent.
  • this embodiment does not limit it.
  • the duration of the high level of the ESTV in a frame can effectively control the brightness of the display screen of the frame.
  • the DDIC chip of this embodiment can determine the ESTV compensation amount according to the target refresh frequency of the display panel, so as to improve the brightness change during the refresh frequency switching process and realize the dynamic and non-inductive switching of the refresh frequency.
  • the gamma voltage (ie, the aforementioned expected output data voltage) may directly determine the brightness of the display screen.
  • the frequency of the display panel is switched (for example, from the original refresh rate to the target refresh rate)
  • the gamma voltage at different refresh rates can be fine-tuned to keep the brightness at different refresh rates consistent sex.
  • the DDIC chip pre-stores a third mapping relationship, and the gamma voltage compensation amount corresponding to the target refresh frequency can be determined according to the third mapping relationship.
  • the third mapping relationship pre-stored in the DDIC chip may include: a column of refresh frequencies and a corresponding column of gamma voltage compensation amounts, and there is a one-to-one correspondence between the refresh frequencies and the gamma voltage compensation amounts.
  • Table 3 may record the refresh frequency corresponding to a gamma voltage compensation amount of 0, and the gamma voltage compensation amounts corresponding to other refresh frequencies.
  • the gamma voltage compensation amount in Table 3 may be greater than zero.
  • this embodiment does not limit it.
  • the gamma voltage compensation amount in Table 3 may be less than zero.
  • FIG. 8 is a schematic diagram of gamma voltage compensation according to at least one embodiment of the present disclosure.
  • the original refresh frequency of the display panel is Q1
  • the target refresh frequency is Q2.
  • Q1 is greater than Q2.
  • the display panel switches from the original refresh rate Q1 to the target refresh rate Q2 (for example, from a high refresh rate to a low refresh rate)
  • screen flickering caused by a decrease in brightness will occur, and the DDIC chip can determine the target refresh rate according to the third mapping relationship
  • the corresponding gamma voltage compensation amount, and the gamma voltage is reduced by the compensation amount, so that the brightness of the display screen remains consistent.
  • the DDIC chip can determine the gamma voltage compensation amount corresponding to the target refresh rate according to the third mapping relationship, and compensate the gamma voltage, so that the display The brightness of the picture remains consistent.
  • the reduction or increase compensation of the gamma voltage is not limited. In practical applications, it can be set in combination with brightness changes of the display panel and transistor types.
  • the control method provided in this embodiment dynamically adjusts the data chopping rule according to the target refresh frequency of the display panel, which can not only ensure better power consumption gains under normal display, but also ensure improved flickering effect during low-frequency display. Moreover, by performing ESTV compensation and gamma voltage compensation during the switching process of the refresh rate, the brightness change during the switching process can be improved, thereby realizing dynamic and non-inductive switching of the refresh rate.
  • FIG. 9 is a schematic diagram of a control device of a display panel according to at least one embodiment of the present disclosure.
  • the control device in this embodiment may include: a frequency determination module 301 , a rule determination module 302 and a control module 303 .
  • the frequency determination module 301 is configured to determine a target refresh frequency of the display panel.
  • the rule determination module 302 is configured to determine a data chopping rule adapted to the target refresh frequency according to the first mapping relationship.
  • the control module 303 is configured to provide the data signal to the display panel according to the data chopping rule.
  • FIG. 10 is another schematic diagram of a control device of a display panel according to at least one embodiment of the present disclosure.
  • the control device of this embodiment may further include: a first compensation module 304 configured to determine the refresh rate corresponding to the target refresh rate according to the second mapping relationship. Lighting start signal compensation amount; when the display panel is switched to the target refresh frequency, the light emitting start signal compensation amount corresponding to the target refresh frequency is used to compensate the light emitting start signal.
  • control device of this embodiment may further include: a second compensation module 305, and the second compensation module 305 is configured to determine the refresh rate corresponding to the target refresh rate according to the third mapping relationship Gamma voltage compensation amount; when the display panel is switched to the target refresh rate, the data voltage provided to the display panel is compensated by using the gamma voltage compensation amount corresponding to the target refresh rate.
  • control device of the display panel of this embodiment For the relevant description of the control device of the display panel of this embodiment, reference may be made to the description of the foregoing embodiment, so details are not repeated here.
  • FIG. 11 is another schematic diagram of a control device according to at least one embodiment of the present disclosure.
  • the control device of this embodiment may include: a memory 401 and a processor 402 .
  • the memory 401 is configured to store computer programs
  • the processor 402 is configured to execute the computer programs to implement the aforementioned control method.
  • the processor 402 of the control device may include a processing device such as a Microcontroller Unit (MCU, Microcontroller Unit) or a Field-Programmable Gate Array (FPGA, Field-Programmable Gate Array).
  • the memory 401 of the control device can store the grayscale conversion comparison table, the parameter comparison table, and software programs and modules of application software, such as program instructions or modules corresponding to the method in this embodiment.
  • the processor 402 executes various functional applications and data processing by running software programs and modules stored in the memory 401 , such as implementing the method provided in this embodiment.
  • the memory 401 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory may include memory located remotely from the processor, which remote memory may be connected to the control device via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • FIG. 12 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device of this embodiment may include: a display panel 502 and a control device 501 .
  • the control device 501 is configured to provide data signals to the display panel 502 .
  • the display panel 502 may include: a pixel array.
  • the pixel array includes a plurality of sub-pixels, and at least one sub-pixel includes a light emitting element and a pixel circuit for driving the light emitting element to emit light.
  • the pixel circuit includes: multiple transistors and at least one capacitor.
  • At least one embodiment of the present disclosure further provides a non-transitory computer-readable storage medium storing a computer program, and implementing the steps of the above control method when the computer program is executed.
  • computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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Abstract

一种显示面板的控制方法，包括：确定显示面板的目标刷新频率；根据第一映射关系，确定与目标刷新频率适配的数据斩波规则；根据数据斩波规则，向显示面板提供数据信号。

Description

显示面板的控制方法及控制装置、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示面板的控制方法及控制装置、显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Display)显示器件由于具备自发光、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围光、构造及制程较简单等优异特性，被认为是下一代平面显示器的新兴应用技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板的控制方法及控制装置、显示装置。
一方面，本公开实施例提供一种显示面板的控制方法，包括：确定显示面板的目标刷新频率；根据第一映射关系，确定与所述目标刷新频率适配的数据斩波规则；根据所述数据斩波规则，向所述显示面板提供数据信号。
在一些示例性实施方式中，所述数据斩波规则包括以下之一：帧翻转、点翻转。
在一些示例性实施方式中，所述确定显示面板的目标刷新频率，包括以下之一：根据接收到的帧率切换命令，确定所述显示面板的目标刷新频率；通过分析接收到的MIPI数据，确定所述显示面板的目标刷新频率。
在一些示例性实施方式中，本实施例的控制方法还包括：根据第二映射关系，确定与所述目标刷新频率对应的发光起始信号补偿量。
在一些示例性实施方式中，本实施例的控制方法还包括：当所述显示面板切换至所述目标刷新频率，利用与所述目标刷新频率对应的发光起始信号 补偿量，对发光起始信号进行补偿。
在一些示例性实施方式中，本实施例的控制方法还包括：根据第三映射关系，确定与所述目标刷新频率对应的伽马电压补偿量。
在一些示例性实施方式中，本实施例的控制方法还包括：当所述显示面板切换至所述目标刷新频率，利用与所述目标刷新频率对应的伽马电压补偿量，对提供给所述显示面板的数据电压进行补偿。
另一方面，本公开实施例提供一种显示面板的控制装置，包括：频率确定模块，配置为确定显示面板的目标刷新频率；规则确定模块，配置为根据第一映射关系，确定与所述目标刷新频率适配的数据斩波规则；控制模块，配置为根据所述数据斩波规则，向所述显示面板提供数据信号。
在一些示例性实施方式中，本实施例的控制装置还包括：第一补偿模块，配置为根据第二映射关系，确定与所述目标刷新频率对应的发光起始信号补偿量；当所述显示面板切换至所述目标刷新频率，利用与所述目标刷新频率对应的发光起始信号补偿量，对发光起始信号进行补偿。
在一些示例性实施方式中，本实施例的控制装置还包括：第二补偿模块，配置为根据第三映射关系，确定与所述目标刷新频率对应的伽马电压补偿量；当所述显示面板切换至所述目标刷新频率，利用与所述目标刷新频率对应的伽马电压补偿量，对提供给所述显示面板的数据电压进行补偿。
另一方面，本公开实施例提供一种显示装置，包括显示面板及如上所述的控制装置。
在一些示例性实施方式中，所述显示面板包括：像素阵列，所述像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动所述发光元件发光的像素电路；所述像素电路包括：多个晶体管和至少一个电容。
另一方面，本公开实施例提供一种控制装置，包括：存储器和处理器；所述存储器配置为存储计算机程序，所述处理器配置为执行所述计算机程序以实现如上所述的控制方法。
另一方面，本公开实施例提供一种非瞬态计算机可读存储介质，存储有计算机程序，所述计算机程序被执行时实现如上所述的控制方法。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示面板的控制方法的流程图；
图2为本公开至少一实施例的显示装置的示意图；
图3为本公开至少一实施例的像素电路的等效电路图；
图4为本公开至少一实施例的像素电路的工作时序图；
图5A和图5B为本公开至少一实施例的数据斩波功能的原理示意图；
图6A和图6B为本公开至少一实施例的数据斩波规则的示意图；
图7为本公开至少一实施例的ESTV的补偿示意图；
图8为本公开至少一实施例的伽马电压的补偿示意图；
图9为本公开至少一实施例的显示面板的控制装置的示意图；
图10为本公开至少一实施例的显示面板的控制装置的另一示意图；
图11为本公开至少一实施例的控制装置的另一示意图；
图12为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量 误差范围内的数值。
随着低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)技术的应用，可以使得OLED显示面板的画面刷新频率降至1赫兹(Hz)甚至更低。由于人眼可识别的亮度变化频率约为24Hz至30Hz，因此，对于基于LTPO技术的显示面板来说，在进行低频(即低于常规60Hz的刷新频率)显示时，需要整个画面亮度保持恒定，显示过程中不能引入低频的亮度变化。
本公开实施例提供一种显示面板的控制方法及控制装置、显示装置，可以改善显示面板的显示效果。
图1为本公开至少一实施例的显示面板的控制方法的流程图。如图1所示，本公开实施例提供一种显示面板的控制方法，包括：
步骤S11、确定显示面板的目标刷新频率；
步骤S12、根据第一映射关系，确定与目标刷新频率适配的数据斩波规则；
步骤S13、根据数据斩波规则，向显示面板提供数据信号。
在一些示例性实施方式中，本实施例的控制方法可以用于控制OLED显示面板的显示。然而，本实施例对此并不限定。
在一些示例性实施方式中，本实施例的控制方法可以应用于显示驱动电路(DDIC，Display Driver Integrated Circuit)芯片。以采用应用处理器(AP，Application Processor)、DDIC芯片以及显示面板架构的显示装置为例，AP渲染生成图像数据后，将图像数据发送至DDIC芯片，由DDIC芯片控制显示面板根据图像数据进行图像显示。在本示例中，DDIC芯片可以根据数据斩波规则，向显示面板输出的数据信号，从而改善显示面板的显示效果。
在一些示例性实施方式中，数据斩波规则可以包括以下之一：帧翻转、点翻转。然而，本实施例对此并不限定。例如，数据斩波规则还可以包括：行翻转、列翻转等。
在一些示例性实施方式中，本实施例的控制方法还可以包括：根据第二映射关系，确定与目标刷新频率对应的发光起始信号补偿量。
在一些示例性实施方式中，本实施例的控制方法还可以包括：当显示面 板切换至目标刷新频率，利用与目标刷新频率对应的发光起始信号补偿量，对发光起始信号进行补偿。本示例性实施方式中，通过在目标刷新频率的切换过程中，对发光起始信号进行补偿，可以消除刷新频率切换过程中带来的亮度变化，实现刷新频率的动态无感切换。
在一些示例性实施方式中，本实施例的控制方法还可以包括：根据第三映射关系，确定与目标刷新频率对应的伽马电压补偿量。
在一些示例性实施方式中，本实施例的控制方法还可以包括：当显示面板切换至目标刷新频率，利用与目标刷新频率对应的伽马电压补偿量，对提供给显示面板的数据电压进行补偿。本示例性实施方式中，通过在目标刷新频率的切换过程中，对伽马电压进行补偿，可以消除刷新频率切换过程中带来的亮度变化，实现刷新频率的动态无感切换。
下面通过多个示例对本实施例的方案进行举例说明。
图2为本公开至少一实施例的显示装置的示意图。在一些示例性实施方式中，如图2所示，本示例性实施例的显示装置可以包括：显示面板以及控制装置。控制装置可以包括DDIC芯片10。显示面板可以包括：像素阵列13、沿第一方向延伸的多条第一信号线(例如，扫描线GL1至GLm、发光控制线EML1至EMLo)以及沿第二方向延伸的多条第二信号线(例如，数据线DL1至DLn)。第一方向(例如水平方向)与第二方向(例如竖直方向)交叉，例如第一方向与第二方向可以相互垂直。其中，m、n和o均为整数。显示面板上还设置有栅驱动电路(例如包括第一栅驱动电路11和第二栅驱动电路12)。DDIC芯片10和栅驱动电路可以配置为驱动像素阵列13。
在一些示例性实施方式中，DDIC芯片10可以将适于第一栅驱动电路11的规格的时钟信号、起始信号等提供到第一栅驱动电路11，以及将适于第二栅驱动电路12的规格的时钟信号、起始信号等提供到第二栅驱动电路12。第一栅驱动电路11可以利用从DDIC芯片10接收的时钟信号、起始信号等来产生提供到扫描线GL1至GLm的扫描信号。第二栅驱动电路12可以利用从DDIC芯片10接收的时钟信号、发光起始信号等来产生提供到发光控制线EML1至EMLm的发光控制信号。DDIC芯片10还可以适于产生提供到数据线DL1至DLn的数据信号。
在一些示例性实施方式中，第一栅驱动电路11可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线GL1至GLm。例如，第一栅驱动电路11可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的起始信号传输到下一级电路的方式产生扫描信号。第二栅驱动电路12可以将具有截止电平脉冲的发光控制信号顺序地提供到发光控制线EML1至EMLo。例如，第二栅驱动电路12可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光起始信号传输到下一级电路的方式产生发光控制信号。然而，本实施例对此并不限定。
在一些示例性实施方式中，像素阵列13可以包括多个子像素PX。一个像素单元可以包括三个子像素。三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例性实施方式中，至少一个子像素PX包括：发光元件以及驱动发光元件发光的像素电路。发光元件与对应的像素电路电连接。发光元件可以为OLED器件，包括阳极、阴极以及位于阳极和阴极之间的有机发光层。在一些示例中，像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以为5T1C、5T2C、6T1C、7T1C、8T1C或8T2C等结构。然而，本实施例对此并不限定。
图3为本公开至少一实施例的像素电路的等效电路图。图4为本公开至少一实施例的像素电路的工作时序图。本示例性实施例的像素电路为7T1C结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图3所示，本示例的像素电路包括六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。 六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL包括阳极、阴极和设置在阳极和阴极之间的有机发光层。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图3所示，显示基板包括扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL配置为向像素电路提供扫描信号SCAN，数据线DL配置为向像素电路提供数据信号DATA，发光控制线EML配置为向像素电路提供发光控制信号EM，第一复位控制线RST1配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2配置为向像素电路提供第二复位控制信号RESET2。在一些示例中，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(n-1)，即第一 复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。第二复位控制线RST2可以与第n行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(n)，即第二复位控制信号RESET2(n)与扫描信号SCAN(n)相同。在一些示例中，第n行像素电路所电连接的第二复位控制线RST2与第n+1行像素电路所电连接的第一复位控制线RST1为一体结构。如此，可以减少显示基板的信号线，实现显示基板的窄边框。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一初始信号线INIT1配置为向像素电路提供第一初始信号，第二初始信号线INIT2配置为向像素电路提供第二初始信号。例如，第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此。
在一些示例性实施方式中，如图3所示，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。阈值补偿晶体管T2的栅极与扫描线GL电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接。第一发光控制晶体管T5的栅极与发光控制线EML电连接，第一发光控制晶体管T5的第一极与第一电源线PL1电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。第二发光控制晶体管T6的栅极与发光控制线EML电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的阳极电连接。第一复位晶体管T1与驱动晶体管T3的栅极电连接，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与第一初始信号线INIT1电连接，第一复位晶体管T1的第二极与驱动晶体管T3的栅极电连接。第二复位晶体管T7的栅极与第二复 位控制线RST2电连接，第二复位晶体管T7的第一极与第二初始信号线INIT2电连接，第二复位晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一电极与驱动晶体管T3的栅极电连接，存储电容Cst的第二电极与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图4对图3示意的像素电路的工作过程进行说明。以图3所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图4所示，在一帧显示时间段，第一结构的像素电路的工作过程包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第二电极为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DL输出的数据电压Vdata 经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段S3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2。
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
在一些示例性实施方式中，DDIC芯片可以至少包括：伽马电压产生电路。伽马电压产生电路可以利用高电压和低电压，产生多个伽马基准电压，并根据多个伽马基准电压生成多个伽马电压。伽马电压产生电路可以通过多个数据输出通道给显示面板提供数据电压，以提高数据电压的驱动能力。
针对OLED显示基板的DDIC芯片中用于数据电压输出的运算放大器(OP，Operational Amplifier)差异带来的显示问题，在DDIC芯片中引入了数据斩波功能。图5A和图5B为本公开至少一实施例的数据斩波功能的原理示意图。在一些示例中，如图5A和图5B所示，数据输出通道可以包括运算放大器(例如运算放大器601和602)，运算放大器的同相输入端可以接收伽马电压产生电路产生的伽马电压，运算放大器的反相输入端与运算放大器的输出端电连接。由于DDIC芯片制程的影响，运算放大器会存在差异，使得数据输出通道会产生偏移电压(offset)。如图5A所示，运算放大器601会产生正极性的偏移电压ΔV，以第一输入端IN1输入伽马电压Vgma为例，第一输出端OUT1输出的数据电压Vout1＝Vgma+ΔV。如图5B所示，运算放大器602会产生负极性的偏移电压ΔV，以第二输入端IN2输入伽马电压Vgma为例，第二输出端OUT2输出的数据电压Vout2＝Vgma-ΔV。
在一些示例中，DDIC芯片的数据输出通道受到运算放大器的差异影响，其输出的数据电压会带有不同的偏移电压。例如，多个数据输出通道的预期输出的数据电压(即伽马电压)分别为Vgma1、Vgma2、Vgma3、……，然而由于运算放大器带来的偏移电压的影响，多个数据电压输出通道实际输出的数据电压会变为Vgma1+ΔV1、Vgma2+ΔV2、Vgma3+ΔV3、……。在OLED显示面板显示纯色画面时，由于不同数据输出通道输出的偏移电压不同，会引起竖条显示问题。为了改善显示效果，引入数据斩波功能，即将不同数据输出通道输出的数据电压在时域进行均匀化处理。按照一定的规则，使不同数据输出通道在不同的时间点分别输出Vgma+ΔV或者Vgma-ΔV，即输出不同极性的偏移电压。如此一来，从时域上来看，数据输出通道的输出数据电压可以平均为Vgma。
在一些示例性实施方式中，为了控制数据输出通道由于运算放大器差异带来的不同的偏移电压，数据输出通道可以包括：运算放大电路和斩波控制 电路。运算放大电路可以包括第一运算放大器(例如图5A中的运算放大器601)和第二运算放大器(例如图5B中的运算放大器602)。运算放大电路的输入端可以与第一运算放大器的同相输入端和第二运算放大器的同相输入端电连接，第一运算放大器的反相输入端与第一运算放大器的输出端电连接，第二运算放大器的反相输入端与第二运算放大器的输出端电连接。斩波控制电路可以与第一运算放大器的输出端和第二运算放大器的输出端电连接，配置为控制第一运算放大器的输出端输出数据电压，或者控制第二运算放大器的输出端输出数据电压。然而，本实施例对此并不限定。
在一些示例性实施方式中，可以按照数据斩波规则对显示面板进行显示控制，以改善显示面板的显示效果。例如，数据斩波规则可以包括以下至少之一：帧翻转、点翻转。在本示例中，数据斩波规则指DDIC芯片实现数据斩波功能的规则。DDIC芯片可以根据数据斩波规则，控制数据电压带有的偏移电压的极性。
图6A和图6B为本公开至少一实施例的数据斩波规则的示意图。图6A所示为帧翻转规则的示意图，图6B所示为点翻转规则的示意图。帧翻转指的是数据信号在相连两帧之间做偏移电压的极性变换，点翻转指的是数据信号在每帧的相邻两点之间做偏移电压的极性变换，且相邻两帧之间也存在偏移电压的极性变换。在图6A和图6B中，“+”表示产生正极性的偏移电压，例如图5A所示，运算放大器的输出端输出的数据电压Vout1＝Vgma+ΔV，其中，ΔV表示偏移电压。在图6A和图6B中，“-”表示产生负极性的偏移电压，例如图5B所示，运算放大器的输出端输出的数据电压Vout2＝Vgma-ΔV，其中，ΔV表示偏移电压。
如图6A所示，左侧图所示为当前第i帧下的偏移电压极性，中间图所示为第i+1帧的偏移电压极性，右侧图所示为第i+2帧的偏移电压极性。当前第i帧的子像素所对应的偏移电压极性都是相同的，例如均为正极性，第i+1帧的子像素所对应的偏移电压极性都与前一帧相反，例如均为负极性，第i+2帧的子像素所对应的偏移电压极性都与前一帧相反，例如均为正极性。如图6B所示，当前第i帧每个子像素所对应的偏移电压极性，都与其上下左右相邻的子像素所对应的偏移电压极性相反，例如第i帧某一子像素所对应的偏 移电压极性为正极性，则该子像素的上下左右四个相邻子像素所对应的偏移电压极性均为负极性。同理，第i+1帧和第i+2帧的子像素所对应的偏移电压极性与第i帧子像素所对应的偏移电压极性具有相似规律。而且，后一帧的子像素所对应的偏移电压极性与前一帧相反。然而，本实施例对此并不限定。在另一些示例中，数据斩波规则还可以包括：行翻转、列翻转等。例如，当前帧同一列的子像素所对应的偏移电压极性是相同的，且左右相邻的列上的子像素所对应的偏移电压极性相反，称为列翻转。当前帧同一行的子像素所对应的偏移电压极性相同，且上下相邻的行上的子像素所对应的偏移电压极性相反，称为行翻转。当前帧上同两行的子像素所对应的偏移电压极性相同，且上下相邻的两行上的子像素所对应的偏移电压极性相反，此时为2行翻转。
在一些示例性实施方式中，DDIC芯片接收到AP发出的帧率切换命令后，DDIC芯片可以确定显示面板待切换至的目标刷新频率。其中，帧率切换命令可以携带显示面板待切换至的目标刷新频率。或者，AP可以发出移动产业处理接口(MIPI，Mobile Industry Processor Interface)数据，DDIC芯片接收并解析MIPI数据之后，可以确定显示面板待切换至的目标刷新频率。然而，本实施例对此并不限定。
在一些示例性实施方式中，DDIC芯片预存有第一映射关系，根据第一映射关系可以确定与目标刷新频率适配的数据斩波规则。如表1所示，DDIC芯片预存的第一映射关系可以包括：一列刷新频率和对应的一列数据斩波规则，且刷新频率和数据斩波规则之间存在一一对应关系。
表1第一映射关系
刷新频率1 数据斩波规则1
刷新频率2 数据斩波规则2
…… ……
刷新频率n 数据斩波规则n
在一些示例性实施方式中，表1中的刷新频率的范围可以约为0Hz至120Hz。例如，刷新频率1为60Hz，对应的数据斩波规则1可以为点翻转； 刷新频率2为70Hz，对应的数据斩波规则2可以为帧翻转。然而，本实施例对此并不限定。
在一些示例性实施方式中，本实施例的DDIC芯片可以根据显示面板的目标刷新频率来自动切换数据斩波规则。例如，在显示面板的目标刷新频率为常规刷新频率，则可以确定数据斩波规则为帧翻转，从而节省功耗；在显示面板的目标刷新频率为低频刷新频率，则可以确定数据斩波规则为点翻转，从而改善低频显示下的闪烁效果，进而改善显示效果。本示例中，数据斩波规则可以根据显示面板的目标刷新频率而动态变化，从而保证显示效果。
在一些示例性实施方式中，当显示面板进行频率切换时(例如，从原始刷新频率切换至目标刷新频率)，由于DDIC芯片的负载、驱动晶体管状态等差异，在不同的刷新频率间切换瞬间会出现亮度变化的情况，从而引起人眼观察到的闪烁问题。在刷新频率切换瞬间，通过引入发光起始信号(ESTV)补偿机制，可以有效避免闪烁问题。在一些示例中，第二栅驱动电路可以包括多个级联的发光控制电路，发光控制电路一般均是通过时钟信号、高电平信号和低电平信号等控制电路中的多个晶体管的导通和截止，从而实现将输入的发光起始信号(ESTV)转换为输出的发光控制信号EM。发光控制电路输出的发光控制信号EM可以通过发光控制线提供给像素电路，用于控制发光元件发光。即发光控制信号EM的占空比能够决定发光元件的显示亮度波形中，处于亮态的占空比，因此，当发光元件的发光亮度不在预定亮度范围内时，可通过调节发光控制信号EM的占空比，调节发光元件的显示亮度波形中处于亮态的占空比，从而实现控制发光元件的发光亮度。在一般的发光控制电路中，都是从输入端输入发光起始信号ESTV，在输出端输出发光控制信号EM，发光控制电路可以根据发光起始信号ESTV产生发光控制信号EM，因此，发光起始信号ESTV的占空比决定了发光控制信号EM的占空比。当发光元件的显示亮度不在预定亮度范围时，可以通过调节发光起始信号ESTV的占空比，调节发光控制信号EM的占空比，进而调节发光元件的显示亮度波形中处于亮态的占空比，从而实现控制发光元件的发光亮度。
在一些示例性实施方式中，DDIC芯片预存有第二映射关系，根据第二映射关系可以确定与目标刷新频率对应的发光起始信号的补偿量。如表2所 示，DDIC芯片预存的第二映射关系可以包括：一列刷新频率和对应的一列发光起始信号补偿量，且刷新频率和发光起始信号补偿量之间存在一一对应关系。
表2第二映射关系
刷新频率1 ESTV补偿量1
刷新频率2 ESTV补偿量2
…… ……
刷新频率n ESTV补偿量n
在一些示例性实施方式中，表2中可以记录ESTV补偿量为0对应的刷新频率，以及其余刷新频率下对应的ESTV补偿量。例如，表2中的ESTV补偿量可以大于0。然而，本实施例对此并不限定。例如，表2中的ESTV补偿量可以小于0。
在一些示例性实施方式中，发光起始信号ESTV的一个重复时长由一个高电平和一个低电平组成。ESTV的占空比为一个重复时长内高电平的持续时长与总时长的比值。
图7为本公开至少一实施例的ESTV补偿示意图。在本示例中，以ESTV在一帧内的低电平时长可以有效控制此帧的显示画面亮度为例进行说明。其中，ESTV的低电平时长越长，显示画面亮度越大。
在一些示例性实施方式中，如图7所示，显示面板的原始刷新频率为Q1，目标刷新频率为Q2。其中，Q1可以大于Q2。在原始刷新频率Q1下，ESTV的高电平时长为a；在目标刷新频率Q2下，ESTV的高电平时长为b+c。其中，c为根据第二映射关系确定的ESTV补偿量。在本示例中，当显示面板从原始刷新频率Q1切换至目标刷新频率Q2(例如，从高刷新频率切换至低刷新频率)时，会发生亮度下降引起的画面闪烁，DDIC芯片可以根据第二映射关系确定目标刷新频率对应的ESTV补偿量c，并将低刷新频率下的ESTV的高电平延长c时长，从而提升显示画面亮度，使得显示画面的亮度保持一致。图7中的虚线的亮度曲线所示为通过ESTV补偿之后的亮度曲线。
在另一些示例中，当显示面板从低刷新频率切换至高刷新频率时，会发 生亮度上升引起的画面闪烁，DDIC芯片可以根据第二映射关系确定目标刷新频率对应的ESTV补偿量，并将高刷新频率下的ESTV的高电平缩短c时长，从而使得显示画面的亮度保持一致。然而，本实施例对此并不限定。在另一些示例中，ESTV在一帧内的高电平时长可以有效控制此帧的显示画面亮度。
本示例性实施方式中，本实施例的DDIC芯片可以根据显示面板的目标刷新频率确定ESTV补偿量，从而改善刷新频率切换过程中的亮度变化，实现刷新频率的动态无感切换。
在一些示例性实施方式中，伽马电压(即，前述的预期输出的数据电压)可以直接决定显示画面亮度。当显示面板进行频率切换时(例如，从原始刷新频率切换至目标刷新频率)，由于显示亮度发生变化，可以通过对不同刷新频率下的伽马电压进行微调，从而保持不同刷新频率下的亮度一致性。
在一些示例性实施方式中，DDIC芯片预存有第三映射关系，根据第三映射关系可以确定与目标刷新频率对应的伽马电压补偿量。如表3所示，DDIC芯片预存的第三映射关系可以包括：一列刷新频率和对应的一列伽马电压补偿量，且刷新频率和伽马电压补偿量之间存在一一对应关系。
表3第三映射关系
刷新频率1 伽马电压补偿量1
刷新频率2 伽马电压补偿量2
…… ……
刷新频率n 伽马电压补偿量n
在一些示例性实施方式中，表3中可以记录伽马电压补偿量为0对应的刷新频率，以及其余刷新频率下对应的伽马电压补偿量。例如，表3中的伽马电压补偿量可以大于0。然而，本实施例对此并不限定。例如，表3中的伽马电压补偿量可以小于0。
图8为本公开至少一实施例的伽马电压补偿的示意图。在一些示例性实施方式中，如图8所示，显示面板的原始刷新频率为Q1，目标刷新频率为Q2。其中，Q1大于Q2。当显示面板从原始刷新频率Q1切换至目标刷新频 率Q2(例如，从高刷新频率切换至低刷新频率)时，会发生亮度下降引起的画面闪烁，DDIC芯片可以根据第三映射关系确定目标刷新频率对应的伽马电压补偿量，并使伽马电压下降该补偿量，从而使得显示画面的亮度保持一致。图8中的虚线的亮度曲线所示为通过伽马电压补偿之后的亮度曲线。然而，本实施例对此并不限定。在另一些示例中，当显示面板从低刷新频率切换至高刷新频率时，DDIC芯片可以根据第三映射关系确定目标刷新频率对应的伽马电压补偿量，并对伽马电压进行补偿，从而使得显示画面的亮度保持一致。本实施例对于伽马电压进行降低或升高的补偿并不限定，在实际应用中，可以结合显示面板的亮度变化和晶体管类型进行设置。
本实施例提供的控制方法，根据显示面板的目标刷新频率来动态调整数据斩波规则，既可以保证常规显示下获得更好的功耗收益，还可以保证低频显示时改善闪烁效果。而且，通过对刷新频率切换过程中进行ESTV补偿和伽马电压补偿，可以改善切换过程中的亮度变化，从而实现刷新频率的动态无感切换。
图9为本公开至少一实施例的显示面板的控制装置的示意图。在一些示例性实施方式中，如图9所示，本实施例的控制装置可以包括：频率确定模块301、规则确定模块302和控制模块303。频率确定模块301，配置为确定显示面板的目标刷新频率。规则确定模块302，配置为根据第一映射关系，确定与目标刷新频率适配的数据斩波规则。控制模块303，配置为根据数据斩波规则，向显示面板提供数据信号。
图10为本公开至少一实施例的显示面板的控制装置的另一示意图。在一些示例性实施方式中，如图10所示，本实施例的控制装置还可以包括：第一补偿模块304，第一补偿模块304配置为根据第二映射关系，确定与目标刷新频率对应的发光起始信号补偿量；当显示面板切换至目标刷新频率，利用与目标刷新频率对应的发光起始信号补偿量，对发光起始信号进行补偿。
在一些示例性实施方式中，如图10所示，本实施例的控制装置还可以包括：第二补偿模块305，第二补偿模块305配置为根据第三映射关系，确定与目标刷新频率对应的伽马电压补偿量；当显示面板切换至目标刷新频率，利用与目标刷新频率对应的伽马电压补偿量，对提供给显示面板的数据电压 进行补偿。
关于本实施例的显示面板的控制装置的相关说明可以参照前述实施例的说明，故于此不再赘述。
图11为本公开至少一实施例的控制装置的另一示意图。在一些示例性实施方式中，如图11所示，本实施例的控制装置可以包括：存储器401和处理器402。存储器401配置为存储计算机程序，处理器402配置为执行计算机程序以实现前述所示的控制方法。
在一些示例性实施方式中，控制装置的处理器402可以包括微控制单元(MCU，Microcontroller Unit)或现场可编程门阵列(FPGA，Field-Programmable Gate Array)等的处理装置。控制装置的存储器401可以存储灰阶转换对照表、参数对照表以及应用软件的软件程序以及模块，如本实施例中的方法对应的程序指令或模块。处理器402通过运行存储在存储器401内的软件程序以及模块，从而执行多种功能应用以及数据处理，比如实现本实施例提供的方法。存储器401可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些示例中，存储器可包括相对于处理器远程设置的存储器，这些远程存储器可以通过网络连接至控制装置。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
图12为本公开至少一实施例的显示装置的示意图。在一些示例性实施方式中，如图12所示，本实施例的显示装置可以包括：显示面板502以及控制装置501。控制装置501配置为向显示面板502提供数据信号。
在一些示例性实施方式中，显示面板502可以包括：像素阵列。像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动发光元件发光的像素电路。像素电路包括：多个晶体管和至少一个电容。关于本实施例的显示装置的相关说明可以参照前述实施例的描述，故于此不再赘述。
此外，本公开至少一实施例还提供一种非瞬态计算机可读存储介质，存储有计算机程序，该计算机程序被执行时实现上述控制方法的步骤。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、 系统、装置中的功能模块或单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块或单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
以上显示和描述了本公开的基本原理、主要特征和本公开的优点。本公开不受上述实施例的限制，上述实施例和说明书中描述的只是说明本公开的原理，在不脱离本公开精神和范围的前提下，本公开还会有多种变化和改进，这些变化和改进都落入要求保护的本公开的范围内。

Claims (14)

  1. 一种显示面板的控制方法，包括：
    确定显示面板的目标刷新频率；
    根据第一映射关系，确定与所述目标刷新频率适配的数据斩波规则；
    根据所述数据斩波规则，向所述显示面板提供数据信号。
  2. 根据权利要求1所述的方法，其中，所述数据斩波规则包括以下之一：帧翻转、点翻转。
  3. 根据权利要求1或2所述的方法，其中，所述确定显示面板的目标刷新频率，包括以下之一：
    根据接收到的帧率切换命令，确定所述显示面板的目标刷新频率；
    通过分析接收到的MIPI数据，确定所述显示面板的目标刷新频率。
  4. 根据权利要求1至3中任一项所述的方法，还包括：根据第二映射关系，确定与所述目标刷新频率对应的发光起始信号补偿量。
  5. 根据权利要求4所述的方法，还包括：当所述显示面板切换至所述目标刷新频率，利用与所述目标刷新频率对应的发光起始信号补偿量，对发光起始信号进行补偿。
  6. 根据权利要求1至5中任一项所述的方法，还包括：根据第三映射关系，确定与所述目标刷新频率对应的伽马电压补偿量。
  7. 根据权利要求6所述的方法，还包括：当所述显示面板切换至所述目标刷新频率，利用与所述目标刷新频率对应的伽马电压补偿量，对提供给所述显示面板的数据电压进行补偿。
  8. 一种显示面板的控制装置，包括：
    频率确定模块，配置为确定显示面板的目标刷新频率；
    规则确定模块，配置为根据第一映射关系，确定与所述目标刷新频率适配的数据斩波规则；
    控制模块，配置为根据所述数据斩波规则，向所述显示面板提供数据信号。
  9. 根据权利要求8所述的控制装置，还包括：第一补偿模块，配置为根据第二映射关系，确定与所述目标刷新频率对应的发光起始信号补偿量；当所述显示面板切换至所述目标刷新频率，利用与所述目标刷新频率对应的发光起始信号补偿量，对发光起始信号进行补偿。
  10. 根据权利要求8或9所述的控制装置，还包括：第二补偿模块，配置为根据第三映射关系，确定与所述目标刷新频率对应的伽马电压补偿量；当所述显示面板切换至所述目标刷新频率，利用与所述目标刷新频率对应的伽马电压补偿量，对提供给所述显示面板的数据电压进行补偿。
  11. 一种显示装置，包括显示面板以及如权利要求8至10中任一项所述的控制装置。
  12. 根据权利要求11所述的显示装置，其中，所述显示面板包括：像素阵列，所述像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动所述发光元件发光的像素电路；所述像素电路包括：多个晶体管和至少一个电容。
  13. 一种控制装置，包括：存储器和处理器；所述存储器配置为存储计算机程序，所述处理器配置为执行所述计算机程序以实现如权利要求1至7中任一项所述的控制方法。
  14. 一种非瞬态计算机可读存储介质，存储有计算机程序，所述计算机程序被执行时实现如权利要求1至7中任一项所述的控制方法。
PCT/CN2022/070150 2022-01-04 2022-01-04 显示面板的控制方法及控制装置、显示装置 WO2023130222A1 (zh)

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CN113793569A (zh) * 2021-10-27 2021-12-14 京东方科技集团股份有限公司 显示面板的控制方法、装置、设备和存储介质

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US20150116373A1 (en) * 2013-10-25 2015-04-30 Samsung Display Co., Ltd. Liquid crystal display and method for driving the same
CN107039010A (zh) * 2017-05-09 2017-08-11 深圳市华星光电技术有限公司 伽马曲线自动修复系统及伽马曲线自动修复方法
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