WO2023092405A1 - 显示面板的控制方法及控制装置、显示装置 - Google Patents

显示面板的控制方法及控制装置、显示装置 Download PDF

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Publication number
WO2023092405A1
WO2023092405A1 PCT/CN2021/133244 CN2021133244W WO2023092405A1 WO 2023092405 A1 WO2023092405 A1 WO 2023092405A1 CN 2021133244 W CN2021133244 W CN 2021133244W WO 2023092405 A1 WO2023092405 A1 WO 2023092405A1
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Prior art keywords
voltage
display
display screen
data
signal
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PCT/CN2021/133244
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English (en)
French (fr)
Inventor
吴宝云
韩新斌
赵西玉
赵辉
王开民
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京东方科技集团股份有限公司
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Priority to CN202180003586.5A priority Critical patent/CN116508092A/zh
Priority to GB2319965.6A priority patent/GB2623660A/en
Priority to PCT/CN2021/133244 priority patent/WO2023092405A1/zh
Publication of WO2023092405A1 publication Critical patent/WO2023092405A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data

Definitions

  • This article relates to but is not limited to the field of display technology, especially a method for controlling a display panel, a control device, and a display device.
  • Organic Light Emitting Diode (OLED, Organic Light Emitting Display) display device has the advantages of self-illumination, high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, light in the use temperature range, simple structure and manufacturing process, etc. characteristics and is considered to be an emerging application technology for next-generation flat-panel displays.
  • Embodiments of the present disclosure provide a control method, a control device, and a display device of a display panel.
  • an embodiment of the present disclosure provides a method for controlling a display panel, including: converting the grayscale data of the display screen into a grayscale voltage at a first refresh rate; The average gray scale voltage of the screen; according to the average gray scale voltage of the displayed screen, determine the display parameters matched by the displayed screen; output the control signal of the displayed screen to the display panel according to the displayed parameters matched by the displayed screen.
  • the control signal includes at least one of the following: a data hold signal, and an anode reset signal of a light emitting element of the display panel.
  • the display phase of the display screen includes: a refresh phase and a hold phase.
  • the display parameters include at least one of the following: a data holding voltage in the holding phase; a first anode reset voltage in the refresh phase and a second anode reset voltage in the holding phase.
  • the converting the grayscale data of the display screen into grayscale voltages includes: for the grayscale data of each display unit of the display screen, look up in the stored grayscale conversion comparison table a grayscale voltage corresponding to the grayscale data.
  • the converting the grayscale data of the display screen into grayscale voltages further includes: not finding the grayscale corresponding to the grayscale data of the display unit in the grayscale conversion comparison table voltage, the gray-scale voltage corresponding to the gray-scale data is calculated by using a preset gray-scale mapping function.
  • the calculating the average gray-scale voltage of the display screen according to the gray-scale voltage of the display screen includes: calculating the average value of the gray-scale voltage of each display row of the display screen , and then use the average value of the gray-scale voltages of all display lines to calculate the average gray-scale voltage of the display screen.
  • the determining the display parameters that match the display screen according to the average gray scale voltage of the display screen includes: searching for the average gray scale of the display screen from a stored parameter comparison table Display parameters for voltage matching.
  • the parameter comparison table records at least one of the following: the mapping relationship between the average gray scale voltage and the data retention voltage, and the mapping relationship between the average gray scale voltage and the first anode reset voltage and the second anode reset voltage.
  • the average gray-scale voltage in the parameter comparison table is proportional to the data retention voltage; the average gray-scale voltage in the parameter comparison table is related to the first anode reset voltage and the second anode reset voltage
  • the absolute value of the differential pressure is inversely proportional.
  • the outputting the control signal of the display screen to the display panel according to the display parameters matched by the display screen includes at least one of the following:
  • the panel outputs the data hold signal, and the data hold signal maintains the data hold voltage; outputs an anode reset signal to the display panel, and the anode reset signal maintains the first anode reset signal in the refresh phase voltage, maintained at the second anode reset voltage during the hold phase.
  • the first refresh frequency is less than 60 Hz.
  • an embodiment of the present disclosure provides a control device for a display panel, including: a grayscale conversion module, a voltage calculation module, a parameter conversion module, and a signal output module.
  • the grayscale conversion module is configured to convert the grayscale data of the display screen into grayscale voltages at the first refresh rate.
  • the voltage calculation module is configured to calculate the average gray-scale voltage of the display screen according to the gray-scale voltage of the display screen.
  • the parameter conversion module is configured to determine the matching display parameters of the display screen according to the average gray scale voltage of the display screen.
  • the signal output module is configured to output a control signal of the display screen to the display panel according to the display parameters matched by the display screen.
  • the control signal includes at least one of the following: a data hold signal, and an anode reset signal of a light emitting element of the display panel.
  • the display phase of the display screen includes: a refresh phase and a hold phase.
  • the display parameters include at least one of the following: a data holding voltage in the holding phase; a first anode reset voltage in the refresh phase and a second anode reset voltage in the holding phase.
  • the parameter conversion module includes: a first parameter conversion module, a second parameter conversion module and a third parameter conversion module.
  • the first parameter conversion module is configured to determine a first anode reset voltage matching the display screen according to the average gray scale voltage of the display screen.
  • the second parameter conversion module is configured to determine a second anode reset voltage matching the display screen according to the average gray scale voltage of the display screen.
  • the third parameter conversion module is configured to determine the matching data holding voltage of the display screen according to the average gray scale voltage of the display screen.
  • the signal output module includes: a first output module and a second output module.
  • the first output module is configured to output an anode reset signal of the display screen to the display panel according to the display parameters matched by the display screen.
  • the second output module is configured to output a data hold signal of the display screen to the display panel according to the display parameters matched by the display screen.
  • an embodiment of the present disclosure provides a display device, including: a display panel and the above-mentioned control device, where the control device is configured to provide a control signal to the display panel.
  • the display panel includes: a pixel array, the pixel array includes a plurality of sub-pixels, at least one sub-pixel includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light; the pixel circuit includes: a plurality of transistors and at least one capacitor.
  • an embodiment of the present disclosure provides a control device, including: a memory and a processor; the memory is configured to store a computer program, and the processor is configured to execute the computer program to implement the above control method.
  • an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing a computer program, and implementing the above-mentioned control method when the computer program is executed.
  • FIG. 1 is a flowchart of a control method of a display panel in at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a display device according to at least one embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a working timing diagram of the pixel circuit provided in FIG. 3;
  • FIG. 5 is a schematic diagram of a frame skip driving method in at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic waveform diagram of a control signal in at least one embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a control device of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 8 is another schematic diagram of a control device of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 9 is another schematic diagram of a control device according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • the screen refresh rate of the OLED display panel can be reduced to 1 Hertz (Hz) or even lower. Since the brightness change frequency recognizable by the human eye is about 24Hz to 30Hz, for a display panel based on LTPO technology, when performing low-frequency (that is, lower than the conventional 60Hz refresh rate) display, the brightness of the entire screen needs to be kept constant. Low-frequency brightness changes cannot be introduced during the display process.
  • LTPO Low Temperature Polycrystalline Oxide
  • Embodiments of the present disclosure provide a control method, a control device, and a display device for a display panel, which can improve the display effect of the display panel.
  • FIG. 1 is a flowchart of a method for controlling a display panel according to at least one embodiment of the present disclosure. As shown in FIG. 1 , an embodiment of the present disclosure provides a method for controlling a display panel, including:
  • Step S11 converting the grayscale data of the display screen into grayscale voltages at the first refresh rate
  • Step S12 calculating the average gray-scale voltage of the display screen according to the gray-scale voltage of the display screen;
  • Step S13 according to the average gray-scale voltage of the display screen, determine the display parameters to match the display screen;
  • Step S14 outputting a control signal of the display screen to the display panel according to the display parameters matched by the display screen.
  • the control method of this embodiment may be applied to a display driver integrated circuit (DDIC, Display Driver Integrated Circuit) chip.
  • DDIC Display Driver Integrated Circuit
  • AP Application Processor
  • DDIC chip controls the display panel to perform image processing based on the image data. show.
  • the DDIC chip can output different control signals to the display panel according to different display images, thereby improving the display effect of the display panel.
  • control signal output to the display panel may include at least one of the following: a data hold signal, and an anode reset signal of a light emitting element of the display panel.
  • a data hold signal may be provided to different display screens according to display parameters, so as to achieve a better display effect.
  • the display phase of the display screen may include: a refresh phase and a hold phase.
  • the display parameters may include at least one of: a data hold voltage in a hold phase; a first anode reset voltage in a refresh phase and a second anode reset voltage in a hold phase.
  • only the data holding voltage matching the display picture can be determined according to the average gray scale voltage of the display picture; or, only the anode reset voltage (including the first anode reset voltage and second anode reset voltage); or, the data holding voltage and anode reset voltage matching the display screen can be determined according to the average gray scale voltage of the display screen. In this example, by selecting a better display parameter or combination, the display effect of the display panel can be improved.
  • step S14 may include at least one of the following: in the hold phase, outputting a data hold signal to the display panel, and the data hold signal maintains the data hold voltage; outputting an anode reset signal to the display panel, and the anode reset signal It is maintained at the first anode reset voltage during the refresh phase, and is maintained at the second anode reset voltage during the hold phase.
  • the data holding signal may be generated according to the data holding voltage
  • the anode reset signal may be generated according to the first anode reset voltage and the second anode reset voltage.
  • the data retention voltage may range from approximately 0.2V to 7.0V.
  • the first anode reset voltage may range from about -0.5V to -6.0V
  • the second anode reset voltage may range from about -0.5V to -6.0V. This embodiment does not limit it.
  • the first refresh frequency may be less than 60 Hz.
  • the control method provided in this example is executed in a low-frequency driving state, so as to improve the low-frequency flickering effect of the display panel.
  • the gray scale data conversion of the display screen and the calculation of the average gray scale voltage may be performed per display unit. That is, the grayscale data of each display unit is converted into a grayscale voltage, and the average grayscale voltage of all display units is calculated.
  • a display unit may be a pixel unit or may be a sub-pixel. However, this embodiment does not limit it.
  • FIG. 2 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device of this exemplary embodiment may include: a display panel and a control device.
  • the control device may include a DDIC chip 10 .
  • the display panel may include: a pixel array 13, a plurality of first signal lines (for example, scanning lines GL1 to GLm, light emission control lines EML1 to EMLo) extending along a first direction, and a plurality of second signal lines extending along a second direction. (eg, data lines DL1 to DLn).
  • the first direction (such as the horizontal direction) intersects with the second direction (such as the vertical direction), for example, the first direction and the second direction may be perpendicular to each other.
  • m, n and o are all integers.
  • the display panel is also provided with a gate driving circuit (eg, including a first gate driving circuit 11 and a second gate driving circuit 12 ).
  • the control device 10 and the gate driving circuit may be configured to drive the pixel array 13 .
  • the DDIC chip 10 may supply a clock signal, a start signal, etc. suitable for the specification of the first gate driving circuit 11 to the first gate driving circuit 11, and may supply a clock signal suitable for the specification of the second gate driving circuit 12.
  • a clock signal, a start signal, etc. of specifications are supplied to the second gate driving circuit 12 .
  • the first gate driving circuit 11 may generate scan signals supplied to the scan lines GL1 to GLm using a clock signal, a start signal, etc. received from the DDIC chip 10 .
  • the second gate driving circuit 12 may generate light emission control signals supplied to the light emission control lines EML1 to EMLm using a clock signal, a start signal, etc. received from the DDIC chip 10 .
  • the DDIC chip 10 may also be adapted to generate data signals provided to the data lines DL1 to DLn.
  • the first gate driving circuit 11 may sequentially supply scan signals having turn-on level pulses to the scan lines GL1 to GLm.
  • the first gate driving circuit 11 may be configured in the form of a shift register, and may sequentially transmit a start signal provided in the form of a conduction level pulse to a next-stage circuit under the control of a clock signal. Generate scan signal.
  • the second gate driving circuit 12 may sequentially supply light emission control signals having off-level pulses to the light emission control lines EML1 to EMLo.
  • the second gate driving circuit 12 may be configured in the form of a shift register, and may be generated in a manner of sequentially transmitting a start signal provided in the form of an off-level pulse to a next-stage circuit under the control of a clock signal. Illuminated control signal. However, this embodiment does not limit it.
  • the pixel array 13 may include a plurality of sub-pixels PX.
  • One pixel unit may include three sub-pixels. The three sub-pixels are red sub-pixel, green sub-pixel and blue sub-pixel respectively. However, this embodiment does not limit it.
  • one pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.
  • the shape of a sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels can be arranged horizontally, vertically or squarely; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely .
  • this embodiment does not limit it.
  • At least one sub-pixel PX includes: a light emitting element and a pixel circuit for driving the light emitting element to emit light.
  • the light emitting element is electrically connected with the corresponding pixel circuit.
  • the light-emitting element may be an OLED device, including an anode, a cathode, and an organic light-emitting layer between the anode and the cathode.
  • a pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may be of a structure such as 5T1C, 5T2C, 6T1C, 7T1C or 8T1C. However, this embodiment does not limit it.
  • FIG. 3 is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit of this exemplary embodiment may have an 8T1C structure, that is, it includes a first transistor T1 to an eighth transistor T8 and a storage capacitor C1 .
  • the first transistor T1 to the seventh transistor T7 of the pixel circuit may be first-type transistors, such as P-type transistors, and the eighth transistor T8 may be second-type transistors, such as N-type transistors.
  • first-type transistors such as P-type transistors
  • the eighth transistor T8 may be second-type transistors, such as N-type transistors.
  • the plurality of transistors of the pixel circuit may all be P-type transistors, or may all be N-type transistors.
  • the first type transistors (for example, the first transistor T1 to the seventh transistor T7 ) of the pixel circuit may use low-temperature polysilicon thin film transistors
  • the second type transistor (for example, the eighth transistor) of the first pixel circuit T8) can use an oxide thin film transistor.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS low Temperature Poly-Silicon
  • oxide semiconductor Oxide
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the plurality of transistors in the pixel circuit may all use low-temperature polysilicon thin film transistors, or all use oxide thin film transistors.
  • the pixel circuit is connected to the first scan line GLa, the second scan line GLb, the data line DL, the first power line PL1, the second power line PL2, the light emission control line EML,
  • the first initial signal line INIT1, the second initial signal line INIT2 and the reset control line RST are electrically connected.
  • the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than The second voltage signal VSS.
  • the first scan line GLa is configured to provide the first scan signal SCAN1 to the pixel circuit
  • the second scan line GLb is configured to provide the second scan signal SCAN2 to the pixel circuit
  • the data line DL is configured to provide the data signal DATA to the pixel circuit
  • the EML is configured to provide an emission control signal EM to the pixel circuit
  • the reset control line RST is configured to provide a reset control signal RESET to the pixel circuit.
  • the first initial signal line INIT1 is configured to provide a first initial signal for resetting the fifth node N5 and the first node N1
  • the second initial signal line INIT2 is configured to provide a signal for resetting the fourth node N4 (that is, the anode of the light emitting element EL). ) of the second initial signal (that is, the anode reset signal).
  • the reset control line RST may be connected to the first scan line GLa of the n-1th row of pixel circuits to be input with the first scan signal SCAN1(n-1) , that is, the reset control signal RESET(n) is the same as the first scan signal SCAN1(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the third transistor T3 The second pole is electrically connected to the third node N3.
  • the control electrode of the fourth transistor T4 is electrically connected to the first scanning line GLa, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.
  • the control electrode of the second transistor T2 is electrically connected to the first scanning line GLa, the first electrode of the second transistor T2 is electrically connected to the fifth node N5, and the second electrode of the second transistor T2 is electrically connected to the third node N3.
  • the control electrode of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2.
  • the control electrode of the sixth transistor T6 is electrically connected to the light emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.
  • the control electrode of the first transistor T1 is electrically connected to the reset control line RST, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5.
  • the control electrode of the seventh transistor T7 is electrically connected to the reset control line RST, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.
  • the control electrode of the eighth transistor T8 is electrically connected to the second scanning line GL2 , the first electrode of the eighth transistor T8 is electrically connected to the fifth node N5 , and the second electrode of the eighth transistor T8 is electrically connected to the first node N1 .
  • a first electrode of the storage capacitor C1 is electrically connected to the first node N1, and a second electrode of the storage capacitor C1 is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor C1, the eighth transistor T8 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3,
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the anode of the light emitting element EL, and the fifth node N5 is a connection point of the first transistor T1, the second transistor T2 and the eighth transistor T8.
  • FIG. 4 is a working timing diagram of the pixel circuit provided in FIG. 3 .
  • the working process of the pixel circuit shown in FIG. 3 will be described below with reference to FIG. 4 .
  • the first transistor T1 to the seventh transistor T7 of the pixel circuit are P-type transistors
  • the eighth transistor T8 is an N-type transistor.
  • the working process of the pixel circuit may include: a first stage S1 , a second stage S2 and a third stage S3 .
  • the first stage S1 is called the reset stage.
  • the reset control signal RESET provided by the reset control line RST is a low-level signal, so that the first transistor T1 and the seventh transistor T7 are turned on, and the second scanning signal SCAN2 provided by the second scanning line GLb is a high-level signal, so that the eighth transistor T7 is turned on.
  • Transistor T8 is turned on.
  • the first initial signal provided by the first initial signal line INIT1 is provided to the fifth node N5 and the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor C1.
  • the first scan signal SCAN1 provided by the first scan line GLa is a high level signal
  • the light emission control signal EM provided by the light emission control line EML is a high level signal
  • the fourth transistor T4, the second transistor T2, the fifth transistor T5, And the sixth transistor T6 is turned off.
  • the seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is supplied to the fourth node N4 to initialize (reset) the anode of the light-emitting element EL, clear its internal pre-stored voltage, and complete the initialization.
  • the light emitting element EL does not emit light.
  • the second stage S2 is called a data writing stage or a threshold compensation stage.
  • the first scan signal SCAN1 provided by the first scan line GLa is a low-level signal
  • the second scan signal SCAN2 provided by the second scan line GLb the reset control signal RESET provided by the reset control line RST
  • the signals EM are all high-level signals
  • the data line DL outputs the data signal DATA.
  • the third transistor T3 is turned on.
  • the first scan signal SCAN1 is a low level signal, which turns on the second transistor T2 and the fourth transistor T4.
  • the second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on, so that the data voltage Vdata output from the data line DL passes through the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second
  • the transistor T2, the fifth node N5 and the turned-on eighth transistor T8 are provided to the first node N1, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor C1, and the storage capacitor
  • the voltage of the first electrode of C1 (that is, the first node N1 ) is Vdata ⁇
  • the reset control signal RESET provided by the reset control line RST is a high level signal, which turns off the first transistor T1 and the seventh transistor T7.
  • the light emission control signal EM provided by the light emission control line EML is a high level signal, which turns off the fifth transistor T5 and the sixth transistor T6.
  • the third stage S3 is called the lighting stage.
  • the light emission control signal EM provided by the light emission control line EML is a low level signal, which turns on the fifth transistor T5 and the sixth transistor T6.
  • the second scan signal SCAN2 provided by the second scan line GLb is a low level signal, which turns off the eighth transistor T8.
  • the first scanning signal SCAN1 provided by the first scanning line GLa and the reset control signal RESET provided by the reset control line RST are high-level signals, so that the second transistor T2, the fourth transistor T4, the seventh transistor T7 and the first transistor T1 are turned off. open.
  • the first voltage signal VDD output from the first power line PLa provides a driving voltage to the anode of the light emitting element EL through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, and drives the light emitting element EL to emit light.
  • the driving current flowing through the third transistor T3 (ie, the driving transistor) is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 ;
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the light-emitting element
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • the threshold voltage of the transistor T3, Vdata is the data voltage output from the data line DL
  • VDD is the first voltage signal output from the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the third transistor T3.
  • FIG. 5 is a schematic diagram of a frame skip driving method according to at least one embodiment of the present disclosure.
  • the display phase of the display screen may include: a refresh phase and a hold phase.
  • Refresh phase includes refresh frame (refresh frame), refresh frame is the frame that needs data refresh.
  • the hold phase includes multiple skip frames, and the hold frame is a frame that does not need to refresh the data and is illuminated by holding the previous picture data.
  • the difference between the refresh frame and the hold frame is that the hold frame maintains the data voltage written in the previous refresh frame without writing new data voltages into the sub-pixels.
  • the driving frequency is relatively low, such as less than 60 Hz. Taking the driving frequency as 1 Hz as an example, 1 refresh frame and 59 hold frames may be included in 1 second. In this way, the effect of reducing power consumption can be achieved.
  • the pixel circuit within one refresh frame, can write the data signal provided by the data line according to the working timing shown in FIG. 4 .
  • the data line provides a data hold signal, and the data hold signal can be maintained at a constant voltage (ie, data hold voltage) to achieve power saving and reduce power consumption.
  • the second initial signal provided by the second initial signal line connected to the pixel circuit is the anode reset signal provided to the light emitting element.
  • the second initial signal line can improve the effect of low-frequency flicker by providing anode reset signals with different voltage values in the refresh phase and the hold phase, so that the display screen maintains a constant brightness.
  • the state of the drive transistor when emitting light is adjusted so that the state of the drive transistor in the refresh frame and the hold frame are basically consistent, and the anode reset signal directly adjusts the state of the light-emitting element.
  • the anode reset signal, the data signal and the data hold signal are generated by a DDIC chip.
  • the DDIC chip can provide the data signal and the data holding signal to the sub-pixel through the data line, and provide the anode reset signal to the sub-pixel through the second initial signal line.
  • the DDIC chip acquires externally input image data, and processes the externally input image data to obtain grayscale data of sub-pixels (or pixel units).
  • a DDIC chip can receive image data from an application processor.
  • the DDIC chip can generate a tearing effect (TE, Tearing Effect) signal, which is used to prevent the tearing problem when the screen is refreshed during the image display process.
  • TE Tearing Effect
  • the DDIC chip will generate TE signal.
  • the AP sends the next frame of image data to the DDIC chip after monitoring the rising edge of the TE signal or detecting that the TE signal is at a high level.
  • the DDIC chip can convert the grayscale of each sub-pixel (or pixel unit) of the display screen to The data is converted to grayscale voltages.
  • the pre-stored grayscale conversion table may include a column of grayscale data and a corresponding column of grayscale voltages, and there is a one-to-one correspondence between the grayscale data and grayscale voltages in the grayscale conversion table.
  • the range of the grayscale data may be 0 to 255, and the range of the grayscale voltage may be approximately 0.2V to 7.0V.
  • the grayscale voltage corresponding to the grayscale data L0 is 7.0V
  • the grayscale voltage corresponding to the grayscale data L8 is 6.0V
  • the grayscale voltage corresponding to the grayscale data L255 is 0.2V.
  • this embodiment does not limit it.
  • the grayscale mapping function may be a linear relationship, or may be an exponential relationship.
  • X represents gray scale data
  • y represents gray scale voltage
  • a and b are constants.
  • this embodiment does not limit it.
  • the gray-scale mapping functions satisfied by the gray-scale data and the gray-scale voltages between any two adjacent gray-scale data in the gray-scale conversion comparison table may be the same, or may be different.
  • the first gray-scale mapping function can be satisfied between the gray-scale data and the gray-scale voltage between the gray-scale data 1 and the gray-scale data 2 in the gray-scale conversion comparison table shown in Table 1, and the gray-scale data 2 and the gray-scale voltage
  • the grayscale data between the grayscale data 3 and the grayscale voltage may satisfy a second grayscale mapping function, and the first grayscale mapping function is different from the second grayscale mapping function.
  • the first grayscale mapping function may be a linear function
  • the second grayscale mapping function may be an exponential function.
  • this embodiment does not limit it.
  • the DDIC chip may look up the grayscale voltage corresponding to the grayscale data in the grayscale conversion table. If the gray-scale voltage corresponding to the gray-scale data is not found in the gray-scale conversion comparison table, the gray-scale data can be converted by interpolation. For example, the gray-scale mapping function corresponding to the gray-scale data to be converted is determined through the gray-scale conversion comparison table, and the corresponding gray-scale voltage is calculated by using the gray-scale mapping function.
  • the DDIC chip after the DDIC chip obtains the grayscale voltage of each sub-pixel of the display image, it can calculate the average grayscale voltage of the display image.
  • the average gray-scale voltage is the ratio of the sum of the gray-scale voltages of all sub-pixels of the display screen to the total number of sub-pixels.
  • the average gray-scale voltage of each row of sub-pixels may be calculated first, and then the average gray-scale voltage of the display screen may be calculated.
  • the average value of the grayscale voltages of each row of sub-pixels can be calculated in the following manner:
  • Vh avg is the average gray-scale voltage of a row of sub-pixels
  • Voltage i is the gray-scale voltage of the i-th sub-pixel in the sub-pixel row
  • W is a weighting factor. W can be set according to requirements, for example, it can be set to 1 by default. However, this embodiment does not limit it.
  • the average grayscale voltage of the displayed picture is calculated by:
  • V avg is the average gray scale voltage of the display screen.
  • this embodiment does not limit the calculation method of the average gray scale voltage of the display screen.
  • the sum of the gray-scale voltages of all sub-pixels can be directly calculated, and then the average gray-scale voltage can be obtained according to the ratio of the sum of the gray-scale voltages to the total number of sub-pixels; or, the average value of the gray-scale voltages of each column of sub-pixels can be calculated first , and then use the average value of the gray-scale voltages of all sub-pixel columns to calculate the average gray-scale voltage of the display screen.
  • the DDIC chip after the DDIC chip calculates the average gray scale voltage of the display screen, it can determine the corresponding data holding voltage, first anode reset voltage and second anode reset voltage according to a pre-stored parameter comparison table.
  • the pre-stored parameter comparison table may include a column of average gray scale voltage Vavg, a column of data holding voltage, a column of first anode reset voltage Vinit2-1 and a column of second anode reset voltage Vinit2-2.
  • the average gray scale voltage and the data retention voltage there is a one-to-one correspondence between the average gray scale voltage and the first anode reset voltage, and there is a one-to-one correspondence between the average gray scale voltage and the second anode reset voltage. a relationship.
  • the data retention voltage, the first anode reset voltage and the second anode reset voltage corresponding to the average gray-scale voltage between any two adjacent average gray-scale voltages in the parameter comparison table can be calculated by interpolation.
  • the average grayscale voltage may range from approximately 0.2V to 7.0V
  • the data retention voltage may range from approximately 0.2V to 7.0V
  • the first anode reset voltage may range from approximately -0.5V to -0.6 V
  • the second anode reset voltage may range from about -0.5V to -0.6V.
  • the average grayscale voltage is 7.0V
  • the corresponding data retention voltage can be 7.0V
  • the first anode reset voltage can be -3.5V
  • the second anode reset voltage can be -4.0V
  • the average grayscale voltage is 6.0V
  • the corresponding data retention voltage can be 6.2V
  • the first anode reset voltage can be -3.6V
  • the second anode reset voltage can be -4.0V
  • the average gray scale voltage is 0.2V
  • the corresponding data retention voltage can be 1.0V
  • the first anode reset voltage may be -3.7V
  • the second anode reset voltage may be -4.0V.
  • this embodiment does not limit it.
  • the average gray scale voltage and the data retention voltage in the parameter comparison table may have a proportional relationship.
  • the average gray scale voltage in the parameter comparison table may be inversely proportional to the absolute value of the voltage difference between the first anode reset voltage and the second anode reset voltage. For example, the larger the gray scale average voltage is, the larger the data retention voltage will be, and the voltage difference between the first anode reset voltage and the second anode reset voltage will be smaller.
  • data collection and sorting can be performed through the output display screen to obtain a parameter comparison table.
  • the parameter combinations provided in the parameter comparison table can achieve the best low-frequency flicker effect.
  • the parameter comparison table shown in Table 2 can be divided into multiple parameter comparison sub-tables.
  • the first parameter comparison subtable can record the correspondence between the average grayscale voltage and the data retention voltage
  • the second parameter comparison subtable can record the correspondence between the average grayscale voltage and the first anode reset voltage and the second anode reset voltage relation.
  • the first parameter comparison subtable can record the correspondence between the average grayscale voltage and the data retention voltage
  • the second parameter comparison subtable can record the correspondence between the average grayscale voltage and the first anode reset voltage
  • the third parameter comparison The sub-table can record the corresponding relationship between the average gray scale voltage and the reset voltage of the second anode.
  • this embodiment does not limit it.
  • the DDIC chip calculates the average gray-scale voltage
  • the display parameter corresponding to the average gray-scale voltage can be looked up from the parameter comparison table.
  • the DDIC chip determines the display parameters of the display screen, it can dynamically output the data hold signal and the anode reset signal to the display panel according to the display parameters.
  • FIG. 6 is a schematic waveform diagram of a control signal according to at least one embodiment of the present disclosure.
  • V-sync is a vertical synchronous signal (Vertical Synchronous Signal), which is used to define a frame period (or a vertical synchronization period).
  • the first scan signal SCAN1 may be provided by the first scan line GLa
  • the second scan signal SCAN2 may be provided by the second scan line GLb.
  • the pixel circuit writes the data signal provided by the data line under the control of the first scan signal SCAN1 and the second scan signal SCAN2; Under the control of SCAN2, no new data signal is written.
  • a first display frame and a second display frame with different grayscale data are taken as an example for illustration.
  • Vinit2-a is the anode reset signal corresponding to the first display frame
  • Vinit2-b is the anode reset signal corresponding to the second display frame.
  • the anode reset signal Vinit2-a maintains the first anode reset voltage V2-1 in the refresh phase Q1, and maintains the second anode reset voltage V2-2 in the hold phase Q2.
  • the anode reset signal Vinit2-b maintains the first anode reset voltage V2-1' in the refresh phase Q1, and maintains the second anode reset voltage V2-2' in the hold phase Q2.
  • the first anode reset voltage V2-1 is greater than the second anode reset voltage V2-2, and the first anode reset voltage V2-1' is greater than the second anode reset voltage V2-2'.
  • the first anode reset voltages V2-1 and V2-1' may be different, and the second anode reset voltages V2-2 and V2-2' may be different. However, this embodiment does not limit it.
  • KV-a is a data holding signal of the first display frame in the holding phase Q2, and the data holding signal KV-a is maintained at the first data holding voltage KV1 in the holding phase Q2.
  • KV-b is a data holding signal of the second display frame in the holding phase Q2, and the data holding signal KV-b is maintained at the second data holding voltage KV2 in the holding phase Q2.
  • the first data retention voltage KV1 may be different from the second data retention voltage KV2, for example, the first data retention voltage KV1 is greater than the second data retention voltage KV2, or the second data retention voltage KV2 is greater than the first data retention voltage KV1.
  • this embodiment does not limit it.
  • the matching display parameters are determined after converting the grayscale data of the display screen into grayscale voltages, so that more accurate display parameters can be obtained, which is beneficial to improve the display effect.
  • FIG. 7 is a schematic diagram of a control device of a display panel according to at least one embodiment of the present disclosure.
  • the control device of this embodiment may include: a gray scale conversion module 301 , a voltage calculation module 302 , a parameter conversion module 303 and a signal output module 304 .
  • the grayscale converting module 301 is configured to convert the grayscale data of the display frame into grayscale voltages at the first refresh rate.
  • the voltage calculation module 302 is configured to calculate the average gray-scale voltage of the display screen according to the gray-scale voltage of the display screen.
  • the parameter conversion module 303 is configured to determine a display parameter matching the display screen according to the average gray scale voltage of the display screen.
  • the signal output module 304 is configured to output a control signal of the display screen to the display panel according to the display parameters matched by the display screen.
  • the control signal includes at least one of the following: a data hold signal, and an anode reset signal of a light emitting element of the display panel.
  • the display phase of the display screen may include: a refresh phase and a hold phase.
  • the display parameters may include at least one of: a data hold voltage in a hold phase; a first anode reset voltage in a refresh phase and a second anode reset voltage in a hold phase.
  • FIG. 8 is another schematic diagram of a control device of a display panel according to at least one embodiment of the present disclosure.
  • the parameter conversion module 303 may include: a first parameter conversion module 3031 , a second parameter conversion module 3032 and a third parameter conversion module 3033 .
  • the first parameter conversion module 3031 is configured to determine the first anode reset voltage matching the display screen according to the average gray scale voltage of the display screen.
  • the second parameter conversion module 3032 is configured to determine a second anode reset voltage matching the display screen according to the average gray scale voltage of the display screen.
  • the third parameter converting module 3033 is configured to determine a data holding voltage matching the display screen according to the average gray scale voltage of the display screen.
  • the signal output module 304 may include: a first output module 3041 and a second output module 3042 .
  • the first output module 3041 is configured to output an anode reset signal of the display screen to the display panel according to the display parameters matched by the display screen.
  • the second output module 3042 is configured to output a data hold signal to the display panel according to the display parameters matched by the display screen.
  • control device of the display panel of this embodiment For the relevant description of the control device of the display panel of this embodiment, reference may be made to the description of the foregoing embodiment, so details are not repeated here.
  • FIG. 9 is another schematic diagram of a control device according to at least one embodiment of the present disclosure.
  • the control device in this embodiment may include: a memory 401 and a processor 402 .
  • the memory 401 is configured to store computer programs
  • the processor 402 is configured to execute the computer programs to implement the aforementioned control method.
  • the processor 402 of the control device may include a processing device such as a Microcontroller Unit (MCU, Microcontroller Unit) or a Field-Programmable Gate Array (FPGA, Field-Programmable Gate Array).
  • the memory 401 of the control device can store the grayscale conversion comparison table, the parameter comparison table, and software programs and modules of application software, such as program instructions or modules corresponding to the method in this embodiment.
  • the processor 402 executes various functional applications and data processing by running software programs and modules stored in the memory 401 , such as implementing the method provided in this embodiment.
  • the memory 401 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory may include memory located remotely from the processor, which remote memory may be connected to the control device via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • FIG. 10 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device of this embodiment may include: a display panel 502 and a control device 501 .
  • the control device 501 is configured to provide a control signal to the display panel 502 .
  • the display panel 502 may include: a pixel array.
  • the pixel array includes a plurality of sub-pixels, and at least one sub-pixel includes a light emitting element and a pixel circuit for driving the light emitting element to emit light.
  • the pixel circuit includes: multiple transistors and at least one capacitor.
  • At least one embodiment of the present disclosure further provides a non-transitory computer-readable storage medium storing a computer program, and implementing the steps of the above control method when the computer program is executed.
  • the functional modules or units in the system, and the device can be implemented as software, firmware, hardware, and an appropriate combination thereof.
  • the division between functional modules or units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components. Components cooperate to execute.
  • Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.
  • Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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Abstract

一种显示面板的控制方法，包括：在第一刷新频率下，将显示画面的灰阶数据转换为灰阶电压；根据显示画面的灰阶电压，计算显示画面的平均灰阶电压；根据显示画面的平均灰阶电压，确定显示画面匹配的显示参数；根据显示画面匹配的显示参数，向显示面板输出显示画面的控制信号。控制信号包括以下至少之一：数据保持信号、显示面板的发光元件的阳极复位信号。

Description

显示面板的控制方法及控制装置、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示面板的控制方法及控制装置、显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Display)显示器件由于具备自发光、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围光、构造及制程较简单等优异特性，被认为是下一代平面显示器的新兴应用技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板的控制方法及控制装置、显示装置。
一方面，本公开实施例提供一种显示面板的控制方法，包括：在第一刷新频率下，将显示画面的灰阶数据转换为灰阶电压；根据所述显示画面的灰阶电压，计算显示画面的平均灰阶电压；根据显示画面的平均灰阶电压，确定显示画面匹配的显示参数；根据显示画面匹配的显示参数，向显示面板输出显示画面的控制信号。控制信号包括以下至少之一：数据保持信号、显示面板的发光元件的阳极复位信号。
在一些示例性实施方式中，所述显示画面的显示阶段包括：刷新阶段和保持阶段。所述显示参数包括以下至少之一：所述保持阶段的数据保持电压；所述刷新阶段的第一阳极复位电压和所述保持阶段的第二阳极复位电压。
在一些示例性实施方式中，所述将显示画面的灰阶数据转换为灰阶电压，包括：针对所述显示画面的每个显示单元的灰阶数据，在存储的灰阶转换对照表中查找与所述灰阶数据对应的灰阶电压。
在一些示例性实施方式中，所述将显示画面的灰阶数据转换为灰阶电压，还包括：在所述灰阶转换对照表中没有查找到所述显示单元的灰阶数据对应的灰阶电压，则利用预设的灰阶映射函数计算出所述灰阶数据对应的灰阶电压。
在一些示例性实施方式中，所述根据所述显示画面的灰阶电压，计算所述显示画面的平均灰阶电压，包括：计算所述显示画面的每一显示行的灰阶电压的平均值，再利用所有显示行的灰阶电压的平均值计算出所述显示画面的平均灰阶电压。
在一些示例性实施方式中，所述根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的显示参数，包括：从存储的参数对照表中查找与所述显示画面的平均灰阶电压匹配的显示参数。其中，所述参数对照表记录以下至少之一：平均灰阶电压与数据保持电压的映射关系、平均灰阶电压与第一阳极复位电压和第二阳极复位电压的映射关系。
在一些示例性实施方式中，所述参数对照表中的平均灰阶电压与数据保持电压呈正比关系；所述参数对照表中的平均灰阶电压与第一阳极复位电压和第二阳极复位电压的压差的绝对值呈反比关系。
在一些示例性实施方式中，所述根据所述显示画面匹配的显示参数，向所述显示面板输出所述显示画面的控制信号，包括以下至少之一：在所述保持阶段，向所述显示面板输出所述数据保持信号，且所述数据保持信号维持所述数据保持电压；向所述显示面板输出阳极复位信号，且所述阳极复位信号在所述刷新阶段维持在所述第一阳极复位电压，在所述保持阶段维持在所述第二阳极复位电压。
在一些示例性实施方式中，所述第一刷新频率小于60Hz。
另一方面，本公开实施例提供一种显示面板的控制装置，包括：灰阶转换模块、电压计算模块、参数转换模块以及信号输出模块。灰阶转换模块配置为在第一刷新频率下，将显示画面的灰阶数据转换为灰阶电压。电压计算模块配置为根据所述显示画面的灰阶电压，计算所述显示画面的平均灰阶电压。参数转换模块配置为根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的显示参数。信号输出模块配置为根据所述显示画面匹配的显示参 数，向所述显示面板输出所述显示画面的控制信号。所述控制信号包括以下至少之一：数据保持信号、所述显示面板的发光元件的阳极复位信号。
在一些示例性实施方式中，所述显示画面的显示阶段包括：刷新阶段和保持阶段。所述显示参数包括以下至少之一：所述保持阶段的数据保持电压；所述刷新阶段的第一阳极复位电压和所述保持阶段的第二阳极复位电压。
在一些示例性实施方式中，所述参数转换模块，包括：第一参数转换模块、第二参数转换模块和第三参数转换模块。所述第一参数转换模块，配置为根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的第一阳极复位电压。所述第二参数转换模块，配置为根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的第二阳极复位电压。所述第三参数转换模块，配置为根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的数据保持电压。
在一些示例性实施方式中，所述信号输出模块包括：第一输出模块和第二输出模块。所述第一输出模块，配置为根据所述显示画面匹配的显示参数，向所述显示面板输出所述显示画面的阳极复位信号。所述第二输出模块，配置为根据所述显示画面匹配的显示参数，向所述显示面板输出所述显示画面的数据保持信号。
另一方面，本公开实施例提供一种显示装置，包括：显示面板以及如上所述的控制装置，所述控制装置配置为向所述显示面板提供控制信号。
在一些示例性实施方式中，所述显示面板包括：像素阵列，所述像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动所述发光元件发光的像素电路；所述像素电路包括：多个晶体管和至少一个电容。
另一方面，本公开实施例提供一种控制装置，包括：存储器和处理器；所述存储器配置为存储计算机程序，所述处理器配置为执行所述计算机程序以实现如上所述的控制方法。
另一方面，本公开实施例提供一种非瞬态计算机可读存储介质，存储有计算机程序，所述计算机程序被执行时实现如上所述的控制方法。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示面板的控制方法的流程图；
图2为本公开至少一实施例的显示装置的示意图；
图3为本公开至少一实施例的像素电路的等效电路图；
图4为图3提供的像素电路的工作时序图；
图5为本公开至少一实施例的跳帧驱动方式的示意图；
图6为本公开至少一实施例的控制信号的波形示意图；
图7为本公开至少一实施例的显示面板的控制装置的示意图；
图8为本公开至少一实施例的显示面板的控制装置的另一示意图；
图9为本公开至少一实施例的控制装置的另一示意图；
图10为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了 理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
随着低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide) 技术的应用，可以使得OLED显示面板的画面刷新频率降至1赫兹(Hz)甚至更低。由于人眼可识别的亮度变化频率约为24Hz至30Hz，因此，对于基于LTPO技术的显示面板来说，在进行低频(即低于常规60Hz的刷新频率)显示时，需要整个画面亮度保持恒定，显示过程中不能引入低频的亮度变化。
本公开实施例提供一种显示面板的控制方法及控制装置、显示装置，可以改善显示面板的显示效果。
图1为本公开至少一实施例的显示面板的控制方法的流程图。如图1所示，本公开实施例提供一种显示面板的控制方法，包括：
步骤S11、在第一刷新频率下，将显示画面的灰阶数据转换为灰阶电压；
步骤S12、根据显示画面的灰阶电压，计算显示画面的平均灰阶电压；
步骤S13、根据显示画面的平均灰阶电压，确定显示画面匹配的显示参数；
步骤S14、根据显示画面匹配的显示参数，向显示面板输出显示画面的控制信号。
在一些示例性实施方式中，本实施例的控制方法可以应用于显示驱动电路(DDIC，Display Driver Integrated Circuit)芯片。以采用应用处理器(AP，Application Processor)、DDIC芯片以及显示面板架构的显示装置为例，AP渲染生成图像数据后，将图像数据发送至DDIC芯片，由DDIC芯片控制显示面板根据图像数据进行图像显示。在本示例中，DDIC芯片可以根据不同显示画面，向显示面板输出不同的控制信号，从而改善显示面板的显示效果。
在一些示例性实施方式中，向显示面板输出的控制信号可以包括以下至少之一：数据保持信号、显示面板的发光元件的阳极复位信号。在本示例性实施方式中，针对不同的显示画面，根据显示参数，可以给不同的显示画面提供不同的控制信号，从而实现较佳的显示效果。
在一些示例性实施方式中，显示画面的显示阶段可以包括：刷新阶段和保持阶段。显示参数可以包括以下至少之一：在保持阶段的数据保持电压；在刷新阶段的第一阳极复位电压和在保持阶段的第二阳极复位电压。在一些示例中，可以根据显示画面的平均灰阶电压，仅确定显示画面匹配的数据保 持电压；或者，可以根据显示画面的平均灰阶电压，仅确定显示画面匹配的阳极复位电压(包括第一阳极复位电压和第二阳极复位电压)；或者，可以根据显示画面的平均灰阶电压，确定显示画面匹配的数据保持电压和阳极复位电压。在本示例中，通过选择较优的显示参数或组合，可以提升显示面板的显示效果。
在一些示例性实施方式中，步骤S14可以包括以下至少之一：在保持阶段，向显示面板输出数据保持信号，且数据保持信号维持数据保持电压；向显示面板输出阳极复位信号，且阳极复位信号在刷新阶段维持在第一阳极复位电压，在保持阶段维持在第二阳极复位电压。在本示例中，数据保持信号可以根据数据保持电压产生，阳极复位信号可以根据第一阳极复位电压和第二阳极复位电压产生。在一些示例中，数据保持电压的范围可以约为0.2V至7.0V。第一阳极复位电压的范围可以约为-0.5V至-6.0V，第二阳极复位电压的范围可以约为-0.5V至-6.0V。本实施例对此并不限定。
在一些示例性实施方式中，第一刷新频率可以小于60Hz。本示例提供的控制方法在低频驱动状态下执行，从而改善显示面板的低频闪烁效果。
在一些示例性实施方式中，显示画面的灰阶数据转换和平均灰阶电压的计算可以按照显示单元进行。即，将每个显示单元的灰阶数据转换为灰阶电压，并计算所有显示单元的平均灰阶电压。在一些示例中，显示单元可以为像素单元或者可以为子像素。然而，本实施例对此并不限定。
下面通过多个示例对本实施例的方案进行举例说明。
图2为本公开至少一实施例的显示装置的示意图。在一些示例性实施方式中，如图2所示，本示例性实施例的显示装置可以包括：显示面板以及控制装置。控制装置可以包括DDIC芯片10。显示面板可以包括：像素阵列13、沿第一方向延伸的多条第一信号线(例如，扫描线GL1至GLm、发光控制线EML1至EMLo)以及沿第二方向延伸的多条第二信号线(例如，数据线DL1至DLn)。第一方向(例如水平方向)与第二方向(例如竖直方向)交叉，例如第一方向与第二方向可以相互垂直。其中，m、n和o均为整数。显示面板上还设置有栅驱动电路(例如包括第一栅驱动电路11和第二栅驱动电路12)。控制装置10和栅驱动电路可以配置为驱动像素阵列13。
在一些示例性实施方式中，DDIC芯片10可以将适于第一栅驱动电路11的规格的时钟信号、起始信号等提供到第一栅驱动电路11，以及将适于第二栅驱动电路12的规格的时钟信号、起始信号等提供到第二栅驱动电路12。第一栅驱动电路11可以利用从DDIC芯片10接收的时钟信号、起始信号等来产生提供到扫描线GL1至GLm的扫描信号。第二栅驱动电路12可以利用从DDIC芯片10接收的时钟信号、起始信号等来产生提供到发光控制线EML1至EMLm的发光控制信号。DDIC芯片10还可以适于产生提供到数据线DL1至DLn的数据信号。
在一些示例性实施方式中，第一栅驱动电路11可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线GL1至GLm。例如，第一栅驱动电路11可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的起始信号传输到下一级电路的方式产生扫描信号。第二栅驱动电路12可以将具有截止电平脉冲的发光控制信号顺序地提供到发光控制线EML1至EMLo。例如，第二栅驱动电路12可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的起始信号传输到下一级电路的方式产生发光控制信号。然而，本实施例对此并不限定。
在一些示例性实施方式中，像素阵列13可以包括多个子像素PX。一个像素单元可以包括三个子像素。三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例性实施方式中，至少一个子像素PX包括：发光元件以及驱动发光元件发光的像素电路。发光元件与对应的像素电路电连接。发光元件可以为OLED器件，包括阳极、阴极以及位于阳极和阴极之间的有机发光层。 在一些示例中，像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以为5T1C、5T2C、6T1C、7T1C或8T1C等结构。然而，本实施例对此并不限定。
图3为本公开至少一实施例的像素电路的示意图。在一些示例性实施方式中，如图3所示，本示例性实施例的像素电路可以为8T1C结构，即包括第一晶体管T1至第八晶体管T8以及存储电容C1。
在一些示例性实施方式中，像素电路的第一晶体管T1至第七晶体管T7可以为第一类型晶体管，例如为P型晶体管，第八晶体管T8可以为第二类型晶体管，例如为N型晶体管。然而，本实施例对此并不限定。例如，像素电路的多个晶体管可以均是P型晶体管，或者可以均是N型晶体管。
在一些示例性实施方式中，像素电路的第一类型晶体管(例如，第一晶体管T1至第七晶体管T7)可以采用低温多晶硅薄膜晶体管，第一像素电路的第二类型晶体管(例如，第八晶体管T8)可以采用氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。然而，本实施例对此并不限定。例如，像素电路的多个晶体管可以均采用低温多晶硅薄膜晶体管，或者，均采用氧化物薄膜晶体管。
在一些示例性实施方式中，如图3所示，像素电路与第一扫描线GLa、第二扫描线GLb、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2以及复位控制线RST电连接。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。第一扫描线GLa配置为向像素电路提供第一扫描信号SCAN1，第二扫描线GLb配置为向像素电路提供第二扫描信号SCAN2，数据线DL配置为向像素电路提供数 据信号DATA，发光控制线EML配置为向像素电路提供发光控制信号EM，复位控制线RST配置为向像素电路提供复位控制信号RESET。第一初始信号线INIT1配置为提供用于复位第五节点N5和第一节点N1的第一初始信号，第二初始信号线INIT2配置为提供用于复位第四节点N4(即发光元件EL的阳极)的第二初始信号(即阳极复位信号)。
在一些示例性实施方式中，在第n行像素电路中，复位控制线RST可以与第n-1行像素电路的第一扫描线GLa连接，以被输入第一扫描信号SCAN1(n-1)，即复位控制信号RESET(n)与第一扫描信号SCAN1(n-1)相同。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在一些示例性实施方式中，如图3所示，第三晶体管T3的控制极与第一节点N1电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接。第四晶体管T4的控制极与第一扫描线GLa电连接，第四晶体管T4的第一极与数据线DL电连接，第四晶体管T4的第二极与第二节点N2电连接。第二晶体管T2的控制极与第一扫描线GLa电连接，第二晶体管T2的第一极与第五节点N5电连接，第二晶体管T2的第二极与第三节点N3电连接。第五晶体管T5的控制极与发光控制线EML电连接，第五晶体管T5的第一极与第一电源线PL1电连接，第五晶体管T5的第二极与第二节点N2电连接。第六晶体管T6的控制极与发光控制线EML电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第四节点N4电连接。第一晶体管T1的控制极与复位控制线RST电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第五节点N5电连接。第七晶体管T7的控制极与复位控制线RST电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与第四节点N4电连接。第八晶体管T8的控制极与第二扫描线GL2电连接，第八晶体管T8的第一极与第五节点N5电连接，第八晶体管T8的第二极与第一节点N1电连接。存储电容C1的第一电极与第一节点N1电连接，存储电容C1的第二电极与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容C1、第八晶体管T8和第三晶体 管T3的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和发光元件EL的阳极的连接点，第五节点N5为第一晶体管T1、第二晶体管T2和第八晶体管T8的连接点。
图4为图3提供的像素电路的工作时序图。下面参照图4对图3所示的像素电路的工作过程进行说明。其中，像素电路的第一晶体管T1至第七晶体管T7为P型晶体管，第八晶体管T8为N型晶体管。
在一些示例性实施方式中，如图3和图4所示，在一帧时长内，像素电路的工作过程可以包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。复位控制线RST提供的复位控制信号RESET为低电平信号，使第一晶体管T1和第七晶体管T7导通，第二扫描线GLb提供的第二扫描信号SCAN2为高电平信号，使第八晶体管T8导通。第一初始信号线INIT1提供的第一初始信号被提供至第五节点N5和第一节点N1，对第一节点N1进行初始化，清除存储电容C1中原有数据电压。第一扫描线GLa提供的第一扫描信号SCAN1为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使第四晶体管T4、第二晶体管T2、第五晶体管T5、以及第六晶体管T6断开。第七晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至第四节点N4，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化。此阶段发光元件EL不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。第一扫描线GLa提供的第一扫描信号SCAN1为低电平信号，第二扫描线GLb提供的第二扫信号SCAN2、复位控制线RST提供的复位控制信号RESET以及发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容C1的第一电极为低电平，因此，第三晶体管T3导通。第一扫描信号SCAN1为低电平信号，使第二晶体管T2和第四晶体管T4导通。第二晶体管T2、第四晶体管T4和第八晶体管T8导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的第三晶体管T3、 第三节点N3、导通的第二晶体管T2、第五节点N5和导通的第八晶体管T8提供至第一节点N1，并将数据线DL输出的数据电压Vdata与第三晶体管T3的阈值电压之差充入存储电容C1，存储电容C1的第一电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为第三晶体管T3的阈值电压。复位控制线RST提供的复位控制信号RESET为高电平信号，使第一晶体管T1和第七晶体管T7断开。发光控制线EML提供的发光控制信号EM为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段S3，称为发光阶段。发光控制线EML提供的发光控制信号EM为低电平信号，使第五晶体管T5和第六晶体管T6导通。第二扫描线GLb提供的第二扫描信号SCAN2为低电平信号，使第八晶体管T8断开。第一扫描线GLa提供的第一扫描信号SCAN1和复位控制线RST提供的复位控制信号RESET为高电平信号，使第二晶体管T2、第四晶体管T4、第七晶体管T7以及第一晶体管T1断开。第一电源线PLa输出的第一电压信号VDD通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路的驱动过程中，流过第三晶体管T3(即驱动晶体管)的驱动电流由其控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2；
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光元件的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件的电流与第三晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿第三晶体管T3的阈值电压。
在基于LTPO技术的显示面板中，为了实现低频驱动，引入跳帧(Frame Skip)驱动方式。图5为本公开至少一实施例的跳帧驱动方式的示意图。如图5所示，显示画面的显示阶段可以包括：刷新阶段和保持阶段。刷新阶段 包括刷新帧(refresh frame)，刷新帧为需要进行数据刷新的帧。保持阶段包括多个保持帧(skip frame)，保持帧为不需要进行数据刷新、靠保持之前的画面数据进行发光的帧。刷新帧和保持帧的区别在于：保持帧保持之前刷新帧写入的数据电压而不将新的数据电压写入子像素。在低频驱动方式下，驱动频率较低，例如小于60Hz。以驱动频率为1Hz为例，1秒内可以包括1帧刷新帧和59帧保持帧。如此，可以达到降低功耗的作用。
在一些示例性实施方式中，在一个刷新帧内，像素电路可以按照图4所示的工作时序写入数据线提供的数据信号。在保持阶段，由于无需进行数据刷新，数据线提供数据保持信号，数据保持信号可以维持在一个恒定的电压(即数据保持电压)，以达到省电目的，降低功耗。像素电路所连接的第二初始信号线提供的第二初始信号即为提供给发光元件的阳极复位信号。第二初始信号线通过在刷新阶段和保持阶段提供电压值不同的阳极复位信号，可以改善低频闪烁效果，使得显示画面保持恒定的亮度。在本示例中，通过在驱动晶体管的源极加载合适的电压，调整驱动晶体管在发光时的状态，使驱动晶体管在刷新帧和保持帧的状态基本一致，而且通过阳极复位信号直接调节发光元件的发光起始电压，拉平刷新帧和保持帧的亮度水平，从而改善低频闪烁效果。
在一些示例性实施方式中，阳极复位信号、数据信号和数据保持信号由DDIC芯片产生。DDIC芯片可以通过数据线将数据信号和数据保持信号提供给子像素，并通过第二初始信号线提供阳极复位信号给子像素。
在一些示例性实施方式中，DDIC芯片获取外部输入的图像数据，对外部输入的图像数据进行处理，得到子像素(或像素单元)的灰阶数据。例如，DDIC芯片可以从应用处理器接收图像数据。DDIC芯片可以产生撕裂效应(TE，Tearing Effect)信号，用于防止图像显示过程中画面刷新时的撕裂问题。当准备好刷新下一帧图像时，DDIC芯片即产生TE信号。示例性地，AP在监听到TE信号上升沿，或检测到TE信号处于高电平状态后，向DDIC芯片发送下一帧图像数据。
在一些示例性实施方式中，DDIC芯片在第一刷新频率(即小于60Hz的刷新频率)下，可以根据预存的灰阶转换对照表，将显示画面的每个子像 素(或像素单元)的灰阶数据转换为灰阶电压。如表1所示，预存的灰阶转换对照表可以包括一列灰阶数据和对应的一列灰阶电压，且灰阶转换对照表内的灰阶数据和灰阶电压之间存在一一对应关系。
表1灰阶转换对照表
灰阶数据1 灰阶电压1
灰阶数据2 灰阶电压2
…… ……
灰阶数据n 灰阶电压n
在一些示例中，灰阶数据的范围可以为0至255，灰阶电压的范围可以约为0.2V至7.0V。例如，灰阶数据L0对应的灰阶电压为7.0V，灰阶数据L8对应的灰阶电压为6.0V，灰阶数据L255对应的灰阶电压为0.2V。然而，本实施例对此并不限定。
在一些示例性实施方式中，灰阶转换对照表中的任两个相邻灰阶数据之间的灰阶数据与灰阶电压之间满足灰阶映射函数。即，Voltage＝f(Graydata)，其中，Voltage表示灰阶电压，Graydata表示灰阶数据。在一些示例中，灰阶映射函数可以为线性关系，或者可以为指数关系。例如，灰阶映射函数可以为y＝a*X+b或y＝X a。其中，X表示灰阶数据，y表示灰阶电压，a和b均为常数。然而，本实施例对此并不限定。
在一些示例性实施方式中，灰阶转换对照表中的任两个相邻灰阶数据之间的灰阶数据与灰阶电压之间满足的灰阶映射函数可以相同，或者可以不同。例如，表1所示的灰阶转换对照表中的灰阶数据1和灰阶数据2之间的灰阶数据和灰阶电压之间可以满足第一灰阶映射函数，灰阶数据2和灰阶数据3之间的灰阶数据和灰阶电压之间可以满足第二灰阶映射函数，且第一灰阶映射函数不同于第二灰阶映射函数。比如，第一灰阶映射函数可以为线性函数，第二灰阶映射函数可以为指数函数。然而，本实施例对此并不限定。
在一些示例性实施方式中，针对显示画面的任一子像素的灰阶数据，DDIC芯片可以在灰阶转换对照表查找与该灰阶数据对应的灰阶电压。若没有在灰阶转换对照表查找到灰阶数据对应的灰阶电压，可以通过插值法对灰 阶数据进行转换。例如，通过灰阶转换对照表，确定待转换的灰阶数据对应的灰阶映射函数，利用灰阶映射函数，计算出对应的灰阶电压。
在一些示例性实施方式中，DDIC芯片得到显示画面的每个子像素的灰阶电压之后，可以计算显示画面的平均灰阶电压。平均灰阶电压为显示画面的所有子像素的灰阶电压总和与子像素总个数的比值。
在一些示例性实施方式中，以分辨率为H*V的显示画面为例，可以先计算每一行子像素的灰阶电压的平均值，再计算显示画面的平均灰阶电压。例如，可以通过以下方式计算每一行子像素的灰阶电压的平均值：
Figure PCTCN2021133244-appb-000001
其中，Vh avg为一行子像素的平均灰阶电压；Voltage i为子像素行中第i个子像素的灰阶电压；W为权重因子。W可以根据需求设置，例如可以默认设置为1。然而，本实施例对此并不限定。
随后，通过以下方式计算出显示画面的平均灰阶电压：
Figure PCTCN2021133244-appb-000002
其中，V avg为显示画面的平均灰阶电压。
然而，本实施例对于显示画面的平均灰阶电压的计算方式并不限定。例如，可以直接计算所有子像素的灰阶电压总和，再根据灰阶电压总和与子像素总个数之比，得到平均灰阶电压；或者，可以先计算每列子像素的灰阶电压的平均值，再利用所有子像素列的灰阶电压的平均值计算出显示画面的平均灰阶电压。
在一些示例性实施方式中，DDIC芯片在计算出显示画面的平均灰阶电压之后，可以根据预存的参数对照表确定对应的数据保持电压、第一阳极复位电压和第二阳极复位电压。如表2所示，预存的参数对照表可以包括一列平均灰阶电压Vavg、一列数据保持电压、一列第一阳极复位电压Vinit2-1以及一列第二阳极复位电压Vinit2-2。其中，平均灰阶电压和数据保持电压之间存在一一对应关系，平均灰阶电压和第一阳极复位电压之间存在一一对应关系，平均灰阶电压和第二阳极复位电压之间存在一一关系。在一些示例中，参数对照表内任两个相邻平均灰阶电压之间的平均灰阶电压对应的数据保持 电压、第一阳极复位电压和第二阳极复位电压均可以通过插值计算得到。
表2参数对照表
Figure PCTCN2021133244-appb-000003
在一些示例中，平均灰阶电压的范围可以约为0.2V至7.0V，数据保持电压的范围可以约为0.2V至7.0V，第一阳极复位电压的范围可以约为-0.5V至-0.6V，第二阳极复位电压的范围可以约为-0.5V至-0.6V。例如，平均灰阶电压为7.0V，对应的数据保持电压可以为7.0V，第一阳极复位电压可以为-3.5V，第二阳极复位电压可以为-4.0V；平均灰阶电压为6.0V，对应的数据保持电压可以为6.2V，第一阳极复位电压可以为-3.6V，第二阳极复位电压可以为-4.0V；平均灰阶电压为0.2V，对应的数据保持电压可以为1.0V，第一阳极复位电压可以为-3.7V，第二阳极复位电压可以为-4.0V。然而，本实施例对此并不限定。
在一些示例性实施方式中，参数对照表中的平均灰阶电压与数据保持电压可以呈正比关系。参数对照表中的平均灰阶电压与第一阳极复位电压和第二阳极复位电压的压差的绝对值可以呈反比关系。例如，灰阶平均电压越大，数据保持电压也会越大，第一阳极复位电压和第二阳极复位电压之间的压差会偏小。
在一些示例性实施方式中，可以通过输出的显示画面进行数据采集并整理而得到参数对照表。参数对照表提供的参数组合可以实现最佳的低频闪烁效果。在一些示例中，表2所示的参数对照表可以分为多个参数对照子表。例如，第一参数对照子表可以记录平均灰阶电压和数据保持电压之间的对应关系，第二参数对照子表可以记录平均灰阶电压与第一阳极复位电压和第二 阳极复位电压的对应关系。或者，第一参数对照子表可以记录平均灰阶电压和数据保持电压之间的对应关系，第二参数对照子表可以记录平均灰阶电压与第一阳极复位电压的对应关系，第三参数对照子表可以记录平均灰阶电压与第二阳极复位电压的对应关系。然而，本实施例对此并不限定。
在一些示例性实施方式中，针对任一显示画面，DDIC芯片计算出平均灰阶电压之后，可以从参数对照表查找与该平均灰阶电压对应的显示参数。DDIC芯片确定显示画面的显示参数之后，可以按照显示参数，向显示面板动态输出数据保持信号和阳极复位信号。
图6为本公开至少一实施例的控制信号的波形示意图。在一些示例性实施方式中，如图6所示，V-sync为垂直同步信号(Vertical Synchronous Signal)，用于定义帧时段(或垂直同步时段)。以显示面板包括图3所示的像素电路为例，第一扫描信号SCAN1可以由第一扫描线GLa提供，第二扫描信号SCAN2可以由第二扫描线GLb提供。在刷新帧Q1，像素电路在第一扫描信号SCAN1和第二扫描信号SCAN2的控制下，写入数据线提供的数据信号；在保持阶段Q2，像素电路在第一扫描信号SCAN1和第二扫描信号SCAN2的控制下，不写入新的数据信号。
在一些示例性实施方式中，如图6所示，以具有不同灰阶数据的第一显示画面和第二显示画面为例进行说明。Vinit2-a为对应第一显示画面的阳极复位信号，Vinit2-b为对应第二显示画面的阳极复位信号。阳极复位信号Vinit2-a在刷新阶段Q1维持第一阳极复位电压V2-1，在保持阶段Q2维持第二阳极复位电压V2-2。阳极复位信号Vinit2-b在刷新阶段Q1维持第一阳极复位电压V2-1’，在保持阶段Q2维持第二阳极复位电压V2-2’。第一阳极复位电压V2-1大于第二阳极复位电压V2-2，第一阳极复位电压V2-1’大于第二阳极复位电压V2-2’。第一阳极复位电压V2-1和V2-1’可以不同，第二阳极复位电压V2-2和V2-2’可以不同。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图6所示，KV-a为第一显示画面在保持阶段Q2的数据保持信号，数据保持信号KV-a在保持阶段Q2维持在第一数据保持电压KV1。KV-b为第二显示画面在保持阶段Q2的数据保持信号，数据保持信号KV-b在保持阶段Q2维持在第二数据保持电压KV2。第一数据保 持电压KV1可以不同于第二数据保持电压KV2，例如，第一数据保持电压KV1大于第二数据保持电压KV2，或者，第二数据保持电压KV2大于第一数据保持电压KV1。然而，本实施例对此并不限定。
本示例性实施方式中，在低频驱动模式下，针对具有不同灰阶数据的显示画面，确定不同的显示参数，给显示面板提供不同的控制信号，从而使得在任意画面下均能实现最佳的低频闪烁效果。而且，本实施例中，将显示画面的灰阶数据转换为灰阶电压之后再确定匹配的显示参数，可以得到更精准的显示参数，有利于提高显示效果。
图7为本公开至少一实施例的显示面板的控制装置的示意图。在一些示例性实施方式中，如图7所示，本实施例的控制装置可以包括：灰阶转换模块301、电压计算模块302、参数转换模块303以及信号输出模块304。灰阶转换模块301配置为在第一刷新频率下，将显示画面的灰阶数据转换为灰阶电压。电压计算模块302配置为根据显示画面的灰阶电压，计算显示画面的平均灰阶电压。参数转换模块303配置为根据显示画面的平均灰阶电压，确定显示画面匹配的显示参数。信号输出模块304配置为根据显示画面匹配的显示参数，向显示面板输出显示画面的控制信号。其中，控制信号包括以下至少之一：数据保持信号、显示面板的发光元件的阳极复位信号。
在一些示例性实施方式中，显示画面的显示阶段可以包括：刷新阶段和保持阶段。显示参数可以包括以下至少之一：在保持阶段的数据保持电压；在刷新阶段的第一阳极复位电压和在保持阶段的第二阳极复位电压。
图8为本公开至少一实施例的显示面板的控制装置的另一示意图。在一些示例性实施方式中，如图8所示，参数转换模块303可以包括：第一参数转换模块3031、第二参数转换模块3032和第三参数转换模块3033。第一参数转换模块3031配置为根据显示画面的平均灰阶电压，确定显示画面匹配的第一阳极复位电压。第二参数转换模块3032配置为根据显示画面的平均灰阶电压，确定显示画面匹配的第二阳极复位电压。第三参数转换模块3033配置为根据显示画面的平均灰阶电压，确定显示画面匹配的数据保持电压。
在一些示例性实施方式中，如图8所示，信号输出模块304可以包括：第一输出模块3041和第二输出模块3042。第一输出模块3041配置为根据显 示画面匹配的显示参数，向显示面板输出显示画面的阳极复位信号。第二输出模块3042配置为根据显示画面匹配的显示参数，向显示面板输出数据保持信号。
关于本实施例的显示面板的控制装置的相关说明可以参照前述实施例的说明，故于此不再赘述。
图9为本公开至少一实施例的控制装置的另一示意图。在一些示例性实施方式中，如图9所示，本实施例的控制装置可以包括：存储器401和处理器402。存储器401配置为存储计算机程序，处理器402配置为执行计算机程序以实现前述所示的控制方法。
在一些示例性实施方式中，控制装置的处理器402可以包括微控制单元(MCU，Microcontroller Unit)或现场可编程门阵列(FPGA，Field-Programmable Gate Array)等的处理装置。控制装置的存储器401可以存储灰阶转换对照表、参数对照表以及应用软件的软件程序以及模块，如本实施例中的方法对应的程序指令或模块。处理器402通过运行存储在存储器401内的软件程序以及模块，从而执行多种功能应用以及数据处理，比如实现本实施例提供的方法。存储器401可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些示例中，存储器可包括相对于处理器远程设置的存储器，这些远程存储器可以通过网络连接至控制装置。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
图10为本公开至少一实施例的显示装置的示意图。在一些示例性实施方式中，如图10所示，本实施例的显示装置可以包括：显示面板502以及控制装置501。控制装置501配置为向显示面板502提供控制信号。
在一些示例性实施方式中，显示面板502可以包括：像素阵列。像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动发光元件发光的像素电路。像素电路包括：多个晶体管和至少一个电容。关于本实施例的显示装置的相关说明可以参照前述实施例的描述，故于此不再赘述。
此外，本公开至少一实施例还提供一种非瞬态计算机可读存储介质，存储有计算机程序，该计算机程序被执行时实现上述控制方法的步骤。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块或单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块或单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
以上显示和描述了本公开的基本原理、主要特征和本公开的优点。本公开不受上述实施例的限制，上述实施例和说明书中描述的只是说明本公开的原理，在不脱离本公开精神和范围的前提下，本公开还会有多种变化和改进，这些变化和改进都落入要求保护的本公开的范围内。

Claims (17)

  1. 一种显示面板的控制方法，包括：
    在第一刷新频率下，将显示画面的灰阶数据转换为灰阶电压；
    根据所述显示画面的灰阶电压，计算所述显示画面的平均灰阶电压；
    根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的显示参数；
    根据所述显示画面匹配的显示参数，向所述显示面板输出所述显示画面的控制信号，所述控制信号包括以下至少之一：数据保持信号、所述显示面板的发光元件的阳极复位信号。
  2. 根据权利要求1所述的方法，其中，所述显示画面的显示阶段包括：刷新阶段和保持阶段；
    所述显示参数包括以下至少之一：所述保持阶段的数据保持电压；所述刷新阶段的第一阳极复位电压和所述保持阶段的第二阳极复位电压。
  3. 根据权利要求1或2所述的方法，其中，所述将显示画面的灰阶数据转换为灰阶电压，包括：
    针对所述显示画面的每个显示单元的灰阶数据，在存储的灰阶转换对照表中查找与所述灰阶数据对应的灰阶电压。
  4. 根据权利要求3所述的方法，其中，所述将显示画面的灰阶数据转换为灰阶电压，还包括：
    在所述灰阶转换对照表中没有查找到所述显示单元的灰阶数据对应的灰阶电压，则利用预设的灰阶映射函数计算出所述灰阶数据对应的灰阶电压。
  5. 根据权利要求1至4中任一项所述的方法，其中，所述根据所述显示画面的灰阶电压，计算所述显示画面的平均灰阶电压，包括：
    计算所述显示画面的每一显示行的灰阶电压的平均值，再利用所有显示行的灰阶电压的平均值计算出所述显示画面的平均灰阶电压。
  6. 根据权利要求2所述的方法，其中，所述根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的显示参数，包括：
    从存储的参数对照表中查找与所述显示画面的平均灰阶电压匹配的显示 参数；
    其中，所述参数对照表记录以下至少之一：平均灰阶电压与数据保持电压的映射关系、平均灰阶电压与第一阳极复位电压和第二阳极复位电压的映射关系。
  7. 根据权利要求6所述的方法，其中，所述参数对照表中的平均灰阶电压与数据保持电压呈正比关系；所述参数对照表中的平均灰阶电压与第一阳极复位电压和第二阳极复位电压的压差的绝对值呈反比关系。
  8. 根据权利要求2所述的方法，其中，所述根据所述显示画面匹配的显示参数，向所述显示面板输出所述显示画面的控制信号，包括以下至少之一：
    在所述保持阶段，向所述显示面板输出所述数据保持信号，且所述数据保持信号维持所述数据保持电压；
    向所述显示面板输出阳极复位信号，且所述阳极复位信号在所述刷新阶段维持在所述第一阳极复位电压，在所述保持阶段维持在所述第二阳极复位电压。
  9. 根据权利要求1至8中任一项所述的方法，其中，所述第一刷新频率小于60Hz。
  10. 一种显示面板的控制装置，包括：
    灰阶转换模块，配置为在第一刷新频率下，将显示画面的灰阶数据转换为灰阶电压；
    电压计算模块，配置为根据所述显示画面的灰阶电压，计算所述显示画面的平均灰阶电压；
    参数转换模块，配置为根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的显示参数；
    信号输出模块，配置为根据所述显示画面匹配的显示参数，向所述显示面板输出所述显示画面的控制信号，所述控制信号包括以下至少之一：数据保持信号、所述显示面板的发光元件的阳极复位信号。
  11. 根据权利要求10所述的控制装置，其中，所述显示画面的显示阶段包括：刷新阶段和保持阶段；
    所述显示参数包括以下至少之一：所述保持阶段的数据保持电压；所述刷新阶段的第一阳极复位电压和所述保持阶段的第二阳极复位电压。
  12. 根据权利要求11所述的控制装置，其中，所述参数转换模块，包括：第一参数转换模块、第二参数转换模块和第三参数转换模块；
    所述第一参数转换模块，配置为根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的第一阳极复位电压；
    所述第二参数转换模块，配置为根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的第二阳极复位电压；
    所述第三参数转换模块，配置为根据所述显示画面的平均灰阶电压，确定所述显示画面匹配的数据保持电压。
  13. 根据权利要求11所述的控制装置，其中，所述信号输出模块包括：第一输出模块和第二输出模块；
    所述第一输出模块，配置为根据所述显示画面匹配的显示参数，向所述显示面板输出所述显示画面的阳极复位信号；
    所述第二输出模块，配置为根据所述显示画面匹配的显示参数，向所述显示面板输出所述显示画面的数据保持信号。
  14. 一种显示装置，包括显示面板以及如权利要求10至13中任一项所述的控制装置，所述控制装置配置为向所述显示面板提供控制信号。
  15. 根据权利要求14所述的显示装置，其中，所述显示面板包括：像素阵列，所述像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动所述发光元件发光的像素电路；所述像素电路包括：多个晶体管和至少一个电容。
  16. 一种控制装置，包括：存储器和处理器；所述存储器配置为存储计算机程序，所述处理器配置为执行所述计算机程序以实现如权利要求1至9中任一项所述的控制方法。
  17. 一种非瞬态计算机可读存储介质，存储有计算机程序，所述计算机程序被执行时实现如权利要求1至9中任一项所述的控制方法。
PCT/CN2021/133244 2021-11-25 2021-11-25 显示面板的控制方法及控制装置、显示装置 WO2023092405A1 (zh)

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