WO2021012311A1 - Photomasque et substrat de réseau et leur procédé de fabrication - Google Patents

Photomasque et substrat de réseau et leur procédé de fabrication Download PDF

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Publication number
WO2021012311A1
WO2021012311A1 PCT/CN2019/099211 CN2019099211W WO2021012311A1 WO 2021012311 A1 WO2021012311 A1 WO 2021012311A1 CN 2019099211 W CN2019099211 W CN 2019099211W WO 2021012311 A1 WO2021012311 A1 WO 2021012311A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pattern
same
array substrate
glass substrate
Prior art date
Application number
PCT/CN2019/099211
Other languages
English (en)
Chinese (zh)
Inventor
陈方甫
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2021012311A1 publication Critical patent/WO2021012311A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the invention relates to the field of display technology, in particular to a photomask, an array substrate and a manufacturing method thereof.
  • LCD panel GOA Gate Driver on Array
  • gate drive on the array substrate is designed to reduce the cost of LCD panel driving consumables, and is widely used in large-size LCD panels.
  • the gate drive is The density and thickness of the metal lines in the manufacturing process of the array substrate increase, which increases the difficulty of controlling the uniformity of the gate drive in the production process.
  • the magnitude of voltage leads to differences in gate-level drive of the product and affects product quality.
  • the trend of the difference is as follows: 1The thicker the gate-level driving metal circuit of the product, the greater the difference; 2The larger the gate-level driving metal density of the product, the greater the difference. The current process cannot resolve this difference.
  • An embodiment of the present application provides a photomask, including: a main pattern area including a first sub-line pattern at one end of the main pattern area and a second sub-line pattern at the opposite end; and,
  • the first virtual circuit pattern is adjacent to the first sub circuit pattern
  • first virtual line pattern and the first sub-line pattern have the same aspect ratio and the same area
  • second virtual line pattern and the second sub-line pattern have the same aspect ratio and the same area
  • the size of the main pattern area is the same as the size of the sub glass substrate.
  • the wiring density and shape of the first virtual circuit pattern and the first sub-circuit pattern are the same; the second virtual circuit pattern is the same as the second sub-circuit pattern.
  • the trace density and shape of the pattern are the same.
  • the embodiment of the present application provides a method for preparing an array substrate using the above photomask, which includes the steps:
  • step S30 the thickness of the photoresist corresponding to the sub-line pattern is monitored.
  • step S30 the thickness of the photoresist at the edge of the array substrate is made consistent with the thickness of the intermediate photoresist.
  • step S40 the photomask and the baffle are simultaneously moved to the next sub-glass substrate to perform the yellowing process.
  • the size of the main pattern area is the same as the size of the sub glass substrate.
  • the wiring density and shape of the first virtual circuit pattern and the first sub-circuit pattern are the same; the second virtual circuit pattern is the same as the first The trace density and shape of the two sub-line patterns are the same.
  • An embodiment of the present application also provides an array substrate made by using the above photomask, including: at least two sets of sub-glass substrates arranged oppositely; the sub-glass substrate includes at least two gate drive circuit modules, and the two gates The pole drive circuit modules are located on both sides of the sub-glass substrate;
  • the edge of the array substrate is provided with gate drive circuit duplication modules corresponding to the gate drive circuit modules one-to-one.
  • the density and shape of the gate drive circuit replica module and the gate drive circuit module are the same.
  • the sub-glass substrate further includes a data line, and the data line is used to connect the two gate drive circuit modules.
  • the size of the main pattern area is the same as the size of the sub glass substrate.
  • the wiring density and shape of the first virtual circuit pattern and the first sub-circuit pattern are the same; the second virtual circuit pattern is the same as the second sub-circuit pattern.
  • the trace density and shape of the pattern are the same.
  • the beneficial effects of the present application are: a photomask, an array substrate and a manufacturing method thereof provided in the embodiments of the present application, by adding gates of the same density and shape beside the photomask gate driving circuit pattern in the new product photomask manufacturing process
  • the yellow light process of the electrode drive circuit sample pattern can improve the uniformity of the gate drive in the production process, reduce the difference in the size of the gate drive channel of the GOA process, and achieve the technical effect of improving product quality.
  • FIG. 1 is a design structure diagram of a photomask provided by an embodiment of the present invention
  • FIG. 3 is a structural diagram of an array substrate provided by an embodiment of the present invention.
  • FIG. 4 is a structural diagram of an array substrate provided by an embodiment of the prior art.
  • an embodiment of the present invention provides a design structure diagram of a new photomask.
  • the photomask includes a main pattern area 101, and the main pattern area 101 includes a first sub-line pattern 102 at one end thereof. And a second sub-line pattern 103 located at the opposite end; and a first virtual line pattern 104 located outside the main pattern area 101, adjacent to the first sub-line pattern 102; a second virtual line pattern 105, Adjacent to the second sub-line pattern 103; wherein the first virtual line pattern 104 and the first sub-line pattern 102 have the same aspect ratio and the same area, and the second virtual line pattern 105 is
  • the second sub-line patterns 103 have the same aspect ratio and the same area.
  • the size of the main pattern area 101 is the same as the size of the sub-glass substrate; the wiring density and shape of the first dummy circuit pattern 104 and the first sub-circuit pattern 102 are the same; The wiring density and shape of the two dummy circuit patterns 105 and the second sub circuit pattern 103 are the same.
  • the embodiment of the present invention provides a method for preparing an array substrate using the above photomask, which includes the steps:
  • step S30 the thickness of the photoresist corresponding to the sub-line pattern is monitored, so that the thickness of the photoresist at the edge of the array substrate is consistent with the thickness of the middle photoresist; in step S40, the photomask is The baffle moves to the next sub-glass substrate to perform the yellowing process.
  • the first step is to design a new photomask pattern of the embodiment of the present invention.
  • the new photomask design includes at least two gate drivers.
  • Circuit patterns a first gate drive circuit pattern 202 and a second gate drive circuit pattern 203, the two gate drive circuit patterns are respectively located on both sides of the main pattern area 201 of the new photomask; wherein, the new photomask There are gate drive circuit sample patterns corresponding to the gate drive circuit pattern one-to-one on the edge of the, the first gate drive circuit sample pattern 204, the second gate drive circuit sample pattern 205; the first gate drive The wiring density and shape of the circuit sample pattern 204 and the second gate driving circuit sample pattern 205 are the same as those of the first gate driving circuit pattern 202 and the second gate driving circuit pattern 203.
  • the second step is to carry out the exposure process. Place the above-mentioned new mask on the photoresist layer of any row and any piece of sub-glass substrate, and align the edge of the main pattern area of the mask with the edge of the sub-glass substrate, and use a baffle to block the sub-glass
  • the gate driving circuit sample pattern 206 between the substrates can achieve the effect of the edge load and the intermediate load of the array substrate being equivalent.
  • the third step is to monitor the thickness of the photoresist corresponding to the gate drive circuit pattern and the sample pattern of the gate drive circuit so that the thickness of the photoresist at the edges 207 and 208 of the array substrate is consistent with the thickness of the photoresist at the middle 209 of the array substrate .
  • the fourth step is the etching process.
  • the pattern of the photoresist after exposure and development (take the positive photoresist as an example) is transferred to the metal film layer or non-metal film layer under the photoresist for circuit molding to achieve the goal of uniform gate channel size.
  • etching methods dry etching and wet etching.
  • the array substrate is made of the above-mentioned photomask and includes: at least two sets of sub-glass substrates arranged oppositely; the sub-glass substrate 301 includes at least two Two gate drive circuit modules, a first gate drive circuit module 302, a second gate drive circuit module 303, the two gate drive circuit modules are located on both sides of the sub glass substrate; wherein, the array substrate
  • the gate drive circuit duplication module corresponding to the gate drive circuit module one-to-one is provided on the edge of, and the density and shape of the gate drive circuit duplication module 304 and the gate drive circuit module 302 are the same;
  • the sub-glass substrate further includes a data line 305, which is used to connect the two gate drive circuit modules.
  • the size of the array substrate is not fixed. It can be two sets of opposed sub-glass substrates, each with three pieces; it can also be multiple groups, and each group can also have multiple sub-glass substrates; A gate drive circuit duplication module is added next to the edge gate drive circuit module of the array substrate, so that the load on the edge 306 and edge 307 of the array substrate is equivalent to the load on the middle 308, and the thickness of the edge photoresist is consistent with the thickness of the middle photoresist. To achieve the goal of the same size of the gate channel and improve product quality.
  • the array substrate includes at least two sets of sub-glass substrates arranged oppositely; the sub-glass substrate 401 includes at least two The gate drive circuit module, the first gate drive circuit module 402, the second gate drive circuit module 403, the two gate drive circuit modules are located on both sides of the small board; the sub glass substrate 401 also includes The data line 404 is used to connect the first gate drive circuit module 402 and the second gate drive circuit module 403.
  • the load on the edge 405 and the edge 406 of the array substrate is inconsistent with the load on the middle 407 of the array substrate, resulting in a difference in the channel size on the left and right sides of the gate driver device, thereby affecting the voltage charged into the pixel, resulting in a product
  • the difference in gate drive affects product quality.
  • the embodiment of the present invention provides gate drive circuit replication modules of the same density and thickness to improve the uniformity of the gate drive in the production process, which effectively solves the problems of the prior art. defect.
  • the embodiment of the present invention provides a photomask, an array substrate and a manufacturing method thereof.
  • gate drivers of the same density and shape are added beside the photomask gate drive circuit pattern.
  • the circuit sample pattern is exposed to the process, which can improve the uniformity of the gate drive in the production process, reduce the difference in the size of the gate drive channel of the GOA process, and achieve the technical effect of improving product quality. It solves the problem of the prior art array substrate.
  • the increase in metal line density and thickness increases the difficulty of gate drive uniformity control in the production process, resulting in differences in the channel sizes on the left and right sides of the gate drive device, which affects the voltage charged into the pixel, resulting in product gate drive differences , Technical issues affecting product quality.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

L'invention concerne un photomasque, comprenant : une région de motif principal comprenant un premier motif de sous-circuit positionné à une extrémité de celui-ci et un second motif de sous-circuit positionné à l'autre extrémité de celui-ci ; un premier motif de circuit virtuel adjacent au premier motif de sous-circuit ; et un second motif de circuit virtuel adjacent au second motif de sous-circuit, le premier motif de circuit virtuel et le premier motif de sous-circuit ayant le même rapport d'aspect et des surfaces équivalentes, et le second motif de circuit virtuel et le second motif de sous-circuit ayant le même rapport d'aspect et des surfaces équivalentes.
PCT/CN2019/099211 2019-07-22 2019-08-05 Photomasque et substrat de réseau et leur procédé de fabrication WO2021012311A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910659215.7A CN110398848A (zh) 2019-07-22 2019-07-22 一种光罩、阵列基板及其制作方法
CN201910659215.7 2019-07-22

Publications (1)

Publication Number Publication Date
WO2021012311A1 true WO2021012311A1 (fr) 2021-01-28

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Application Number Title Priority Date Filing Date
PCT/CN2019/099211 WO2021012311A1 (fr) 2019-07-22 2019-08-05 Photomasque et substrat de réseau et leur procédé de fabrication

Country Status (2)

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CN (1) CN110398848A (fr)
WO (1) WO2021012311A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043006A (zh) * 2006-03-23 2007-09-26 中华映管股份有限公司 薄膜电晶体的制造方法
TW200924062A (en) * 2007-11-28 2009-06-01 Au Optronics Corp Photo-mask and thin-film transistor substrate
US20090258302A1 (en) * 2008-04-10 2009-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Sub-resolution assist feature of a photomask

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601177B1 (ko) * 2000-02-10 2006-07-13 삼성전자주식회사 액정 표시 장치용 박막 트랜지스터 기판 및 그의 제조 방법
CN100339940C (zh) * 2003-08-28 2007-09-26 友达光电股份有限公司 薄膜电晶体阵列基板及其微影制造方法与光罩设计结构
CN100561339C (zh) * 2007-12-18 2009-11-18 友达光电股份有限公司 光掩模及薄膜晶体管基板的制造方法
CN203838448U (zh) * 2014-05-16 2014-09-17 北京京东方光电科技有限公司 显示基板母板、显示面板和显示装置
CN107329341B (zh) * 2017-08-22 2019-12-24 深圳市华星光电半导体显示技术有限公司 Goa阵列基板及tft显示大板
CN107678219A (zh) * 2017-10-23 2018-02-09 深圳市华星光电技术有限公司 液晶显示母板
TWI637217B (zh) * 2017-10-27 2018-10-01 友達光電股份有限公司 顯示裝置
CN109375441B (zh) * 2018-12-21 2022-03-01 信利半导体有限公司 基板走线结构和走线制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043006A (zh) * 2006-03-23 2007-09-26 中华映管股份有限公司 薄膜电晶体的制造方法
TW200924062A (en) * 2007-11-28 2009-06-01 Au Optronics Corp Photo-mask and thin-film transistor substrate
US20090258302A1 (en) * 2008-04-10 2009-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Sub-resolution assist feature of a photomask

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