WO2021008136A1 - 先进工艺和低电压下的集成电路统计时序分析方法 - Google Patents

先进工艺和低电压下的集成电路统计时序分析方法 Download PDF

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WO2021008136A1
WO2021008136A1 PCT/CN2020/076447 CN2020076447W WO2021008136A1 WO 2021008136 A1 WO2021008136 A1 WO 2021008136A1 CN 2020076447 W CN2020076447 W CN 2020076447W WO 2021008136 A1 WO2021008136 A1 WO 2021008136A1
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delay
circuit
under
input signal
step input
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曹鹏
杨泰
郭静静
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Southeast University
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

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  • the invention relates to the time sequence analysis of an integrated circuit manufactured by an advanced technology under low voltage, and in particular to a statistical time sequence analysis method of an integrated circuit under an advanced technology and low voltage.
  • circuit design technology poses severe challenges. Due to equipment accuracy or process limitations in the integrated circuit manufacturing process, process parameters such as transistor size, gate oxide thickness, and doping concentration inevitably deviate from their nominal values, making the physical characteristics of integrated circuits such as circuit timing (ie, circuit delay) vary The fluctuation.
  • the circuit timing becomes more sensitive to the fluctuation of the process parameters, and the fluctuation of the process parameters causes the circuit timing fluctuation to increase significantly; on the other hand, under low voltage, the integrated circuit
  • the current characteristics and even the timing characteristics have an exponential relationship with the process parameters, which further causes the circuit timing fluctuations to increase, and the distribution is non-Gaussian.
  • the traditional integrated circuit static timing analysis method is based on the nominal value of circuit timing, and evaluates the statistical distribution range of circuit timing by multiplying by a specific proportional coefficient.
  • the scale factor varies with the cell type, size, load, and process angle in the circuit. Improper setting may cause timing violations in the case of integrated circuit delay fluctuations, that is, fail to meet the predetermined design function and performance requirements, or cause excessive timing margins. Large, in order to accommodate the extreme conditions of the circuit resulting in reduced energy efficiency.
  • the object of the present invention is to provide an integrated circuit statistical time sequence analysis method under advanced technology and low voltage, which can more accurately analyze the circuit delay distribution under the fluctuation of process parameters.
  • the advanced technology and low-voltage integrated circuit statistical time sequence analysis method refers to the process below 40nm, the low voltage refers to the operating voltage of the integrated circuit is lower than the transistor threshold voltage 0.35V; the integrated circuit
  • the circuit path includes at least two stages of circuit units; the method includes the following steps:
  • S2 Perform Monte Carlo simulation on the circuit units at all levels in the circuit path under step input signals, and calculate the mean, variance and skewness of the delay statistics from the statistical sample set obtained by the simulation;
  • S5 Calculate the probability density function, the maximum value and the minimum value of the delay statistics of the circuit path under the step input signal.
  • step S1 specifically includes the following steps:
  • t di represents the nominal value of the delay under the non-step input signal of the i-th circuit unit in the circuit path
  • ⁇ ((i-1) represents the coefficient of the i-1th stage circuit unit, 2 ⁇ i ⁇ n, n means The total number of circuit units in the circuit path;
  • the random variable t dr represents the delay of the r-th stage circuit unit under the step input signal of the circuit path.
  • the random variable represents the delay of the nth level circuit unit under the step input signal
  • ⁇ j represents the coefficient of the jth level circuit unit
  • step S2 Monte Carlo simulation is performed on each level of circuit unit in the circuit path under the step input signal, and the statistical sample set obtained by the simulation is calculated by formula (3) to obtain the Mean value, variance and skewness of delay statistics under step input signal:
  • E(x r ) represents the average value of the delay statistics of the r-th stage circuit unit under the step input signal
  • D(x r ) represents the delay of the r-th stage circuit unit under the step input signal.
  • the variance of the statistical value at time, S(x r ) represents the skewness of the delay statistical value of the r-th stage circuit unit under the step input signal
  • 1 ⁇ r ⁇ n, n represents the total number of circuit units in the circuit path
  • random variable x r represents the delay of the r-th circuit unit under step input
  • X r,k represents the k-th delayed sample data of the r-th circuit unit under step input
  • the mean value, variance and skewness of the delay statistics of the circuit path under the step input signal are calculated by formula (4):
  • E(y) represents the mean value of y
  • D(y) represents the variance of y
  • S(y) represents the skewness of y
  • E(x r ) represents the mean value of x r
  • D(x r ) represents the variance of x r
  • Means The mean of, Means The mean of, Means The variance of, 1 ⁇ r ⁇ n, a j 1+ ⁇ j
  • ⁇ j represents the coefficient of the j-th stage circuit unit, 1 ⁇ j ⁇ n-1
  • n represents the total number of circuit units in the circuit path
  • the distribution parameters in the step S4 include the position parameter ⁇ , the scale parameter ⁇ and the first shape parameter ⁇ , which are calculated by formula (6):
  • the random variable y represents the delay of the circuit path under the step input
  • ⁇ p represents the p-order moment of origin of the random variable y
  • 1 ⁇ p ⁇ 3 ⁇ represents the second shape parameter
  • E(y) represents the average value of the delay statistics of the circuit path under the step input signal
  • D(y) represents the variance of the delay statistics of the circuit path under the step input signal
  • S(y) represents the circuit path in the The skewness of the delay statistical value under the step input signal
  • E(y 2 ) represents the second-order moment of origin of the random variable y
  • E(y 3 ) represents the third-order moment of origin of the random variable y.
  • the probability density function of the delay statistics of the circuit path is calculated by formula (7):
  • f LSN (y) represents the probability density function of the statistical value of the circuit path delay
  • the corresponding solution y is the maximum value of the circuit path delay statistics;
  • the corresponding solution y is the minimum value of the circuit path delay statistics;
  • F LSN (y) represents the cumulative distribution function of the circuit path delay statistics, Calculated by formula (9);
  • the present invention discloses an integrated circuit statistical time sequence analysis method under advanced technology and low voltage, which is based on the integrated circuit delay and technology under low voltage by simulating and modeling the process parameter fluctuation of integrated circuits under advanced technology.
  • the relationship between the parameters establishes a circuit timing statistical model, and analyzes the maximum delay and minimum delay in the case of IC timing fluctuations.
  • it can more accurately analyze the delay distribution of the circuit under the fluctuation of the process parameters, which is of great significance to the advanced technology and integrated circuit design under low voltage.
  • FIG. 1 is a schematic diagram of the influence of the distribution parameters of the LSN distribution on its probability density function in a specific embodiment of the present invention
  • Figure 2 is a schematic diagram of a buffer chain in a specific embodiment of the present invention.
  • Fig. 3 is a curve of path delay probability density function in a specific embodiment of the present invention.
  • the advanced process refers to a process below 40 nm
  • the low voltage refers to the operating voltage of the integrated circuit being lower than the transistor threshold voltage 0.35V.
  • the circuit path of the integrated circuit includes at least two stages of circuit units; for example, the integrated circuit may be a buffer chain, as shown in Fig. 2, in which an inverter is used as a stage of circuit unit. This method includes the following steps:
  • S2 Monte Carlo simulation is performed on all levels of circuit units in the circuit path under step input signals, and the mean, variance and skewness of the delay statistics are calculated on the statistical sample set obtained by the simulation; for example: delay to the circuit path Perform 10,000 Monte Carlo simulations. This step is to compare the fitting results with the simulation results. Perform 10,000 Monte Carlo simulations for each level of circuit unit in the circuit path under step input signals to obtain the delay at this time. Time simulation results, sort the 10,000 delay simulation results from small to large, consider that the 13th delay simulation result is the actual minimum delay of the circuit path, and the 9987th delay simulation result is the actual maximum delay of the circuit path;
  • step S4 According to step S3, the mean value, variance and skewness of the delay statistics of the circuit path under the step input signal are fitted to the distribution parameters of the circuit path delay; for example: the solid line in Figure 1 is a certain obeyed pair
  • PDF probability density function
  • S5 Calculate the probability density function, the maximum value and the minimum value of the delay statistics of the circuit path under the step input signal.
  • Step S1 specifically includes the following steps:
  • t di represents the nominal value of the delay under the non-step input signal of the i-th circuit unit in the circuit path
  • ⁇ ((i-1) represents the coefficient of the i-1th stage circuit unit, 2 ⁇ i ⁇ n, n means The total number of circuit units in the circuit path;
  • the random variable t dr represents the delay of the r-th stage circuit unit under the step input signal of the circuit path.
  • the random variable represents the delay of the nth level circuit unit under the step input signal
  • ⁇ j represents the coefficient of the jth level circuit unit
  • step S2 m Monte Carlo simulations are performed on each level of the circuit unit in the circuit path under the step input signal, and the statistical sample set obtained by the simulation is calculated by formula (3) to obtain the step input signal of each level of circuit unit
  • the mean, variance and skewness of the delay statistics under:
  • E(x r ) represents the average value of the delay statistics of the r-th stage circuit unit under the step input signal
  • D(x r ) represents the delay of the r-th stage circuit unit under the step input signal.
  • the variance of the statistical value at time, S(x r ) represents the skewness of the delay statistical value of the r-th stage circuit unit under the step input signal
  • 1 ⁇ r ⁇ n, n represents the total number of circuit units in the circuit path
  • random variable x r represents the delay of the r-th circuit unit under step input
  • X r,k represents the k-th delayed sample data of the r-th circuit unit under step input
  • step S3 the mean value, variance and skewness of the delay statistics of the circuit path under the step input signal are calculated by formula (4):
  • E(y) represents the mean value of y
  • D(y) represents the variance of y
  • S(y) represents the skewness of y
  • E(x r ) represents the mean value of x r
  • D(x r ) represents the variance of x r
  • Means The mean of, Means The mean of, Means The variance of, 1 ⁇ r ⁇ n, a j 1+ ⁇ j
  • ⁇ j represents the coefficient of the j-th stage circuit unit, 1 ⁇ j ⁇ n-1
  • n represents the total number of circuit units in the circuit path
  • the distribution parameters in step S4 include the position parameter ⁇ , the scale parameter ⁇ and the first shape parameter ⁇ , which are calculated by formula (6):
  • the random variable y represents the delay of the circuit path under the step input
  • ⁇ p represents the p-order moment of origin of the random variable y
  • 1 ⁇ p ⁇ 3 ⁇ represents the second shape parameter
  • E(y) represents the average value of the delay statistics of the circuit path under the step input signal
  • D(y) represents the variance of the delay statistics of the circuit path under the step input signal
  • S(y) represents the circuit path in the The skewness of the delay statistical value under the step input signal
  • E(y 2 ) represents the second-order moment of origin of the random variable y
  • E(y 3 ) represents the third-order moment of origin of the random variable y.
  • step S5 the probability density function of the delay statistics of the circuit path is calculated by formula (7):
  • f LSN (y) represents the probability density function of the statistical value of the circuit path delay
  • Figure 3 is the path delay probability density function curve when n takes different values, n represents the total number of circuit units in the circuit path, "MC simulation PDF” represents the probability density histogram of the circuit path delay result obtained by Monte Carlo simulation , Used to compare with the fitting results, the histogram is drawn by the hist function of MATLAB; "MC simulation fitting PDF” represents the probability density distribution curve of the circuit path delay number results obtained by Monte Carlo simulation, The curve is fitted by the ksdensity function of MATLAB, which is represented by the solid line marked with "+” in the figure; “LSN distribution fitting PDF” means the probability density distribution curve obtained by fitting the statistical model of the method of the present invention, in the figure It is indicated by a solid line without a mark.

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Abstract

本发明公开了一种先进工艺和低电压下的集成电路统计时序分析方法，通过对先进工艺下集成电路的工艺参数波动情况进行仿真建模，基于低电压下集成电路延时与工艺参数间的关系建立电路时序统计模型，分析集成电路时序波动情况下的最大延时和最小延时。与传统的静态时序分析方法相比，能够更准确的分析工艺参数波动下的电路延时分布情况，对于先进工艺和低电压下集成电路设计具有重要意义。

Description

先进工艺和低电压下的集成电路统计时序分析方法 技术领域
本发明涉及先进工艺制造的集成电路在低电压下的时序分析，特别是涉及一种先进工艺和低电压下的集成电路统计时序分析方法。
背景技术
随着集成电路规模与计算能力的不断增长，能耗逐渐成为制约各类计算系统包括物联网、嵌入式设备、移动终端、超算与数据中心等发展的一个重要限制。发展高能效集成电路技术，是解决计算系统能耗问题的一个重要手段。传统的集成电路通过追求先进工艺尺寸以及供电电压的等比例缩放来满足降低芯片能耗密度的要求，然而随着摩尔定律与Dennard Scaling定律发展到极限，功耗大幅度降低的工艺红利正在逐渐消失。传统的发展路线已经无法维持。以往几乎每一代新制造工艺的出现都意味着供电电压的等比例缩放，因此能够带来本征能效(ICE)的阶跃式发展以适应芯片计算能力与规模的增长，但在130nm工艺之后，工艺的演进已经很难保证工作电压的大幅下降，其亚线性的增长趋势使得计算系统能效跟不上规模的增长。与此同时，常用的低功耗技术如动态电压调制(DVFS)、功率门控(Power Gating)、多阈值器件、时钟门控等，也随着工作电压与阈值电压的逼近，优化空间变得相对有限。因此，如何进一步降低工作电压幅度，实现能效阶跃式提升成为计算系统亟需解决的问题之一。
近阈值(Near-Threshold)集成电路设计通过将芯片或电路的供电电压降低到接近晶体管阈值电压水平，能取得大幅度的能效降低，被认为是未来提升一个数量级计算能效的设计技术。与传统的高能效技术关注特定的功耗组成部份、或采用针对应用的定向优化思路相比，近阈值设计降低功耗原理基于功耗-电压平方法则(P＝CV 2F)，能够从电路工作原理角度对集成电路能效实现更显著的提升。
然而，伴随着先进工艺和以近阈值设计为代表的低电压技术的兴起以及在集成电路性能和能效方面取得的显著优势，集成电路工艺参数波动对电路时序的影响愈发凸显而不可忽视，对集成电路设计技术提出了严峻挑战。集成电路制造过程中由于设备精度或工艺限制导致晶体管尺寸、栅氧化层厚度、掺杂浓度等工艺参数不可避免的偏离其标称值，使得集成电路物理特性例如电路时序(即电路延时)随之波动。一方面，在先进工艺下，随着集成电路制程线宽的不断降低，电路时序对工艺参数波动愈发敏感，工艺参数波动导致电路时序波动显著增加；另一方面，在低电 压下，集成电路电流特性乃至时序特征与工艺参数呈指数关系，进一步导致电路时序波动加剧，且呈非高斯分布。
为了分析先进工艺和低电压设计中工艺参数波动影响下的电路时序，传统的集成电路静态时序分析方法以电路时序标称值为基础，通过乘以特定的比例系数评估电路时序的统计分布范围。显然，该比例系数随着电路中单元类型、尺寸、负载和工艺角变化，设置不当要么导致集成电路延时波动情况下时序违规，即无法满足预定设计功能和性能要求，要么导致时序裕量过大，为迁就电路极端情况导致能效降低。
发明内容
发明目的：本发明的目的是提供一种先进工艺和低电压下的集成电路统计时序分析方法，能够更准确地分析工艺参数波动下的电路延时分布情况。
技术方案：为达到此目的，本发明采用以下技术方案：
本发明所述的先进工艺和低电压下的集成电路统计时序分析方法，所述先进工艺是指40nm以下工艺，低电压是指集成电路的工作电压低于晶体管阈值电压0.35V；所述集成电路的电路路径中包含至少两级电路单元；所述方法包括以下步骤：
S1：根据电路路径中各级电路单元在非阶跃输入信号下的延时标称值与本级电路单元在阶跃输入信号下的延时标称值及前一级电路单元在阶跃输入信号下的延时标称值之间的线性关系，求得各级电路单元的系数，再根据各级电路单元的系数得出电路路径延时随机变量；
S2：对电路路径中各级电路单元在阶跃输入信号下进行蒙特卡洛仿真，对仿真获得的统计样本集计算延时统计值的均值、方差和偏度；
S3：根据步骤S2得到的电路路径中各级电路单元在阶跃输入信号下的延时统计值的均值、方差和偏度计算电路路径在阶跃输入信号下的延时统计值的均值、方差和偏度；
S4：根据步骤S3得到的电路路径在阶跃输入信号下的延时统计值的均值、方差和偏度拟合电路路径延时的分布参数；
S5：计算阶跃输入信号下电路路径的延时统计值的概率密度函数、最大值和最小值。
进一步，所述步骤S1具体包括以下步骤：
S11：根据式(1)所示的线性关系求得各级电路单元的系数：
Figure PCTCN2020076447-appb-000001
式(1)中，t di表示电路路径中的第i级电路单元非阶跃输入信号下的延时标称值，
Figure PCTCN2020076447-appb-000002
表示电路路径中的第i级电路单元阶跃输入信号下的延时标称值，
Figure PCTCN2020076447-appb-000003
表示电路路径中的第i-1级电路单元阶跃输入信号下的延时标称值，η ((i-1)表示第i-1级电路单元的系数，2≤i≤n，n表示电路路径中电路单元的总数；
S12：将η ((i-1)代入到式(2)中，求得电路路径延时随机变量t_path：
Figure PCTCN2020076447-appb-000004
式(2)中，随机变量t dr表示电路路径在阶跃输入信号下第r级电路单元的延时，随机变量
Figure PCTCN2020076447-appb-000005
表示阶跃输入信号下第n级电路单元的延时，η j表示第j级电路单元的系数，随机变量
Figure PCTCN2020076447-appb-000006
表示阶跃输入信号下第j级电路单元的延时。
进一步，所述步骤S2中，对电路路径中各级电路单元在阶跃输入信号下均进行m次蒙特卡洛仿真，对仿真获得的统计样本集通过式(3)计算得到各级电路单元在阶跃输入信号下的延时统计值的均值、方差和偏度：
Figure PCTCN2020076447-appb-000007
Figure PCTCN2020076447-appb-000008
Figure PCTCN2020076447-appb-000009
式(3)中，E(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的均值，D(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的方差，S(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的偏度，1≤r≤n，n表示电路路径中电路单元的总数，随机变量x r表示第r级电路单元在阶跃输入下的延时，X r,k表示第r级电路单元在阶跃输入下的第k个延时样本数据，
Figure PCTCN2020076447-appb-000010
表示随机变量x r的三阶原点矩，
Figure PCTCN2020076447-appb-000011
进一步，所述步骤S3中，电路路径在阶跃输入信号下的延时统计值的均值、方差和偏度通过式(4)计算得到：
Figure PCTCN2020076447-appb-000012
式(4)中，y＝t_path表示阶跃输入信号下电路路径的延时随机变量，E(y)表示y的均值，D(y)表示y的方差，S(y)表示y的偏度，
Figure PCTCN2020076447-appb-000013
表示阶跃输入信号下第r级电路单元的延时随机变量，E(x r)表示x r的均值，D(x r)表示x r的方差，
Figure PCTCN2020076447-appb-000014
表示
Figure PCTCN2020076447-appb-000015
的均值，
Figure PCTCN2020076447-appb-000016
表示
Figure PCTCN2020076447-appb-000017
的均值，
Figure PCTCN2020076447-appb-000018
表示
Figure PCTCN2020076447-appb-000019
的方差，1≤r≤n，a j＝1+η j，η j表示第j级电路单元的系数，1≤j≤n-1，n表示电路路径中电路单元的总数，a n＝1，μ＝-E(y)；
公式(4)中第三个偏度表达式进一步展开写成公式(5)：
Figure PCTCN2020076447-appb-000020
其中，t s由表达式
Figure PCTCN2020076447-appb-000021
约束，1≤s≤n+1；对于1≤q≤n-1，a q＝1+η q，η q表示第q级电路单元的系数；对于q＝n，，a q＝1；x q表示阶跃输入信号下第q级电路单元的延时随机变量。
进一步，所述步骤S4中的分布参数包括位置参数ε、比例参数ω和第一形状参数λ，通过式(6)计算得到：
E(y)＝α 1
D(y)＝E(y 2)-(E(y)) 2,E(y 2)＝α 2        (6)
Figure PCTCN2020076447-appb-000022
式(6)中，随机变量y表示电路路径在阶跃输入下的延时，α p表示随机变量 y的p阶原点矩，1≤p≤3，
Figure PCTCN2020076447-appb-000023
β表示第二形状参数，
Figure PCTCN2020076447-appb-000024
E(y)表示电路路径在阶跃输入信号下的延时统计值的均值，D(y)表示电路路径在阶跃输入信号下的延时统计值的方差，S(y)表示电路路径在阶跃输入信号下的延时统计值的偏度，E(y 2)表示随机变量y的二阶原点矩，E(y 3)表示随机变量y的三阶原点矩。
进一步，所述步骤S5中，电路路径的延时统计值的概率密度函数通过式(7)计算得到：
Figure PCTCN2020076447-appb-000025
式(7)中，f LSN(y)表示电路路径延时统计值的概率密度函数，
Figure PCTCN2020076447-appb-000026
电路路径的延时统计值的最大值和最小值通过式(8)计算得到：
Figure PCTCN2020076447-appb-000027
式(8)中，
Figure PCTCN2020076447-appb-000028
令
Figure PCTCN2020076447-appb-000029
对应的解y为电路路径延时统计值的最大值；令
Figure PCTCN2020076447-appb-000030
对应的解y为电路路径延时统计值的最小值；F LSN(y)表示电路路径延时统计值的累计分布函数，
Figure PCTCN2020076447-appb-000031
通过式(9)计算得到；
Figure PCTCN2020076447-appb-000032
式(9)中，
Figure PCTCN2020076447-appb-000033
A＝λ。
有益效果：本发明公开了一种先进工艺和低电压下的集成电路统计时序分析方法，通过对先进工艺下集成电路的工艺参数波动情况进行仿真建模，基于低电压下集成电路延时与工艺参数间的关系建立电路时序统计模型，分析集成电路时序波动情况下的最大延时和最小延时。与传统的静态时序分析方法相比，能够更准确的 分析工艺参数波动下的电路延时分布情况，对于先进工艺和低电压下集成电路设计具有重要意义。
附图说明
图1为本发明具体实施方式中LSN分布的分布参数对其概率密度函数的影响的示意图；
图2为本发明具体实施方式中缓冲器链的示意图；
图3为本发明具体实施方式中路径延时概率密度函数曲线；
图3(a)为n＝2时的路径延时概率密度函数曲线；
图3(b)为n＝4时的路径延时概率密度函数曲线；
图3(c)为n＝12时的路径延时概率密度函数曲线；
图3(d)为n＝15时的路径延时概率密度函数曲线。
具体实施方式
下面结合具体实施方式对本发明的技术方案作进一步的介绍。
本具体实施方式公开了一种先进工艺和低电压下的集成电路统计时序分析方法，先进工艺是指40nm以下工艺，低电压是指集成电路的工作电压低于晶体管阈值电压0.35V。集成电路的电路路径中包含至少两级电路单元；例如：集成电路可以是缓冲器链，如图2所示，其中一个反相器作为一级电路单元。本方法包括以下步骤：
S1：根据电路路径中各级电路单元在非阶跃输入信号下的延时标称值与本级电路单元在阶跃输入信号下的延时标称值及前一级电路单元在阶跃输入信号下的延时标称值之间的线性关系，求得各级电路单元的系数，再根据各级电路单元的系数得出电路路径延时随机变量；
S2：对电路路径中各级电路单元均在阶跃输入信号下进行蒙特卡洛仿真，对仿真获得的统计样本集计算延时统计值的均值、方差和偏度；例如：对电路路径延时进行10000次蒙特卡洛仿真，这一步是为了拟合结果能够与仿真结果进行对比；对电路路径中每一级电路单元在阶跃输入信号下均进行10000次蒙特卡洛仿真获得此时的延时仿真结果，将这10000个延时仿真结果从小到大排序，认为第13个延时仿真结果是电路路径的实际最小延时，第9987个延时仿真结果是电路路径的实际最大延时；
S3：根据步骤S2得到的电路路径中各级电路单元在阶跃输入信号下的延时统计值的均值、方差和偏度计算电路路径在阶跃输入信号下的延时统计值的均值、方 差和偏度；
S4：根据步骤S3得到的电路路径在阶跃输入信号下的延时统计值的均值、方差和偏度拟合电路路径延时的分布参数；例如：图1中的实线是某个服从对数斜正态(LSN)分布的随机变量的概率密度函数(PDF)曲线，分别单独改变该分布的位置参数ε、比例参数ω和第一形状参数λ，得到三条新的概率密度函数曲线，从而可以发现三个参数对于概率密度函数的影响；
S5：计算阶跃输入信号下电路路径的延时统计值的概率密度函数、最大值和最小值。
步骤S1具体包括以下步骤：
S11：根据式(1)所示的线性关系求得各级电路单元的系数：
Figure PCTCN2020076447-appb-000034
式(1)中，t di表示电路路径中的第i级电路单元非阶跃输入信号下的延时标称值，
Figure PCTCN2020076447-appb-000035
表示电路路径中的第i级电路单元阶跃输入信号下的延时标称值，
Figure PCTCN2020076447-appb-000036
表示电路路径中的第i-1级电路单元阶跃输入信号下的延时标称值，η ((i-1)表示第i-1级电路单元的系数，2≤i≤n，n表示电路路径中电路单元的总数；
S12：将η ((i-1)代入到式(2)中，求得电路路径延时随机变量t_path：
Figure PCTCN2020076447-appb-000037
式(2)中，随机变量t dr表示电路路径在阶跃输入信号下第r级电路单元的延时，随机变量
Figure PCTCN2020076447-appb-000038
表示阶跃输入信号下第n级电路单元的延时，η j表示第j级电路单元的系数，随机变量
Figure PCTCN2020076447-appb-000039
表示阶跃输入信号下第j级电路单元的延时。
步骤S2中，对电路路径中各级电路单元在阶跃输入信号下均进行m次蒙特卡洛仿真，对仿真获得的统计样本集通过式(3)计算得到各级电路单元在阶跃输入信号下的延时统计值的均值、方差和偏度：
Figure PCTCN2020076447-appb-000040
Figure PCTCN2020076447-appb-000041
Figure PCTCN2020076447-appb-000042
式(3)中，E(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的均值，D(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的方差，S(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的偏度，1≤r≤n，n表示电路路径中电路单元的总数，随机变量x r表示第r级电路单元在阶跃输入下的延时，X r,k表示第r级电路单元在阶跃输入下的第k个延时样本数据，
Figure PCTCN2020076447-appb-000043
表示随机变量x r的三阶原点矩，
Figure PCTCN2020076447-appb-000044
步骤S3中，电路路径在阶跃输入信号下的延时统计值的均值、方差和偏度通过式(4)计算得到：
Figure PCTCN2020076447-appb-000045
式(4)中，y＝t_path表示阶跃输入信号下电路路径的延时随机变量，E(y)表示y的均值，D(y)表示y的方差，S(y)表示y的偏度，
Figure PCTCN2020076447-appb-000046
表示阶跃输入信号下第r级电路单元的延时随机变量，E(x r)表示x r的均值，D(x r)表示x r的方差，
Figure PCTCN2020076447-appb-000047
表示
Figure PCTCN2020076447-appb-000048
的均值，
Figure PCTCN2020076447-appb-000049
表示
Figure PCTCN2020076447-appb-000050
的均值，
Figure PCTCN2020076447-appb-000051
表示
Figure PCTCN2020076447-appb-000052
的方差，1≤r≤n，a j＝1+η j，η j表示第j级电路单元的系数，1≤j≤n-1，n表示电路路径中电路单元的总数，a n＝1，μ＝-E(y)；
公式(4)中第三个偏度表达式进一步展开写成公式(5)：
Figure PCTCN2020076447-appb-000053
其中，t s由表达式
Figure PCTCN2020076447-appb-000054
约束，1≤s≤n+1；对于1≤q≤n-1，a q＝1+η q，η q 表示第q级电路单元的系数；对于q＝n，，a q＝1；x q表示阶跃输入信号下第q级电路单元的延时随机变量。
步骤S4中的分布参数包括位置参数ε、比例参数ω和第一形状参数λ，通过式(6)计算得到：
E(y)＝α 1
D(y)＝E(y 2)-(E(y)) 2,E(y 2)＝α 2       (6)
Figure PCTCN2020076447-appb-000055
式(6)中，随机变量y表示电路路径在阶跃输入下的延时，α p表示随机变量y的p阶原点矩，1≤p≤3，
Figure PCTCN2020076447-appb-000056
β表示第二形状参数，
Figure PCTCN2020076447-appb-000057
E(y)表示电路路径在阶跃输入信号下的延时统计值的均值，D(y)表示电路路径在阶跃输入信号下的延时统计值的方差，S(y)表示电路路径在阶跃输入信号下的延时统计值的偏度，E(y 2)表示随机变量y的二阶原点矩，E(y 3)表示随机变量y的三阶原点矩。
步骤S5中，电路路径的延时统计值的概率密度函数通过式(7)计算得到：
Figure PCTCN2020076447-appb-000058
式(7)中，f LSN(y)表示电路路径延时统计值的概率密度函数，
Figure PCTCN2020076447-appb-000059
电路路径的延时统计值的最大值和最小值通过式(8)计算得到：
Figure PCTCN2020076447-appb-000060
式(8)中，
Figure PCTCN2020076447-appb-000061
令
Figure PCTCN2020076447-appb-000062
对应的解y为电路路径延时统计值的最大值；令
Figure PCTCN2020076447-appb-000063
对应的解y为电路路径延时统计值的最小值；F LSN(y)表示电路路径延时统计值的累计分布函数，
Figure PCTCN2020076447-appb-000064
通过式(9)计算得到；
Figure PCTCN2020076447-appb-000065
式(9)中，
Figure PCTCN2020076447-appb-000066
A＝λ。
图3为n取不同值时的路径延时概率密度函数曲线，n表示电路路径中电路单元的总数，“MC仿真PDF”表示由蒙特卡洛仿真得到的电路路径延时结果的概率密度柱状图，用于和拟合结果进行对比，该柱状图由MATLAB的hist函数绘制；“MC仿真拟合PDF”表示由蒙特卡洛仿真得到的电路路径延时数结果合而来的概率密度分布曲线，该曲线由MATLAB的ksdensity函数拟合，由图中标有“+”标记的实线表示；“LSN分布拟合PDF”表示用本发明方法的统计模型拟合得到的概率密度分布曲线，在图中用不带标记的实线表示。

Claims (6)

  1. 先进工艺和低电压下的集成电路统计时序分析方法，其特征在于：所述先进工艺是指40nm以下工艺，低电压是指集成电路的工作电压低于晶体管阈值电压0.35V；所述集成电路的电路路径中包含至少两级电路单元；所述方法包括以下步骤：
    S1：根据电路路径中各级电路单元在非阶跃输入信号下的延时标称值与本级电路单元在阶跃输入信号下的延时标称值及前一级电路单元在阶跃输入信号下的延时标称值之间的线性关系，求得各级电路单元的系数，再根据各级电路单元的系数得出电路路径延时随机变量；
    S2：对电路路径中各级电路单元在阶跃输入信号下进行蒙特卡洛仿真，对仿真获得的统计样本集计算延时统计值的均值、方差和偏度；
    S3：根据步骤S2得到的电路路径中各级电路单元在阶跃输入信号下的延时统计值的均值、方差和偏度计算电路路径在阶跃输入信号下的延时统计值的均值、方差和偏度；
    S4：根据步骤S3得到的电路路径在阶跃输入信号下的延时统计值的均值、方差和偏度拟合电路路径延时的分布参数；
    S5：计算阶跃输入信号下电路路径的延时统计值的概率密度函数、最大值和最小值。
  2. 根据权利要求1所述的先进工艺和低电压下的集成电路统计时序分析方法，其特征在于：所述步骤S1具体包括以下步骤：
    S11：根据式(1)所示的线性关系求得各级电路单元的系数：
    Figure PCTCN2020076447-appb-100001
    式(1)中，t di表示电路路径中的第i级电路单元非阶跃输入信号下的延时标称值，
    Figure PCTCN2020076447-appb-100002
    表示电路路径中的第i级电路单元阶跃输入信号下的延时标称值，
    Figure PCTCN2020076447-appb-100003
    表示电路路径中的第i-1级电路单元阶跃输入信号下的延时标称值，η ((i-1)表示第i-1级电路单元的系数，2≤i≤n，n表示电路路径中电路单元的总数；
    S12：将η ((i-1)代入到式(2)中，求得电路路径延时随机变量t_path：
    Figure PCTCN2020076447-appb-100004
    式(2)中，随机变量t dr表示电路路径在阶跃输入信号下第r级电路单元的延时，随机变量
    Figure PCTCN2020076447-appb-100005
    表示阶跃输入信号下第n级电路单元的延时，η j表示第j级电路单元的系数，随机变量
    Figure PCTCN2020076447-appb-100006
    表示阶跃输入信号下第j级电路单元的延时。
  3. 根据权利要求1所述的先进工艺和低电压下的集成电路统计时序分析方法，其特征在于：所述步骤S2中，对电路路径中各级电路单元在阶跃输入信号下均进行m次蒙特卡洛仿真，对仿真获得的统计样本集通过式(3)计算得到各级电路单元在阶跃输入信号下的延时统计值的均值、方差和偏度：
    Figure PCTCN2020076447-appb-100007
    Figure PCTCN2020076447-appb-100008
    Figure PCTCN2020076447-appb-100009
    式(3)中，E(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的均值，D(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的方差，S(x r)表示第r级电路单元在阶跃输入信号下的延时统计值的偏度，1≤r≤n，n表示电路路径中电路单元的总数，随机变量x r表示第r级电路单元在阶跃输入下的延时，X r,k表示第r级电路单元在阶跃输入下的第k个延时样本数据，
    Figure PCTCN2020076447-appb-100010
    表示随机变量x r的三阶原点矩，
    Figure PCTCN2020076447-appb-100011
  4. 根据权利要求1所述的先进工艺和低电压下的集成电路统计时序分析方法，其特征在于：所述步骤S3中，电路路径在阶跃输入信号下的延时统计值的均值、方差和偏度通过式(4)计算得到：
    Figure PCTCN2020076447-appb-100012
    式(4)中，y＝t_path表示阶跃输入信号下电路路径的延时随机变量，E(y)表示y的均值，D(y)表示y的方差，S(y)表示y的偏度，
    Figure PCTCN2020076447-appb-100013
    表示阶跃输入信号下第r级电路单元的延时随机变量，E(x r)表示x r的均值，D(x r)表示x r的方差，
    Figure PCTCN2020076447-appb-100014
    表示
    Figure PCTCN2020076447-appb-100015
    的均值，
    Figure PCTCN2020076447-appb-100016
    表示
    Figure PCTCN2020076447-appb-100017
    的均值，
    Figure PCTCN2020076447-appb-100018
    表示
    Figure PCTCN2020076447-appb-100019
    的方差，1≤r≤n，a j＝1+η j，η j表示第j级电路单元的系数，1≤j≤n-1，n表示电路路径中电路单元的总数，a n＝1，μ＝-E(y)；
    公式(4)中第三个偏度表达式进一步展开写成公式(5)：
    Figure PCTCN2020076447-appb-100020
    其中，t s由表达式
    Figure PCTCN2020076447-appb-100021
    约束，1≤s≤n+1；对于1≤q≤n-1，a q＝1+η q，η q表示第q级电路单元的系数；对于q＝n，，a q＝1；x q表示阶跃输入信号下第q级电路单元的延时随机变量。
  5. 根据权利要求1所述的先进工艺和低电压下的集成电路统计时序分析方法，其特征在于：所述步骤S4中的分布参数包括位置参数ε、比例参数ω和第一形状参数λ，通过式(6)计算得到：
    Figure PCTCN2020076447-appb-100022
    式(6)中，随机变量y表示电路路径在阶跃输入下的延时，α p表示随机变量y的p阶原点矩，1≤p≤3，
    Figure PCTCN2020076447-appb-100023
    β表示第二形状参数，
    Figure PCTCN2020076447-appb-100024
    E(y)表示电路路径在阶跃输入信号下的延时统计值的均值，D(y)表示电路路径在阶跃输入信号下的延时统计值的方差，S(y)表示电路路径在阶跃输入信号下的延时统计值的偏度，E(y 2)表示随机变量y的二阶原点矩，E(y 3)表示随机变量y的三阶原点矩。
  6. 根据权利要求5所述的先进工艺和低电压下的集成电路统计时序分析方法，其特征在于：所述步骤S5中，电路路径的延时统计值的概率密度函数通过式(7)计算得到：
    Figure PCTCN2020076447-appb-100025
    式(7)中，f LSN(y)表示电路路径延时统计值的概率密度函数，
    Figure PCTCN2020076447-appb-100026
    电路路径的延时统计值的最大值和最小值通过式(8)计算得到：
    Figure PCTCN2020076447-appb-100027
    式(8)中，
    Figure PCTCN2020076447-appb-100028
    令
    Figure PCTCN2020076447-appb-100029
    对应的解y为电路路径延时统计值的最大值；令
    Figure PCTCN2020076447-appb-100030
    对应的解y为电路路径延时统计值的最小值；F LSN(y)表示电路路径延时统计值的累计分布函数，
    Figure PCTCN2020076447-appb-100031
    通过式(9)计算得到；
    Figure PCTCN2020076447-appb-100032
    式(9)中，
    Figure PCTCN2020076447-appb-100033
    A＝λ。
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