WO2021007897A1 - 单晶硅局域soi衬底、光电器件及制备方法 - Google Patents

单晶硅局域soi衬底、光电器件及制备方法 Download PDF

Info

Publication number
WO2021007897A1
WO2021007897A1 PCT/CN2019/100557 CN2019100557W WO2021007897A1 WO 2021007897 A1 WO2021007897 A1 WO 2021007897A1 CN 2019100557 W CN2019100557 W CN 2019100557W WO 2021007897 A1 WO2021007897 A1 WO 2021007897A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
single crystal
local soi
crystal silicon
substrate
Prior art date
Application number
PCT/CN2019/100557
Other languages
English (en)
French (fr)
Inventor
汪巍
方青
涂芝娟
曾友宏
蔡艳
余明斌
Original Assignee
上海新微技术研发中心有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201921122297.3U external-priority patent/CN210837756U/zh
Priority claimed from CN201910646559.4A external-priority patent/CN112242343A/zh
Application filed by 上海新微技术研发中心有限公司 filed Critical 上海新微技术研发中心有限公司
Publication of WO2021007897A1 publication Critical patent/WO2021007897A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the invention belongs to the field of semiconductor materials and devices, and particularly relates to a single crystal silicon local SOI substrate, a photoelectric device and a preparation method.
  • Optoelectronic integration technology is one of the key technologies for the development of the information industry in the future. It is a key technical solution to realize chip miniaturization, overcome signal delay and break through the bottleneck of Moore's Law.
  • the optoelectronic integration scheme is to make the electric chip and the optical chip on different chips, and then realize the optoelectronic interconnection through technologies such as lead wire, flip-chip bonding, 2.5D/3D, etc.
  • CMOS technology to achieve monolithic integration of electrical and optical chips on the same substrate, which can effectively improve chip integration and chip speed, while reducing process costs, is one of the important development directions of optoelectronic integrated chips.
  • CMOS process lacks a semiconductor material with appropriate optical performance to achieve large active Passive photon function. So far, all efforts to integrate optical chips into CMOS have been limited to silicon-on-insulator (SOI) material vendors.
  • SOI silicon-on-insulator
  • the purpose of the present invention is to provide a monocrystalline silicon local SOI substrate, optoelectronic device and preparation method, which is used to solve the problem of performance of optical chips prepared based on polycrystalline silicon SOI materials in the prior art.
  • the question of raising is to provide a monocrystalline silicon local SOI substrate, optoelectronic device and preparation method, which is used to solve the problem of performance of optical chips prepared based on polycrystalline silicon SOI materials in the prior art. The question of raising.
  • the present invention provides a method for preparing a single crystal silicon local SOI substrate.
  • the preparation method includes the steps: 1) providing a silicon substrate, and etching on the silicon substrate Out of the local SOI area groove; 2) Deposit a dielectric layer on the local SOI area groove and the surface of the silicon substrate, and perform a chemical mechanical polishing process to form a flat surface, the flat surface revealing the surface of the silicon substrate; 3 ) Depositing an amorphous silicon layer on the surface of the silicon substrate and the dielectric, and recrystallizing the amorphous silicon layer through a thermal annealing solid phase epitaxy process to form a single crystal covering the surface of the silicon substrate and the dielectric layer A silicon layer to form the single crystal silicon local SOI substrate.
  • the depth of the local SOI region groove is between 1 micrometer and 10 micrometers.
  • step 2) using a chemical vapor deposition process to deposit a dielectric layer on the surface of the local SOI area groove and the silicon substrate, the thickness of the dielectric layer is greater than the depth of the local SOI area groove, the The material of the dielectric layer includes one of silicon dioxide, silicon oxynitride, and silicon nitride.
  • step 3 depositing an amorphous silicon layer on the surface of the silicon substrate using a magnetron sputtering method or a chemical vapor deposition method, and the thickness of the amorphous silicon layer is between 50 nanometers and 5000 nanometers.
  • the annealing temperature of the thermal annealing solid-phase epitaxy process in step 3) is between 500 and 1200° C.
  • the annealing time is between 0.5 minutes and 120 minutes.
  • the present invention also provides a method for preparing a photoelectric device based on a single crystal silicon local SOI substrate.
  • the preparation method includes the steps: 1) Using a single crystal silicon local SOI substrate preparation method to prepare a single crystal silicon local SOI Substrate; 2) Prepare electrical devices on the silicon substrate and the single crystal silicon layer above, and prepare optical devices on the single crystal silicon layer on the dielectric layer.
  • the electrical device includes one or more of semiconductor transistors, diodes, resistors and capacitors
  • the optical device includes one or more of optical waveguides, active devices, and passive devices.
  • the present invention also provides a single crystal silicon local SOI substrate, including: a silicon substrate with a local SOI region groove on the silicon substrate; a dielectric layer filled in the local SOI region groove; and The crystalline silicon layer covers the surface of the silicon substrate and the dielectric layer.
  • the depth of the local SOI region groove is between 1 micrometer and 10 micrometers.
  • the material of the dielectric layer includes one of silicon dioxide, silicon oxynitride, and silicon nitride.
  • the thickness of the amorphous silicon layer is between 50 nanometers and 5000 nanometers.
  • the present invention also provides an optoelectronic device based on a single crystal silicon local SOI substrate, including: a single crystal silicon local SOI substrate; an electrical device, prepared on the silicon substrate and the single crystal silicon layer above; The optical device is prepared on the single crystal silicon layer on the dielectric layer.
  • the electrical device includes a semiconductor transistor
  • the optical device includes an optical waveguide, an active device, and a passive device.
  • the crystalline silicon local SOI substrate, optoelectronic device and preparation method of the present invention have the following beneficial effects:
  • the present invention can realize optoelectronic device integration on bulk silicon and local SOI, that is, it can integrate electrical devices on bulk silicon and integrate optical devices on local SOI. It has better electrical performance and lower cost.
  • the present invention can realize single crystal silicon local SOI through a special solid phase epitaxy process, which can effectively improve the performance of optical devices.
  • FIG. 1 is a schematic diagram of the steps of a method for manufacturing a photoelectric device based on a single crystal silicon local SOI substrate according to an embodiment of the present invention.
  • 2-9 are schematic diagrams showing the structure of each step of the method for manufacturing a photoelectric device based on a single crystal silicon local SOI substrate according to an embodiment of the present invention.
  • spatial relation words such as “below”, “below”, “below”, “below”, “above”, “up”, etc. may be used herein to describe an element or The relationship between a feature and other elements or features. It will be understood that these spatial relationship terms are intended to encompass directions other than the directions depicted in the drawings of the device in use or operation.
  • a layer when referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.
  • the described structure where the first feature is "above" the second feature may include an embodiment in which the first and second features are formed in direct contact, or may include other features formed on the first and second features.
  • the embodiment between the second feature, so that the first and second features may not be in direct contact.
  • this embodiment provides a method for manufacturing a single crystal silicon local SOI substrate and a photoelectric device based on the single crystal silicon local SOI substrate.
  • the manufacturing method includes the steps:
  • step 1) S11 is performed to provide a silicon substrate 101, and a local SOI region trench 102 is etched on the silicon substrate 101.
  • a photolithography process may be used to define a local SOI region groove 102 in the silicon substrate 101 (such as a single crystal silicon wafer, etc.), and then an etching process may be used to etch the silicon substrate 101.
  • the local SOI area groove 102, the depth of the local SOI area groove 102 may be between 1 ⁇ m and 10 ⁇ m.
  • the above depth range can ensure that the subsequent dielectric layer 103 has sufficient isolation effect while avoiding the depth of the area groove It is too large to increase the etching cost.
  • the depth of the opening is 2.2 microns.
  • the width of the local SOI region groove 102 can be determined according to the area required by subsequent devices, such as 10 micrometers to 100 micrometers, etc. Of course, the depth and width of the local SOI region groove 102 can be selected according to actual requirements, and Not limited to the giant examples listed here.
  • the silicon substrate 101 can be oxidized and cleaned to change the top corner of the silicon substrate 101 on the top of the local SOI region trench 102.
  • the corners are rounded to improve the compression resistance and breakdown resistance of the device.
  • step 2) S12 is performed, a dielectric layer 103 is deposited on the surface of the local SOI area groove 102 and the silicon substrate 101, and a chemical mechanical polishing process is performed to form a flat surface , The flat surface exposes the surface of the silicon substrate 101.
  • a chemical vapor deposition process may be used to deposit a dielectric layer 103 on the surface of the local SOI area groove 102 and the silicon substrate 101, and the thickness of the dielectric layer 103 is greater than the depth of the local SOI area groove 102, so
  • the material of the dielectric layer 103 includes one of silicon dioxide, silicon oxynitride, and silicon nitride.
  • the thickness of the dielectric layer 103 is 2.3 ⁇ m to 2.8 ⁇ m, which is slightly larger than the depth of the local SOI region groove 102 to ensure that the dielectric layer 103 can fill the local SOI region groove 102. It is beneficial to the subsequent polishing process, and the time required for the polishing process is shorter.
  • the thickness of the dielectric layer 103 on the silicon substrate 101 will be greater than the thickness of the dielectric layer 103 above the trench 102 in the local SOI region.
  • the dielectric layer 103 with a large thickness above the silicon substrate 101 can be removed by the first step of photolithography and etching process to reduce the surface height difference of the dielectric layer 103, and then a flat surface can be formed by a chemical mechanical polishing process. It can greatly improve the surface flatness and efficiency.
  • step 3) S13 is performed, an amorphous silicon layer 104 is deposited on the surface of the silicon substrate 101 and the dielectric 103, and the thermal annealing solid phase epitaxy process makes the The amorphous silicon layer 104 is recrystallized to form a single crystal silicon layer 105 covering the surfaces of the silicon substrate 101 and the dielectric layer 103 to form the single crystal silicon local SOI substrate, as shown in FIG. 8.
  • a magnetron sputtering method or a chemical vapor deposition method may be used to deposit the amorphous silicon layer 104 on the surface of the silicon substrate 101, and the thickness of the amorphous silicon layer 104 is between 50 nanometers and 5000 nanometers.
  • a magnetron sputtering method is used to deposit an amorphous silicon layer 104 on the surface of the silicon substrate 101, and the thickness of the amorphous silicon layer 104 is 220 nanometers.
  • the annealing temperature of the thermal annealing solid phase epitaxy process is between 500 and 1200° C., and the annealing time is between 0.5 minutes and 120 minutes.
  • the amorphous silicon layer on the surface of the silicon substrate 101 104 first undergoes vertical solid phase epitaxy to form single crystal silicon, and then lateral solid phase epitaxy occurs based on the single crystal silicon toward the amorphous silicon above the dielectric layer 103, thereby forming a single crystal silicon layer 105 on the dielectric layer 103 .
  • the annealing temperature of the solid phase epitaxy is 700° C., and the annealing time is 5 minutes.
  • step 4) S14 is finally performed, an electrical device 106 is prepared on the silicon substrate 101 and the single crystal silicon layer 105 above, and the single crystal silicon layer 105 on the dielectric layer 103 The optical device 107 is prepared above.
  • the electrical device 106 may be the electrical device including semiconductor transistors, diodes, resistors and capacitors, such as N-type metal semiconductor field effect transistors, P-type metal semiconductor field effect transistors, CMOS devices, etc.
  • the optical device 107 It can be optical waveguide, active device, passive device, etc.
  • this embodiment also provides a single crystal silicon local SOI substrate, including: a silicon substrate 101 having a local SOI area groove 102; a dielectric layer 103 filled in In the local SOI area groove 102; and a single crystal silicon layer 105 covering the surface of the silicon substrate 101 and the dielectric layer 103.
  • the depth of the local SOI region groove 102 is between 1 ⁇ m and 10 ⁇ m.
  • the material of the dielectric layer 103 includes one of silicon dioxide, silicon oxynitride, and silicon nitride.
  • the thickness of the amorphous silicon layer 104 is between 50 nanometers and 5000 nanometers.
  • this embodiment also provides an optoelectronic device based on a single crystal silicon local SOI substrate.
  • the optoelectronic device includes: the single crystal silicon local SOI substrate as described above; and the electrical device 106 is prepared On the silicon substrate 101 and the single crystal silicon layer 105 thereon; and the optical device 107 is prepared on the single crystal silicon layer 105 on the dielectric layer 103.
  • the electrical device 106 may be the electrical device including semiconductor transistors, diodes, resistors and capacitors, such as N-type metal semiconductor field effect transistors, P-type metal semiconductor field effect transistors, CMOS devices, etc.
  • the optical The device 107 can be an optical waveguide, an active device, a passive device, and the like.
  • the present invention can realize the integration of optoelectronic devices on bulk silicon and local SOI, that is, it can integrate electrical devices 106 on bulk silicon and optical devices 107 on local SOI. , Has better electrical performance and lower cost. Compared with the existing local SOI solution of polysilicon on bulk silicon, the present invention can realize local SOI of single crystal silicon and can effectively improve the performance of the optical device 107.
  • the crystalline silicon local SOI substrate, optoelectronic device and preparation method of the present invention have the following beneficial effects:
  • the present invention can realize optoelectronic device integration on bulk silicon and local SOI, that is, it can integrate electrical devices on bulk silicon and integrate optical devices on local SOI. It has better electrical performance and lower cost.
  • the present invention can realize local SOI of single crystal silicon and can effectively improve the performance of optical devices.
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial value.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

一种单晶硅局域SOI衬底、光电器件及制备方法，制备方法包括：1)在硅衬底(101)上刻蚀出局域SOI区域槽(102)；2)于局域SOI区域槽(102)及硅衬底(101)表面沉积介质层(103)，并抛光形成平坦表面；3)沉积非晶硅层(104)于硅衬底(101)表面，并通过热退火固相外延工艺使非晶硅层(104)重新结晶形成覆盖于硅衬底(101)及介质层(103)表面的单晶硅层(105)，以形成单晶硅局域SOI衬底，于硅衬底(101)及其上方的单晶硅层(105)制备电学器件，于介质层(103)上的单晶硅层(105)上制备光学器件。采用上述方法可以在体硅衬底(101)上形成局域SOI，从而实现光芯片与电芯片的单片集成。

Description

单晶硅局域SOI衬底、光电器件及制备方法 技术领域
本发明属于半导体材料与器件领域，特别是涉及一种单晶硅局域SOI衬底、光电器件及制备方法。
背景技术
光电集成技术是未来信息产业发展的关键技术之一，是实现芯片小型化、克服信号延迟及突破摩尔定律瓶颈的关键技术方案。现阶段光电集成的方案是将电芯片和光芯片做在不同的芯片上，然后通过引线、倒装焊、2.5D/3D等技术实现光电互联。在同一衬底上采用标准CMOS工艺实现电芯片与光芯片的单片集成，能有效提升芯片集成度与芯片速率，同时降低工艺成本，是光电集成芯片的重要发展方向之一。然而，作为微电子芯片(Intel、Apple、Nvidia CPU/GPU、全电脑内存、闪存等)的主导制造平台，体硅CMOS工艺中缺乏一种具有合适光学性能的半导体材料来实现大块的有源无源光子功能。到目前为止，所有将光芯片集成到CMOS中的努力都局限于绝缘体上的硅(SOI)材料商。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种单晶硅局域SOI衬底、光电器件及制备方法，用于解决现有技术中基于多晶硅SOI材料制备的光芯片性能难以提高的问题。
为实现上述目的及其他相关目的，本发明提供一种单晶硅局域SOI衬底的制备方法，所述制备方法包括步骤：1)提供一硅衬底，在所述硅衬底上刻蚀出局域SOI区域槽；2)于所述局域SOI区域槽及所述硅衬底表面沉积介质层，并进行化学机械抛光工艺形成平坦表面，所述平坦表面显露所述硅衬底表面；3)沉积非晶硅层于所述硅衬底及所述介质表面，并通过热退火固相外延工艺使所述非晶硅层重新结晶形成覆盖于所述硅衬底及介质层表面的单晶硅层，以形成所述单晶硅局域SOI衬底。
可选地，所述局域SOI区域槽的深度介于1微米～10微米之间。
可选地，步骤2)采用化学气相沉积工艺于所述局域SOI区域槽及所述硅衬底表面沉积介质层，所述介质层的厚度大于所述局域SOI区域槽的深度，所述介质层的材料包括二氧化硅、氮氧化硅及氮化硅中的一种。
可选地，步骤3)采用磁控溅射方法或化学气相沉积方法沉积非晶硅层于所述硅衬底表 面，所述非晶硅层的厚度介于50纳米～5000纳米之间。
可选地，步骤3)所述热退火固相外延工艺的退火温度介于500～1200℃之间，退火时间介于0.5分钟～120分钟。
本发明还提供一种基于单晶硅局域SOI衬底的光电器件的制备方法，所述制备方法包括步骤：1)采用单晶硅局域SOI衬底的制备方法制备单晶硅局域SOI衬底；2)于所述硅衬底及其上方的单晶硅层制备电学器件，于所述介质层上的单晶硅层上制备光学器件。
可选地，所述电学器件包括半导体晶体管、二极管、电阻及电容中的一种或多种，所述光学器件包括光波导、有源器件及无源器件中的一种或多种。
本发明还提供一种单晶硅局域SOI衬底，包括：硅衬底，所述硅衬底上具有局域SOI区域槽；介质层，填充于所述局域SOI区域槽中；以及单晶硅层，覆盖于所述硅衬底及所述介质层表面。
可选地，所述局域SOI区域槽的深度介于1微米～10微米之间。
可选地，所述介质层的材料包括二氧化硅、氮氧化硅及氮化硅中的一种。
可选地，所述非晶硅层的厚度介于50纳米～5000纳米之间。
本发明还提供一种基于单晶硅局域SOI衬底的光电器件，包括：单晶硅局域SOI衬底；电学器件，制备于所述硅衬底及其上方的单晶硅层上；光学器件，制备于所述介质层上的单晶硅层上。
可选地，所述电学器件包括半导体晶体管，所述光学器件包括光波导、有源器件及无源器件。
如上所述，本发明的晶硅局域SOI衬底、光电器件及制备方法，具有以下有益效果：
第一，与在SOI衬底上集成光电器件方案相比，本发明可以在体硅及局域SOI上实现光电器件集成，即可以体硅上集成电学器件，在局域SOI上集成光学器件，具有更优的电学性能以及更低的成本。
第二，与现有体硅上多晶硅局域SOI方案相比，本发明通过特殊的固相外延工艺，可实现单晶硅局域SOI，能有效提升光学器件性能。
附图说明
图1显示为本发明实施例的基于单晶硅局域SOI衬底的光电器件的制备方法的步骤流程示意图。
图2～图9显示为本发明实施例的基于单晶硅局域SOI衬底的光电器件的制备方法各步骤 所呈现的结构示意图。
元件标号说明
101                    硅衬底
102                    局域SOI区域槽
103                    介质层
104                    非晶硅层
105                    单晶硅层
106                    电学器件
107                    光学器件
S11～S14               步骤1)～步骤4)
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
如在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
经研究发现，可以通过在二氧化硅(SiO 2)上沉积多晶硅材料，形成局部SOI衬底，进而制备光学芯片。然而，基于多晶硅SOI材料制备的光芯片在性能上与基于单晶硅SOI材料制备的光芯片仍然存在着较大的差距。
如图1及图2～图9所示，本实施例提供一种单晶硅局域SOI衬底、基于单晶硅局域SOI衬底的光电器件的制备方法，所述制备方法包括步骤：
如图1及图2～图3所示，首先进行步骤1)S11，提供一硅衬底101，在所述硅衬底101上刻蚀出局域SOI区域槽102。
例如，可以采用光刻工艺在所述硅衬底101(如单晶硅晶圆等)中定义出局域SOI区域槽102，然后采用刻蚀工艺在所述硅衬底101上刻蚀出所述局域SOI区域槽102，所述局域SOI区域槽102的深度可以介于1微米～10微米之间，上述深度范围可以保证后续介质层103的具有足够的隔离效果的同时，避免区域槽深度过大而导致刻蚀成本的增加。在本实施例中，所述开孔深度为2.2微米。所述局域SOI区域槽102的宽度可以依据后续器件所需面积进行确定，如10微米～100微米等，当然，所述局域SOI区域槽102的深度及宽度可以依据实际需求进行选择，并不限于此处所列巨的示例。
更进一步地，可以在刻蚀出所述局域SOI区域槽102后，对硅衬底101进行氧化及清洗等步骤，使所述局域SOI区域槽102顶部的硅衬底101顶部尖角变为圆角，以提高器件的抗压及抗击穿能力。
如图1及图4～图6所示，然后进行步骤2)S12，于所述局域SOI区域槽102及所述硅衬底101表面沉积介质层103，并进行化学机械抛光工艺形成平坦表面，所述平坦表面显露所述硅衬底101表面。
例如，可以采用化学气相沉积工艺于所述局域SOI区域槽102及所述硅衬底101表面沉积介质层103，所述介质层103的厚度大于所述局域SOI区域槽102的深度，所述介质层103的材料包括二氧化硅、氮氧化硅及氮化硅中的一种。在本实施例中，所述介质层103的厚度为2.3微米～2.8微米，略大于所述局域SOI区域槽102的深度，以保证所述介质层103能填满所述局域SOI区域槽102，有利于后续抛光工艺的进行，且使得抛光工艺所需时间较短。
如图4～图5所示，由于介质层103的沉积具有沟槽填充，因此，位于硅衬底101上的介质层103厚度会大于位于局域SOI区域槽102上方的介质层103厚度，在本实施例中，可以先通过第一步光刻刻蚀工艺去除硅衬底101上方厚度较大的介质层103，减小介质层103表面高度差，然后再通过化学机械抛光工艺形成平坦表面，可以大大提高表面平坦度及提高效率。
如图1及图7～图8所示，接着进行步骤3)S13，沉积非晶硅层104于所述硅衬底101及所述介质103表面，并通过热退火固相外延工艺使所述非晶硅层104重新结晶形成覆盖于所述硅衬底101及介质层103表面的单晶硅层105，以形成所述单晶硅局域SOI衬底，如图8所示。
例如，可以采用磁控溅射方法或化学气相沉积方法沉积非晶硅层104于所述硅衬底101表面，所述非晶硅层104的厚度介于50纳米～5000纳米之间。在本实施例中，采用磁控溅射方法沉积非晶硅层104于所述硅衬底101表面，所述非晶硅层104的厚度为220纳米。
所述热退火固相外延工艺的退火温度介于500～1200℃之间，退火时间介于0.5分钟～120分钟，在退火过程中，位于所述硅衬底101表面的所述非晶硅层104首先发生纵向的固相外延，形成单晶硅，然后基于该单晶硅朝所述介质层103上方的非晶硅发生横向的固相外延，从而在介质层103上形成单晶硅层105。在本实施例中，固相外延的退火温度为700℃，退火时间为5分钟。
如图1及图9所示，最后进行步骤4)S14，于所述硅衬底101及其上方的单晶硅层105制备电学器件106，于所述介质层103上的单晶硅层105上制备光学器件107。
例如，所述电学器件106可以为所述电学器件包括半导体晶体管、二极管、电阻及电容等，如N型金属半导体场效应晶体管、P型金属半导体场效应晶体管、CMOS器件等，所述光学器件107可以为光波导、有源器件及无源器件等。
如图8所示，本实施例还提供一种单晶硅局域SOI衬底，包括：硅衬底101，所述硅衬底101上具有局域SOI区域槽102；介质层103，填充于所述局域SOI区域槽102中；以及单晶硅层105，覆盖于所述硅衬底101及所述介质层103表面。例如，所述局域SOI区域槽102的深度介于1微米～10微米之间。所述介质层103的材料包括二氧化硅、氮氧化硅及氮化硅中的一种。所述非晶硅层104的厚度介于50纳米～5000纳米之间。
如图9所示，本实施例还提供一种基于单晶硅局域SOI衬底的光电器件，所述光电器件包括：如上所述的单晶硅局域SOI衬底；电学器件106，制备于所述硅衬底101及其上方的单晶硅层105上；以及光学器件107，制备于所述介质层103上的单晶硅层105上。
例如，例如，所述电学器件106可以为所述电学器件包括半导体晶体管、二极管、电阻及电容等，如N型金属半导体场效应晶体管、P型金属半导体场效应晶体管、CMOS器件等，所述光学器件107可以为光波导、有源器件及无源器件等。
本发明与在SOI衬底上集成光电器件方案相比，本发明可以在体硅及局域SOI上实现光电器件集成，即可以体硅上集成电学器件106，在局域SOI上集成光学器件107，具有更优的 电学性能以及更低的成本。与现有体硅上多晶硅局域SOI方案相比，本发明可实现单晶硅局域SOI，能有效提升光学器件107性能。
如上所述，本发明的晶硅局域SOI衬底、光电器件及制备方法，具有以下有益效果：
第一，与在SOI衬底上集成光电器件方案相比，本发明可以在体硅及局域SOI上实现光电器件集成，即可以体硅上集成电学器件，在局域SOI上集成光学器件，具有更优的电学性能以及更低的成本。
第二，与现有体硅上多晶硅局域SOI方案相比，本发明可实现单晶硅局域SOI，能有效提升光学器件性能。
所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (13)

  1. 一种单晶硅局域SOI衬底的制备方法，其特征在于，所述制备方法包括步骤：
    1)提供一硅衬底，在所述硅衬底上刻蚀出局域SOI区域槽；
    2)于所述局域SOI区域槽及所述硅衬底表面沉积介质层，并进行化学机械抛光工艺形成平坦表面，所述平坦表面显露所述硅衬底表面；
    3)沉积非晶硅层于所述硅衬底及所述介质层表面，并通过热退火固相外延工艺使所述非晶硅层重新结晶形成覆盖于所述硅衬底及介质层表面的单晶硅层，以形成所述单晶硅局域SOI衬底。
  2. 根据权利要求1所述的单晶硅局域SOI衬底的制备方法，其特征在于：所述局域SOI区域槽的深度介于1微米～10微米之间。
  3. 根据权利要求1所述的单晶硅局域SOI衬底的制备方法，其特征在于：步骤2)采用化学气相沉积工艺于所述局域SOI区域槽及所述硅衬底表面沉积介质层，所述介质层的厚度大于所述局域SOI区域槽的深度，所述介质层的材料包括二氧化硅、氮氧化硅及氮化硅中的一种。
  4. 根据权利要求1所述的单晶硅局域SOI衬底的制备方法，其特征在于：步骤3)采用磁控溅射方法或化学气相沉积方法沉积非晶硅层于所述硅衬底表面，所述非晶硅层的厚度介于50纳米～5000纳米之间。
  5. 根据权利要求1所述的单晶硅局域SOI衬底的制备方法，其特征在于：步骤3)所述热退火固相外延工艺的退火温度介于500～1200℃之间，退火时间介于0.5分钟～120分钟。
  6. 一种基于单晶硅局域SOI衬底的光电器件的制备方法，其特征在于，所述制备方法包括步骤：
    1)采用如权利要求1～5任意一项所述的单晶硅局域SOI衬底的制备方法制备单晶硅局域SOI衬底；
    2)于所述硅衬底及其上方的单晶硅层制备电学器件，于所述介质层上的单晶硅层上制备光学器件。
  7. 根据权利要求6所述的基于单晶硅局域SOI衬底的光电器件的制备方法，其特征在于：所 述电学器件包括半导体晶体管、二极管、电阻及电容中的一种或多种，所述光学器件包括光波导、有源器件及无源器件中的一种或多种。
  8. 一种单晶硅局域SOI衬底，其特征在于，包括：
    硅衬底，所述硅衬底上具有局域SOI区域槽；
    介质层，填充于所述局域SOI区域槽中；
    单晶硅层，覆盖于所述硅衬底及所述介质层表面。
  9. 根据权利要求8所述的单晶硅局域SOI衬底，其特征在于：所述局域SOI区域槽的深度介于1微米～10微米之间。
  10. 根据权利要求8所述的单晶硅局域SOI衬底，其特征在于：所述介质层的材料包括二氧化硅、氮氧化硅及氮化硅中的一种。
  11. 根据权利要求8所述的单晶硅局域SOI衬底，其特征在于：所述非晶硅层的厚度介于50纳米～5000纳米之间。
  12. 一种基于单晶硅局域SOI衬底的光电器件，其特征在于，包括：
    如权利要求8～11任意一项所述的单晶硅局域SOI衬底；
    电学器件，制备于所述硅衬底及其上方的单晶硅层上；
    光学器件，制备于所述介质层上的单晶硅层上。
  13. 根据权利要求12所述的基于单晶硅局域SOI衬底的光电器件，其特征在于：所述电学器件包括半导体晶体管、二极管、电阻及电容中的一种或多种，所述光学器件包括光波导、有源器件及无源器件中的一种或多种。
PCT/CN2019/100557 2019-07-17 2019-08-14 单晶硅局域soi衬底、光电器件及制备方法 WO2021007897A1 (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201921122297.3U CN210837756U (zh) 2019-07-17 2019-07-17 单晶硅局域soi衬底及光电器件
CN201910646559.4A CN112242343A (zh) 2019-07-17 2019-07-17 单晶硅局域soi衬底、光电器件及制备方法
CN201921122297.3 2019-07-17
CN201910646559.4 2019-07-17

Publications (1)

Publication Number Publication Date
WO2021007897A1 true WO2021007897A1 (zh) 2021-01-21

Family

ID=74210066

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/100557 WO2021007897A1 (zh) 2019-07-17 2019-08-14 单晶硅局域soi衬底、光电器件及制备方法

Country Status (1)

Country Link
WO (1) WO2021007897A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060160322A1 (en) * 2005-01-17 2006-07-20 International Business Machines Corporation Nitridation of sti fill oxide to prevent the loss of sti fill oxide during manufacturing process
JP2008042207A (ja) * 2006-08-04 2008-02-21 Toshiba Corp 半導体装置の製造方法
US20110049637A1 (en) * 2009-08-31 2011-03-03 Maciej Wiatr Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices
CN102141650A (zh) * 2009-12-03 2011-08-03 三星电子株式会社 光学器件及其制造方法
US9293474B2 (en) * 2013-07-02 2016-03-22 International Business Machines Corporation Dual channel hybrid semiconductor-on-insulator semiconductor devices
CN107039459A (zh) * 2016-02-03 2017-08-11 上海硅通半导体技术有限公司 Soi和体硅混合晶圆结构及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060160322A1 (en) * 2005-01-17 2006-07-20 International Business Machines Corporation Nitridation of sti fill oxide to prevent the loss of sti fill oxide during manufacturing process
JP2008042207A (ja) * 2006-08-04 2008-02-21 Toshiba Corp 半導体装置の製造方法
US20110049637A1 (en) * 2009-08-31 2011-03-03 Maciej Wiatr Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices
CN102141650A (zh) * 2009-12-03 2011-08-03 三星电子株式会社 光学器件及其制造方法
US9293474B2 (en) * 2013-07-02 2016-03-22 International Business Machines Corporation Dual channel hybrid semiconductor-on-insulator semiconductor devices
CN107039459A (zh) * 2016-02-03 2017-08-11 上海硅通半导体技术有限公司 Soi和体硅混合晶圆结构及其制备方法

Similar Documents

Publication Publication Date Title
US9646938B2 (en) Integrated circuit with backside structures to reduce substrate warp
US8738167B2 (en) 3D integrated circuit device fabrication with precisely controllable substrate removal
CN103426732B (zh) 低温晶圆键合的方法及通过该方法形成的结构
CN104733435B (zh) 3dic互连装置和方法
US8298914B2 (en) 3D integrated circuit device fabrication using interface wafer as permanent carrier
US8846452B2 (en) Semiconductor device package and methods of packaging thereof
US20080044979A1 (en) Integrated circuitry, electromagnetic radiation interaction components, transistor devices and semiconductor construction; and methods of forming integrated circuitry, electromagnetic radiation interaction components, transistor devices and semiconductor constructions
TWI582913B (zh) 半導體封裝件及其製法
CN202855741U (zh) 晶圆与晶圆、晶圆与芯片、芯片与芯片键合的结构
CN112242342A (zh) 单晶硅局域soi衬底、光电器件及制备方法
TW202015230A (zh) 影像感測器與其形成方法
TWI500132B (zh) 半導體裝置之製法、基材穿孔製程及其結構
WO2020133732A1 (zh) 封装方法及封装结构
CN210837756U (zh) 单晶硅局域soi衬底及光电器件
TW202220152A (zh) 半導體架構及其製造方法
CN112285827B (zh) 一种多层硅光子器件的制备方法
US20230411299A1 (en) Device packages including redistribution layers with carbon-based conductive elements, and methods of fabrication
TW201705458A (zh) 半導體晶圓、其製造方法及半導體晶圓之接合方法
CN210607255U (zh) 单晶硅局域soi衬底及光电器件
WO2021007897A1 (zh) 单晶硅局域soi衬底、光电器件及制备方法
CN112242343A (zh) 单晶硅局域soi衬底、光电器件及制备方法
CN112713215A (zh) 一种探测器的集成结构及集成方法
CN104517959A (zh) 半导体结构及其形成方法
WO2020237707A1 (zh) 硅光模块的封装方法及硅光模块
CN111584498B (zh) 一种cmos片内三维结构的形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19938063

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19938063

Country of ref document: EP

Kind code of ref document: A1