WO2021000842A1 - 印制电路板pcb的测试方法及装置方法及装置 - Google Patents

印制电路板pcb的测试方法及装置方法及装置 Download PDF

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Publication number
WO2021000842A1
WO2021000842A1 PCT/CN2020/099015 CN2020099015W WO2021000842A1 WO 2021000842 A1 WO2021000842 A1 WO 2021000842A1 CN 2020099015 W CN2020099015 W CN 2020099015W WO 2021000842 A1 WO2021000842 A1 WO 2021000842A1
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Prior art keywords
area
tested
strain gauge
pcb
insulating layer
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PCT/CN2020/099015
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English (en)
French (fr)
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肖守春
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中兴通讯股份有限公司
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Publication of WO2021000842A1 publication Critical patent/WO2021000842A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
    • G01B21/32—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring the deformation in a solid
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/20—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress
    • G01L1/22—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits

Definitions

  • the present disclosure relates to the field of communications, and in particular to a method and device for testing PCBs.
  • PCBA printed Circuit Board + Assembly, PCB for short
  • the problem of device stress failure has become increasingly prominent, which has become a bottleneck restricting the improvement of product performance and customer evaluation.
  • the PCBA mentioned in the following refers to the circuit board product after the empty PCB board has been assembled with electronic components through SMT and plug-in processes.
  • the stress means that when an object is deformed due to external factors (force, humidity, temperature field changes, etc.), internal forces that interact between various parts of the object are generated to resist the action of such external factors and try to deform the object The rear position is restored to the position before the deformation.
  • the stress failure means that under the condition that the PCBA is subjected to external stress, the PCB, device body, solder joints, etc. contained in the PCBA are deformed, causing the material to appear plastic fracture, fatigue fracture and other damage forms, resulting in the overall or partial mechanical Failure of electrical performance.
  • the PCBA industry in order to measure and evaluate the above-mentioned stress failure risk of its products, the PCBA industry usually sticks strain gauges on specific positions on the PCB surface to measure the strain, which is used to characterize the stress risk of the target location or target object.
  • the specific location is usually located on the upper or lower surface of the PCB.
  • the test procedure of the prior art is: remove the interference at the target position with a knife or soldering iron-sand the target position-clean the target position with alcohol-stick the strain gauge to the target position-connect the strain gauge to the collector-test the strain .
  • the above process has the following shortcomings: (1) The test needs to clean and polish the target location, causing damage to the local devices, surface layers, conductive layers, etc., which is equivalent to destroying the entire PCBA, resulting in high cost of test samples. (2) The strain gauge is pasted without reference, and it is difficult to paste it accurately according to the standard, resulting in lower accuracy and validity of test data.
  • the embodiments of the present disclosure provide a method and a device for determining a PCB, so as to at least solve the problem of high cost caused by the scrapping of the PCB after the traditional test method in the related art.
  • a PCB testing method including: determining the position of an area to be tested on the PCB; removing a designated layer at the position to expose the surface of the insulating layer to generate the area to be tested ; Use the auxiliary image marks set around the area to be tested to adjust and place the strain gauge on the area to be tested for bonding; connect the test equipment to the strain gauge and test the area to be tested .
  • a device for determining a printed circuit board PCB including: a determining module configured to determine the position of the area to be tested on the PCB; and the removing module configured to remove the position of the Specify the layer to expose the surface of the insulating layer to generate the area to be tested; the bonding module is set to use auxiliary image marks set around the area to be tested in the PCB, adjust and place the strain gauge on the area to be tested Bonding; a test module, which is configured to connect a test device to the strain gauge and test the area to be tested.
  • a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.
  • an electronic device including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute any one of the foregoing Steps in the method embodiment.
  • Fig. 1 is a flowchart of a method for determining a PCB according to an embodiment of the present disclosure
  • Fig. 2 is a PCB for testing according to an embodiment of the present disclosure
  • FIG. 3 is a cross-sectional view of a PCB used for testing according to an embodiment of the present disclosure
  • Fig. 4 is another PCB for testing according to an embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional view of a PCB used for testing according to an embodiment of the present disclosure
  • Fig. 6 is a structural block diagram of a PCB determining device according to an embodiment of the present disclosure.
  • FIG. 1 is a flowchart of a PCB determination method according to an embodiment of the present disclosure. As shown in FIG. 1, the process includes the following steps:
  • Step S102 determining the position of the area to be tested on the PCB
  • Step S104 removing the designated layer at the position to expose the surface of the insulating layer to generate the area to be tested;
  • Step S106 using auxiliary image marks set around the area to be tested, adjust and place a strain gauge on the area to be tested for bonding;
  • Step S108 connecting a testing device to the strain gauge and testing the area to be tested.
  • step S102 and step S104 are implemented in the design phase, and the specific location requirements and removal methods are configured in the design file, instead of determining the test location and corresponding removal during the test process. . Therefore, the problem of high cost caused by the scrapping of the PCB after the traditional test method is tested is avoided.
  • strain gauges are thin slices that can locally deform relative objects under the action of external forces and non-uniform temperature fields.
  • setting the auxiliary image mark around the designated area includes: setting a plurality of auxiliary positioning points around the area to be tested at a preset angle through a screen printing process, wherein the The center of the intersection of the extension lines of the multiple auxiliary positioning points is the center of the area to be tested.
  • the strain gauge includes at least one of the following: a triaxial strain gauge and a uniaxial strain gauge.
  • the strain gauge is the triaxial strain gauge, wherein it is determined that the area to be tested is The position on the PCB includes: extending according to a predetermined length according to the diagonal of the BGA chip to determine the position of the area to be tested, and/or determining the position corresponding to the back of the solder joint of the BGA chip; The determined location determines the area to be tested.
  • BGA Ball Grid Array
  • a PCB whose secondary outer layer is an insulating layer in the designated area, and the designated layer is the outermost insulating layer; a PCB whose secondary outer layer is a conductive layer in the designated area, and the designated layer is The outermost insulating layer and the second outer conductive layer; wherein, the insulating layer is removed by means of solder resist window opening; the second outer conductive layer is removed by etching.
  • the method further includes: cleaning the area to be tested.
  • placing a strain gauge on the area to be tested for bonding includes: adding an adhesive to the strain gauge and/or the cleaned area to be tested; in the area to be tested Press the strain gauge to make the strain gauge adhere to the surface of the insulating layer.
  • the method further includes: cleaning the area to be tested.
  • organic solvents such as alcohol can be used as cleaning agents to remove oxides, oil stains and other impurities on the surface of the target area to be tested.
  • the above operations contribute to the stability of the test and the protection of the PCB.
  • placing a strain gauge on the cleaned area to be tested for bonding includes: adding an adhesive to the strain gauge and the cleaned area to be tested; in the area to be tested Press the strain gauge to make the strain gauge adhere to the surface of the insulating layer.
  • the above-mentioned adhesives can be 502 adhesives or special adhesives for strain gauges in the industry, so that the strain gauges can be closely combined with the conductive layer or secondary outer insulating layer of the measured area. Accurately sense the strain of the measured area.
  • this embodiment also provides the following two scenarios to understand the foregoing technical solutions.
  • Scenario 1 Using three-axis strain gauges to test the strain of solder joints of BGA chips.
  • FIG. 2 is a PCB for testing according to an embodiment of the present disclosure. As shown in FIG. 2, FIG. 2 includes: a substrate 20, a BGA chip 21, an area to be tested 22, and auxiliary image marks 231, 232, and 233.
  • the area to be tested specifically refers to the position of the diagonal extension of the BGA chip 21 by 5 mm, and/or the corresponding position on the back of the 2*2 solder joints of the BGA chip.
  • the triaxial intersection of the triaxial strain gauge is located at the 5mm point of the diagonal extension of the BGA chip, and/or the corresponding point on the back of the 2*2 solder joint of the BGA chip.
  • the triaxial strain gauge is pasted on the surface of the bare insulating layer in the designated pattern area corresponding to the area to be tested.
  • the designated graphic area is a circle or other graphic that can accommodate triaxial strain gauges, and its circle diameter or circumscribed circle diameter is slightly larger than the diameter of the triaxial strain gauge or circumscribed circle used, usually around 5.5 ⁇ 2mm.
  • the center of the designated graphic area is located on the diagonal epitaxy and/or the corresponding point on the back of the 2*2 solder joint of the BGA chip.
  • the area to be tested there is at least one designated pattern area that exposes the inner insulating layer, and the triaxial strain gauge is attached to the surface of the insulating layer.
  • an auxiliary graphic logo is added for auxiliary positioning of the strain gauge placement during the test.
  • the auxiliary graphic logo is to add an auxiliary positioning graphic on the outermost insulating layer near the designated graphic area by the PCB processing technology of screen printing, that is, the auxiliary graphic signs 231, 232 and 233 as shown in Figure 2 at the intersection of the three That corresponds to the intersection of the three-axis strain gauge axis, where 231 is on the diagonal extension of the BGA chip.
  • the angle between 232 and 233 is 90°, and the angle between 231 and 232 is 45°. Any one or any combination of 231, 232 and 233 can be used as a possibility of auxiliary positioning graphics for triaxial strain gauges.
  • FIG. 3 is a cross-sectional view of a PCB used for testing according to an embodiment of the present disclosure. As shown in FIG. 3, on the basis of FIG. 2, FIG. 3 also includes: the outermost insulating layer 31, the secondary outer insulating layer 32, the PCB inner layer 33 and the surface 34 of the area to be tested.
  • the PCB board is specifically composed of an outermost insulating layer 31, a secondary outer insulating layer 32, and other inner layers 33.
  • the outermost insulating layer 31 can be specifically implemented by a solder resist layer for insulation and surface protection of the PCB.
  • the secondary outer insulating layer 32 may be specifically realized by an insulating medium for insulation.
  • the outermost insulating layer 31 in the designated pattern area is removed by the PCB processing technology of solder mask opening window, so that the upper surface 34 of the secondary outer insulating layer 32 in the designated pattern area is exposed.
  • Step 1 Clean the area to be tested with alcohol, and the specific cleaning object is the exposed insulating layer surface 34 of the area.
  • Step 2 Add adhesive to the adhesive surface of the strain gauge and/or the insulating layer surface 34 in the area to be tested.
  • Step 3 Place the strain gauge in the area to be tested, and adjust the strain gauge to the correct angle with reference to the auxiliary image marks 231-233.
  • Step 4 Press the strain gauge until the adhesive is cured, so that the strain gauge is bonded to the surface of the insulating layer of the area to be tested.
  • Step 5 Connect the data cable that comes with the strain gauge to the existing strain test instrument.
  • Step 6 Turn on the strain test instrument and perform a strain test.
  • Scenario 2 Applied to the strain test of unidirectional stress risk.
  • Fig. 4 is another PCB for testing according to an embodiment of the present disclosure. As shown in Fig. 4, Fig. 4 includes: a substrate 40, an area to be tested 41, and auxiliary image marks 421, 422.
  • the test principle of unidirectional strain in the stress risk area is parallel to the stress risk direction, and it is in a position that can fully characterize the maximum or typical strain value of the area.
  • a uniaxial strain gauge is attached to the surface of the bare insulating layer in the area to be tested corresponding to the stress risk area.
  • the area to be tested is rectangular or other graphics that can accommodate uniaxial strain gauges, and its size is slightly larger than the size of the uniaxial strain gauge used.
  • the graphic specification of this example is 4.3mm*1.9mm.
  • At least one area to be tested exposes the inner insulating layer, and the uniaxial strain gauge is attached to the surface of the insulating layer.
  • auxiliary graphic logo is added for auxiliary positioning of the strain gauge placement during the test.
  • Auxiliary graphic identification is to add auxiliary positioning graphics on the outermost insulating layer near the area to be tested by the PCB processing technology of screen printing, namely 421 and 422 as shown in Figure 4, located on the central axis of the rectangular graphic shown , And parallel to the long side of the rectangle. Any one or any combination of 421 and 422 can be used as a possibility of auxiliary positioning graphics for uniaxial strain gauges.
  • Fig. 5 is a cross-sectional view of a PCB used for testing according to an embodiment of the present disclosure. As shown in Fig. 3, on the basis of Fig. 4, Fig. 5 also includes: the outermost insulating layer 51, the secondary outer conductive layer 52, and the adjacent insulating layers of the secondary outer conductive layer 52 in the direction pointing to the inside of the PCB Layer 53, PCB internal layer 54 and surface 55 of the area to be tested.
  • the outermost insulating layer 51 can be specifically implemented by a solder resist layer for insulation and surface protection of the PCB.
  • the secondary outer conductive layer 52 may be specifically implemented by copper foil, which is used to realize current conduction.
  • the adjacent insulating layer 53 of the secondary outer conductive layer in the direction pointing to the inside of the PCB can be specifically realized by a resin insulating layer for insulation.
  • the outermost insulating layer 51 in the designated pattern area is removed by the PCB processing technique of solder mask and window opening, and the secondary outer conductive layer 52 of the designated pattern area is removed by the etching PCB processing technique to make the secondary outer layer conductive
  • the upper surface 55 of the adjacent insulating layer 53 in the direction pointing to the inside of the PCB is exposed.
  • Step 1 Clean the area to be tested with alcohol.
  • the specific cleaning object is the exposed insulating layer surface 55 of the area.
  • Step 2 Add adhesive to the adhesive surface of the strain gauge and/or the insulating layer surface 55 in the area to be tested.
  • Step 3 Place the strain gauge in the area to be tested, and adjust the strain gauge to the correct angle with reference to the auxiliary image marks 421-422.
  • Step 4 Press the strain gauge until the adhesive is cured, so that the strain gauge is bonded to the surface of the insulating layer of the area to be tested.
  • Step 5 Connect the data cable that comes with the strain gauge to the existing strain test instrument.
  • Step 6 Turn on the strain test instrument and perform a strain test.
  • the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is Better implementation.
  • the technical solution of the present disclosure essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, The optical disc) includes several instructions to enable a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in each embodiment of the present disclosure.
  • a PCB testing device is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementations, and those that have been explained will not be repeated.
  • the term "module” can implement a combination of software and/or hardware with predetermined functions.
  • the devices described in the following embodiments are preferably implemented by software, hardware or a combination of software and hardware is also possible and conceived.
  • Fig. 6 is a structural block diagram of a PCB determining device according to an embodiment of the present disclosure. As shown in Fig. 6, the device includes: a determining module 62 configured to determine the position of the area to be tested on the PCB;
  • the removing module 64 is configured to remove the designated layer at the position to expose the surface of the insulating layer to generate the area to be tested;
  • the bonding module 66 is configured to use auxiliary image marks set around the area to be tested in the PCB to adjust and place the strain gauge on the area to be tested for bonding;
  • the test module 68 is configured to connect a test device to the strain gauge and test the area to be tested.
  • each of the above modules can be implemented by software or hardware.
  • it can be implemented in the following manner, but not limited to this: the above modules are all located in the same processor; or, the above modules are combined in any combination The forms are located in different processors.
  • the embodiment of the present disclosure also provides a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any of the foregoing method embodiments when running.
  • the above-mentioned storage medium may be configured to store a computer program for performing the following steps: S1, determining the position of the area to be tested on the PCB;
  • the foregoing storage medium may include, but is not limited to: U disk, Read-Only Memory (Read-Only Memory, ROM for short), Random Access Memory (Random Access Memory, RAM for short), Various media that can store computer programs, such as mobile hard disks, magnetic disks, or optical disks.
  • An embodiment of the present disclosure also provides an electronic device, including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the foregoing method embodiments.
  • the aforementioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the aforementioned processor, and the input-output device is connected to the aforementioned processor.
  • the foregoing processor may be configured to execute the following steps through a computer program:
  • modules or steps of the present disclosure can be implemented by a general computing device, and they can be concentrated on a single computing device or distributed in a network composed of multiple computing devices.
  • they can be implemented with program codes executable by the computing device, so that they can be stored in the storage device for execution by the computing device, and in some cases, can be executed in a different order than here.
  • the auxiliary image identification set around the area to be tested is used to determine, therefore, it can solve the problem of high cost caused by traditional testing methods that PCB will be scrapped after testing, and achieve the effect of reducing PCB testing costs. .

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  • Microelectronics & Electronic Packaging (AREA)
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  • Investigating Strength Of Materials By Application Of Mechanical Stress (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)

Abstract

一种印制电路板PCB的处理方法，包括：确定待测试的区域（22，41）在PCB上的位置（S102）；去除该位置的指定层（31；51，52），以裸露绝缘层表面（34，55）生成待测试区域（22，41）（S104）；利用待测试区域（22，41）周围设置的辅助图像标识（231，232，233；421，422），调整并将应变片放置在待测试区域（22，41）上进行粘合（S106）；将测试设备接入至应变片并对待测试区域（22，41）进行测试（S108）。还公开了印制电路板PCB的处理装置。解决了传统测试方法在测试后PCB会报废带来的高昂成本的问题，达到了降低PCB测试成本的效果。

Description

印制电路板PCB的测试方法及装置方法及装置 技术领域
本公开涉及通信领域，具体而言，涉及一种PCB的测试方法及装置。
背景技术
随着多层印制电路板产品在重量、尺寸、复杂度等方面的增大，以及市场对产品可靠性要求的提升，印制电路板(Printed Circuit Board+Assembly，简称PCB)上所组装的器件的应力失效问题日益突出，成为制约产品性能和客户评价提升的瓶颈。下文中所述的PCBA是指PCB空板经过SMT和插件等工序，组装了电子元器件之后的电路板产品。所述应力是指物体由于外因(受力、湿度、温度场变化等)而变形时，在物体内各部分之间产生相互作用的内力，以抵抗这种外因的作用，并试图使物体从变形后的位置恢复到变形前的位置。所述应力失效是指PCBA在受到外部应力的条件下，PCBA所包含的PCB、器件本体、焊点等产生形变，使材料出现塑性断裂、疲劳断裂等破坏形态，导致PCBA整体或局部的机械、电气等性能失效。
现有技术中，PCBA行业为衡量评估其产品所受的上述应力失效风险，通常在PCB表面特定位置粘贴应变片以测量应变，用于表征目标位置或目标对象的应力风险。该特定位置通常位于PCB上表面或下表面。现有技术测试流程为：用刀具或烙铁除去目标位置的干涉物——砂纸打磨目标位置——酒精清洁目标位置——将应变片粘贴到目标位置——应变片连接到采集仪——测试应变。
然而上述流程中存在如下的缺点：(1)测试需清理打磨目标位置，对局部区域的器件、表层、导电层等造成破坏，即等于破坏整个PCBA，导致测试样本成本高昂。(2)应变片粘贴无参考物，难以准确地按标准粘贴，导致测试数据准确性和有效性较低。
发明内容
本公开实施例提供了一种PCB的确定方法及装置，以至少解决相关技术中传统测试方法在测试后PCB会报废带来的高昂成本的问题。
根据本公开的一个实施例，提供了一种PCB的测试方法，包括：确定待测试的区域在PCB上的位置；去除该位置的指定层，以裸露所述绝缘层表面生成所述待测试区域；利用所述待测试区域周围设置的辅助图像标识，调整并将应变片放置在所述待测试区域上进行粘合；将测试设备接入至所述应变片并对所述待测试区域进行测试。
根据本公开的又一个实施例，还提供了一种印制电路板PCB的确定装置，包括：确定模块，设置为确定待测试的区域在PCB上的位置；去除模块，设置为去除该位置的指定层，以裸露所述绝缘层表面生成所述待测试区域；粘合模块，设置为利用PCB中待测试区域周围设置的辅助图像标识，调整并将应变片放置在所述待测试区域上进行粘合；测试模块，设置为将测试设备接入至所述应变片并对所述待测试区域进行测试。
根据本公开的又一个实施例，还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
根据本公开的又一个实施例，还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项方法实施例中的步骤。
通过本公开，由于利用所述待测试区域周围设置的辅助图像标识确定，因此，可以解决了传统测试方法在测试后PCB会报废带来的高昂成本的问题，达到了降低PCB测试成本的效果。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本申请的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公 开的不当限定。在附图中：
图1是根据本公开实施例的一种PCB的确定方法的流程图；
图2是根据本公开实施例的一种用于进行测试的PCB；
图3是根据本公开实施例的一种用于进行测试的PCB剖面图；
图4是根据本公开实施例的另一种用于进行测试的PCB；
图5是根据本公开实施例的一种用于进行测试的PCB剖面图；
图6是根据本公开实施例的一种PCB的确定装置的结构框图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
实施例1
在本实施例中提供了一种PCB的测试方法，图1是根据本公开实施例的一种PCB的确定方法的流程图，如图1所示，该流程包括如下步骤：
步骤S102，确定待测试的区域在PCB上的位置；
步骤S104，去除该位置的指定层，以裸露所述绝缘层表面生成所述待测试区域；
步骤S106，利用所述待测试区域周围设置的辅助图像标识，调整并将应变片放置在所述待测试区域上进行粘合；
步骤S108，将测试设备接入至所述应变片并对所述待测试区域进行测试。
需要说明的是，步骤S102与步骤S104是在设计阶段实现的，同时具体的确定位置的要求和去除的方式则是配置设计文件当中，而非在测试过 程中再进行确定测试位置以及相应的去除。因此，避免了传统测试方法在测试后PCB会报废带来的高昂成本的问题。
具体需要解释的是，应变的含义为，在外力和非均匀温度场等因素作用下物体局部的相对变形。因此，应变片是能够在外力和非均匀温度场等因素作用下物体局部的相对变形的薄片。
可选地，将所述辅助图像标识设置在所述指定区域周围，包括：通过丝网印刷加工工艺，将多个辅助定位点按照预设角度设置在所述待测试区域周围，其中，所述多个辅助定位点延长线交叉的中心为所述待测试区域的中心。
可选地，所述应变片至少包括以下其中之一：三轴应变片，单轴应变片。
可选地，在所述待测试对象为焊球阵列封装(Ball Grid Array，简称为BGA)芯片时，所述应变片为所述三轴应变片，其中，确定所述待测试的区域在所述PCB上的位置，包括：根据所述BGA芯片的对角线按照预设长度进行外延，以确定所述待测试区域的位置，和/或确定所述BGA芯片焊点背面对应的位置；根据确定后的位置确定所述待测试区域。
可选地，在所述指定区域内次外层为绝缘层的PCB，所述指定层为最外层绝缘层；在所述指定区域内次外层为导电层的PCB，所述指定层为最外层绝缘层和次外层导电层；其中，所述绝缘层通过阻焊开窗方式去除；所述次外层导电层通过蚀刻方式去除。
可选地，在调整并将应变片放置在所述待测试区域上进行粘合之前，所述方法还包括：对所述待测试区域进行清洁。
可选地，将应变片放置在所述待测试区域上进行粘合，包括：在所述应变片和/或清洁后的所述待测试区域上添加粘合剂；在所述待测试区域中按压所述应变片以使所述应变片与所述绝缘层表面粘合。
需要指出的是，通过裸露绝缘层表面，而不是将整个PCB的待测试区域进行打磨，因此在测试过程中，既不会对局部区域的器件、表层、导 电层等造成破坏，同时节省了对成品PCB进行表面打磨的时间，因此，也变相提高了测试的效率。
可选地，在调整并将应变片放置在所述待测试区域上进行粘合之前，所述方法还包括：对所述待测试区域进行清洁。
具体而言，上述实施例中提到的清洁目标待测试区域工序，可以采用酒精等有机溶剂作为清洗剂，用于去除目标待测试区域表面的氧化物、油污等杂质。上述操作有助于测试的稳定性和PCB的保护。
可选地，将应变片放置在清洁后的所述待测试区域上进行粘合，包括：在所述应变片和清洁后的所述待测试区域上添加粘合剂；在所述待测试区域中按压所述应变片以使所述应变片与所述绝缘层表面粘合。
具体而言，上述提到的粘合剂，可以采用业界已有的502粘合剂或应变片专用粘合剂等，使应变片能与被测区域的导电层或次外绝缘层紧密结合，准确感应被测区域的应变。
为了更好的理解上述实施例中记载的技术方案，本实施例中还提供了如下两个场景，以便理解上述技术方案。
场景一：应用三轴应变片测试BGA芯片焊点应变的测试。
图2是根据本公开实施例的一种用于进行测试的PCB，如图2所示，图2中包括：基板20，BGA芯片21，待测试区域22，辅助图像标识231,232以及233。
如图2所示，待测试区域特指该BGA芯片21的对角线外延5mm位置，和/或BGA芯片2*2焊点背面对应位置。同时，三轴应变片的三轴交叉点位于BGA芯片对角线外延5mm点处，和/或BGA芯片2*2焊点背面对应点处。
需要说明的是，上述举例只是一种可选的方式，在实际应用当中，可以根据不同规格的PCB对参数进行调整，下同，在此不做过多赘述。
三轴应变片粘贴在待测试区域对应的指定图形区域内的裸露绝缘层 表面。指定图形区域为圆形或其他可容纳三轴应变片的图形，其圆直径或外切圆直径稍大于所用三轴应变片的直径或外切圆直径，通常在5.5±2mm左右。具体而言，该指定图形区域的中心位于对角线外延上和/或BGA芯片2*2焊点背面对应点。
具体而言，在场景1中，基板30的表层，待测试区域内(区域可不连续)，有至少一个指定图形区域露出内层绝缘层，三轴应变片粘贴于此绝缘层表面。
在该指定图形区域外，添加辅助图形标识，用于测试过程中应变片放置的辅助定位。该辅助图形标识，是在指定图形区域附近的最外层绝缘层上，以丝网印刷的PCB加工工艺添加辅助定位图形，即如图2所示的辅助图像标识231,232以及233，三者交叉点即对应三轴应变片轴交叉点，其中231在BGA芯片对角线延长线上。232和233夹角为90°，231和232夹角为45°。231,232以及233中的任意一个或任意几个的组合，均可作为三轴应变片适用的辅助定位图形的一种可能。
图3是根据本公开实施例的一种用于进行测试的PCB剖面图。如图3所示，在图2的基础之上，图3中还包括：最外层绝缘层31、次外层绝缘层32，以及PCB内部层33，待测试区域表面34。
场景1中，所述PCB板具体由最外层绝缘层31、次外层绝缘层32以及内部其他层33组成。其中，最外层绝缘层31可具体由阻焊层实现，用于绝缘和PCB的表面防护。次外层绝缘层32可具体由绝缘介质实现，用于绝缘。
如图3所示，以阻焊开窗的PCB加工工艺去除指定图形区域的最外层绝缘层31，使得指定图形区域的次外层绝缘层32上表面的34裸露。
在完成上述准备工作后，场景1中的PCB的测试流程如下：
步骤1：用酒精清洁待测试区域，具体清洁对象为该区域裸露的绝缘层表面34。
步骤2：在应变片的粘贴面，和/或待测试区域内的绝缘层表面34，添 加粘合剂。
步骤3：将应变片放置到待测试区域，并参考辅助图像标识231-233调整应变片至正确角度。
步骤4：按压应变片至粘合剂固化，使应变片粘接到待测试区域的绝缘层表面。
步骤5：将应变片自带数据线连接到已有的应变测试仪器上。
步骤6：开启应变测试仪器，进行应变测试。
场景二：应用于单向应力风险的应变测试。
图4是根据本公开实施例的另一种用于进行测试的PCB，如图4所示，图4中包括：基板40，待测试区域41，辅助图像标识421,422。
具体而言，应力风险区域的单向应变的测试原则：单轴应变片的轴向平行于应力风险方向，且处于能够充分表征该区域最大或典型应变值的位置。
在场景2中，单轴应变片粘贴在应力风险区域对应的待测试区域内的裸露绝缘层表面。待测试区域为矩形或其他可容纳单轴应变片的图形，其尺寸稍大于所用单轴应变片的尺寸，本实例图形规格为4.3mm*1.9mm。
在场景2中，在PCB基板40的表层，应力风险区域内(区域可不连续)，有至少一个待测试区域露出内层绝缘层，单轴应变片粘贴于此绝缘层表面。
在场景2中，在该待测试区域外，添加辅助图形标识，用于测试过程中应变片放置的辅助定位。辅助图形标识，是在待测试区域附近的最外层绝缘层上，以丝网印刷的PCB加工工艺添加辅助定位图形，即如图4所示的421及422，位于所示矩形图形的中轴线上，且平行于矩形长边方向。421及422中的任意一个或任意几个的组合，均可作为单轴应变片适用的辅助定位图形的一种可能。
图5是根据本公开实施例的一种用于进行测试的PCB剖面图。如图3所示，在图4的基础之上，图5中还包括：最外层绝缘层51、次外层导电层52，次外层导电层52在指向PCB内部方向上的相邻绝缘层53，PCB内部层54以及待测试区域表面55。
其中，最外层绝缘层51可具体由阻焊层实现，用于绝缘和PCB的表面防护。次外层导电层52可具体由铜箔实现，用于实现电流导通。次外层导电层在指向PCB内部方向上的相邻绝缘层53可具体由树脂绝缘层实现，用于绝缘。
如图5所示，以阻焊开窗的PCB加工工艺去除指定图形区域的最外层绝缘层51，以蚀刻的PCB加工工艺去除指定图形区域的次外层导电层52，使得次外层导电层在指向PCB内部方向上的相邻绝缘层53的上表面55裸露。
在完成上述准备工作后，场景2中的PCB的测试流程如下：
步骤1：用酒精清洁待测试区域，具体清洁对象为该区域裸露的绝缘层表面55。
步骤2：在应变片的粘贴面，和/或待测试区域内的绝缘层表面55，添加粘合剂。
步骤3：将应变片放置到待测试区域，并参考辅助图像标识421-422调整应变片至正确角度。
步骤4：按压应变片至粘合剂固化，使应变片粘接到待测试区域的绝缘层表面。
步骤5：将应变片自带数据线连接到已有的应变测试仪器上。
步骤6：开启应变测试仪器，进行应变测试。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理 解，本公开的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本公开各个实施例所述的方法。
实施例2
在本实施例中还提供了一种PCB的测试装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图6是根据本公开实施例的一种PCB的确定装置的结构框图，如图6所示，该装置包括：确定模块62，设置为确定待测试的区域在PCB上的位置；
去除模块64，设置为去除该位置的指定层，以裸露所述绝缘层表面生成所述待测试区域；
粘合模块66，设置为利用PCB中待测试区域周围设置的辅助图像标识，调整并将应变片放置在所述待测试区域上进行粘合；
测试模块68，设置为将测试设备接入至所述应变片并对所述待测试区域进行测试。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
实施例3
本公开的实施例还提供了一种存储介质，该存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
可选地，在本实施例中，上述存储介质可以被设置为存储用于执行以下步骤的计算机程序：S1，确定待测试的区域在PCB上的位置；
S2，去除该位置的指定层，以裸露所述绝缘层表面生成所述待测试区域；
S3，利用所述待测试区域周围设置的辅助图像标识，调整并将应变片放置在所述待测试区域上进行粘合；
S4，将测试设备接入至所述应变片并对所述待测试区域进行测试。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
本公开的实施例还提供了一种电子装置，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
可选地，上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
可选地，在本实施例中，上述处理器可以被设置为通过计算机程序执行以下步骤：
S1，确定待测试的区域在PCB上的位置；
S2，去除该位置的指定层，以裸露所述绝缘层表面生成所述待测试区域；
S3，利用所述待测试区域周围设置的辅助图像标识，调整并将应变片放置在所述待测试区域上进行粘合；
S4，将测试设备接入至所述应变片并对所述待测试区域进行测试。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本公开的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
工业实用性
基于上述技术方案，由于利用所述待测试区域周围设置的辅助图像标识确定，因此，可以解决了传统测试方法在测试后PCB会报废带来的高昂成本的问题，达到了降低PCB测试成本的效果。

Claims (10)

  1. 一种印制电路板PCB的处理方法，包括：
    确定待测试的区域在PCB上的位置；
    去除该位置的指定层，以裸露所述绝缘层表面生成所述待测试区域；
    利用所述待测试区域周围设置的辅助图像标识，调整并将应变片放置在所述待测试区域上进行粘合；
    将测试设备接入至所述应变片并对所述待测试区域进行测试。
  2. 根据权利要求1所述的方法，其中，将所述辅助图像标识设置在所述指定区域周围，包括：
    通过丝网印刷加工工艺，将多个辅助定位点按照预设角度设置在所述待测试区域周围，其中，所述多个辅助定位点延长线交叉的中心为所述待测试区域的中心。
  3. 根据权利要求1或2任一项所述的方法，其中，所述应变片至少包括以下其中之一：三轴应变片，单轴应变片。
  4. 根据权利要求3所述的方法，其中，在所述待测试对象为焊球阵列封装BGA芯片时，所述应变片为所述三轴应变片，其中，确定所述待测试的区域在所述PCB上的位置，包括：
    根据所述BGA芯片的对角线按照预设长度进行外延，以确定所述待测试区域的位置，和/或确定所述BGA芯片焊点背面对应的位置；
    根据确定后的位置确定所述待测试区域。
  5. 根据权利要求1所述的方法，其中，包括：
    在所述指定区域内次外层为绝缘层的PCB，所述指定层为最外层绝缘层；
    在所述指定区域内次外层为导电层的PCB，所述指定层为最外层绝缘层和次外层导电层；
    其中，所述绝缘层通过阻焊开窗方式去除；所述次外层导电层通过蚀刻方式去除。
  6. 根据权利要求1所述的方法，其中，包括：在调整并将应变片放置在所述待测试区域上进行粘合之前，所述方法还包括：对所述待测试区域进行清洁。
  7. 根据权利要求6所述的方法，其中，将应变片放置在所述待测试区域上进行粘合，包括：
    在所述应变片和/或清洁后的所述待测试区域上添加粘合剂；
    在所述待测试区域中按压所述应变片以使所述应变片与所述绝缘层表面粘合。
  8. 一种印制电路板PCB的处理装置，包括：
    确定模块，设置为确定待测试的区域在PCB上的位置；
    去除模块，设置为去除该位置的指定层，以裸露所述绝缘层表面生成所述待测试区域；
    粘合模块，设置为利用PCB中待测试区域周围设置的辅助图像标识，调整并将应变片放置在所述待测试区域上进行粘合；
    测试模块，设置为将测试设备接入至所述应变片并对所述待测试区域进行测试。
  9. 一种计算机可读的存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求1至7任一项中所述的方法。
  10. 一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行所述权利要求1至7任一项中所述的方法。
PCT/CN2020/099015 2019-07-02 2020-06-29 印制电路板pcb的测试方法及装置方法及装置 WO2021000842A1 (zh)

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