WO2020262775A1 - Dispositif et procédé de décodage d'un code polaire - Google Patents

Dispositif et procédé de décodage d'un code polaire Download PDF

Info

Publication number
WO2020262775A1
WO2020262775A1 PCT/KR2019/015834 KR2019015834W WO2020262775A1 WO 2020262775 A1 WO2020262775 A1 WO 2020262775A1 KR 2019015834 W KR2019015834 W KR 2019015834W WO 2020262775 A1 WO2020262775 A1 WO 2020262775A1
Authority
WO
WIPO (PCT)
Prior art keywords
partial sum
pruning
operation unit
node
candidate
Prior art date
Application number
PCT/KR2019/015834
Other languages
English (en)
Korean (ko)
Inventor
이제민
이영주
감동윤
Original Assignee
재단법인대구경북과학기술원
포항공과대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 재단법인대구경북과학기술원, 포항공과대학교 산학협력단 filed Critical 재단법인대구경북과학기술원
Publication of WO2020262775A1 publication Critical patent/WO2020262775A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing

Definitions

  • the present invention relates to an extreme code decoding apparatus and method, and in particular, to an extreme code decoding apparatus and method for implementing ultra-low latency characteristics in 5G and next-generation wireless communication.
  • the 5G communication system or the pre-5G communication system is called a communication system after a 4G network (Beyond 4G Network) or a system after an LTE system (Post LTE).
  • the 5G communication system is being considered for implementation in the ultra-high frequency (mmWave) band (eg, such as the 60 Giga (60 GHz) band).
  • mmWave ultra-high frequency
  • ACM advanced coding modulation
  • FQAM Hybrid FSK and QAM Modulation
  • SWSC Soliding Window Superposition Coding
  • FBMC Filter Bank Multi Carrier
  • NOMA non orthogonal multiple access
  • SCMA sparse code multiple access
  • IoT Internet of Things
  • M2M Machine to machine
  • MTC Machine Type Communication
  • IoT Internet Technology
  • IoT is the field of smart home, smart building, smart city, smart car or connected car, smart grid, healthcare, smart home appliance, advanced medical service, etc. through the convergence and combination of existing IT (information technology) technology and various industries. Can be applied to.
  • a 5G communication system to an IoT network.
  • technologies such as sensor network, machine to machine (M2M), and MTC (Machine Type Communication) are implemented by techniques such as beamforming, MIMO, and array antenna, which are 5G communication technologies.
  • M2M machine to machine
  • MTC Machine Type Communication
  • beamforming MIMO
  • array antenna which are 5G communication technologies.
  • cloud RAN cloud radio access network
  • an error correction coding scheme exists as a coding scheme designed to correct an error generated by a communication channel in a receiver.
  • This error correction code is also referred to as channel coding.
  • the error correction coding technique is a technique in which redundancy bits are added to the data to be transmitted and transmitted.
  • error correction coding techniques there are various methods of error correction coding techniques. For example, there are convolutional coding, turbo coding, LDPC coding, and polar coding.
  • the polar code technique is the first code that has been theoretically proven to achieve a point-to-point channel capacity by using channel polarization.
  • the extreme code it is possible to design a code optimized for each channel or code rate through density evolution and reciprocal channel approximation (RCA).
  • RCA reciprocal channel approximation
  • index sequence polar code sequence
  • eMBB Enhanced Mobile Broadband
  • URLLC Ultra-Reliable and Low Latency Communication
  • mMTC Massive Machine Type Communication
  • the polar decoding system was adopted by 3GPP, a standardization organization, as an error correction system for 5G wireless communication control channels.
  • Polar abdominal coding systems include SC (Successive Cancellation), SSC (Simplified Successive Cancellation), SCL (Successive Cancellation List), Fast-SSCL-SPC (Fast-simplified SCL-SPC), and the like.
  • the SCL scheme proposed to improve the error correction performance of the existing SC decoding method could improve the error correction performance, but there is a limitation in that the delay time is long due to the sequential protection characteristics.
  • the SSC method which is another method to compensate for the problem of the SC decoding method, does not visit a child node when all child nodes are frozen bits or information bits, and multi-bits in the corresponding mode. bit).
  • the Fast-SSCL-SPC decoding method can decode several bits at the same time without visiting a lower child node in a special node (Rate-0, Rate-1, REP, SPC) having a specific pattern of the tree.
  • a special node Rate-0, Rate-1, REP, SPC
  • the Fast-SSCL-SPC method has the effect of significantly reducing the delay time compared to the SCL method, but it is known that there is a problem in the utilization of a processing element (PE).
  • PE processing element
  • US Patent No. 10,075,193B2 proposes a decoding algorithm and hardware configuration for the SC scheme, and describes a configuration for reducing the delay time through pruning or comprising in the case of a special node.
  • FIG. 1 is a block diagram of a conventional Fast-SSCL decoding apparatus.
  • a conventional decoding apparatus includes a memory 100 for storing received bits, a processing element 200 for performing an F operation or a G operation according to a node of a received bit of the memory 100. , A metric computing unit (300) that performs pruning to output the decoded information bits, a partial sum network (400) that calculates a subtotal, and an output bit of the memory (100). It includes a pointer 500.
  • the configuration including the memory 100, the processing element 200, the metric operation unit 300, the subtotal network 400, and the pointer 500 is a configuration of an extreme code decoding device, and the decoding device is a separate The operation is controlled by the controller of
  • the decoding device is a device added to a receiver for wireless communication and decodes information data from received data.
  • the controller performs F operation or G operation according to the characteristics of the node to be currently operated, and performs pruning. Pruning is a process of omitting unnecessary node visits along the decoding tree and finally sorting.
  • FIG. 2 is an exemplary diagram of a conventional decoding tree.
  • a decoding tree is a structure in which a layer and a leaf layer of the layer are connected, and a specific leaf node is visited according to log-likelihood ratios (LLR).
  • LLR log-likelihood ratios
  • the node includes a special node.
  • Special nodes are usually labeled as Rate-0, Rate-1, REP, and SPC, and multiple bits can be decoded at the same time without visiting a lower leaf node (or child node).
  • G operation must be performed after pruning of the special node.
  • the G operation or F operation is performed according to the cycle of the system clock, and one system clock is allocated for the operation.
  • F operation F-function
  • G operation G-function
  • the likelihood for the repetitive node may be calculated by performing the G operation.
  • the processing element 200 performs an F operation or a G operation according to the type of a node, and the metric operation unit 300 performs pruning according to the likelihood calculated by the processing element 200 to output the decoded bit value. do.
  • pruning includes sorting, and classification is the most time-consuming process in the pruning process.
  • the processing element 200 becomes an idle state in which no operation is performed. This is because a subtotal, which is an output of the subtotal network 400 in the previous state, is required to perform the G operation.
  • the G operation cannot be performed in advance, and the G operation is possible after the pruning of the previous state is completed.
  • the processing element 200 When pruning of the metric calculation unit 300 is completed, the processing element 200 performs an F operation or a G operation according to the node type again at the next system clock. If the node is a special node, the partial sum of the previous state Perform G operation using.
  • the operation of the processing element 200 is stopped during the pruning process, which acts as a delay factor of the entire decoding apparatus and method.
  • the technical problem to be solved by the present invention in consideration of the above problems is to provide an extreme code decoding apparatus and method capable of further reducing a delay time in an SCL-based decoding scheme.
  • An extreme code decoding apparatus for solving the above problems, performs F operation or G operation according to a memory storing a received bit and a node of the received bit of the memory, Simultaneously with the pruning process, a processing element that performs G operation using Candidate Partial Sum, and outputs the decoded information bits by performing pruning, and sorting during the pruning process Includes a metric computing unit that selectively outputs a previous value, and a partial sum network that calculates a subtotal and calculates and outputs the candidate subtotal using the pre-classification value of the metric calculation unit. do.
  • the processing element includes an F operation unit for performing an F operation, a G operation unit for performing G operation, and a superposition for selecting and outputting one of two operation results of the G operation unit according to the candidate subtotal. It may include an operation unit.
  • the overlapping operation unit includes a pair of multiplexers each selecting one of two operation results of the G operation unit, and the pair of multiplexers is the G operation unit according to different candidate subtotals. One of the two calculation results of can be selected and output.
  • the metric calculation unit selects and outputs one of a metric calculation unit including a plurality of classifiers to perform pruning including sorting, and calculation values of the front end of the classifiers. May contain multiplexers.
  • the polar code decoding method includes: a) checking whether a special node is processed, and b) selecting one of an operation value of the front end of the classifier of claim 4 in the pruning process if the processing is a special node. Steps, c) calculating a candidate partial sum using one of the operation values selected in step b), and d) performing a G operation according to the candidate partial sum value, wherein the G operation and the rounding process The last process can be performed superimposed on the same clock cycle.
  • one of the outputs of the G operation unit that performs the G operation may be selected according to the candidate partial sum.
  • the G operation may be performed by being superimposed on the same clock cycle as the classification process of the pruning process.
  • the extreme code decoding apparatus and method of the present invention has the effect of shortening the delay time by performing the G operation performed after the special node operation in the fast-SSCL method extreme code decoding in the same clock cycle as the operation of the special node. .
  • the polar code decoding apparatus and method of the present invention enables the operation of the PE to be performed in advance without stopping the operation of the PE during the operation of the special node, thereby reducing the delay time.
  • FIG. 1 is a block diagram of a conventional pole code decoding apparatus.
  • FIG. 2 is a block diagram of a conventional decoding tree.
  • FIG. 3 is a block diagram of an extreme code decoding apparatus according to a preferred embodiment of the present invention.
  • FIG. 4 is a block diagram of a processing element applied to the present invention.
  • FIG. 5 is a block diagram of a metric calculation unit applied to the present invention.
  • FIG. 6 is an exemplary diagram of a decoding tree according to the present invention.
  • FIG. 7 is a graph comparing the processing of the present invention and the conventional processing according to the type of special node.
  • each block of the flowchart diagrams and combinations of the flowchart diagrams may be executed by computer program instructions. Since these computer program instructions can be mounted on the processor of a general purpose computer, special purpose computer or other programmable data processing equipment, the instructions executed by the processor of the computer or other programmable data processing equipment are described in the flowchart block(s). It creates a means to perform functions. These computer program instructions can also be stored in computer-usable or computer-readable memory that can be directed to a computer or other programmable data processing equipment to implement a function in a particular way, so that the computer-usable or computer-readable memory It is also possible to produce an article of manufacture containing instruction means for performing the functions described in the flowchart block(s).
  • Computer program instructions can also be mounted on a computer or other programmable data processing equipment, so that a series of operating steps are performed on a computer or other programmable data processing equipment to create a computer-executable process to create a computer or other programmable data processing equipment. It is also possible for instructions to perform processing equipment to provide steps for executing the functions described in the flowchart block(s).
  • each block may represent a module, segment, or part of code that contains one or more executable instructions for executing the specified logical function(s).
  • functions mentioned in blocks may occur out of order. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order depending on the corresponding function.
  • the term' ⁇ unit' used in the present embodiment refers to software or hardware components such as FPGA or ASIC, and' ⁇ unit' performs certain roles.
  • The' ⁇ unit' may be configured to be in an addressable storage medium or may be configured to reproduce one or more processors.
  • ' ⁇ unit' refers to components such as software components, object-oriented software components, class components and task components, processes, functions, properties, and procedures. , Subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, database, data structures, tables, arrays, and variables. Components and functions provided in the' ⁇ units' may be combined into a smaller number of elements and' ⁇ units', or may be further separated into additional elements and' ⁇ units'.
  • components and' ⁇ units' may be implemented to play one or more CPUs in a device or a security multimedia card.
  • the polar code is an error correction code and may have a performance higher than a certain level while having low coding performance and low complexity.
  • the extreme code it is a code that can achieve the data transmission limit, channel capacity, in all binary discrete memoryless channels.
  • the polar code has similar performance to the turbo code and LDPC (low-density parity-check) code, which are other channel capacity proximity codes, and in the case of the polar code, the performance when transmitting a code of a shorter length compared to the other codes. It can have an advantage. Accordingly, it is possible to transmit/receive a signal to which a polar code is applied throughout the communication system, and more specifically, it is possible to consider using a polar code to transmit control information of a predetermined length or less.
  • the polar code is an error correction code that can be defined based on a phenomenon called channel polarization under the assumption of binary discrete memoryless channel (B-DMC).
  • B-DMC binary discrete memoryless channel
  • each bit can be independently and statistically a channel W having the same characteristics.
  • the channel capacity of each channel is 0 ⁇ C(W) ⁇ 1
  • N bits through B-DMC without any operation all channels through which each bit is transmitted have a channel capacity of C(W), and information as much as N ⁇ C(W) bits is theoretically transmitted. Can be.
  • channel polarization The basic concept of channel polarization is to combine (channel combining) and splitting (channel splitting) channels through which N bits pass, so that the channel capacity of the resulting channel experienced by a specific ratio of bits is equal to 1.
  • the channel capacity of the resulting channel which becomes a close value, and the remaining bits experience, can be adjusted to be close to zero.
  • the transmission effect can be maximized by transmitting the information bit to a channel with a high channel capacity after channel polarization and fixing the information bit to a specific value on a channel with a low channel capacity. have.
  • FIG. 3 is a block diagram of a polar decoding apparatus according to an embodiment of the present invention.
  • the extreme code decoding apparatus performs an F operation or a G operation according to a memory 10 storing received bits and a node of a received bit of the memory 10.
  • a processing element (20) that performs G operation in advance using a candidate partial sum, and a decoded information bit by performing pruning are output, but sorting (sorting) )
  • a metric computing unit (30) that provides a candidate partial sum by providing a previous value, a partial sum network (40) that calculates a subtotal, and an output bit of the memory 10 It includes a pointer 50 to designate.
  • the received bits stored in the memory 10 are selected by the pointer 50, and the received bits are input to the processing element 20, and the F operation or the G operation is performed depending on the node.
  • FIG. 4 is a block diagram of the processing element 20 of the present invention.
  • the processing element 20 applied to the present invention includes an F operation unit 21 and a G operation unit 22, and superimposes the selection and output of the G operation result by a candidate partial sum. It is configured to further include an overlaping) operation unit (23).
  • the superposition operation unit 23 includes two multiplexers that select and output one of the two output values of the G operation unit 22 according to a plurality of candidate partial sums (Candidate Partial Sum 0, Candidate Partial Sum 1).
  • the F operation unit 21 and the G operation unit 22 are elements of a typical processing element, and perform F operation or G operation on information bits ⁇ according to nodes.
  • the G operation unit 22 generates two result values, and selects and outputs one of the two result values according to the subtotal.
  • the G operation is performed in advance before the subtotal of the previous state required by the G operation unit 22 is calculated, so that the processing element 20 becomes the idle state by performing the G operation while performing pruning. Can be prevented.
  • FIG. 5 is a block diagram of a metric calculation unit 30 applied to the present invention.
  • a result of the F operation of the processing element 20 or the result of the superimposition G operation of the superimposition operation unit 23 are selectively input and pruned to output decoded bits.
  • the reason why the superimposed G operation result is received is because there is a possibility that the next operation process after the operation of the superimposition operation unit 23 is a pruning operation of a special node.
  • the configuration of the metric calculation unit 30 applied to the present invention includes a metric calculation unit 31 that performs pruning, and a multi-layer for selecting processed values before being input to sorters in the calculation process of the metric calculation unit 31. It consists of a flexor (32).
  • the configuration of the metric calculation unit 31 itself may be the same as that of a typical metric calculation unit (MCU).
  • MCU typical metric calculation unit
  • the value selected by the multiplexer 32 may be selected according to the type of the special node.
  • the value selected by the multiplexer 32 is provided to the subtotal network 40, and the subtotal network 40 obtains a candidate subtotal and provides it to the superposition operation unit 23 of the processing element 20 described above.
  • the G operation can be performed in the processing element 20 together with the sorting process that takes the most time in the pruning process, thereby preventing loss of the system clock cycle.
  • FIG. 6 is an exemplary diagram of a decoding tree according to the present invention.
  • a classification operation is performed in a 5-layer 16-bit decoding tree, and the following G operation is superimposed and calculated.
  • the delay factor because it is not necessary to use a separate system clock for the G operation, which must be performed after the processing of the special node.
  • the delay factor can be further reduced.
  • FIG. 7 is a graph comparing the processing of the present invention and the conventional processing according to the type of special node.
  • the operation of the processing element, the pruning operation of the metric operation unit, and the G operation each use a clock, but in the present invention, the pruning operation of the metric operation unit and the G operation are simultaneously performed The clock cycle can be reduced.
  • Rate 1 the operation of the processing element and the operation of the metric calculation unit occur simultaneously, and in the next clock cycle, the G operation is performed again in the next clock cycle after the sorting operation, but in the present invention, the classification operation and Since the G operation can be performed simultaneously, the clock cycle can be reduced.
  • the G operation was conventionally performed by separating the G operation in a clock cycle following the clock cycle of the classification operation, but in the present invention, the clock cycle can be reduced by overlapping the classification operation and the G operation in the same clock cycle. have.
  • the clock cycle is reduced by overlapping the G operation in the clock cycle for the last parity check.
  • the present invention has a feature of reducing delay by reducing one clock cycle in all special nodes.
  • the present invention is to shorten the delay time by performing the G operation after the special node operation in the same clock cycle as the operation of the special node in Fast-SSCL extreme code decoding using the natural law. There is this.

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

La présente invention concerne un dispositif et un procédé de décodage d'un code polaire, le dispositif comprenant: une mémoire pour stocker un bit reçu ; un élément de traitement pour effectuer un calcul F ou un calcul G selon un nœud d'un bit reçu dans la mémoire, le calcul G étant effectué à l'aide d'une somme partielle candidate simultanément à une procédure d'élagage d'un nœud spécial ; une unité de calcul métrique pour effectuer un élagage afin de délivrer en sortie un bit d'information décodé tout en délivrant sélectivement une valeur avant le tri pendant l'élagage ; et un réseau de somme partielle pour calculer une somme partielle, calculer la somme partielle candidate en utilisant la valeur avant le tri par l'unité de calcul métrique, et délivrer la somme partielle candidate calculée.
PCT/KR2019/015834 2019-06-28 2019-11-19 Dispositif et procédé de décodage d'un code polaire WO2020262775A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2019-0077703 2019-06-28
KR1020190077703A KR102115216B1 (ko) 2019-06-28 2019-06-28 극부호 복호 장치 및 방법

Publications (1)

Publication Number Publication Date
WO2020262775A1 true WO2020262775A1 (fr) 2020-12-30

Family

ID=70914911

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2019/015834 WO2020262775A1 (fr) 2019-06-28 2019-11-19 Dispositif et procédé de décodage d'un code polaire

Country Status (2)

Country Link
KR (1) KR102115216B1 (fr)
WO (1) WO2020262775A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102511779B1 (ko) 2021-04-12 2023-03-17 아주대학교산학협력단 극 부호 연속 제거 비트 반전 복호 장치 및 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170054046A (ko) * 2015-11-09 2017-05-17 삼성전자주식회사 무선 통신 시스템에서 복호화 방법 및 장치
US20170366199A1 (en) * 2016-06-17 2017-12-21 Huawei Technologies Co., Ltd. Apparatus and methods for error detection coding
KR20190013374A (ko) * 2017-07-28 2019-02-11 삼성전자주식회사 통신 또는 방송 시스템에서 극부호 부호화/복호화 방법 및 장치
KR20190051245A (ko) * 2017-11-06 2019-05-15 삼성전자주식회사 폴라 부호 복호화 장치 및 방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102452618B1 (ko) * 2017-06-08 2022-10-11 삼성전자주식회사 미리 정의된 정보를 사용하는 폴라 인코딩 및 디코딩

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170054046A (ko) * 2015-11-09 2017-05-17 삼성전자주식회사 무선 통신 시스템에서 복호화 방법 및 장치
US20170366199A1 (en) * 2016-06-17 2017-12-21 Huawei Technologies Co., Ltd. Apparatus and methods for error detection coding
KR20190013374A (ko) * 2017-07-28 2019-02-11 삼성전자주식회사 통신 또는 방송 시스템에서 극부호 부호화/복호화 방법 및 장치
KR20190051245A (ko) * 2017-11-06 2019-05-15 삼성전자주식회사 폴라 부호 복호화 장치 및 방법

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MOUSAVI, MAHSA ET AL.: "Efficient Partial-Sum Netwolk Architectures for List Successive-Cancellation Decoding of Polar Codes", IEEE TRANSACTIONS ON SIGNAL PROCESSING, vol. 66, 25 August 2018 (2018-08-25), pages 3848 - 3858, XP055778362 *

Also Published As

Publication number Publication date
KR102115216B1 (ko) 2020-05-26

Similar Documents

Publication Publication Date Title
WO2018231023A1 (fr) Procédé de génération de séquence de code polaire, support d'informations associé, et procédé et appareil de transmission de données l'utilisant
AU2018288906B2 (en) Method and apparatus of rate-matching for communication and broadcasting systems
WO2014092516A1 (fr) Procédé et appareil de décodage de paquets
WO2014092502A1 (fr) Procédé et appareil de codage à l'aide d'un code crc et d'un code polaire
WO2018174615A1 (fr) Procédé et appareil de mise en correspondance de débits de codes polaires
WO2011159089A2 (fr) Procédé et appareil de traitement parallèle dans un décodeur ldpc gigabit
CN110268653A (zh) 具有自适应错误检测的级联极化码
WO2017082626A1 (fr) Procédé et appareil de décodage dans un système de communication sans fil
WO2018236114A1 (fr) Procédé et appareil pour l'adaptation de débit pour des systèmes de communication et de diffusion
JP7279779B2 (ja) Ｐｏｌａｒ符号の構築のための方法および装置
JP6803969B2 (ja) 識別情報を搬送するための方法および装置
WO2010074537A2 (fr) Procédé de turbocodage de convolution et dispositif de mise en oeuvre du procédé de codage
CN110402553A (zh) 用于多级控制信息的编码技术
WO2019024594A1 (fr) Procédés, appareils et dispositifs permettant de coder et décoder un code de polarisation
WO2018202140A1 (fr) Procédé, dispositif et appareil de codage
CN112260798B (zh) 一种基于极化码的物理层控制信道盲检测方法
WO2020262775A1 (fr) Dispositif et procédé de décodage d'un code polaire
EP3965345A1 (fr) Procédés d'envoi et de réception d'informations, terminal et dispositif réseau
CN110582942A (zh) 利用分布式crc极化码的提前终止
Shen et al. Low-latency segmented list-pruning software polar list decoder
WO2019021188A1 (fr) Séquences d'information améliorées pour codes polaires
WO2016043509A1 (fr) Procédé et appareil de décodage dans un système utilisant des codes binaires raccordés de manière séquentielle
WO2018176495A1 (fr) Procédé et appareil de transmission de code polaire
WO2020262777A1 (fr) Dispositif de réseau à somme partielle multibits de décodeur sc parallèle
EP3396862A1 (fr) Utilisation de bits de parité et crc pour une terminaison précoce du décodage de code polaire pour des réseaux sans fil

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19935377

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19935377

Country of ref document: EP

Kind code of ref document: A1