WO2020262775A1

WO2020262775A1 - Device and method for decoding polar code

Info

Publication number: WO2020262775A1
Application number: PCT/KR2019/015834
Authority: WO
Inventors: 이제민; 이영주; 감동윤
Original assignee: 재단법인대구경북과학기술원; 포항공과대학교 산학협력단
Priority date: 2019-06-28
Filing date: 2019-11-19
Publication date: 2020-12-30
Also published as: KR102115216B1

Abstract

The present invention relates to a device and a method for decoding a polar code, the device comprising: a memory for storing a received bit; a processing element for performing computation F or computation G according to a node of a received bit in the memory, wherein computation G is performed using a candidate partial sum concurrently with a pruning procedure of a special node; a metric computing unit for performing pruning to output a decoded information bit while selectively outputting a value before sorting during the pruning; and a partial sum network for computing a partial sum, computing the candidate partial sum by using the value before sorting by the metric computing unit, and outputting the computed candidate partial sum.

Description

Polar code decoding apparatus and method

The present invention relates to an extreme code decoding apparatus and method, and in particular, to an extreme code decoding apparatus and method for implementing ultra-low latency characteristics in 5G and next-generation wireless communication.

Efforts are being made to develop an improved 5G communication system or a pre-5G communication system in order to meet the increasing demand for wireless data traffic after the commercialization of 4G communication systems. For this reason, the 5G communication system or the pre-5G communication system is called a communication system after a 4G network (Beyond 4G Network) or a system after an LTE system (Post LTE). In order to achieve a high data rate, the 5G communication system is being considered for implementation in the ultra-high frequency (mmWave) band (eg, such as the 60 Giga (60 GHz) band). In order to mitigate the path loss of radio waves in the ultra high frequency band and increase the transmission distance of radio waves, in 5G communication systems, beamforming, massive MIMO, and Full Dimensional MIMO (FD-MIMO) ), array antenna, analog beam-forming, and large scale antenna technologies are being discussed.

In addition, in order to improve the network of the system, in 5G communication systems, evolved small cells, advanced small cells, cloud radio access networks (cloud RAN), and ultra-dense networks ), Device to Device communication (D2D), wireless backhaul, moving network, cooperative communication, CoMP (Coordinated Multi-Points), and interference cancellation ), and other technologies are being developed. In addition, in the 5G system, advanced coding modulation (ACM) methods such as Hybrid FSK and QAM Modulation (FQAM) and SWSC (Sliding Window Superposition Coding), advanced access technologies such as Filter Bank Multi Carrier (FBMC), NOMA (non orthogonal multiple access), and sparse code multiple access (SCMA) have been developed.

On the other hand, the Internet is evolving from a human-centered network in which humans generate and consume information, to an Internet of Things (IoT) network that exchanges and processes information between distributed components such as objects. IoE (Internet of Everything) technology, which combines IoT technology with big data processing technology through connection with cloud servers, is also emerging. In order to implement IoT, technological elements such as sensing technology, wired/wireless communication and network infrastructure, service interface technology, and security technology are required, and recently, a sensor network for connection between objects, machine to machine, M2M) and MTC (Machine Type Communication) technologies are being studied.

In the IoT environment, intelligent IT (Internet Technology) services that create new value in human life by collecting and analyzing data generated from connected objects can be provided. IoT is the field of smart home, smart building, smart city, smart car or connected car, smart grid, healthcare, smart home appliance, advanced medical service, etc. through the convergence and combination of existing IT (information technology) technology and various industries. Can be applied to.

Accordingly, various attempts have been made to apply a 5G communication system to an IoT network. For example, technologies such as sensor network, machine to machine (M2M), and MTC (Machine Type Communication) are implemented by techniques such as beamforming, MIMO, and array antenna, which are 5G communication technologies. will be. As the big data processing technology described above, a cloud radio access network (cloud RAN) is applied as an example of the convergence of 5G technology and IoT technology.

In general, when data is transmitted and received between a transmitter and a receiver in a communication system, data errors may occur due to noise present in the communication channel. As described above, an error correction coding scheme exists as a coding scheme designed to correct an error generated by a communication channel in a receiver. This error correction code is also referred to as channel coding. The error correction coding technique is a technique in which redundancy bits are added to the data to be transmitted and transmitted.

There are various methods of error correction coding techniques. For example, there are convolutional coding, turbo coding, LDPC coding, and polar coding. Among these error correction coding techniques, the polar code technique is the first code that has been theoretically proven to achieve a point-to-point channel capacity by using channel polarization. As for the extreme code, it is possible to design a code optimized for each channel or code rate through density evolution and reciprocal channel approximation (RCA). However, in order to apply the polar code technique in an actual communication system, it is necessary to have an index sequence (polar code sequence) optimized for each code rate in advance.

Meanwhile, in the 5th generation (5G) mobile communication technology, which has been recently proposed as a next-generation mobile communication system, the following three scenarios are largely mentioned. First, eMBB (Enhanced Mobile Broadband), second URLLC (Ultra-Reliable and Low Latency Communication), and third mMTC (Massive Machine Type Communication) scenario. Error correction codes to support such various methods must support various code rates with stable performance.

The polar decoding system was adopted by 3GPP, a standardization organization, as an error correction system for 5G wireless communication control channels.

Polar abdominal coding systems include SC (Successive Cancellation), SSC (Simplified Successive Cancellation), SCL (Successive Cancellation List), Fast-SSCL-SPC (Fast-simplified SCL-SPC), and the like.

The SCL scheme proposed to improve the error correction performance of the existing SC decoding method could improve the error correction performance, but there is a limitation in that the delay time is long due to the sequential protection characteristics.

The SSC method, which is another method to compensate for the problem of the SC decoding method, does not visit a child node when all child nodes are frozen bits or information bits, and multi-bits in the corresponding mode. bit).

In order to solve the problem of the SCL method, a study on a method of reducing the delay time by reducing the number of visited nodes based on the SCL has been conducted. Among these studies, Fast-SSCL-SPC is known to have the best performance with minimal delay time.

The Fast-SSCL-SPC decoding method can decode several bits at the same time without visiting a lower child node in a special node (Rate-0, Rate-1, REP, SPC) having a specific pattern of the tree.

However, the Fast-SSCL-SPC method has the effect of significantly reducing the delay time compared to the SCL method, but it is known that there is a problem in the utilization of a processing element (PE).

Specifically, when a special node is reached, an additional clock cycle is consumed in order to perform a special operation with high complexity instead of visiting a child node.

When the additional clock cycle is performed, the operation of the PE is meaningless, and the PE is actually stopped. In 5G mobile communication, since there are many special nodes with a code length of 1024 and 512 bits actually used, there is a problem that the PE is frequently interrupted.

US Patent No. 10,075,193B2 proposes a decoding algorithm and hardware configuration for the SC scheme, and describes a configuration for reducing the delay time through pruning or comprising in the case of a special node.

In addition, in order to solve the problem of a fully parallel PE (Fully Parallel PE) in which PE operates independently using a line decoder, a system that operates in semi-parallel by reducing the number of PEs is proposed.

However, such a system has the advantage of reducing hardware cost by directly reducing the number of PEs, but it cannot shorten the delay time.

As a prior art for shortening the delay time of other polar code decoding, "Fast and Flexible Successive-Cancellation List Decoders for Polar Codes, Seyyed Ali Hashemi, Student Member, IEEE, Carlo Condo, and Warren J. Gross, Senior Member, IEEE, IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 65, NO. 21, NOVEMBER 1, 2017".

In the above paper, the contents of Fast-SSCL or Fast-SSCL-SPC polar code decoder are described. In the conventional SCL, differently from the SC, since the list is ranked and selected, an additional operation of scoring and classifying each list is required.

Moreover, a method of performing list scoring for pruning of a special node in SCL has not been developed before, but in this paper, a method capable of pruning of SCL while maintaining error correction performance was proposed.

However, since the PE operation is stopped during the operation of the special node, a separate clock cycle is consumed.

1 is a block diagram of a conventional Fast-SSCL decoding apparatus.

Referring to FIG. 1, a conventional decoding apparatus includes a memory 100 for storing received bits, a processing element 200 for performing an F operation or a G operation according to a node of a received bit of the memory 100. , A metric computing unit (300) that performs pruning to output the decoded information bits, a partial sum network (400) that calculates a subtotal, and an output bit of the memory (100). It includes a pointer 500.

The configuration including the memory 100, the processing element 200, the metric operation unit 300, the subtotal network 400, and the pointer 500 is a configuration of an extreme code decoding device, and the decoding device is a separate The operation is controlled by the controller of

The decoding device is a device added to a receiver for wireless communication and decodes information data from received data.

The controller performs F operation or G operation according to the characteristics of the node to be currently operated, and performs pruning. Pruning is a process of omitting unnecessary node visits along the decoding tree and finally sorting.

2 is an exemplary diagram of a conventional decoding tree.

Referring to FIG. 2, a decoding tree is a structure in which a layer and a leaf layer of the layer are connected, and a specific leaf node is visited according to log-likelihood ratios (LLR).

The node includes a special node. Special nodes are usually labeled as Rate-0, Rate-1, REP, and SPC, and multiple bits can be decoded at the same time without visiting a lower leaf node (or child node).

At this time, G operation must be performed after pruning of the special node.

The G operation or F operation is performed according to the cycle of the system clock, and one system clock is allocated for the operation.

Two operations, F operation (F-function) and G operation (G-function), which are performed during decoding, may be performed, F operation in a single parity check node, and G operation in a repetitive node.

When the bit value for the node is hard-determined and predicted or determined, the likelihood for the repetitive node may be calculated by performing the G operation.

The processing element 200 performs an F operation or a G operation according to the type of a node, and the metric operation unit 300 performs pruning according to the likelihood calculated by the processing element 200 to output the decoded bit value. do.

At this time, pruning includes sorting, and classification is the most time-consuming process in the pruning process.

As described above, in the system clock period in which pruning is performed in the metric operation unit 300, the processing element 200 becomes an idle state in which no operation is performed. This is because a subtotal, which is an output of the subtotal network 400 in the previous state, is required to perform the G operation.

That is, since the subtotal of the previous state has not been calculated, the G operation cannot be performed in advance, and the G operation is possible after the pruning of the previous state is completed.

When pruning of the metric calculation unit 300 is completed, the processing element 200 performs an F operation or a G operation according to the node type again at the next system clock. If the node is a special node, the partial sum of the previous state Perform G operation using.

Accordingly, in the conventional decoding apparatus and method, the operation of the processing element 200 is stopped during the pruning process, which acts as a delay factor of the entire decoding apparatus and method.

The technical problem to be solved by the present invention in consideration of the above problems is to provide an extreme code decoding apparatus and method capable of further reducing a delay time in an SCL-based decoding scheme.

In particular, to provide an extreme code decoding apparatus and method capable of shortening the delay time by optimizing the operation of the PE in the Fast-SSCL method in which the delay time of the SCL method is shortened.

An extreme code decoding apparatus according to an aspect of the present invention for solving the above problems, performs F operation or G operation according to a memory storing a received bit and a node of the received bit of the memory, Simultaneously with the pruning process, a processing element that performs G operation using Candidate Partial Sum, and outputs the decoded information bits by performing pruning, and sorting during the pruning process Includes a metric computing unit that selectively outputs a previous value, and a partial sum network that calculates a subtotal and calculates and outputs the candidate subtotal using the pre-classification value of the metric calculation unit. do.

In an embodiment of the present invention, the processing element includes an F operation unit for performing an F operation, a G operation unit for performing G operation, and a superposition for selecting and outputting one of two operation results of the G operation unit according to the candidate subtotal. It may include an operation unit.

In an embodiment of the present invention, the overlapping operation unit includes a pair of multiplexers each selecting one of two operation results of the G operation unit, and the pair of multiplexers is the G operation unit according to different candidate subtotals. One of the two calculation results of can be selected and output.

In an embodiment of the present invention, the metric calculation unit selects and outputs one of a metric calculation unit including a plurality of classifiers to perform pruning including sorting, and calculation values of the front end of the classifiers. May contain multiplexers.

The polar code decoding method according to another aspect of the present invention includes: a) checking whether a special node is processed, and b) selecting one of an operation value of the front end of the classifier of claim 4 in the pruning process if the processing is a special node. Steps, c) calculating a candidate partial sum using one of the operation values selected in step b), and d) performing a G operation according to the candidate partial sum value, wherein the G operation and the rounding process The last process can be performed superimposed on the same clock cycle.

In an embodiment of the present invention, in step d), one of the outputs of the G operation unit that performs the G operation may be selected according to the candidate partial sum.

In an embodiment of the present invention, the G operation may be performed by being superimposed on the same clock cycle as the classification process of the pruning process.

The extreme code decoding apparatus and method of the present invention has the effect of shortening the delay time by performing the G operation performed after the special node operation in the fast-SSCL method extreme code decoding in the same clock cycle as the operation of the special node. .

More specifically, the polar code decoding apparatus and method of the present invention enables the operation of the PE to be performed in advance without stopping the operation of the PE during the operation of the special node, thereby reducing the delay time.

1 is a block diagram of a conventional pole code decoding apparatus.

2 is a block diagram of a conventional decoding tree.

3 is a block diagram of an extreme code decoding apparatus according to a preferred embodiment of the present invention.

4 is a block diagram of a processing element applied to the present invention.

5 is a block diagram of a metric calculation unit applied to the present invention.

6 is an exemplary diagram of a decoding tree according to the present invention.

7 is a graph comparing the processing of the present invention and the conventional processing according to the type of special node.

-Explanation of the sign-

10: memory 20: processing element

21: F operation unit 22: G operation unit

23: superimposed operation unit 30: metrack operation unit

31: metric calculation unit 32: multiplexer

40: subtotal network 50: pointer

Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. In this case, it should be noted that the same components in the accompanying drawings are indicated by the same reference numerals as possible. In addition, the accompanying drawings of the present invention are provided to aid understanding of the present invention, and it should be noted that the present invention is not limited in the form or arrangement illustrated in the drawings of the present invention. In addition, detailed descriptions of known functions and configurations that may obscure the subject matter of the present invention will be omitted. In the following description, it should be noted that only parts necessary to understand the operation according to various embodiments of the present invention will be described, and descriptions of other parts will be omitted so as not to obscure the gist of the present invention.

In describing the embodiments, descriptions of technical contents that are well known in the technical field to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly convey the gist of the present invention by omitting unnecessary description.

For the same reason, some components in the accompanying drawings are exaggerated, omitted, or schematically illustrated. In addition, the size of each component does not fully reflect the actual size. The same reference numerals are assigned to the same or corresponding components in each drawing.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in a variety of different forms, only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have it, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same components throughout the specification.

In this case, it will be appreciated that each block of the flowchart diagrams and combinations of the flowchart diagrams may be executed by computer program instructions. Since these computer program instructions can be mounted on the processor of a general purpose computer, special purpose computer or other programmable data processing equipment, the instructions executed by the processor of the computer or other programmable data processing equipment are described in the flowchart block(s). It creates a means to perform functions. These computer program instructions can also be stored in computer-usable or computer-readable memory that can be directed to a computer or other programmable data processing equipment to implement a function in a particular way, so that the computer-usable or computer-readable memory It is also possible to produce an article of manufacture containing instruction means for performing the functions described in the flowchart block(s). Computer program instructions can also be mounted on a computer or other programmable data processing equipment, so that a series of operating steps are performed on a computer or other programmable data processing equipment to create a computer-executable process to create a computer or other programmable data processing equipment. It is also possible for instructions to perform processing equipment to provide steps for executing the functions described in the flowchart block(s).

In addition, each block may represent a module, segment, or part of code that contains one or more executable instructions for executing the specified logical function(s). In addition, it should be noted that in some alternative execution examples, functions mentioned in blocks may occur out of order. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order depending on the corresponding function.

In this case, the term'~ unit' used in the present embodiment refers to software or hardware components such as FPGA or ASIC, and'~ unit' performs certain roles. However,'~ part' is not limited to software or hardware. The'~ unit' may be configured to be in an addressable storage medium or may be configured to reproduce one or more processors. Thus, as an example,'~ unit' refers to components such as software components, object-oriented software components, class components and task components, processes, functions, properties, and procedures. , Subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, database, data structures, tables, arrays, and variables. Components and functions provided in the'~ units' may be combined into a smaller number of elements and'~ units', or may be further separated into additional elements and'~ units'.

In addition, components and'~ units' may be implemented to play one or more CPUs in a device or a security multimedia card.

The polar code is an error correction code and may have a performance higher than a certain level while having low coding performance and low complexity. In addition, in the case of the extreme code, it is a code that can achieve the data transmission limit, channel capacity, in all binary discrete memoryless channels. In addition, the polar code has similar performance to the turbo code and LDPC (low-density parity-check) code, which are other channel capacity proximity codes, and in the case of the polar code, the performance when transmitting a code of a shorter length compared to the other codes. It can have an advantage. Accordingly, it is possible to transmit/receive a signal to which a polar code is applied throughout the communication system, and more specifically, it is possible to consider using a polar code to transmit control information of a predetermined length or less.

In addition, the polar code is an error correction code that can be defined based on a phenomenon called channel polarization under the assumption of binary discrete memoryless channel (B-DMC). In the case of applying such a polar code, each bit can be independently and statistically a channel W having the same characteristics. In this case, if the channel capacity of each channel is 0≦C(W)≦1, it is theoretically possible to transfer information as much as C(W) bits when a certain bit is transmitted through the channel. In the case of transmitting N bits through B-DMC without any operation, all channels through which each bit is transmitted have a channel capacity of C(W), and information as much as N×C(W) bits is theoretically transmitted. Can be. The basic concept of channel polarization is to combine (channel combining) and splitting (channel splitting) channels through which N bits pass, so that the channel capacity of the resulting channel experienced by a specific ratio of bits is equal to 1. The channel capacity of the resulting channel, which becomes a close value, and the remaining bits experience, can be adjusted to be close to zero. In this simple, conceptual description of the polar code, the transmission effect can be maximized by transmitting the information bit to a channel with a high channel capacity after channel polarization and fixing the information bit to a specific value on a channel with a low channel capacity. have.

3 is a block diagram of a polar decoding apparatus according to an embodiment of the present invention.

Referring to FIG. 3, the extreme code decoding apparatus according to a preferred embodiment of the present invention performs an F operation or a G operation according to a memory 10 storing received bits and a node of a received bit of the memory 10. , In the pruning process of the special node, a processing element (20) that performs G operation in advance using a candidate partial sum, and a decoded information bit by performing pruning are output, but sorting (sorting) ) A metric computing unit (30) that provides a candidate partial sum by providing a previous value, a partial sum network (40) that calculates a subtotal, and an output bit of the memory 10 It includes a pointer 50 to designate.

Hereinafter, the configuration and operation of the pole code decoding apparatus according to a preferred embodiment of the present invention configured as described above will be described in more detail.

First, it is assumed that the received bits stored in the memory 10 are selected by the pointer 50, and the received bits are input to the processing element 20, and the F operation or the G operation is performed depending on the node.

4 is a block diagram of the processing element 20 of the present invention.

Referring to FIG. 4, the processing element 20 applied to the present invention includes an F operation unit 21 and a G operation unit 22, and superimposes the selection and output of the G operation result by a candidate partial sum. It is configured to further include an overlaping) operation unit (23).

The superposition operation unit 23 includes two multiplexers that select and output one of the two output values of the G operation unit 22 according to a plurality of candidate partial sums (Candidate Partial Sum 0, Candidate Partial Sum 1).

The F operation unit 21 and the G operation unit 22 are elements of a typical processing element, and perform F operation or G operation on information bits α according to nodes. For G operation, the partial sum (β) of the previous state is required.

The G operation unit 22 generates two result values, and selects and outputs one of the two result values according to the subtotal.

In the present invention, the G operation is performed in advance before the subtotal of the previous state required by the G operation unit 22 is calculated, so that the processing element 20 becomes the idle state by performing the G operation while performing pruning. Can be prevented.

In this way, in order to perform G operation at the same time as pruning in the superimposition operation unit 23, the subtotal information of the previous state is required. Make it possible to find the candidate subtotal.

5 is a block diagram of a metric calculation unit 30 applied to the present invention.

Referring to FIG. 5, according to the present invention, a result of the F operation of the processing element 20 or the result of the superimposition G operation of the superimposition operation unit 23 are selectively input and pruned to output decoded bits.

The reason why the superimposed G operation result is received is because there is a possibility that the next operation process after the operation of the superimposition operation unit 23 is a pruning operation of a special node.

The configuration of the metric calculation unit 30 applied to the present invention includes a metric calculation unit 31 that performs pruning, and a multi-layer for selecting processed values before being input to sorters in the calculation process of the metric calculation unit 31. It consists of a flexor (32).

The configuration of the metric calculation unit 31 itself may be the same as that of a typical metric calculation unit (MCU).

The value selected by the multiplexer 32 may be selected according to the type of the special node.

The value selected by the multiplexer 32 is provided to the subtotal network 40, and the subtotal network 40 obtains a candidate subtotal and provides it to the superposition operation unit 23 of the processing element 20 described above.

As described above, according to the present invention, the G operation can be performed in the processing element 20 together with the sorting process that takes the most time in the pruning process, thereby preventing loss of the system clock cycle.

That is, by preventing the processing element 20 from operating in an idle state, there is a characteristic that the delay time can be reduced.

Referring to FIG. 6, a classification operation is performed in a 5-layer 16-bit decoding tree, and the following G operation is superimposed and calculated. As described above, by performing the classification operation and the G operation simultaneously, it is possible to reduce the delay factor because it is not necessary to use a separate system clock for the G operation, which must be performed after the processing of the special node.

In particular, when the number of special nodes is large, the delay factor can be further reduced.

Referring to FIG. 7, for Rate 0, conventionally, the operation of the processing element, the pruning operation of the metric operation unit, and the G operation each use a clock, but in the present invention, the pruning operation of the metric operation unit and the G operation are simultaneously performed The clock cycle can be reduced.

In the case of Rate 1, the operation of the processing element and the operation of the metric calculation unit occur simultaneously, and in the next clock cycle, the G operation is performed again in the next clock cycle after the sorting operation, but in the present invention, the classification operation and Since the G operation can be performed simultaneously, the clock cycle can be reduced.

In the case of the REF node, the G operation was conventionally performed by separating the G operation in a clock cycle following the clock cycle of the classification operation, but in the present invention, the clock cycle can be reduced by overlapping the classification operation and the G operation in the same clock cycle. have.

Finally, in the SPC node, in the conventional method of performing the classification operation for two clock cycles between two clock cycles for parity check, the clock cycle is reduced by overlapping the G operation in the clock cycle for the last parity check. There are features that can be.

As described above, the present invention has a feature of reducing delay by reducing one clock cycle in all special nodes.

It is apparent to those of ordinary skill in the art that the present invention is not limited to the above embodiments and can be variously modified and modified within the scope of the technical gist of the present invention. will be.

The present invention is to shorten the delay time by performing the G operation after the special node operation in the same clock cycle as the operation of the special node in Fast-SSCL extreme code decoding using the natural law. There is this.

Claims

A memory for storing received bits;

A processing element that performs an F operation or a G operation according to a node of the received bit of the memory, and performs a G operation using a candidate partial sum at the same time as the pruning process of the special node;

A metric computing unit that performs pruning to output decoded information bits and selectively outputs a value before sorting during a pruning process; And

An extreme code decoding apparatus comprising a partial sum network that calculates a partial sum and calculates and outputs the candidate partial sum using a value before classification of the metric calculation unit.
The method of claim 1,

The processing element,

An F operation unit that performs an F operation;

A G operation unit that performs G operation;

An extreme code decoding apparatus comprising a superposition operation unit for selecting and outputting one of two operation results of the G operation unit according to the candidate subsum.
The method of claim 2,

The overlapping operation unit,

Each includes a pair of multiplexers for selecting one of the two operation results of the G operation unit,

Wherein the pair of multiplexers selects and outputs one of two calculation results of the G operation unit according to different candidate subsums.
The method of claim 1,

The metric calculation unit,

A pole code decoding apparatus including a metric calculating unit including a plurality of classifiers to perform pruning including sorting, and a multiplexer for selecting and outputting one of calculated values of the front end of the classifiers.
a) checking whether the special node is processed;

b) selecting one of the calculation values of the front end of the classifier of claim 4 in the pruning process in case of processing of the special node;

c) calculating a candidate partial sum using one of the operation values selected in step b);

d) Perform G operation according to the candidate partial sum value,

The extreme code decoding method, characterized in that the G operation and the final process of the Fourning process are performed superimposed on the same clock cycle.
The method of claim 5,

Step d),

An extreme code decoding method, characterized in that one of the outputs of the G operation unit performing the G operation is selected according to a value of the candidate partial sum.
The method of claim 6,

The G operation is performed by being superimposed on the same clock cycle as the classification process of the pruning process.