WO2020259030A1 - 显示面板及其制造方法和显示装置 - Google Patents

显示面板及其制造方法和显示装置 Download PDF

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Publication number
WO2020259030A1
WO2020259030A1 PCT/CN2020/085628 CN2020085628W WO2020259030A1 WO 2020259030 A1 WO2020259030 A1 WO 2020259030A1 CN 2020085628 W CN2020085628 W CN 2020085628W WO 2020259030 A1 WO2020259030 A1 WO 2020259030A1
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Prior art keywords
line
display area
insulating layer
via hole
layer
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PCT/CN2020/085628
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English (en)
French (fr)
Inventor
郝学光
吴新银
乔勇
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to BR112020019341A priority Critical patent/BR112020019341A2/pt
Priority to US17/040,340 priority patent/US11211012B2/en
Priority to EP20771184.7A priority patent/EP3993053A4/en
Priority to KR1020207028228A priority patent/KR102443121B1/ko
Priority to MX2020010340A priority patent/MX2020010340A/es
Priority to RU2020132003A priority patent/RU2756485C1/ru
Priority to AU2020239614A priority patent/AU2020239614B2/en
Priority to JP2020551343A priority patent/JP2022539621A/ja
Publication of WO2020259030A1 publication Critical patent/WO2020259030A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels

Definitions

  • the embodiments of the present disclosure relate to a display panel, a manufacturing method thereof, and a display device.
  • Organic light emitting diode display devices (Organic Light Emitting Diode, OLED) are widely used in various electronic products.
  • the OLED display panel may adopt a rectangular screen, and the OLED display panel generally adopts a GOA (Gate on Array) circuit.
  • GOA Gate on Array
  • the embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device.
  • a display panel including:
  • a display area including at least one rounded corner
  • a plurality of first dummy pixels located outside the at least one rounded corner of the display area, and a first power line of each of the first dummy pixels is connected to a high-level signal line of the gate driving circuit.
  • each of the first dummy pixels is located between the gate driving circuit and the display area, and each of the first dummy pixels is configured to not emit light.
  • the plurality of first virtual pixels are arranged in a stepped manner.
  • the plurality of first virtual pixels includes at least one column in a first direction and at least one row in a second direction, and the first direction and the second direction are perpendicular to each other.
  • the display panel further includes a binding area, wherein the binding area is located on one side of the display area, and a plurality of second virtual devices are arranged on the opposite side of the display area to the binding area. Pixels, each of the second virtual pixels is configured to not emit light.
  • the second power line of each second dummy pixel is connected to the high-level signal line of the gate driving circuit.
  • the pitches of the plurality of second virtual pixels in at least one of the first direction and the second direction are equal to each other, and the first direction and the second direction are perpendicular to each other.
  • the plurality of second virtual pixels include at least one column in the first direction and at least one row in the second direction.
  • the display panel includes a first rounded corner and a second rounded corner close to the binding area, and the plurality of first virtual pixels are arranged outside the first rounded corner and the second rounded corner.
  • the display panel includes a third rounded corner and a fourth rounded corner away from the binding area, and the plurality of first virtual pixels are arranged outside the third rounded corner and the fourth rounded corner.
  • each of the virtual pixels includes at least a pixel drive circuit
  • the pixel drive circuit includes a first scan line, a second scan line, and a third scan line, the first scan line, the second scan line, and the third scan line
  • the wire is connected to the gate driving circuit or is in a suspended state.
  • each of the dummy pixels further includes a light emitting unit
  • the pixel driving circuit includes a driving transistor
  • the driving transistor includes a drain electrode
  • the light emitting unit includes an anode and does not include a light emitting layer
  • the leakage of the driving transistor The pole is electrically connected to the anode of the light-emitting unit.
  • each of the dummy pixels further includes a light emitting unit
  • the pixel driving circuit includes a driving transistor
  • the driving transistor includes a drain electrode
  • the light emitting unit includes an anode, a light emitting layer, and a cathode
  • the drain electrode of the driving transistor It is electrically isolated from the anode of the light-emitting unit.
  • each of the virtual pixels includes:
  • the buffer layer is arranged on the substrate
  • the active layer is arranged on the buffer layer
  • the first scan line, the second scan line, the third scan line, and the first gate electrode arranged in the same layer, the first scan line, the second scan line, and the third scan line And the first gate electrode is disposed on the first insulating layer;
  • a second insulating layer covering the first scan line, the second scan line, the third scan line and the first gate electrode;
  • An initial voltage line and a second gate electrode provided in the same layer, the initial voltage line and the second gate electrode are provided on the second insulating layer;
  • the third insulating layer covers the initial voltage line and the second gate electrode.
  • the third insulating layer is provided with a plurality of via holes, and the plurality of via holes includes: exposing the second gate electrode
  • the first via, the second via, and the third via expose the fourth, fifth, and sixth vias of the active layer, and expose the seventh via of the initial voltage line ;
  • the data line, the power line, the connection line and the drain electrode are arranged in the same layer, the data line, the power line, the connection line and the drain electrode are arranged on the third insulating layer, and the leakage One end of the electrode is connected to the second gate electrode through the first via hole, the other end of the drain electrode is connected to the active layer through the fifth via hole, and the data line passes through the fourth A via hole is connected to the active layer, the power line is connected to the second gate electrode through the second via hole and the third via hole, and one end of the connecting line passes through the sixth via hole Connected to the active layer, and the other end of the connecting line is connected to the initial voltage line through the seventh via;
  • a fourth insulating layer covering the data line, the power line, the connection line and the drain electrode, and an eighth via hole exposing the drain electrode is opened on the fourth insulating layer;
  • a pixel defining layer is disposed on the fourth insulating layer and defines a pixel opening, and the eighth via is located in the pixel opening;
  • the anode is disposed in the pixel opening and connected to the drain electrode through the eighth via.
  • a display device including the above-mentioned display panel.
  • a method for manufacturing a display panel including:
  • the substrate including a display area and a non-display area located at the periphery of the display area, the display area including at least one rounded corner;
  • a plurality of first dummy pixels are formed outside the at least one rounded corner of the display area, and a first power line of each of the first dummy pixels is connected to a high-level signal line of the gate driving circuit.
  • the above method further includes forming a plurality of pixel units in the display area, wherein each of the pixel units is configured to emit light, and each of the dummy pixels is configured to not emit light.
  • the forming a plurality of first virtual pixels includes:
  • a third insulating layer is formed, wherein the third insulating layer covers the initial voltage line and the second gate electrode, and a plurality of via holes are opened on the third insulating layer, and the plurality of via holes includes: The first via hole, the second via hole and the third via hole of the second gate electrode are exposed to expose the fourth via hole, the fifth via hole and the sixth via hole of the active layer, and the The seventh via hole of the initial voltage line;
  • a data line, a power line, a connection line, and a drain electrode are formed on the third insulating layer, one end of the drain electrode is connected to the second gate electrode through the first via hole, and the other end of the drain electrode Connected to the active layer through the fifth via, the data line is connected to the active layer through the fourth via, and the power line is connected through the second via and the third
  • the via hole is connected to the second gate electrode, one end of the connecting line is connected to the active layer through the sixth via hole, and the other end of the connecting line is connected to the initial layer through the seventh via hole.
  • the fourth insulating layer is provided with an eighth via hole exposing the drain electrode
  • the pixel definition layer defines a pixel opening, and the eighth via is located in the pixel opening;
  • An anode is formed in the pixel opening, and the anode is connected to the drain electrode through the eighth via.
  • FIG. 1 is a schematic structural diagram of a display panel of an embodiment of the disclosure
  • FIGS. 2a to 2c are schematic diagrams of the structure of stepped virtual pixels in an embodiment of the disclosure.
  • FIG. 3a is a schematic diagram of the structure of a virtual pixel in an embodiment of the disclosure.
  • Figure 3b is a cross-sectional view along the line A-A in Figure 3a;
  • 4a is a schematic diagram of an embodiment of the disclosure after forming an active layer pattern
  • Figure 4b is a cross-sectional view along the A-A direction in Figure 4a;
  • FIG. 5a is a schematic diagram after forming a first gate electrode pattern according to an embodiment of the disclosure.
  • Figure 5b is a cross-sectional view along the line A-A in Figure 5a;
  • 6a is a schematic diagram after forming a second gate electrode pattern according to an embodiment of the disclosure.
  • Figure 6b is a cross-sectional view along the A-A direction in Figure 6a;
  • FIG. 7a is a schematic diagram after forming a third insulating layer pattern according to an embodiment of the disclosure.
  • Figure 7b is a cross-sectional view along the A-A direction in Figure 7a;
  • FIG. 8a is a schematic diagram of an embodiment of the disclosure after forming a drain electrode pattern
  • Figure 8b is a cross-sectional view along the line A-A in Figure 8a;
  • FIG. 9a is a schematic structural diagram of a virtual pixel in another embodiment of the present disclosure.
  • Figure 9b is a cross-sectional view along the line A-A in Figure 9a;
  • FIG. 10 is a schematic diagram of a power line connected to a high-level signal line according to an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of scanning lines connected to a gate driving circuit according to an embodiment of the disclosure.
  • FIG. 12 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a display panel according to still another embodiment of the present disclosure.
  • FIG. 14 is a flowchart of a manufacturing method of a display panel according to an embodiment of the disclosure.
  • FIG. 15 is a block diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • the rounded corner design of the OLED display panel (that is, the corner design of the panel is rounded corners, referred to as the OLED heterogeneous screen) is becoming more and more common, in order to realize the concept of a full screen with a uniform outline shape of the screen and the electronic product.
  • the existing OLEDs with rounded corners have the problems of lower display quality, reliability and yield. Therefore, how to improve the display quality, reliability, and yield of OLEDs is an urgent technical problem to be solved.
  • the inventors of the present disclosure have discovered that the reasons for the low display quality, reliability, and low yield rate of the existing OLED special-shaped screens are caused by the position of the rounded corners affecting the etching uniformity. Specifically, because the position of the rounded corner is not conducive to the layout of the gate drive circuit and the pixel drive circuit, a large blank area is provided on the outside of the rounded corner, resulting in poor etching uniformity of the pixel unit in the display area near the rounded corner , Which reduces reliability and yield.
  • an embodiment of the present disclosure provides a display panel.
  • the display panel of the present disclosure includes a display area and a non-display area located at the periphery of the display area, the display area includes at least one rounded corner, the non-display area includes a gate drive circuit and the at least one circle located in the display area A plurality of dummy pixels outside the corner, and the power line of each dummy pixel is connected to the high-level signal line of the gate driving circuit.
  • the virtual pixels are located outside the rounded corners of the display area, which effectively improves the etching uniformity of the rounded corners, and at the same time, the power lines of the virtual pixels are connected to the grid
  • the high-level signal line of the pole drive circuit reduces the load of the gate drive circuit, improves the electrical performance of the pixel circuit in the display area, and effectively solves the low display quality, reliability and yield rate of existing OLED special-shaped screens. problem.
  • the above-mentioned display panel may be an Organic Light Emitting Diode (OLED) display panel, Quantum Dot Light Emitting Diodes (QLED) display panel, Micro Light Emitting Diodes (Micro LED)
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diodes
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.
  • the display panel of this embodiment includes a display area 100, a non-display area 200 located at the periphery of the display area 100 (for example, around the display area 100 ), and a binding area 300 located on one side of the display area 100.
  • the display area 100 includes a first side L1 and a second side L2, and the first side L1 and the second side L2 are connected by rounded corners (or rounded corners).
  • the display area 100 of the display panel of the present disclosure is provided with at least one rounded corner.
  • the first side L1 and the second side L2 are connected by rounded corners, that is, the first side L1 transitions to the second side L2 through the arc corresponding to the rounded corner.
  • the display area 100 may include multiple rounded corners. As shown in FIG. 1, the display area 100 may include a set of two oppositely arranged first sides (L1 and L1'), and a set of oppositely arranged two second sides (L2 and L2'), two The first side (L1 and L1') is connected to the two second sides (L2 and L2') at both ends by rounded corners. In this case, the display area 100 includes 4 rounded corners.
  • the display area 100 may include a set of two first sides (L1 and L1') and a second side (L2) that are arranged oppositely, and two first sides (L1 and L1'). Two ends of the second side (L2) are respectively connected to the second side (L2) by round corners.
  • the display area 100 includes 2 rounded corners.
  • a plurality of gate lines SL and a plurality of data lines DL are provided in the display area 100.
  • the gate lines SL and the data lines DL intersect to form a plurality of pixel units P arranged in a matrix. Used to achieve normal display.
  • the plurality of pixel units P includes at least a first color pixel unit, a second color pixel unit, and a third color pixel unit.
  • the first color, the second color, and the third color are three primary colors (for example, red, green, and blue).
  • the non-display area 200 is located at the periphery of the display area 100.
  • the non-display area 200 is provided with a gate driving circuit, a power signal circuit VDD, and a plurality of dummy pixels 400, such as gates in the display area.
  • the pole line is connected with the gate driving circuit, and the gate driving circuit provides a driving voltage for the gate line.
  • the gate driving circuit is configured as a GOA circuit, that is, the gate driving circuit is directly integrated into the array substrate in the display panel. As shown in FIG.
  • the GOA circuits are located on both sides of the display area 100, the power signal circuit VDD is located on the lower side of the display area 100, and the dummy pixels 400 are respectively arranged outside the lower left corner of the display area 100 and the lower right corner of the display area 100 In the area between the GOA circuit and the display area 100, a plurality of dummy pixels 400 are used to improve the uniformity of the rounded corners and cannot emit light.
  • the bonding area 300 is located on one side (for example, the lower side) of the display area 100 and includes a bonding pad 301, the GOA circuit is connected to the bonding pad 301 through the first lead 302, and the power signal circuit VDD passes through The second lead 303 is connected to the bonding pad 301.
  • each dummy pixel 400 includes at least a pixel driving circuit.
  • the difference between the dummy pixel 400 and the pixel unit P of the display area 100 is that the dummy pixel 400 is only provided with a pixel driving circuit with the same structure as the pixel unit P, and there is no light emitting unit, that is, the dummy pixel 400 cannot Achieve display. Therefore, the pixel driving circuit of the dummy pixel 400 is electrically connected to the scan line, the data line, and the power line, and the power line is connected to the high-level signal line VGH of the GOA circuit. For example, as shown in FIG.
  • the pixel driving circuit of each pixel unit P in the display area includes a driving unit and a light emitting unit (for example, an organic light emitting diode OLED).
  • the driving unit includes a transistor and a capacitor.
  • the driving unit in the pixel driving circuit is only schematically illustrated in FIG. 15 with a 2T1C (a driving transistor T1, a switching transistor T2, and a storage capacitor Cst) structure as an example, but the present disclosure The embodiments are not limited to this.
  • the driving unit may also adopt 3T1C, 4T1C, and other circuit structures. As shown in FIG.
  • an OLED includes a cathode and an anode, and a light-emitting function layer located between the cathode and the anode.
  • the light-emitting functional layer may include an organic light-emitting layer, a hole transport layer between the organic light-emitting layer and the anode, and an electron transport layer between the organic light-emitting layer and the cathode.
  • a hole injection layer may be provided between the hole transport layer and the anode
  • an electron injection layer may be provided between the electron transport layer ETL and the cathode.
  • the plurality of virtual pixels 400 outside the lower left corner of the display area 100 are located in the area between the GOA circuit and the display area 100, and the plurality of virtual pixels 400 are arranged in a stepped manner.
  • the multiple virtual pixels 400 outside the rounded corners of the lower right corner of the display area 100 are located in the area between the GOA circuit and the display area 100.
  • the multiple virtual pixels 400 are arranged in a stepped manner, so that the multiple virtual pixels 400 follow the rounded trend. Arrangement. In this way, in the vertical direction, the dummy pixels 400 arranged in a stepped manner include at least one column; in the horizontal direction, the dummy pixels 400 arranged in a stepped manner include at least one row.
  • FIG. 2a, 2b and 2c are schematic diagrams of the structure of the stepped virtual pixel according to the first embodiment of the disclosure.
  • the stepped virtual pixel 400 shown in FIG. 2a includes 6 rows and 3 columns
  • the stepped virtual pixel 400 shown in FIG. 2b includes 3 rows and 6 columns
  • the stepped virtual pixel 400 shown in FIG. 2c includes 6 rows. Rows and 6 columns.
  • the display area 100 is also provided with a plurality of virtual pixels 400 on the outer side (upper side) of the side (upper side) away from the binding area 300, that is, a plurality of virtual pixels 400 are provided in the non-display area 200 on the opposite side of the binding area 300.
  • Pixels 400 and multiple virtual pixels 400 are arranged regularly. In the vertical direction, the regularly arranged virtual pixels 400 include at least one column; in the horizontal direction, the regularly arranged virtual pixels 400 include at least one row.
  • stepped virtual pixels are arranged outside the lower left corner and the lower right corner of the display area, so that the virtual pixels fill the area between the gate drive circuit and the display area according to the trend of the round corners.
  • the problem of uneven etching in the fillet area is solved, the uniformity of the etching in the fillet area is improved, and the reliability and yield of the display panel are improved.
  • the high-level signal line of the gate drive circuit is connected through the power line of the virtual pixel, so that the high-level signal line is connected in parallel with the power line of the virtual pixel, which reduces the resistance of the high-level signal line and effectively reduces the gate
  • the load of the driving circuit improves the working stability of the panel and reduces the power consumption.
  • FIG. 3a is a schematic diagram of the structure of a virtual pixel according to an embodiment of the disclosure
  • FIG. 3b is a cross-sectional view along the A-A direction in FIG. 3a.
  • the virtual pixels of the display panel of this embodiment include:
  • the buffer layer 11 is arranged on the substrate 10;
  • the active layer 12 is arranged on the buffer layer 11;
  • the first insulating layer 13 covers the active layer 12;
  • the first scan line GN1, the second scan line GN2, the third scan line GN3 and the first gate electrode 14 are arranged on the first insulating layer 13;
  • the second insulating layer 15 covers the first scan line GN1, the second scan line GN2, the third scan line GN3 and the first gate electrode 14;
  • the initial voltage line VI and the second gate electrode 16 are arranged on the second insulating layer 15;
  • the third insulating layer 17, covering the initial voltage line VI and the second gate electrode 16, is provided with a plurality of via holes, the plurality of via holes including: the first via hole exposing the second gate electrode 16, that is, the second via hole
  • the hole and the third via hole expose the fourth via hole, the fifth via hole and the sixth via hole of the active layer 12, and expose the seventh via hole of the initial voltage line VI;
  • the data line DA, the power line VD, the connection line LI and the drain electrode 18 are arranged on the third insulating layer 17. One end of the drain electrode 18 is connected to the second gate electrode through the first via hole, and the other end of the drain electrode 18 passes through the The five via holes are connected to the active layer 12, the data line DA is connected to the active layer 12 through the fourth via hole, and the power line VD is connected to the second gate electrode 16 through the second via hole and the third via hole. One end is connected to the active layer 12 through the sixth via hole, and the other end of the connecting line LI is connected to the initial voltage line VI through the seventh via hole;
  • the fourth insulating layer 19 covers the data line DA, the power line VD, the connection line LI and the drain electrode 18, and an eighth via hole exposing the drain electrode 18 is opened thereon;
  • the pixel defining layer 20 is disposed on the fourth insulating layer 19 to define a pixel opening, and the eighth via is located in the pixel opening;
  • the anode 21 is arranged in the pixel opening and is connected to the drain electrode 18 through the eighth via hole.
  • an embodiment of the present disclosure also provides a method for manufacturing the above-mentioned display panel, including:
  • the substrate including a display area and a non-display area located at the periphery of the display area, the display area including at least one rounded corner;
  • a plurality of first dummy pixels are formed outside the at least one rounded corner of the display area, and a first power line of each of the first dummy pixels is connected to a high-level signal line of the gate driving circuit.
  • the virtual pixels are located outside the rounded corners of the display area, which effectively improves the etching uniformity of the rounded corners, and at the same time, the virtual pixels
  • the power line is connected to the high-level signal line of the gate drive circuit, which reduces the load of the gate drive circuit, improves the electrical performance of the pixel circuit in the display area, and effectively solves the display quality, reliability and quality of the existing OLED special-shaped screens. The problem with lower rates.
  • the above method further includes forming a plurality of pixel units in the display area, wherein each of the pixel units is configured to emit light, and each of the virtual pixels is configured to not emit light.
  • the forming a plurality of first virtual pixels includes:
  • a third insulating layer is formed, wherein the third insulating layer covers the initial voltage line and the second gate electrode, and a plurality of via holes are opened on the third insulating layer, and the plurality of via holes includes: The first via hole, the second via hole and the third via hole of the second gate electrode are exposed to expose the fourth via hole, the fifth via hole and the sixth via hole of the active layer, and the The seventh via hole of the initial voltage line;
  • a data line, a power line, a connection line, and a drain electrode are formed on the third insulating layer, one end of the drain electrode is connected to the second gate electrode through the first via hole, and the other end of the drain electrode Connected to the active layer through the fifth via, the data line is connected to the active layer through the fourth via, and the power line is connected through the second via and the third
  • the via hole is connected to the second gate electrode, one end of the connecting line is connected to the active layer through the sixth via hole, and the other end of the connecting line is connected to the initial layer through the seventh via hole.
  • the fourth insulating layer is provided with an eighth via hole exposing the drain electrode
  • the pixel definition layer defines a pixel opening, and the eighth via is located in the pixel opening;
  • An anode is formed in the pixel opening, and the anode is connected to the drain electrode through the eighth via.
  • the preparation method of the display panel will be further explained by examples below.
  • the "patterning process" referred to in the present disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping photoresist.
  • the deposition may use known processes such as sputtering, vapor deposition, chemical vapor deposition, etc.
  • the coating may use a known coating process
  • the etching may use a known method, which is not specifically limited here.
  • “thin film” refers to a layer of thin film formed by depositing a certain material on a substrate or using other processes.
  • the "thin film” does not require a patterning process in the whole production method, the “thin film” can also be called a “layer”. If the "thin film” needs a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • a buffer layer pattern and an active layer pattern are formed on the substrate.
  • Forming an active layer pattern on the substrate includes: sequentially depositing a buffer film and an active layer film on the substrate 10, patterning the active layer film through a patterning process, forming a pattern of the buffer layer 11 covering the entire substrate 10 and setting it on the buffer layer
  • the pattern of the active layer 12 on 11 is shown in FIG. 4a and FIG. 4b, and FIG. 4b is a cross-sectional view along the AA direction in FIG. 4a.
  • the substrate may be a flexible substrate, using materials such as polyimide PI, polyethylene terephthalate PET, or surface-treated polymer soft film.
  • the buffer film can be silicon nitride SiNx or silicon oxide SiOx, etc., can be a single layer, or a multilayer structure of silicon nitride/silicon oxide, and the active layer can be made of monocrystalline silicon, polycrystalline silicon or oxide semiconductor materials.
  • Forming the first scan line, the second scan line, the third scan line and the first gate electrode pattern includes: sequentially depositing a first insulating film and a first metal film on the substrate forming the foregoing structure, and applying a patterning process to the first metal
  • the thin film is patterned to form a first insulating layer 13 covering the active layer 12 and the buffer layer 11, and a first scanning line GN1, a second scanning line GN2, a third scanning line GN3, and a first scanning line GN1 disposed on the first insulating layer 13.
  • the pattern of the gate electrode 14 is shown in FIG. 5a and FIG. 5b, and FIG. 5b is a cross-sectional view along the AA direction in FIG. 5a.
  • Forming the initial voltage line VI and the second gate electrode pattern includes: sequentially depositing a second insulating film and a second metal film on the substrate forming the aforementioned structure, and patterning the second metal film through a patterning process to form a covering first scan line GN1, the second scan line GN2, the third scan line GN3, the second insulating layer 15 of the first gate electrode 14, and the pattern of the initial voltage line VI and the second gate electrode 16 provided on the second insulating layer 15, as shown in FIG. 6a
  • Fig. 6b is a cross-sectional view along the AA direction in Fig. 6a.
  • Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate forming the foregoing structure, and patterning the third insulating film through a patterning process to form a third insulating layer 17 pattern with a plurality of via holes.
  • the via holes include: a first via hole H1, a second via hole H2, and a third via hole H3 exposing the second gate electrode 16, and a fourth via hole H4, a fifth via hole H5, and a third via hole H4 that expose the active layer 12;
  • the six via holes H6 expose the seventh via hole H7 of the initial voltage line VI, as shown in FIG. 7a and FIG. 7b, and FIG. 7b is a cross-sectional view along the AA direction in FIG. 7a.
  • the formation of data lines, power lines, connection lines, and drain electrode patterns includes: depositing a third metal film on the substrate forming the aforementioned structure, and patterning the third metal film through a patterning process to form data lines DA, power lines VD and connection
  • the line LI and the drain electrode 18 pattern of the driving transistor, one end of the drain electrode 18 is connected to the second gate electrode 16 through the first via H1, and the other end of the drain electrode 18 is connected to the active layer 12 through the fifth via H5.
  • the line DA is connected to the active layer 12 through the fourth via H4, the power line VD is connected to the second gate electrode 16 through the second via H2 and the third via H3, and one end of the connecting line LI is connected to the second gate electrode 16 through the sixth via H6.
  • the active layer 12 is connected, and the other end of the connecting line LI is connected to the initial voltage line VI through a seventh via H7, as shown in FIG. 8a and FIG. 8b, and FIG. 8b is a cross-sectional view along the AA direction in FIG. 8a.
  • Forming the pixel defining layer and the anode pattern includes: forming a fourth insulating layer 19 covering the data line DA, the power line VD, the connecting line LI, and the drain electrode 18 on the substrate forming the foregoing structure, and setting it on the fourth insulating layer 19
  • the pixel definition layer 20 defines the pixel opening, and the fourth insulating layer 19 in the pixel opening is provided with an eighth via hole exposing the drain electrode 18; subsequently, a transparent conductive layer is deposited on the substrate forming the aforementioned pattern
  • the thin film, the transparent conductive film is patterned by a patterning process, and a pattern of anode 21 is formed in the pixel opening defined by the pixel defining layer 20, and the anode 21 is connected to the drain electrode 18 through an eighth via hole, as shown in FIGS. 3a and 3b.
  • the pixel definition layer can be polyimide, acrylic, polyethylene terephthalate, etc., and the transparent insulating layer 19 covering the data line DA, the power
  • the above-mentioned structure of the dummy pixel is formed synchronously with the pixel unit of the display area, and the structure of the first scan line, the second scan line, the third scan line, the initial voltage line, the data line, the power line, and the connection line and The function is the same as the structure and function of the corresponding line in the pixel drive circuit of the display area.
  • the first insulating layer and the second insulating layer are also called gate insulating layer (GI)
  • the third insulating layer is also called interlayer insulating layer (ILD)
  • the fourth insulating layer is also called planarization layer (PLN) .
  • the virtual pixel further includes a light-emitting unit.
  • the OLED pixel unit includes a light-emitting layer subsequently formed on the anode, and the position of the dummy pixel does not form a light-emitting layer, that is, only includes the anode and the cathode, so the dummy pixel does not Perform light.
  • the dummy pixel may include an anode, a cathode, and a light-emitting layer, but the anode is not electrically connected to the drain electrode, and therefore, the light-emitting layer cannot emit light either.
  • FIG. 9a is a schematic structural diagram of a virtual pixel according to another embodiment of the present disclosure
  • FIG. 9b is a cross-sectional view along the A-A direction in FIG. 9a.
  • the structure of this embodiment is a modification of the virtual pixels shown in FIGS. 3a and 3b.
  • the difference from the structure of the foregoing embodiments is that there is no definition on the pixel definition layer 20 of the virtual pixels of the structure of this embodiment. Out of the pixel opening, there is no via hole on the fourth insulating layer 19.
  • the anode, the light-emitting layer, and the cathode when an anode, a light-emitting layer, and a cathode are subsequently formed in the pixel unit of the display area, the anode, the light-emitting layer, and the cathode can be formed at the position of the dummy pixel, which can further improve the etching uniformity of the rounded position.
  • the pixel driving circuit of the dummy pixel is not electrically connected to the light-emitting layer, that is, the anode of the dummy pixel is not connected to the drain electrode of the dummy pixel, and the drain electrode and the anode are electrically isolated, so the dummy pixel does not emit light.
  • the structure of the pixel driving circuit of the virtual pixel of this embodiment is basically the same as the structure of the pixel driving circuit of the pixel unit of the display area, and the two are formed synchronously.
  • the inner side of the rounded corner and the outer side of the rounded corner form basically the same film structure, thus ensuring the structure of the rounded inner side and the rounded outer side. Continuity effectively improves the uniformity of etching at the fillet position.
  • the uniformity of the etching of the pixel unit in the display area near the rounded corners ensures that the line width and thickness of the signal lines such as data lines, power lines, and gate lines meet the design values, and will not affect signal transmission speed and transmission capacity.
  • the data line of the virtual pixel is connected to the data driving circuit, and the power line of the virtual pixel is connected to the high-level signal line of the gate driving circuit, which is equivalent to connecting the power line in parallel to the high-level signal line of the gate driving circuit.
  • the resistance of the high-level signal line is reduced, the load of the gate driving circuit is effectively reduced, and the working stability of the pixel driving circuit in the display area is improved.
  • first scan line, the second scan line, and the third scan line of the virtual pixel can be set to be in a "suspended" state, that is, not electrically connected to any driving circuit, so as to prevent the pixel driving circuit of the virtual pixel from affecting the pixels in the display area
  • the work of the drive circuit can also be set to connect the output of the gate drive circuit. Since the output of the gate drive circuit has a stable potential, the virtual pixel pixel drive circuit Can play a role in improving electrical stability.
  • the patterning times of the display panel prepared in the embodiment of the present disclosure is basically the same as that of the existing manufacturing method.
  • the implementation of the present disclosure does not need to change the existing process flow, does not need to change the existing process equipment, and has good process compatibility and practicality. It has strong performance and good application prospects.
  • the display panel of the present disclosure effectively solves the problems of low display quality, reliability, and low yield rate of existing OLED special-shaped screens.
  • FIG. 10 is a schematic diagram of a power line connected to a high-level signal line in an embodiment of the disclosure.
  • the power line VD and the high-level signal line VGH are formed at the same time in the patterning process of forming the data line DA and the power line VD.
  • the two are an integral structure connected to each other.
  • FIG. 11 is a schematic diagram of a scan line connected to a gate driving circuit in an embodiment of the disclosure. As shown in FIG.
  • the first scan line GN1 can be connected to the first GOA unit (GOA1)
  • the second scan line GN2 is connected to the second GOA unit (GOA2)
  • the third scan line GN3 is connected to the second GOA unit (GOA2).
  • a control circuit EMG1 is not connected to the third GOA unit (GOA3).
  • the above-mentioned connection can either form an integral structure connected to each other in a single patterning process, or realize the connection through via holes.
  • FIG. 12 is a schematic structural diagram of a display panel according to another embodiment of the disclosure. This embodiment is a modification of the display panel of FIG. 1 and its structure is basically the same.
  • the display panel of FIG. 12 includes a display area 100, a non-display area 200 located at the periphery of the display area 100, and a binding area 300.
  • the difference from the display panel in FIG. 1 is that the virtual pixels 400 of the present embodiment as shown in FIG. 12 are respectively arranged outside the upper left rounded corner of the display area 100 and outside the upper right rounded corner of the display area 100, and are located in the GOA circuit and the display area 100.
  • a plurality of virtual pixels 400 are provided in the non-display area 200 on the opposite side of the binding area 300.
  • a plurality of dummy pixels 400 arranged in the area between the GOA circuit and the display area 100 are arranged in a stepped manner.
  • the stepped virtual pixel 400 includes at least one column, and in the horizontal direction, the stepped virtual pixel 400 includes at least one row.
  • the multiple virtual pixels 400 arranged on the opposite side of the binding area 300 are arranged regularly, for example, the multiple virtual pixels 400 are arranged at equal intervals, which is beneficial to reduce manufacturing difficulty.
  • the regularly arranged virtual pixels 400 include at least one column, and in the horizontal direction, the regularly arranged virtual pixels 400 include at least one row.
  • This embodiment also achieves the technical effects of the aforementioned embodiment in FIG. 1, improves the etching uniformity of the fillet position, reduces the load of the gate drive circuit, and improves electrical stability.
  • FIG. 13 is a schematic structural diagram of a display panel according to still another embodiment of the disclosure.
  • This embodiment is a modification of the embodiment in FIG. 1, and the structure is basically the same as that of the foregoing first embodiment.
  • the display panel of FIG. 13 includes a display area 100, a non-display area 200 located at the periphery of the display area 100, and a binding area 300.
  • the difference from the embodiment in FIG. 1 is that in this embodiment as shown in FIG. 13, the virtual pixels 400 are respectively arranged outside the four rounded corners of the display area 100, and the four rounded corners are the upper left corner, the upper right corner, and the lower left corner. And the lower right corner, and is located between the GOA circuit and the display area 100.
  • a plurality of virtual pixels 400 are provided in the non-display area 200 located on the opposite side of the binding area 300.
  • a plurality of dummy pixels 400 arranged in the area between the GOA circuit and the display area 100 are arranged in a stepped manner.
  • the step-shaped virtual pixel 400 includes at least one column, and in the horizontal direction, the step-shaped virtual pixel 400 includes at least one row.
  • the multiple virtual pixels 400 arranged on the opposite side of the binding area 300 are arranged regularly.
  • multiple virtual pixels 400 are arranged at equal intervals, which is beneficial to reduce manufacturing difficulty.
  • the regularly arranged virtual pixels 400 include at least one column, and in the horizontal direction, the regularly arranged virtual pixels 400 include at least one row.
  • This embodiment also achieves the technical effects of the aforementioned embodiment in FIG. 1, improves the etching uniformity of the fillet position, reduces the load of the gate drive circuit, and improves electrical stability.
  • the present disclosure is also applicable to the display area having one rounded corner, two rounded corners, three rounded corners, or multiple rounded corners.
  • the virtual pixels can also be set only on the outside of one rounded corner or three rounded corners, or set on the outside of the upper left rounded corner and the lower left rounded corner, and set the upper right rounded corner and the lower right rounded corner. , Set on the outer side of the upper left rounded corner and the lower right rounded corner, or set on the outer side of the lower left rounded corner and the upper right rounded corner, etc.
  • the embodiment of the present disclosure also provides a display device including the aforementioned display panel.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the display device has the technical effect of the front display panel, which will not be repeated here.

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Abstract

一种显示面板及其制造方法和显示装置。该显示面板包括：显示区域(100)，所述显示区域(100)包括至少一个圆角；位于所述显示区域(100)外围的非显示区域(200)，所述非显示区域(200)包括：栅极驱动电路；和位于所述显示区域(100)的所述至少一个圆角外侧的多个第一虚拟像素(400)，每个所述第一虚拟像素(400)的第一电源线连接所述栅极驱动电路的高电平信号线。

Description

显示面板及其制造方法和显示装置
相关申请的交叉引用
本申请基于并且要求于2019年6月26日递交、名称为“显示面板和显示装置”的中国专利申请第201920973397.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种显示面板及其制造方法和显示装置。
背景技术
有机发光二极管显示装置(Organic Light Emitting Diode，OLED)广泛应用于各种电子产品中。例如，OLED显示面板可以采用矩形屏，该OLED显示面板一般采用GOA(Gate on Array)电路。
发明内容
本公开实施例提供一种显示面板及其制造方法和显示装置。
根据本公开第一方面，提供一种显示面板，包括：
显示区域，所述显示区域包括至少一个圆角；
位于所述显示区域外围的非显示区域，所述非显示区域包括：
栅极驱动电路；和
位于所述显示区域的所述至少一个圆角外侧的多个第一虚拟像素，每个所述第一虚拟像素的第一电源线连接所述栅极驱动电路的高电平信号线。
例如，每个所述第一虚拟像素位于所述栅极驱动电路与所述显示区域之间，每个所述第一虚拟像素配置为不发光。
例如，所述多个第一虚拟像素呈阶梯状排列。
例如，所述多个第一虚拟像素在第一方向上包括至少一列，在第二方向上包括至少一行，所述第一方向和所述第二方向相互垂直。
例如，所述显示面板还包括绑定区域，其中所述绑定区域位于所述显示区域的其中一 侧，所述显示区域的与所述绑定区域的相反侧上设置有多个第二虚拟像素，每个所述第二虚拟像素配置为不发光。
例如，每个所述第二虚拟像素的第二电源线连接所述栅极驱动电路的所述高电平信号线。
例如，所述多个第二虚拟像素在第一方向和第二方向的至少一个方向上的间距彼此相等，所述第一方向和所述第二方向相互垂直。
例如，所述多个第二虚拟像素在所述第一方向上包括至少一列，在所述第二方向上包括至少一行。
例如，所述显示面板包括靠近所述绑定区域的第一圆角和第二圆角，所述多个第一虚拟像素设置在所述第一圆角和所述第二圆角的外侧。
例如，所述显示面板包括远离所述绑定区域的第三圆角和第四圆角，所述多个第一虚拟像素设置在所述第三圆角和所述第四圆角的外侧。
例如，每个所述虚拟像素至少包括像素驱动电路，所述像素驱动电路包括第一扫描线、第二扫描线和第三扫描线，所述第一扫描线、第二扫描线和第三扫描线与所述栅极驱动电路连接，或者处于悬置状态。
例如，每个所述虚拟像素还包括发光单元，所述像素驱动电路包括驱动晶体管，所述驱动晶体管包括漏电极，所述发光单元包括阳极且不包括发光层，所述驱动晶体管的所述漏电极与所述发光单元的所述阳极电连接。
例如，每个所述虚拟像素还包括发光单元，所述像素驱动电路包括驱动晶体管，所述驱动晶体管包括的漏电极，所述发光单元包括阳极、发光层和阴极，所述驱动晶体管的漏电极与所述发光单元的阳极电隔离。
例如，每个所述虚拟像素包括：
基底；
缓冲层，设置在所述基底上；
有源层，设置在缓冲层上；
第一绝缘层，覆盖所述有源层；
同层设置的所述第一扫描线、所述第二扫描线、所述第三扫描线和第一栅电极，所述第一扫描线、所述第二扫描线、所述第三扫描线和所述第一栅电极设置在所述第一绝缘层上；
第二绝缘层，所述第一绝缘层覆盖所述第一扫描线、所述第二扫描线、所述第三扫描 线和所述第一栅电极；
同层设置的初始电压线和第二栅电极，所述初始电压线和所述第二栅电极设置在所述第二绝缘层上；
第三绝缘层，覆盖所述初始电压线和所述第二栅电极，所述第三绝缘层上开设有多个过孔，所述多个过孔包括：暴露出所述第二栅电极的第一过孔、第二过孔和第三过孔，暴露出所述有源层的第四过孔、第五过孔和第六过孔，暴露出所述初始电压线的第七过孔；
同层设置的数据线、电源线、连接线和所述漏电极，所述数据线、所述电源线、所述连接线和所述漏电极设置在所述第三绝缘层上，所述漏电极的一端通过所述第一过孔与所述第二栅电极连接，所述漏电极的另一端通过所述第五过孔与所述有源层连接，所述数据线通过所述第四过孔与所述有源层连接，所述电源线通过所述第二过孔和所述第三过孔与所述第二栅电极连接，所述连接线的一端通过所述第六过孔与所述有源层连接，所述连接线的另一端通过所述第七过孔与所述初始电压线连接；
第四绝缘层，覆盖所述数据线、所述电源线、所述连接线和所述漏电极，所述第四绝缘层上开设有暴露出所述漏电极的第八过孔；
像素定义层，设置在所述第四绝缘层上并且定义出像素开口，所述第八过孔位于所述像素开口内；和
所述阳极，设置在像素开口内并且通过所述第八过孔与所述漏电极连接。
根据本公开第二方面，提供了一种显示装置，包括上述的显示面板。
根据本公开第三方面，提供了一种显示面板的制造方法，包括：
提供基底，所述基底包括显示区域和位于所述显示区域外围的非显示区域，所述显示区域包括至少一个圆角；
在所述非显示区域中形成栅极驱动电路；和
在位于所述显示区域的所述至少一个圆角外侧形成多个第一虚拟像素，每个所述第一虚拟像素的第一电源线连接所述栅极驱动电路的高电平信号线。
例如，上述方法还包括在所述显示区域中形成多个像素单元，其中每个所述像素单元配置为发光，每个所述虚拟像素配置为不发光。
例如，所述形成多个第一虚拟像素包括：
在所述基底上依次形成缓冲层和有源层；
在所述有源层上形成第一扫描线、第二扫描线、第三扫描线和第一栅电极；
形成第二绝缘层；
在所述第二绝缘层上形成初始电压线和第二栅电极；
形成第三绝缘层，其中所述第三绝缘层覆盖所述初始电压线和所述第二栅电极，所述第三绝缘层上开设有多个过孔，所述多个过孔包括：暴露出所述第二栅电极的第一过孔、第二过孔和第三过孔，暴露出所述有源层的第四过孔、第五过孔和第六过孔，暴露出所述初始电压线的第七过孔；
在所述第三绝缘层上形成数据线、电源线、连接线和漏电极，所述漏电极的一端通过所述第一过孔与所述第二栅电极连接，所述漏电极的另一端通过所述第五过孔与所述有源层连接，所述数据线通过所述第四过孔与所述有源层连接，所述电源线通过所述第二过孔和所述第三过孔与所述第二栅电极连接，所述连接线的一端通过所述第六过孔与所述有源层连接，所述连接线的另一端通过所述第七过孔与所述初始电压线连接；
形成第四绝缘层，所述第四绝缘层上开设有暴露出所述漏电极的第八过孔；
在所述第四绝缘层上形成像素定义层，所述像素定义层定义出像素开口，所述第八过孔位于所述像素开口内；和
在所述像素开口内形成阳极，所述阳极通过所述第八过孔与所述漏电极连接。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开实施例的显示面板的结构示意图；
图2a～图2c为本公开实施例中阶梯状虚拟像素的结构示意图；
图3a为本公开实施例中虚拟像素的结构示意图；
图3b为图3a中A-A向的剖面图；
图4a为本公开实施例形成有源层图案后的示意图；
图4b为图4a中A-A向的剖面图；
图5a为本公开实施例形成第一栅电极图案后的示意图；
图5b为图5a中A-A向的剖面图；
图6a为本公开实施例形成第二栅电极图案后的示意图；
图6b为图6a中A-A向的剖面图；
图7a为本公开实施例形成第三绝缘层图案后的示意图；
图7b为图7a中A-A向的剖面图；
图8a为本公开实施例形成漏电极图案后的示意图；
图8b为图8a中A-A向的剖面图；
图9a为本公开另一实施例中虚拟像素的结构示意图；
图9b为图9a中A-A向的剖面图；
图10为本公开实施例电源线连接高电平信号线的示意图；
图11为本公开实施例扫描线连接栅极驱动电路的示意图；
图12为本公开另一实施例的显示面板的结构示意图；
图13为本公开再一实施例的显示面板的结构示意图；
图14为本公开实施例的显示面板的制造方法的流程图；
图15为本公开实施例的像素驱动电路的框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前，OLED显示面板的圆角设计(即面板的拐角设计为圆角，简称OLED异性屏)越来越普遍，以实现屏幕与电子产品外轮廓形状均一的全面屏概念。但与OLED矩形屏相比，现有具有圆角设计的OLED存在显示品质、可靠性和良品率较低的问题。因此，如何提高OLED的显示品质、可靠性和良品率，是亟待解决的技术问题。
经本公开发明人研究发现，现有OLED异形屏存在显示品质、可靠性和良品率较低问题的原因，是由于圆角位置影响刻蚀均一性造成的。具体地说，由于圆角所在位置不利 于栅极驱动电路和像素驱动电路的的布置，在圆角外侧设置大片的留白区域，造成圆角附近显示区域的像素单元的刻蚀均一性变差，降低了可靠性和良品率。此外，由于刻蚀均一性变差，会引起数据线、电源线、栅极线等信号线的线宽和厚度较大的偏差，使信号线的电阻偏离实际设计值，增加信号延迟，进而影响信号传输速度和传输能力，降低显示区域像素驱动电路的工作稳定性，导致显示品质降低。
为了解决至少一个上述问题，本公开实施例提供了一种显示面板。本公开显示面板包括显示区域和位于所述显示区域外围的非显示区域，所述显示区域包括至少一个圆角，所述非显示区域包括栅极驱动电路和位于所述显示区域的该至少一个圆角外侧的多个虚拟像素，每个所述虚拟像素的电源线连接所述栅极驱动电路的高电平信号线。
本公开实施例提供的显示面板中，通过在非显示区域设置虚拟像素，虚拟像素位于显示区域的圆角外侧，有效提高了圆角位置的刻蚀均一性，同时通过虚拟像素的电源线连接栅极驱动电路的高电平信号线，降低了栅极驱动电路的负载，提高了显示区域像素电路的电性能，有效解决了现有OLED异形屏存在的显示品质、可靠性和良品率较低的问题。
上述显示面板可以为有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板、微发光二极管(Micro Light Emitting Diodes，简称Micro LED)显示面板等，本公开对此不做具体限定。下面通过以上述显示面板为OLED显示面板为例详细说明本公开实施例的技术方案。
图1为本公开实施例的显示面板的结构示意图。如图1所示，本实施例显示面板包括显示区域100、位于显示区域100外围的非显示区域200(例如，围绕显示区100四周)和位于显示区域100的其中一侧的绑定区域300。显示区100包括第一侧边L1和第二侧边L2，且第一侧边L1和第二侧边L2之间通过圆角(或称倒圆角)连接。例如，本公开的显示面板的显示区100至少设置有一个圆角。上述第一侧边L1和第二侧边L2通过圆角连接，即第一侧边L1通过圆角对应的圆弧过渡至第二侧边L2。进一步，至少一个示例中，显示区100可以包括多个圆角。如图1所示，显示区100可以包括一组相对设置的两个第一侧边(L1和L1’)，以及一组相对设置的两个第二侧边(L2和L2’)，两个第一侧边(L1和L1’)在两端与两个第二侧边(L2和L2’)分别通过圆角连接。在此情况下，显示区100包括4个圆角。在其他实施例中，显示区100可以包括一组相对设置的两个第一侧边(L1和L1’)以及一个第二侧边(L2)，两个第一侧边(L1和L1’)在第二侧边(L2)两端分别通过圆角与该第二侧边(L2)连接。在此情况下，显示区100包括2个圆角。以下描述均是以图1中示 出的显示区100包括4个圆角为例做进一步说明。如图1所示，显示区域100中设置有多条栅极线SL和多条数据线DL，栅极线SL和数据线DL交叉形成矩阵排布的多个像素单元P，多个像素单元P用于实现正常显示。多个像素单元P至少包括第一颜色像素单元、第二颜色像素单元和第三颜色像素单元。第一颜色、第二颜色和第三颜色为三基色(例如红色、绿色和蓝色)。
如图1所示，非显示区域200位于显示区域100的外围，非显示区域200中设置有栅极驱动电路、电源信号电路VDD和多个虚拟(Dummy)像素400，例如，显示区域中的栅极线与所述栅极驱动电路连接，栅极驱动电路为栅极线提供驱动电压。至少一个示例中，为了窄化显示装置的边框宽度，降低制作成本，将栅极驱动电路设置为GOA电路，也即将上述栅极驱动电路直接集成在显示面板中的阵列基板中。如图1所示，GOA电路位于显示区域100的两侧，电源信号电路VDD位于显示区域100的下侧，虚拟像素400分别设置在显示区域100左下圆角的外侧和显示区域100右下圆角的外侧，且位于GOA电路与显示区域100之间的区域，多个虚拟像素400用于提高圆角位置的刻蚀均一性，且不能发光。本实施例中，绑定区域300位于显示区域100的其中一侧(例如下侧)并且包括绑定焊盘301，GOA电路通过第一引线302与绑定焊盘301连接，电源信号电路VDD通过第二引线303与绑定焊盘301连接。
至少一些实施例中，每个虚拟像素400至少包括像素驱动电路。例如，如图1所示，虚拟像素400与显示区域100的像素单元P不同的是，虚拟像素400仅设置有与像素单元P相同结构的像素驱动电路，没有设置发光单元，即虚拟像素400不能实现显示。因此，虚拟像素400的像素驱动电路分别与扫描线、数据线和电源线电连接，且电源线连接GOA电路的高电平信号线VGH。例如，如图15所示，显示区域中每个像素单元P的像素驱动电路包括驱动单元和发光单元(例如有机发光二极管OLED)。驱动单元包括晶体管和电容，图15中仅是示意的以该像素驱动电路中的驱动单元为2T1C(一个驱动晶体管T1、一个开关晶体管T2、一个存储电容Cst)结构为例说明的，但本公开实施例并不限制于此，在一些实施例中，驱动单元还可以采用3T1C、4T1C等电路结构。如图15所示，驱动晶体管T1的第一极连接电源线VDD和存储电容Cst的第一电极板，驱动晶体管T1的第二极连接OLED，驱动晶体管T1的栅电极连接开关晶体管T2的第一极和存储电容Cst的第二电极板，开关晶体管T2的栅电极连接扫描线SL，开关晶体管T2的第二极连接数据线DL。例如，OLED包括阴极和阳极，以及位于阴极和阳极之间的发光功能层。发光功能层可以包括有机发光层、位于有机发光层和阳极之间的空穴传输层、位于有机发光层和阴极之间 的电子传输层。当然，根据需要，在一些实施例中，还可以在空穴传输层和阳极之间设置空穴注入层，可以在电子传输层ETL和阴极之间设置电子注入层等等，本公开对此不做限定。
至少一些实施例中，显示区域100左下圆角外侧的多个虚拟像素400，位于GOA电路与显示区域100之间的区域，多个虚拟像素400呈阶梯状排列。同样，显示区域100右下圆角外侧的多个虚拟像素400，位于GOA电路与显示区域100之间的区域，多个虚拟像素400呈阶梯状排列，使多个虚拟像素400按照圆角的走势排布。这样，在竖直方向上，阶梯状排列的虚拟像素400至少包括1列；在水平方向上，阶梯状排列的虚拟像素400至少包括1行。图2a、图2b和图2c为本公开第一实施例阶梯状虚拟像素的结构示意图。图2a所示的阶梯状排列的虚拟像素400包括6行3列，图2b所示的阶梯状排列的虚拟像素400包括3行6列，图2c所示的阶梯状排列的虚拟像素400包括6行6列。
至少一些实施例中，显示区域100远离绑定区域300一侧(上侧)的外侧也设置有多个虚拟像素400，即位于绑定区域300对侧的非显示区域200中设置有多个虚拟像素400，多个虚拟像素400规则排布。在竖直方向上，规则排布的虚拟像素400至少包括1列；在水平方向上，规则排布的虚拟像素400至少包括1行。
上述实施例的显示面板中，通过在显示区域左下圆角外侧和右下圆角外侧设置阶梯状的虚拟像素，使虚拟像素按照圆角的走势填补栅极驱动电路与显示区域之间的区域，解决了圆角区域刻蚀不均的问题，提高了圆角区域刻蚀的均一性，提高了显示面板的可靠性及良品率。同时，通过虚拟像素的电源线连接栅极驱动电路的高电平信号线，使得高电平信号线与虚拟像素的电源线并联连接，降低了高电平信号线的电阻，有效降低了栅极驱动电路的负载，提高了面板的工作稳定性，并降低了功耗。
图3a为本公开实施例的虚拟像素的结构示意图，图3b为图3a中A-A向的剖面图。如图3a和图3b所示，本实施例显示面板的虚拟像素包括：
基底10；
缓冲层11，设置在基底10上；
有源层12，设置在缓冲层11上；
第一绝缘层13，覆盖有源层12；
第一扫描线GN1、第二扫描线GN2、第三扫描线GN3和第一栅电极14，设置在第一绝缘层13上；
第二绝缘层15，覆盖第一扫描线GN1、第二扫描线GN2、第三扫描线GN3和第一栅 电极14；
初始电压线VI和第二栅电极16，设置在第二绝缘层15上；
第三绝缘层17，覆盖初始电压线VI和第二栅电极16，其上开设有多个过孔，多个过孔包括：暴露出第二栅电极16的第一过孔即、第二过孔和第三过孔，暴露出有源层12的第四过孔、第五过孔和第六过孔，暴露出初始电压线VI的第七过孔；
数据线DA、电源线VD、连接线LI和漏电极18，设置在第三绝缘层17上，漏电极18的一端通过第一过孔与第二栅电极连接，漏电极18的另一端通过第五过孔与有源层12连接，数据线DA通过第四过孔与有源层12连接，电源线VD通过第二过孔和第三过孔与第二栅电极16连接，连接线LI的一端通过第六过孔与有源层12连接，连接线LI的另一端通过第七过孔与初始电压线VI连接；
第四绝缘层19，覆盖数据线DA、电源线VD、连接线LI和漏电极18，其上开设有暴露出漏电极18的第八过孔；
像素定义层20，设置在第四绝缘层19上，定义出像素开口，第八过孔位于像素开口内；
阳极21，设置在像素开口内，通过第八过孔与漏电极18连接。
参照图1和图14，本公开实施例还提供了一种上述显示面板的制造方法，包括：
提供基底，所述基底包括显示区域和位于所述显示区域外围的非显示区域，所述显示区域包括至少一个圆角；
在所述非显示区域中形成栅极驱动电路；和
在位于所述显示区域的所述至少一个圆角外侧形成多个第一虚拟像素，每个所述第一虚拟像素的第一电源线连接所述栅极驱动电路的高电平信号线。
本公开实施例提供的显示面板的制造方法中，通过在非显示区域中形成虚拟像素，虚拟像素位于显示区域的圆角外侧，有效提高了圆角位置的刻蚀均一性，同时通过虚拟像素的电源线连接栅极驱动电路的高电平信号线，降低了栅极驱动电路的负载，提高了显示区域像素电路的电性能，有效解决了现有OLED异形屏存在的显示品质、可靠性和良品率较低的问题。
至少一些实施例中，上述方法还包括在所述显示区域中形成多个像素单元，其中每个所述像素单元配置为发光，每个所述虚拟像素配置为不发光。
至少一些实施例中，所述形成多个第一虚拟像素包括：
在所述基底上依次形成缓冲层和有源层；
在所述有源层上形成第一扫描线、第二扫描线、第三扫描线和第一栅电极；
形成第二绝缘层；
在所述第二绝缘层上形成初始电压线和第二栅电极；
形成第三绝缘层，其中所述第三绝缘层覆盖所述初始电压线和所述第二栅电极，所述第三绝缘层上开设有多个过孔，所述多个过孔包括：暴露出所述第二栅电极的第一过孔、第二过孔和第三过孔，暴露出所述有源层的第四过孔、第五过孔和第六过孔，暴露出所述初始电压线的第七过孔；
在所述第三绝缘层上形成数据线、电源线、连接线和漏电极，所述漏电极的一端通过所述第一过孔与所述第二栅电极连接，所述漏电极的另一端通过所述第五过孔与所述有源层连接，所述数据线通过所述第四过孔与所述有源层连接，所述电源线通过所述第二过孔和所述第三过孔与所述第二栅电极连接，所述连接线的一端通过所述第六过孔与所述有源层连接，所述连接线的另一端通过所述第七过孔与所述初始电压线连接；
形成第四绝缘层，所述第四绝缘层上开设有暴露出所述漏电极的第八过孔；
在所述第四绝缘层上形成像素定义层，所述像素定义层定义出像素开口，所述第八过孔位于所述像素开口内；和
在所述像素开口内形成阳极，所述阳极通过所述第八过孔与所述漏电极连接。
下面通过示例进一步说明显示面板的制备方法。本公开中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本公开的描述中，“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。若在整个制作方法当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
(1)在基底上形成缓冲层图案和有源层图案。在基底上形成有源层图案包括：在基底10上依次沉积缓冲薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成覆盖整个基底10的缓冲层11图案以及设置在缓冲层11上的有源层12图案，如图4a和图4b所示，图4b为图4a中A-A向的剖面图。其中，基底可以为柔性基底，采用聚酰亚胺PI、聚对苯二甲酸乙二酯PET或经表面处理的聚合物软膜等材料。缓冲薄膜可以采用氮化硅SiNx或氧化硅SiOx等，可以是单层，也可以是氮化硅/氧化硅的多层结构，有源层可以采用单晶硅、多晶硅或氧化物半导体材料。
(2)形成第一扫描线、第二扫描线、第三扫描线和第一栅电极图案。形成第一扫描线、第二扫描线、第三扫描线和第一栅电极图案包括：在形成前述结构的基底上，依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层12和缓冲层11的第一绝缘层13以及设置在第一绝缘层13上的第一扫描线GN1、第二扫描线GN2、第三扫描线GN3和第一栅电极14图案，如图5a和图5b所示，图5b为图5a中A-A向的剖面图。
(3)形成初始电压线VI和第二栅电极图案。形成初始电压线VI和第二栅电极图案包括：在形成前述结构的基底上，依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一扫描线GN1、第二扫描线GN2、第三扫描线GN3和第一栅电极14的第二绝缘层15以及设置在第二绝缘层15上的初始电压线VI和第二栅电极16图案，如图6a和图6b所示，图6b为图6a中A-A向的剖面图。
(4)形成第三绝缘层图案。形成第三绝缘层图案包括：在形成前述结构的基底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成开设有多个过孔的第三绝缘层17图案，多个过孔包括：暴露出第二栅电极16的第一过孔H1、第二过孔H2和第三过孔H3，暴露出有源层12的第四过孔H4、第五过孔H5和第六过孔H6，暴露出初始电压线VI的第七过孔H7，如图7a和图7b所示，图7b为图7a中A-A向的剖面图。
(5)形成数据线、电源线、连接线和漏电极图案。形成数据线、电源线、连接线和漏电极图案包括：在形成前述结构的基底上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成数据线DA、电源线VD、连接线LI和驱动晶体管的漏电极18图案，漏电极18的一端通过第一过孔H1与第二栅电极16连接，漏电极18的另一端通过第五过孔H5与有源层12连接，数据线DA通过第四过孔H4与有源层12连接，电源线VD通过第二过孔H2和第三过孔H3与第二栅电极16连接，连接线LI的一端通过第六过孔H6与有源层12连接，连接线LI的另一端通过第七过孔H7与初始电压线VI连接，如图8a和图8b所示，图8b为图8a中A-A向的剖面图。
(6)形成像素定义层和阳极图案。形成像素定义层和阳极图案包括：在形成前述结构的基底上，先形成覆盖数据线DA、电源线VD、连接线LI和漏电极18的第四绝缘层19以及设置在第四绝缘层19上的像素定义层20，像素定义层20定义出像素开口，像素开口内的第四绝缘层19上开设有暴露出漏电极18的第八过孔；随后，在形成前述图案的基底上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在像素定义层20定义出的像素开口内形成阳极21图案，阳极21通过第八过孔与漏电极18连接，如图3a和 图3b所示。其中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。
至少一些实施例中，虚拟像素的上述结构与显示区域的像素单元同步形成，第一扫描线、第二扫描线、第三扫描线、初始电压线、数据线、电源线、连接线的结构和作用与显示区域像素驱动电路中相应线的结构和作用相同。第一绝缘层和第二绝缘层也称之为栅绝缘层(GI)，第三绝缘层也称之为层间绝缘层(ILD)，第四绝缘层也称之为平坦化层(PLN)。本实施例中，虚拟像素还包括发光单元。与显示区域中像素单元的OLED发光单元不同的是，OLED像素单元包括后续在阳极上形成的发光层，而虚拟像素所在位置没有形成发光层，即，仅包括阳极和阴极，因此虚拟像素不会进行发光。作为另一种实施方式，虚拟像素可以包括阳极、阴极和发光层，但是阳极不与漏电极电连接，因此，该发光层同样无法发光。
图9a为本公开另一实施例的虚拟像素的结构示意图，图9b为图9a中A-A向的剖面图。如图9a和图9b所示，本实施结构是前述图3a和图3b所示的虚拟像素的一种变型，与前述实施结构不同的是，本实施结构虚拟像素的像素定义层20上没有定义出像素开口，第四绝缘层19上没有开设过孔。本实施例中，显示区域的像素单元后续形成阳极、发光层和阴极时，虚拟像素所在位置可以同样形成阳极、发光层和阴极，可以进一步提高圆角位置的刻蚀均一性。但由于虚拟像素的像素驱动电路与发光层没有电连接，即虚拟像素的阳极没有连接虚拟像素的漏电极，漏电极与阳极属于电隔离，因此虚拟像素不会进行发光。
通过本实施例显示面板的制备过程可以看出，本实施例虚拟像素的像素驱动电路结构与显示区域的像素单元的像素驱动电路结构基本上相同，且两者同步形成，这样，同时在圆角内侧形成显示区域的像素单元和在圆角外侧形成非显示区域的虚拟像素过程中，圆角内侧和圆角外侧同时形成基本相同的膜层结构，因而保证了圆角内侧和圆角外侧结构的连续性，有效提高了圆角位置的刻蚀均一性。圆角附近显示区域的像素单元的刻蚀均一性，保证了数据线、电源线、栅极线等信号线的线宽和厚度符合设计值，不会影响信号传输速度和传输能力。同时，设置虚拟像素的数据线连接数据驱动电路，设置虚拟像素的电源线连接栅极驱动电路的高电平信号线，相当于给栅极驱动电路的高电平信号线走线并联了电源线，降低了高电平信号线的电阻，有效降低了栅极驱动电路的负载，提高了显示区域像素驱动电路的工作稳定性。进一步地，可以设置虚拟像素的第一扫描线、第二扫描线和第三扫描线处于“悬置”状态，即不与任何驱动电路电连接，避免虚拟像素的像素驱动电路影响显示区域的像素驱动电路的工作。实际实施时，也可以设置虚拟像素的第一扫描线、第 二扫描线和第三扫描线连接栅极驱动电路的输出，由于栅极驱动电路的输出具有稳定的电位，使得虚拟像素像素驱动电路可以起到提高电学稳定性的作用。进一步地，本公开实施例制备显示面板的构图次数与现有制备方式的构图次数基本上相同，实施本公开不需要改变现有工艺流程，不需改变现有工艺设备，工艺兼容性好，实用性强，具有良好的应用前景。综上所述，本公开显示面板有效解决了现有OLED异形屏存在的显示品质、可靠性和良品率较低的问题。
图10为本公开的实施例中电源线连接高电平信号线的示意图。如图10所示，由于GOA电路和高电平信号线VGH与虚拟像素同步制备，因此在形成数据线DA和电源线VD的构图工艺中，同时形成电源线VD和高电平信号线VGH，两者为相互连接的一体结构。图11为本公开实施例中扫描线连接栅极驱动电路的示意图。如图11所示，作为一种具体实施方式，可以设置第一扫描线GN1连接第一GOA单元(GOA1)，第二扫描线GN2连接第二GOA单元(GOA2)，第三扫描线GN3连接第一控制电路EMG1，而不连接第三GOA单元(GOA3)。实际实施时，上述连接既可以在一次构图工艺中形成相互连接的一体结构，也可以通过过孔实现连接。
图12为本公开另一实施例的显示面板的结构示意图。本实施例是图1显示面板的一种变型，结构与其基本上相同，图12的显示面板包括显示区域100、位于显示区域100外围的非显示区域200和绑定区域300。与图1显示面板不同的是，如图12所示的本实施例虚拟像素400分别设置在显示区域100左上圆角的外侧和显示区域100右上圆角的外侧，且位于GOA电路与显示区域100之间的区域，此外，位于绑定区域300对侧的非显示区域200中设置有多个虚拟像素400。
例如，在GOA电路与显示区域100之间的区域设置的多个虚拟像素400呈阶梯状排列。进一步，至少一个示例中，在竖直方向上，阶梯状的虚拟像素400至少包括1列，在水平方向上，阶梯状的虚拟像素400至少包括1行。在绑定区域300对侧设置的多个虚拟像素400呈规则排布，例如，多个虚拟像素400等间距排布，这样有利于降低制造难度。至少一个示例中，在竖直方向上，规则排布的虚拟像素400至少包括1列，在水平方向上，规则排布的虚拟像素400至少包括1行。
本实施例同样实现了前述图1实施例的技术效果，提高了圆角位置的刻蚀均一性、降低栅极驱动电路的负载以及提高电学稳定性等。
图13为本公开再一实施例的显示面板的结构示意图。本实施例是图1实施例的一种变型，结构与前述第一实施例基本上相同。图13的显示面板包括显示区域100、位于显 示区域100外围的非显示区域200和绑定区域300。与图1实施例不同的是，如图13所示的本实施例中，虚拟像素400分别设置在显示区域100四个圆角的外侧，四个圆角分别为左上角、右上角、左下角和右下角，且位于GOA电路与显示区域100之间的区域，此外，位于绑定区域300对侧的非显示区域200中设置有多个虚拟像素400。
例如，在GOA电路与显示区域100之间的区域设置的多个虚拟像素400呈阶梯状排列。至少一个示例中，在竖直方向上，阶梯状的虚拟像素400至少包括1列，在水平方向上，阶梯状的虚拟像素400至少包括1行。在绑定区域300对侧设置的多个虚拟像素400呈规则排布。例如，多个虚拟像素400等间距排布，这样有利于降低制造难度。至少一个示例中，在竖直方向上，规则排布的虚拟像素400至少包括1列，在水平方向上，规则排布的虚拟像素400至少包括1行。
本实施例同样实现了前述图1实施例的技术效果，提高了圆角位置的刻蚀均一性、降低栅极驱动电路的负载以及提高电学稳定性等。
虽然前述实施例以显示区域具有四个圆角为例进行了说明，但本公开同样适用于显示区域具有一个圆角、二个圆角、三个圆角或多个圆角。对于显示区域具有四个圆角，虚拟像素也可以仅设置在一个圆角或三个圆角的外侧，或者设置在左上圆角和左下圆角的外侧、设置在右上圆角和右下圆角的外侧、设置在左上圆角和右下圆角的外侧或者设置在左下圆角和右上圆角的外侧等。
本公开实施例还提供了一种显示装置，包括前述的显示面板。显示装置可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置具有前面显示面板的技术效果，此处不再赘述。
本文中，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (18)

  1. 一种显示面板，包括：
    显示区域，所述显示区域包括至少一个圆角；
    位于所述显示区域外围的非显示区域，所述非显示区域包括：
    栅极驱动电路；和
    位于所述显示区域的所述至少一个圆角外侧的多个第一虚拟像素，每个所述第一虚拟像素的第一电源线连接所述栅极驱动电路的高电平信号线。
  2. 根据权利要求1所述的显示面板，其中每个所述第一虚拟像素位于所述栅极驱动电路与所述显示区域之间，每个所述第一虚拟像素配置为不发光。
  3. 根据权利要求1或2所述的显示面板，其中所述多个第一虚拟像素呈阶梯状排列。
  4. 根据权利要求3所述的显示面板，其中所述多个第一虚拟像素在第一方向上包括至少一列，在第二方向上包括至少一行，所述第一方向和所述第二方向相互垂直。
  5. 根据权利要求1至4任一所述的显示面板，其中所述显示面板还包括绑定区域，其中所述绑定区域位于所述显示区域的其中一侧，所述显示区域的与所述绑定区域的相反侧上设置有多个第二虚拟像素，每个所述第二虚拟像素配置为不发光。
  6. 根据权利要求5所述的显示面板，其中每个所述第二虚拟像素的第二电源线连接所述栅极驱动电路的所述高电平信号线。
  7. 根据权利要求5或6所述的显示面板，其中所述多个第二虚拟像素在第一方向和第二方向的至少一个方向上的间距彼此相等，所述第一方向和所述第二方向相互垂直。
  8. 根据权利要求7所述的显示面板，其中所述多个第二虚拟像素在所述第一方向上包括至少一列，在所述第二方向上包括至少一行。
  9. 根据权利要求5至8任一所述的显示面板，包括靠近所述绑定区域的第一圆角和第二圆角，所述多个第一虚拟像素设置在所述第一圆角和所述第二圆角的外侧。
  10. 根据权利要求5至9任一所述的显示面板，包括远离所述绑定区域的第三圆角和第四圆角，所述多个第一虚拟像素设置在所述第三圆角和所述第四圆角的外侧。
  11. 根据权利要求1至10任一所述的显示面板，其中每个所述虚拟像素至少包括像素驱动电路，所述像素驱动电路包括第一扫描线、第二扫描线和第三扫描线，所述第一扫描线、第二扫描线和第三扫描线与所述栅极驱动电路连接，或者处于悬置状态。
  12. 根据权利要求11所述的显示面板，其中每个所述虚拟像素还包括发光单元，所 述像素驱动电路包括驱动晶体管，所述驱动晶体管包括漏电极，所述发光单元包括阳极且不包括发光层，所述驱动晶体管的所述漏电极与所述发光单元的所述阳极电连接。
  13. 根据权利要求11所述的显示面板，其中每个所述虚拟像素还包括发光单元，所述像素驱动电路包括驱动晶体管，所述驱动晶体管包括的漏电极，所述发光单元包括阳极、发光层和阴极，所述驱动晶体管的漏电极与所述发光单元的阳极电隔离。
  14. 根据权利要求12所述的显示面板，其中每个所述虚拟像素包括：
    基底；
    缓冲层，设置在所述基底上；
    有源层，设置在缓冲层上；
    第一绝缘层，覆盖所述有源层；
    同层设置的所述第一扫描线、所述第二扫描线、所述第三扫描线和第一栅电极，所述第一扫描线、所述第二扫描线、所述第三扫描线和所述第一栅电极设置在所述第一绝缘层上；
    第二绝缘层，所述第一绝缘层覆盖所述第一扫描线、所述第二扫描线、所述第三扫描线和所述第一栅电极；
    同层设置的初始电压线和第二栅电极，所述初始电压线和所述第二栅电极设置在所述第二绝缘层上；
    第三绝缘层，覆盖所述初始电压线和所述第二栅电极，所述第三绝缘层上开设有多个过孔，所述多个过孔包括：暴露出所述第二栅电极的第一过孔、第二过孔和第三过孔，暴露出所述有源层的第四过孔、第五过孔和第六过孔，暴露出所述初始电压线的第七过孔；
    同层设置的数据线、电源线、连接线和所述漏电极，所述数据线、所述电源线、所述连接线和所述漏电极设置在所述第三绝缘层上，所述漏电极的一端通过所述第一过孔与所述第二栅电极连接，所述漏电极的另一端通过所述第五过孔与所述有源层连接，所述数据线通过所述第四过孔与所述有源层连接，所述电源线通过所述第二过孔和所述第三过孔与所述第二栅电极连接，所述连接线的一端通过所述第六过孔与所述有源层连接，所述连接线的另一端通过所述第七过孔与所述初始电压线连接；
    第四绝缘层，覆盖所述数据线、所述电源线、所述连接线和所述漏电极，所述第四绝缘层上开设有暴露出所述漏电极的第八过孔；
    像素定义层，设置在所述第四绝缘层上并且定义出像素开口，所述第八过孔位于所述像素开口内；和
    所述阳极，设置在像素开口内并且通过所述第八过孔与所述漏电极连接。
  15. 一种显示装置，其中包括如权利要求1至14任一所述的显示面板。
  16. 一种显示面板的制造方法，包括：
    提供基底，所述基底包括显示区域和位于所述显示区域外围的非显示区域，所述显示区域包括至少一个圆角；
    在所述非显示区域中形成栅极驱动电路；和
    在位于所述显示区域的所述至少一个圆角外侧形成多个第一虚拟像素，每个所述第一虚拟像素的第一电源线连接所述栅极驱动电路的高电平信号线。
  17. 根据权利要求16所述的方法，还包括在所述显示区域中形成多个像素单元，其中每个所述像素单元配置为发光，每个所述虚拟像素配置为不发光。
  18. 根据权利要求16或17所述的方法，其中，所述形成多个第一虚拟像素包括：
    在所述基底上依次形成缓冲层和有源层；
    在所述有源层上形成第一扫描线、第二扫描线、第三扫描线和第一栅电极；
    形成第二绝缘层；
    在所述第二绝缘层上形成初始电压线和第二栅电极；
    形成第三绝缘层，其中所述第三绝缘层覆盖所述初始电压线和所述第二栅电极，所述第三绝缘层上开设有多个过孔，所述多个过孔包括：暴露出所述第二栅电极的第一过孔、第二过孔和第三过孔，暴露出所述有源层的第四过孔、第五过孔和第六过孔，暴露出所述初始电压线的第七过孔；
    在所述第三绝缘层上形成数据线、电源线、连接线和漏电极，所述漏电极的一端通过所述第一过孔与所述第二栅电极连接，所述漏电极的另一端通过所述第五过孔与所述有源层连接，所述数据线通过所述第四过孔与所述有源层连接，所述电源线通过所述第二过孔和所述第三过孔与所述第二栅电极连接，所述连接线的一端通过所述第六过孔与所述有源层连接，所述连接线的另一端通过所述第七过孔与所述初始电压线连接；
    形成第四绝缘层，所述第四绝缘层上开设有暴露出所述漏电极的第八过孔；
    在所述第四绝缘层上形成像素定义层，所述像素定义层定义出像素开口，所述第八过孔位于所述像素开口内；和
    在所述像素开口内形成阳极，所述阳极通过所述第八过孔与所述漏电极连接。
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