WO2018038814A1

WO2018038814A1 - Dummy pixels in electronic device displays

Info

Publication number: WO2018038814A1
Application number: PCT/US2017/041410
Authority: WO
Original assignee: Groturbel Research Llc
Priority date: 2016-08-26
Filing date: 2017-07-10
Publication date: 2018-03-01

Abstract

An organic light-emitting diode display may have an active area and an inactive area. The active area may include an array of display pixels that emit light, while the inactive area may include dummy pixels that do not emit light. To provide increased flexibility for placement of electronic components around the display, at least one row of dummy pixels may have a first portion that is positioned above the active area and a second portion that is positioned below the active area. The last row in the active area of the display may be coupled to a gate driver row block. That gate driver row block may output in parallel a first control signal and a second control signal for first and second respective gate driver row blocks.

Description

Dummy Pixels in Electronic Device Displays

This application claims priority to United States provisional patent application No. 62/380, 110, filed on August 26, 2016, which is hereby incorporated herein in its entirety.

Background

[0001] This relates generally to electronic devices, and, more particularly, to electronic devices with displays.

[0002] Electronic devices often include displays. For example, an electronic device may have an organic light-emitting diode display based on organic-light-emitting diode pixels or a liquid crystal display based on liquid crystal pixels. In organic light-emitting diode displays, each pixel includes a light-emitting diode and thin-film transistors for controlling application of a signal to the light-emitting diode to produce light. The thin- film transistors include drive transistors. Each drive transistor is coupled in series with a respective light-emitting diode and controls current flow through that light-emitting diode.

[0003] The threshold voltages of the drive transistors in an organic light-emitting diode display may vary due to operating history effects, which can lead to brightness

nonuniformity. If care is not taken, effects such as these may adversely affect display performance.

[0004] It would therefore be desirable to be able to provide improved displays for electronic devices.

Summary

[0005] An electronic device may have a display such as an organic light-emitting diode display. The organic light-emitting diode display may have an array of organic light-emitting diode pixels that each have a light-emitting diode and a drive transistor.

[0006] An organic light-emitting diode display may have an active area and an inactive area. The active area may include an array of display pixels that emit light, while the inactive area may include dummy pixels that do not emit light. The dummy pixels may be formed below the active area of the display. Alternatively, at least one row of dummy pixels may have a first portion that is positioned above the active area and a second portion that is positioned below the active area.

[0007] The display may include gate driver circuitry with a gate driver row block coupled to each row in the display. The last row in the active area of the display may be coupled to a gate driver row block. That gate driver row block may output in parallel a first control signal and a second control signal. The first control signal may be received by a gate driver row block for dummy pixels above the active area, whereas the second control signal may be received by a gate driver row block for dummy pixels below the active area.

[0008] The active area of the display may have a rectangular shape with an upper left rounded corner, an upper right rounded corner, a lower left rounded corner, and a lower right rounded corner. The upper left rounded corner and the upper right rounded corner may be connected by a planar upper surface of the active area. A first portion of at least one row of dummy pixels may be positioned beneath the lower left rounded corner and the lower right rounded corner, while a second portion of the at least one row of dummy pixels may be positioned above the planar upper surface of the active area. The lower left rounded corner and the lower right rounded corner may be connected by a planar lower surface of the active area and an electronic component may be positioned adjacent the planar lower surface of the active area. Brief Description of the Drawings

[0009] FIG. 1 is a schematic diagram of an illustrative electronic device having a display in accordance with an embodiment.

[0010] FIG. 2 is a schematic diagram of an illustrative display in accordance with an embodiment.

[0011] FIG. 3 is a diagram of an illustrative pixel circuit in accordance with an

embodiment.

[0012] FIG. 4 is a timing diagram of illustrative gate driver circuitry for an electronic device display in accordance with an embodiment.

[0013] FIG. 5 is a top view of an illustrative display with four rows of dummy pixels positioned below the active area of the display in accordance with an embodiment.

[0014] FIG. 6 is a top view of the lower left corner of the illustrative display shown in FIG. 5 in accordance with an embodiment.

[0015] FIG. 7 is a schematic diagram showing illustrative gate driver circuitry for the display of FIG. 5 in accordance with an embodiment.

[0016] FIG. 8 is a top view of an illustrative display with two rows of dummy pixels positioned below the active area of the display and two rows of dummy pixels positioned above the active area of the display in accordance with an embodiment.

[0017] FIG. 9 is a top view of the lower left corner of the illustrative display shown in FIG. 8 in accordance with an embodiment.

[0018] FIG. 10 is a top view of the upper left corner of the illustrative display shown in FIG. 8 in accordance with an embodiment.

[0019] FIG. 11 is a schematic diagram showing illustrative gate driver circuitry for the display of FIG. 8 in accordance with an embodiment.

[0020] FIG. 12 is a top view of an illustrative display with four rows of dummy pixels positioned above the active area of the display in accordance with an embodiment.

[0021] FIG. 13 is a top view of the upper left corner of the illustrative display shown in FIG. 12 in accordance with an embodiment.

[0022] FIG. 14 is a schematic diagram showing illustrative gate driver circuitry for the display of FIG. 12 in accordance with an embodiment.

[0023] FIG. 15 is a top view of an illustrative display with portions of four rows of dummy pixels positioned below the active area of the display and portions of four rows of dummy pixels positioned above the active area of the display in accordance with an embodiment.

[0024] FIG. 16 is a top view of the upper left corner of the illustrative display shown in FIG. 15 in accordance with an embodiment.

[0025] FIG. 17 is a top view of the lower left corner of the illustrative display shown in FIG. 15 in accordance with an embodiment.

[0026] FIG. 18 is a schematic diagram showing illustrative gate driver circuitry for the display of FIG. 15 in accordance with an embodiment.

Detailed Description

[0027] An illustrative electronic device of the type that may be provided with a display is shown in FIG. 1. Electronic device 10 may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic device, a smaller device such as a wrist-watch device, a pendant device, a headphone or earpiece device, a device embedded in eyeglasses or other equipment worn on a user's head, or other wearable or miniature device, a display, a computer display that contains an embedded computer, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment with a display is mounted in a kiosk or automobile, or other electronic equipment. Electronic device 10 may have the shape of a pair of eyeglasses (e.g., supporting frames), may form a housing having a helmet shape, or may have other configurations to help in mounting and securing the components of one or more displays on the head or near the eye of a user.

[0028] As shown in FIG. 1, electronic device 10 may include control circuitry 16 for supporting the operation of device 10. The control circuitry may include storage such as hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically- programmable-read-only memory configured to form a solid state drive), volatile memory (e.g., static or dynamic random-access memory), etc. Processing circuitry in control circuitry 16 may be used to control the operation of device 10. The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc.

[0029] Input-output circuitry in device 10 such as input-output devices 12 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands through input-output devices 12 and may receive status information and other output from device 10 using the output resources of input-output devices 12.

[0030] Input-output devices 12 may include one or more displays such as display 14. Display 14 may be a touch screen display that includes a touch sensor for gathering touch input from a user or display 14 may be insensitive to touch. A touch sensor for display 14 may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements. A touch sensor for display 14 may be formed from electrodes formed on a common display substrate with the pixels of display 14 or may be formed from a separate touch sensor panel that overlaps the pixels of display 14. If desired, display 14 may be insensitive to touch (i.e., the touch sensor may be omitted). Display 14 in electronic device 10 may be a head-up display that can be viewed without requiring users to look away from a typical viewpoint or may be a head-mounted display that is incorporated into a device that is worn on a user's head. If desired, display 14 may also be a holographic display used to display holograms.

[0031] Control circuitry 16 may be used to run software on device 10 such as operating system code and applications. During operation of device 10, the software running on control circuitry 16 may display images on display 14.

[0032] FIG. 2 is a diagram of an illustrative display. As shown in FIG. 2, display 14 may include layers such as substrate layer 26. Substrate layers such as layer 26 may be formed from rectangular planar layers of material or layers of material with other shapes (e.g., circular shapes or other shapes with one or more curved and/or straight edges). The substrate layers of display 14 may include glass layers, polymer layers, composite films that include polymer and inorganic materials, metallic foils, etc.

[0033] Display 14 may have an array of pixels 22 for displaying images for a user such as pixel array 28. Pixels 22 in array 28 may be arranged in rows and columns. The edges of array 28 may be straight or curved (i.e., each row of pixels 22 and/or each column of pixels 22 in array 28 may have the same length or may have a different length). There may be any suitable number of rows and columns in array 28 (e.g., ten or more, one hundred or more, or one thousand or more, etc.). Display 14 may include pixels 22 of different colors. As an example, display 14 may include red pixels, green pixels, and blue pixels. If desired, a backlight unit may provide backlight illumination for display 14.

[0034] Display driver circuitry 20 may be used to control the operation of pixels 28.

Display driver circuitry 20 may be formed from integrated circuits, thin-film transistor circuits, and/or other suitable circuitry. Illustrative display driver circuitry 20 of FIG. 2 includes display driver circuitry 20A and additional display driver circuitry such as gate driver circuitry 20B. Gate driver circuitry 20B may be formed along one or more edges of display 14. For example, gate driver circuitry 20B may be arranged along the left and right sides of display 14 as shown in FIG. 2.

[0035] As shown in FIG. 2, display driver circuitry 20A (e.g., one or more display driver integrated circuits, thin-film transistor circuitry, etc.) may contain communications circuitry for communicating with system control circuitry over signal path 24. Path 24 may be formed from traces on a flexible printed circuit or other cable. The control circuitry may be located on one or more printed circuits in electronic device 10. During operation, control circuitry (e.g., control circuitry 16 of FIG. 1) may supply circuitry such as a display driver integrated circuit in circuitry 20 with image data for images to be displayed on display 14. Display driver circuitry 20A of FIG. 2 is located at the top of display 14. This is merely illustrative. Display driver circuitry 20 A may be located at both the top and bottom of display 14 or in other portions of device 10.

[0036] To display the images on pixels 22, display driver circuitry 20A may supply corresponding image data to data lines D while issuing control signals to supporting display driver circuitry such as gate driver circuitry 20B over signal paths 30. With the illustrative arrangement of FIG. 2, data lines D run vertically through display 14 and are associated with respective columns of pixels 22.

[0037] Gate driver circuitry 20B (sometimes referred to as gate line driver circuitry or horizontal control signal circuitry) may be implemented using one or more integrated circuits and/or may be implemented using thin-film transistor circuitry on substrate 26. Horizontal control lines G (sometimes referred to as gate lines, scan lines, emission control lines, etc.) run horizontally through display 14. Each gate line G is associated with a respective row of pixels 22. If desired, there may be multiple horizontal control lines such as gate lines G associated with each row of pixels. Individually controlled and/or global signal paths in display 14 may also be used to distribute other signals (e.g., power supply signals, etc.).

[0038] Gate driver circuitry 20B may assert control signals on the gate lines G in display

14. For example, gate driver circuitry 20B may receive clock signals and other control signals from circuitry 20A on paths 30 and may, in response to the received signals, assert a gate line signal on gate lines G in sequence, starting with the gate line signal G in the first row of pixels 22 in array 28. As each gate line is asserted, data from data lines D may be loaded into a corresponding row of pixels. In this way, control circuitry such as display driver circuitry 20A and 20B may provide pixels 22 with signals that direct pixels 22 to display a desired image on display 14. Each pixel 22 may have a light-emitting diode and circuitry (e.g., thin- film circuitry on substrate 26) that responds to the control and data signals from display driver circuitry 20.

[0039] Gate driver circuitry 20B may include blocks of gate driver circuitry such as gate driver row blocks. Each gate driver row block may include circuitry such output buffers and other output driver circuitry, register circuits (e.g., registers that can be chained together to form a shift register), and signal lines, power lines, and other interconnects. Each gate driver row block may supply one or more gate signals to one or more respective gate lines in a corresponding row of the pixels of the array of pixels in the active area of display 14.

[0040] A schematic diagram of an illustrative pixel circuit of the type that may be used for each pixel 22 in array 28 is shown in FIG. 3. As shown in FIG. 3, display pixel 22 may include light-emitting diode 38. A positive power supply voltage ELVDD may be supplied to positive power supply terminal 34 and a ground power supply voltage ELVSS may be supplied to ground power supply terminal 36. Diode 38 has an anode (terminal AN) and a cathode (terminal CD). The state of drive transistor 32 controls the amount of current flowing through diode 38 and therefore the amount of emitted light 40 from display pixel 22. Cathode CD of diode 38 is coupled to ground terminal 36, so cathode terminal CD of diode 38 may sometimes be referred to as the ground terminal for diode 38.

[0041] To ensure that transistor 38 is held in a desired state between successive frames of data, display pixel 22 may include a storage capacitor such as storage capacitor Cst. The voltage on storage capacitor Cst is applied to the gate of transistor 32 at node A to control transistor 32. Data can be loaded into storage capacitor Cst using one or more switching transistors such as switching transistor 30. When switching transistor 30 is off, data line D is isolated from storage capacitor Cst and the gate voltage on terminal A is equal to the data value stored in storage capacitor Cst (i.e., the data value from the previous frame of display data being displayed on display 14). When gate line G (sometimes referred to as a scan line) in the row associated with display pixel 22 is asserted, switching transistor 30 will be turned on and a new data signal on data line D will be loaded into storage capacitor Cst. The new signal on capacitor Cst is applied to the gate of transistor 32 at node A, thereby adjusting the state of transistor 32 and adjusting the corresponding amount of light 40 that is emitted by light-emitting diode 38. If desired, the circuitry for controlling the operation of light-emitting diodes for display pixels in display 14 (e.g., transistors, capacitors, etc. in display pixel circuits such as the display pixel circuit of FIG. 3) may be formed using other configurations (e.g., configurations that include circuitry for compensating for threshold voltage variations in drive transistor 32, etc.). The display pixel circuit of FIG. 3 is merely illustrative.

Additionally, the example in FIG. 3 of pixel 22 being a light-emitting diode pixel is merely illustrative. If desired, display 14 of electronic device 10 may have liquid crystal pixels or any other desired type of pixels.

[0042] FIG. 4 is a timing diagram for an illustrative display showing how the gate line signal G may be asserted in sequence for each row in the display. The display may have a number of rows (n) in the active area and each row may have a corresponding gate line signal G (i.e., Gi, G2, G3. . . Gn-4, G_n-3, G_n-2, G_n-i , G_n). The timing diagram of FIG. 4 begins with gate line signal G_n-4 (i-e., the gate line signal for the row four rows above the last row in the active area). As shown, the gate line signal may be pulsed three times for each row. The first two gate line signal pulses 42 and 44 may occur during an initialization period for the row, while the final gate line signal pulse 46 may occur during an emission period for the row. The gate line signal for the subsequent row (Gn-3) may follow a similar pattern as G_n-4 with a slightly offset timing. This pattern may continue throughout each row in the display. The last row in the active area of the display may have an associated gate line signal G_n. The gate line signal G_n may have associated gate line pulses 48, 50, and 52.

[0043] As shown in FIG. 4, the sequence of gate line signal pulses results in different rows asserting the gate line signal at the same time. For example, consider the first pulse of G_n

(48). This gate line pulse occurs at the same time as pulse 46 of G_n-4 and pulse 54 of G_n-2- In general, each gate line signal assertion may occur at the same time as two other gate line signal assertions. This scheme relies upon each row having a sufficient number of rows below each row in the display. The third pulse 46 of G_n-4, for example, overlaps the pulses of

Gn-2 and G_n. Four rows of pixels below G_n-4 are required for pulse 46 to overlap two additional pulses as desired. This may become problematic for the last rows in the active area of the display. Take the last row in the active area of the display as an example. G_n may be the gate line signal for the last row in the active area of the display. Without any rows of dummy pixels, the third pulse 52 of G_n may not overlap any other pulses. This inconsistency may result in the data loading of the final row being inconsistent with the other rows, resulting in a non-uniform display. To prevent these inconsistencies, four rows of dummy pixels may be provided for each column of display pixels. The dummy pixels may have gate line signals G_n+i , G_n+2, G_n+3, and G_n+4, that are pulsed with the same scheme as the pixels in the active area. The dummy pixels, however, will not actually emit light. The pulsing of the dummy pixels may ensure that the loading of the last rows in the active area of the display is consistent. For example, the third pulse 52 of G_nmay overlap pulse 56 of Gn+2 and pulse 58

[0044] Each column of pixels in the display may require four dummy pixels. There are a number of ways to position the dummy pixels within the display. FIG. 5 shows an illustrative arrangement for dummy pixels below the active area of the display. As shown, active area 62 may have a rectangular shape with rounded corners 66. Each rounded corner may be defined by a spline, which may be the optimal outline for the active area of the display. There may be an upper left rounded corner that is connected to an upper right rounded corner by planar upper surface 84. The lower left rounded corner may be connected to the lower right rounded corner by planar lower surface 86. Outside of the spline, dummy pixels 64 may be positioned below the active area of the display. Each column of pixels may have an associated four dummy pixels, such that the dummy pixels have a rounded corner similar to the active area of the display.

[0045] Also shown in FIG. 5 is illustrative gate driver circuitry. Gate driver circuitry for display 14 may include blocks of gate driver circuitry such as gate driver row blocks 68. Each gate driver row block may include circuitry such output buffers and other output driver circuitry, register circuits (e.g., registers that can be chained together to form a shift register), and signal lines, power lines, and other interconnects. During operation of display 14, a signal (such as a clock signal) may be provided to the gate driver row block associated with the first row in the display. The signal may propagate through the subsequent gate driver row blocks all the way to the bottom of the display along path 70. The gate driver row blocks may assert their respective gate line signal upon receiving the input signal. Thus, by propagating the input signal through all of the rows in the display, all of the rows in the display will load the corresponding data for illumination.

[0046] FIG. 6 is a zoomed in version of a portion of an illustrative display with dummy pixels below the active area of the display. FIG. 6 shows the lower left rounded corner of a display such as display 14 in FIG. 5. The display may include display pixels 22-1 and dummy pixels 22-2. As shown, each column of pixels may have four dummy pixels below the last display pixel. This ensures that each column has a sufficient number of dummy pixels for precise data loading of the pixels in the active area. The dummy pixels may have a spline edge that matches the spline edge of the active area of the display.

[0047] FIG. 7 is a diagram of illustrative gate driver circuitry for a display such as display 14 in FIG. 5. As shown, gate driver circuitry 20B may include a number of gate driver row blocks 68. Because the gate driver row blocks may be chained together to form a shift register, gate driver row block 1 may pass a control signal (such as a clock signal) to gate driver row block 2 after receiving the signal. The signal may in turn be passed from gate driver row block 2 to subsequent gate driver row blocks. When the signal reaches the last gate driver row block in the active area of the display (gate driver row block N), the signal may be passed to the gate driver row block for the first row of dummy pixels (gate driver row block N+l). The signal may ultimately be passed to gate driver row block N+2, gate driver row block N+3, and gate driver row block N+4. As shown in FIG. 7, the gate driver row blocks for the dummy pixels may all be positioned below the gate driver row block for the last row in the active area of the display.

[0048] The example in FIGS. 5-7 of four dummy pixel rows being included below the active area of the display is merely illustrative. If desired, some of the dummy pixels may be positioned below the active area of the display while other dummy pixels may be positioned above the active area of the display.

[0049] FIG. 8 shows an illustrative example where two rows of dummy pixels are positioned below the active area of the display and two rows of dummy pixels are positioned above the active area of the display. The first portion of dummy pixels 64-1 may be positioned below active area 62. Dummy pixels 64- 1 may include two rows of dummy pixels below each column that is between the planar upper surface and the planar lower surface of the active area. Some of the columns that form the rounded corners of the active area may have three or four dummy pixels below the active area. Display 14 may also include a second portion of dummy pixels 64-2. Dummy pixels 64-2 may include two rows of dummy pixels above each column that is between the planar upper surface and the planar lower surface of the active area. Additional dummy pixels may be necessary to ensure that each column has four dummy pixels. However, unlike the dummy pixels below the active area, the dummy pixels above the active area may not follow the rounded corners of the upper portion of the active area. If dummy pixels 64-2 conformed to the border of the active area (similar to dummy pixels 64-1), then some of the dummy pixels 64-2 would be in the same row as active area pixels. This would undesirably require readdressing the active area pixels to address the dummy pixels. To prevent this from occurring, dummy pixels 64-2 may not be positioned in the same row as active area pixels.

[0050] Also shown in FIG. 8 is an arrangement for gate driver row blocks 68. During operation of display 14, a signal (such as a clock signal) may be provided to the gate driver row block associated with the first row in the display. The signal may propagate through the subsequent gate driver row blocks all the way to the bottom of the display (including the dummy pixel rows) along path 70. However, in order to then reach the dummy pixels at the top of the display, the signal may continue along path 70 to dummy pixels 64-2. The signal may propagate through dummy pixels 64-2 until all of the rows have been addressed.

[0051] FIG. 9 is a zoomed in version of a portion of an illustrative display with dummy pixels below and above the active area of the display. FIG. 9 shows the lower left rounded corner of a display such as display 14 in FIG. 8. The display may include display pixels 22-1 and dummy pixels 22-2. As shown, each column of pixels that forms the planar lower surface may have two dummy pixels below the last display pixel. The dummy pixels 64-1 may have a spline edge that approximately matches the spline edge of the active area of the display. However, to ensure each row of dummy pixels is kept continuous, no dummy pixels may be included after the second row of dummy pixels that is below the planar lower surface.

[0052] FIG. 10 is a zoomed in version of a portion of an illustrative display with dummy pixels below and above the active area of the display. FIG. 10 shows the upper left rounded corner of a display such as display 14 in FIG. 8. The display may include display pixels 22-

1 and dummy pixels 22-2. As shown, each column of pixels that forms the planar upper surface may have two dummy pixels above the active area. However, unlike in FIG. 9, dummy pixels 64-2 do not have a spline edge that matches the spline edge of the active area of the display. Dummy pixels 64-2 may be arranged such that no dummy pixels 22-2 are included in the same row as display pixels 22-1. Thus, additional dummy pixels may be included to ensure that each column has four dummy pixels. However, some of these dummy pixels may be separated from the underlying active area pixels by a gap such as gap 88.

[0053] FIG. 11 is a diagram of illustrative gate driver circuitry for a display such as display

14 in FIG. 8. As shown, gate driver circuitry 20B may include a number of gate driver row blocks 68. Because the gate driver row blocks may be chained together to form a shift register, gate driver row block 1 may pass a signal (such as a clock signal) to gate driver row block 2 after receiving the signal. The signal may in turn be passed from gate driver row block 2 to subsequent gate driver row blocks. When the signal reaches the last gate driver row block in the active area of the display (gate driver row block N), the signal may be passed to the gate driver row block for the first row of dummy pixels (gate driver row block N+l) and then the second row of dummy pixels (gate driver row block N+2). Gate driver row blocks N+l and N+2 may be positioned at the bottom of the display below the active area. Then, in order to reach the dummy pixels that are above the active area of the display, the signal may be passed from gate driver row block N+2 below the active area of the display to gate driver row block N+3 above the active area of the display. The signal may finally reach gate driver row block N+4 to ensure all of the dummy pixels are addressed.

[0054] FIG. 12 shows yet another arrangement for dummy pixels in a display. Four rows of dummy pixels may be positioned above the active area of the display. Dummy pixels 64-2 may include four rows of dummy pixels above each column that forms the planar upper surface of the active area. Additionally, in the rounded corner regions dummy pixels 64-1 may be included. Dummy pixels 64- 1 may include four dummy pixels below each column if possible, while ensuring no dummy pixels are positioned below the last row of the active area of the display. The dummy pixels above the active area may not follow the rounded corners of the upper portion of the active area. If dummy pixels 64-2 conformed to the border of the active area, then some of the dummy pixels 64-2 would be in the same row as active area pixels. This would undesirably require readdressing the active area pixels to address the dummy pixels. To prevent this from occurring, dummy pixels 64-2 may be arranged such that no dummy pixels are included in the same row as display pixels in the active area.

[0055] Also shown in FIG. 12 is an arrangement for gate driver row blocks 68. During operation of display 14, a signal (such as a clock signal) may be provided to the gate driver row block associated with the first row in the display. The signal may propagate through the subsequent gate driver row blocks all the way to the bottom of the display along path 70. In order to then reach the dummy pixels at the top of the display, the signal may continue along path 70 to dummy pixels 64-2. The signal may propagate through dummy pixels 64-2 until all of the rows have been addressed.

[0056] FIG. 13 is a zoomed in version of a portion of an illustrative display with dummy pixels above the active area of the display. FIG. 13 shows the upper left rounded corner of a display such as display 14 in FIG. 12. The display may include display pixels 22-1 and dummy pixels 22-2. As shown, each column of pixels that forms the planar upper surface of the active area may have four dummy pixels above the active area. Additionally, dummy pixels may be included to ensure that each column has four dummy pixels. However, the dummy pixels may not have a spline edge that matches the spline edge of the active area of the display. Dummy pixels 64-2 may be arranged such that no dummy pixels 22-2 are included in the same row as display pixels 22-1. However, some of these dummy pixels may be separated from the underlying active area pixels by a gap such as gap 88.

[0057] FIG. 14 is a diagram of illustrative gate driver circuitry for a display such as display 14 in FIG. 12. As shown, gate driver circuitry 20B may include a number of gate driver row blocks 68. Because the gate driver row blocks may be chained together to form a shift register, gate driver row block 1 may pass a signal (such as a clock signal) to gate driver row block 2 after receiving the signal. The signal may in turn be passed from gate driver row block 2 to subsequent gate driver row blocks. After the signal reaches the last gate driver row block in the active area of the display (gate driver row block N), the signal may be passed to the gate driver row block for the first row of dummy pixels (gate driver row block N+l) above the active area of the display. The signal may then propagate through gate driver row blocks N+2, N+3, and N+4. Gate driver row blocks N+l, N+2, N+3, and N+4 may be positioned at the top of the display above the active area.

[0058] The embodiments shown in FIGS. 5, 8, and 12 are merely illustrative. The examples of all of the rows of dummy pixels being positioned above the active area, all of the rows of dummy pixels being positioned below the active area, and two rows of dummy pixels being positioned below the active area with two rows of dummy pixels being positioned above the active area are not meant to be limiting in any way, and other arrangements may be used if desired. The pixels may be positioned on opposing sides (i.e., top and bottom) of the active area with a row split of one-to-three (i.e., one row above the active area and three rows below the active area) or three-to-one (i.e., three rows above the active area and one row below the active area), as examples. The particular arrangement of the dummy pixels may depend on where additional electronic components in the electronic device are located. For example, if it was necessary to include an electronic component above the active area of the display, the dummy pixels may all be positioned below the active area of the display. Similarly, if it was necessary to include an electronic component below the active area of the display, the dummy pixels may all be positioned above the active area of the display. To further optimize the space for electronic components around the display, the rows of dummy pixels may be split into separate parts. In the embodiments shown in FIGS. 5, 8, and 12, each row of dummy pixels was kept in a continuous row. However, if desired, a row of dummy pixels may be split such that a portion of the row is above the active area of the display and a portion of the row is below the active area of the display.

[0059] FIG. 15 shows an illustrative display with rows of dummy pixels that are split into separate parts. As shown in FIG. 15, a first portion of dummy pixels 64-1 may be positioned below the active area of the display, whereas a second portion of dummy pixels 64-2 may be positioned above the active area of the display. Dummy pixels 64- 1 may include four rows of dummy pixels that are positioned adjacent the rounded corners of the active area of the display. Dummy pixels 64-2 may include four rows of dummy pixels that are positioned adjacent the planar upper portion of the active area. Therefore, the first row of dummy pixels has a first portion that is positioned below the active area and a second portion that is positioned above the active area. This type of arrangement may provide additional room for electronic components such as electronic components 82.

[0060] Components 82 may include integrated circuits, connectors, sensors, display components, audio components, switches, discrete components such as inductors, capacitors, and resistors, buttons, a camera flash (e.g., a light-emitting diode), antennas, integrated circuits, vibrator motors and other actuators, cameras, SIM cards, memory cards, and other electrical components. Components 82 may also include mechanical components such as lanyard mounting hardware, internal housing frame structures, and other components.

[0061] Also shown in FIG. 15 is an arrangement for gate driver row blocks 68. During operation of display 14, a signal (such as a clock signal) may be provided to the gate driver row block associated with the first row in the display. The signal may propagate through the subsequent gate driver row blocks all the way to the bottom of the active area of the display along path 70. However, in order to reach the dummy pixels at both the top and bottom of the display, path 70 may diverge into a first portion that continues to dummy pixels 64-1 and a second portion that continues to dummy pixels 64-2 at the top of the display. The signal may propagate in parallel through dummy pixels 64- 1 and 64-2 until all of the rows have been addressed. [0062] It should be noted that the examples of gate driver row blocks 68 being positioned on the left side of active area 62 in FIGS. 5, 8, 12, and 15 are merely illustrative. If desired, gate driver row blocks 68 may be positioned on the right side of active area 62. In yet another embodiment, gate driver row blocks 68 may be positioned on both the left and right sides of active area 62 (as shown in FIG. 2, for example).

[0063] FIG. 16 is a zoomed in version of a portion of an illustrative display with dummy pixels below and above the active area of the display. FIG. 16 shows the upper left rounded corner of a display such as display 14 in FIG. 15. The display may include display pixels

22-1 and dummy pixels 22-2. As shown, each column of pixels that forms a planar upper surface of the active area may have four dummy pixels above the active area. The columns of pixels in the rounded edge region may have no dummy pixels above the active area.

[0064] FIG. 17 is a zoomed in version of a portion of an illustrative display with dummy pixels below and above the active area of the display. FIG. 17 shows the lower left rounded corner of a display such as display 14 in FIG. 15. The display may include display pixels

22-1 and dummy pixels 22-2. As shown, each column of pixels that forms a planar lower surface of the active area may have no dummy pixels below the active area. The columns of pixels in the rounded edge region may have four dummy pixels below the active area.

[0065] FIG. 18 is a diagram of illustrative gate driver circuitry for a display such as display

14 in FIG. 15. As shown, gate driver circuitry 20B may include a number of gate driver row blocks 68. Because the gate driver row blocks may be chained together to form a shift register, gate driver row block 1 may pass a signal (such as a clock signal) to gate driver row block 2 after receiving the signal. The signal may in turn be passed from gate driver row block 2 to subsequent gate driver row blocks. After the signal reaches the last gate driver row block in the active area of the display (gate driver row block N), the signal may be output to two different gate driver row blocks in parallel to reach both the first portion (i.e., 64-1) and second portion (i.e., 64-2) of the rows of dummy pixels. Gate driver row block N may pass a first signal to gate driver row block N+1 below the active area of the display. The signal may then propagate through gate driver row blocks N+2, N+3, and N+4. Gate driver row blocks

N+1, N+2, N+3, and N+4 may be positioned at the bottom of the display below the active area. Gate driver row block N may pass a second signal to gate driver row block Ν+ above the active area of the display. The signal may then propagate through gate driver row blocks

N+2', N+3' , and N+4'. Gate driver row blocks N+1 ', N+2', N+3' , and N+4' may be positioned at the top of the display above the active area.

[0066] In various embodiments, a display may have an active area and an inactive area. The display may include a plurality of display pixels in the active area and a plurality of dummy pixels in the inactive area. Each display pixel may include a light-emitting diode and a drive transistor, and the active area may have first and second opposing sides. At least one row of dummy pixels may have a first portion that is positioned on the first side of the active area and a second portion that is positioned on the second side of the active area.

[0067] The display may include gate driver circuitry with a gate driver row block coupled to each row in the active area. The plurality of display pixels in the active area may have a last row and a corresponding last gate driver row block and the last gate driver row block may be configured to output at least two control signals in parallel. The first portion of the at least one row of dummy pixels may be coupled to a first gate driver row block and the second portion of the at least one row of dummy pixels may be coupled to a second gate driver row block. The last gate driver row block may be configured to output a first of the at least two control signals to the first gate driver row block and a second of the at least two control signals to the second gate driver row block.

[0068] The active area may have a rectangular shape with rounded corners. The rounded corners may include an upper left rounded corner, an upper right rounded corner, a lower left rounded corner, and a lower right rounded corner. The first portion of the at least one row of dummy pixels may include dummy pixels positioned beneath the lower left rounded corner and the lower right rounded corner. The upper left rounded corner and the upper right rounded corner may be connected by a planar upper surface of the active area, and the second portion of the at least one row of dummy pixels includes dummy pixels positioned above the planar upper surface. The lower left rounded corner and the lower right rounded corner may be connected by a planar lower surface of the active area, and an electronic component may be positioned adjacent the planar lower surface of the active area. The first portion of the at least one row of dummy pixels may be positioned above the active area and the second portion of the at least one row of dummy pixels may be positioned below the active area.

[0069] In various embodiments, an organic light-emitting diode display may include an active area with an array of display pixels that are configured to emit light, a plurality of dummy pixels adjacent to the active area, data lines that supply data to the array of display pixels, gate lines that run perpendicular to the data lines and that supply control signals to the array of display pixels, and gate driver circuitry in the inactive area that includes a plurality of gate driver row blocks with register circuits that are coupled together to form a shift register. The array of display pixels may have a first row and a last row. Each gate driver row block may be coupled to a respective gate line, a first gate driver row block coupled to the first row may be configured to propagate a control signal to a second gate driver row block coupled to the last row, and the second gate driver row block may be configured to provide the control signal to a third gate driver row block that is associated with a first portion of the plurality of dummy pixels and a fourth gate driver row block that is associated with a second portion of the plurality of dummy pixels.

[0070] The first portion of the plurality of dummy pixels may be positioned above the active area and the second portion of the plurality of dummy pixels may be positioned below the active area. The active area may have first and second opposing sides, the first portion of the plurality of dummy pixels may be positioned on the first side of the active area, and the second portion of the plurality of dummy pixels may be positioned on the second side of the active area. The first portion of the plurality of dummy pixels may include portions of at least one row of dummy pixels and the second portion of the plurality of dummy pixels may include remaining portions of the at least one row of dummy pixels. The second gate driver row block may be configured to provide the control signal to the third gate driver row block and the fourth gate driver row block in parallel.

[0071] In various embodiments, a display may include an array of display pixels that form an active area of the display. The active area of the display may have an edge that has first and second rounded corners coupled by a planar upper surface and third and fourth rounded corners coupled by a planar lower surface, the array of pixels may include a first plurality of columns in between the first rounded corner and the third rounded corner, the array of pixels may include a second plurality of columns in between the second rounded corner and the fourth rounded corner, and the array of pixels may include a third plurality of columns in between the planar upper surface and the planar lower surface. The display may also include a first plurality of dummy pixels positioned below each column in the first plurality of columns, a second plurality of dummy pixels positioned below each column in the second plurality of columns, and a third plurality of dummy pixels positioned above each column in the third plurality of columns.

[0072] The first plurality of dummy pixels positioned below each column in the first plurality of columns may include four dummy pixels positioned below each column in the first plurality of columns. The third plurality of dummy pixels positioned above each column in the third plurality of columns may include four dummy pixels positioned above each column in the third plurality of columns. The second plurality of dummy pixels positioned below each column in the second plurality of columns may include four dummy pixels positioned below each column in the second plurality of columns. An electronic component may be interposed between the first plurality of dummy pixels and the second plurality of dummy pixels.

[0073] In accordance with an embodiment, a display with an active area and an inactive area is provided that includes a plurality of display pixels in the active area, each display pixel includes a light-emitting diode and a drive transistor and the active area has first and second opposing sides, and a plurality of dummy pixels in the inactive area, at least one row of dummy pixels has a first portion that is positioned on the first side of the active area and a second portion that is positioned on the second side of the active area.

[0074] In accordance with another embodiment, the display includes gate driver circuitry with a gate driver row block coupled to each row in the active area.

[0075] In accordance with another embodiment, the plurality of display pixels in the active area has a last row and a corresponding last gate driver row block and the last gate driver row block is configured to output at least two control signals in parallel.

[0076] In accordance with another embodiment, the first portion of the at least one row of dummy pixels is coupled to a first gate driver row block and the second portion of the at least one row of dummy pixels is coupled to a second gate driver row block.

[0077] In accordance with another embodiment, the last gate driver row block is configured to output a first of the at least two control signals to the first gate driver row block and a second of the at least two control signals to the second gate driver row block.

[0078] In accordance with another embodiment, the active area has a rectangular shape with rounded corners and the rounded corners include an upper left rounded corner, an upper right rounded corner, a lower left rounded corner, and a lower right rounded corner.

[0079] In accordance with another embodiment, the first portion of the at least one row of dummy pixels includes dummy pixels positioned beneath the lower left rounded corner and the lower right rounded corner.

[0080] In accordance with another embodiment, the upper left rounded corner and the upper right rounded corner are connected by a planar upper surface of the active area and the second portion of the at least one row of dummy pixels includes dummy pixels positioned above the planar upper surface.

[0081] In accordance with another embodiment, the lower left rounded corner and the lower right rounded corner are connected by a planar lower surface of the active area and an electronic component is positioned adjacent the planar lower surface of the active area.

[0082] In accordance with another embodiment, the first portion of the at least one row of dummy pixels is positioned above the active area and the second portion of the at least one row of dummy pixels is positioned below the active area.

[0083] In accordance with an embodiment, an organic light-emitting diode display is provided that includes an active area with an array of display pixels that are configured to emit light, the array of display pixels has a first row and a last row, a plurality of dummy pixels adjacent to the active area, data lines that supply data to the array of display pixels, gate lines that run perpendicular to the data lines and that supply control signals to the array of display pixels, and gate driver circuitry in the inactive area that includes a plurality of gate driver row blocks with register circuits that are coupled together to form a shift register, each gate driver row block is coupled to a respective gate line, a first gate driver row block coupled to the first row is configured to propagate a control signal to a second gate driver row block coupled to the last row, and the second gate driver row block is configured to provide the control signal to a third gate driver row block that is associated with a first portion of the plurality of dummy pixels and a fourth gate driver row block that is associated with a second portion of the plurality of dummy pixels.

[0084] In accordance with another embodiment, the first portion of the plurality of dummy pixels is positioned above the active area and the second portion of the plurality of dummy pixels is positioned below the active area.

[0085] In accordance with another embodiment, the active area has first and second opposing sides, the first portion of the plurality of dummy pixels is positioned on the first side of the active area, and the second portion of the plurality of dummy pixels is positioned on the second side of the active area.

[0086] In accordance with another embodiment, the first portion of the plurality of dummy pixels includes portions of at least one row of dummy pixels and the second portion of the plurality of dummy pixels includes remaining portions of the at least one row of dummy pixels.

[0087] In accordance with another embodiment, the second gate driver row block is configured to provide the control signal to the third gate driver row block and the fourth gate driver row block in parallel.

[0088] In accordance with an embodiment, a display is provided that includes an array of display pixels that form an active area of the display, the active area of the display has an edge that has first and second rounded corners coupled by a planar upper surface and third and fourth rounded corners coupled by a planar lower surface, the array of pixels includes a first plurality of columns in between the first rounded corner and the third rounded corner, the array of pixels includes a second plurality of columns in between the second rounded corner and the fourth rounded corner, and the array of pixels includes a third plurality of columns in between the planar upper surface and the planar lower surface, and a first plurality of dummy pixels positioned below each column in the first plurality of columns, a second plurality of dummy pixels positioned below each column in the second plurality of columns, and a third plurality of dummy pixels positioned above each column in the third plurality of columns.

[0089] In accordance with another embodiment, the first plurality of dummy pixels positioned below each column in the first plurality of columns includes four dummy pixels positioned below each column in the first plurality of columns.

[0090] In accordance with another embodiment, the third plurality of dummy pixels positioned above each column in the third plurality of columns includes four dummy pixels positioned above each column in the third plurality of columns.

[0091] In accordance with another embodiment, the second plurality of dummy pixels positioned below each column in the second plurality of columns includes four dummy pixels positioned below each column in the second plurality of columns.

[0092] In accordance with another embodiment, an electronic component is interposed between the first plurality of dummy pixels and the second plurality of dummy pixels.

[0093] The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination.

Claims

Claims What is Claimed is:

1. A display with first and second areas, the display comprising:

a plurality of display pixels that emit light in the first area, wherein each display pixel comprises a light-emitting diode and a drive transistor and wherein the first area has first and second opposing sides; and

a plurality of dummy pixels that do not emit light in the second area, wherein at least one row of dummy pixels has a first portion that is positioned on the first side of the first area and a second portion that is positioned on the second side of the first area.

2. The display defined in claim 1, wherein the first area is an active area and the second area is an inactive area.

3. The display defined in claim 1, wherein the first area covers a majority of the display and the second area surrounds at least portions of the first area.

4. The display defined in claim 1, wherein the display comprises gate driver circuitry with a gate driver row block coupled to each row in the first area.

5. The display defined in claim 4, wherein the plurality of display pixels in the first area has a last row and a corresponding last gate driver row block and wherein the last gate driver row block is configured to output at least two control signals in parallel.

6. The display defined in claim 5, wherein the first portion of the at least one row of dummy pixels is coupled to a first gate driver row block and wherein the second portion of the at least one row of dummy pixels is coupled to a second gate driver row block.

7. The display defined in claim 6, wherein the last gate driver row block is configured to output a first of the at least two control signals to the first gate driver row block and a second of the at least two control signals to the second gate driver row block.

8. The display defined in claim 1, wherein the first area has a rectangular shape with rounded comers and wherein the rounded comers include an upper left rounded corner, an upper right rounded comer, a lower left rounded corner, and a lower right rounded corner.

9. The display defined in claim 8, wherein the first portion of the at least one row of dummy pixels includes dummy pixels positioned beneath the lower left rounded corner and the lower right rounded corner.

10. The display defined in claim 9, wherein the upper left rounded corner and the upper right rounded corner are connected by a planar upper surface of the first area and wherein the second portion of the at least one row of dummy pixels includes dummy pixels positioned above the planar upper surface.

11. The display defined in claim 10, wherein the lower left rounded corner and the lower right rounded corner are connected by a planar lower surface of the first area and wherein an electronic component is positioned adjacent the planar lower surface of the first area.

12. The display defined in claim 1, wherein the first portion of the at least one row of dummy pixels is positioned above the first area and wherein the second portion of the at least one row of dummy pixels is positioned below the first area.

13. An organic light-emitting diode display, comprising:

an active area with an array of display pixels that are configured to emit light, wherein the array of display pixels has a first row and a last row;

a plurality of dummy pixels adjacent to the active area;

data lines that supply data to the array of display pixels;

gate lines that run perpendicular to the data lines and that supply control signals to the array of display pixels; and

gate driver circuitry in the inactive area that includes a plurality of gate driver row blocks with register circuits that are coupled together to form a shift register, wherein each gate driver row block is coupled to a respective gate line, wherein a first gate driver row block coupled to the first row is configured to propagate a control signal to a second gate driver row block coupled to the last row, and wherein the second gate driver row block is configured to provide the control signal to a third gate driver row block that is associated with a first portion of the plurality of dummy pixels and a fourth gate driver row block that is associated with a second portion of the plurality of dummy pixels.

14. The organic light-emitting diode display defined in claim 13, wherein the first portion of the plurality of dummy pixels is positioned above the active area and wherein the second portion of the plurality of dummy pixels is positioned below the active area.

15. The organic light-emitting diode display defined in claim 13, wherein the active area has first and second opposing sides, wherein the first portion of the plurality of dummy pixels is positioned on the first side of the active area, and wherein the second portion of the plurality of dummy pixels is positioned on the second side of the active area.

16. The organic light-emitting diode display defined in claim 15, wherein the first portion of the plurality of dummy pixels comprises portions of at least one row of dummy pixels and wherein the second portion of the plurality of dummy pixels comprises remaining portions of the at least one row of dummy pixels.

17. The organic light-emitting diode display defined in claim 13, wherein the second gate driver row block is configured to provide the control signal to the third gate driver row block and the fourth gate driver row block in parallel.

18. A display comprising:

an array of display pixels that form an active area of the display, wherein the active area of the display has an edge that has first and second rounded corners coupled by a planar upper surface and third and fourth rounded corners coupled by a planar lower surface, wherein the array of pixels includes a first plurality of columns in between the first rounded corner and the third rounded corner, wherein the array of pixels includes a second plurality of columns in between the second rounded corner and the fourth rounded corner, and wherein the array of pixels includes a third plurality of columns in between the planar upper surface and the planar lower surface; and

a first plurality of dummy pixels positioned below each column in the first plurality of columns;

a second plurality of dummy pixels positioned below each column in the second plurality of columns; and

a third plurality of dummy pixels positioned above each column in the third plurality of columns.

19. The display defined in claim 18, wherein the first plurality of dummy pixels positioned below each column in the first plurality of columns comprises four dummy pixels positioned below each column in the first plurality of columns.

20. The display defined in claim 19, wherein the third plurality of dummy pixels positioned above each column in the third plurality of columns comprises four dummy pixels positioned above each column in the third plurality of columns.

21. The display defined in claim 20, wherein the second plurality of dummy pixels positioned below each column in the second plurality of columns comprises four dummy pixels positioned below each column in the second plurality of columns.

22. The display defined in claim 21, wherein an electronic component is interposed between the first plurality of dummy pixels and the second plurality of dummy pixels.