WO2020253397A1 - Substrat de réseau, écran d'affichage et dispositif d'affichage - Google Patents

Substrat de réseau, écran d'affichage et dispositif d'affichage Download PDF

Info

Publication number
WO2020253397A1
WO2020253397A1 PCT/CN2020/087808 CN2020087808W WO2020253397A1 WO 2020253397 A1 WO2020253397 A1 WO 2020253397A1 CN 2020087808 W CN2020087808 W CN 2020087808W WO 2020253397 A1 WO2020253397 A1 WO 2020253397A1
Authority
WO
WIPO (PCT)
Prior art keywords
common electrode
thin film
film transistor
electrode
array substrate
Prior art date
Application number
PCT/CN2020/087808
Other languages
English (en)
Chinese (zh)
Inventor
程鸿飞
先建波
李会
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020253397A1 publication Critical patent/WO2020253397A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the embodiments of the present disclosure relate to an array substrate, a display panel, and a display device.
  • array substrates are widely used in display devices, and the performance of the array substrate has also received extensive attention.
  • the array substrate is easy to generate static electricity during the preparation process or the use process.
  • static discharge lines are usually arranged on the array substrate to release the static electricity generated on the array substrate and prevent static electricity from affecting the electronic components on the array substrate. Cause damage.
  • the embodiment of the present disclosure discloses an array substrate including a plurality of gate lines, a plurality of data lines, pixel electrodes, a common electrode, and a common electrode line formed on the substrate, the common electrode is connected to the common electrode line, and The array substrate further includes at least one first thin film transistor, the first electrode of the first thin film transistor is connected to the data line, the gate of the first thin film transistor is connected to the common electrode line, the first The second electrode of the thin film transistor is suspended, and the orthographic projection on the substrate and the orthographic projection of the common electrode on the substrate at least partially overlap; wherein, the array substrate includes a display area and a non-display area, so The first thin film transistor and the common electrode line are arranged in the non-display area.
  • the orthographic projection of the second electrode of the first thin film transistor on the substrate and the orthographic projection of the common electrode line on the substrate at least partially overlap.
  • the common electrode line is provided with an opening, and the orthographic projection of the second electrode of the first thin film transistor on the plane where the common electrode line is located is located in the opening.
  • the array substrate further includes an electrostatic discharge unit, and the electrostatic discharge unit is connected to the common electrode line.
  • the common electrode is connected to the common electrode line through a first via hole.
  • the gate line and the data line intersect to form a plurality of pixel units, the pixel unit includes a second crystal thin film tube, and the pixel electrode passes through a second via hole and is connected to the second crystal thin film tube. Two-pole connection.
  • the common electrode is disposed between the pixel electrode and the first thin film transistor, and an opening is disposed on the common electrode at a position corresponding to the second via hole.
  • the gate of the first thin film transistor and the common electrode line are arranged in the same layer; the first thin film transistor is arranged at the intersection of the data line and the common electrode line.
  • Another embodiment of the present disclosure also discloses a display screen, which includes the above-mentioned array substrate.
  • an embodiment of the present application also discloses a display device including the above-mentioned display panel.
  • a discharge capacitor may be formed between the second electrode and the common electrode to release the electrostatic charge on the data line connected to the first electrode to realize electrostatic protection of the array substrate.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by the present disclosure
  • FIG. 2 is a cross-sectional view of the cross section A-A' of the array substrate shown in FIG. 1;
  • FIG. 3 is a cross-sectional view of section B-B' in the array substrate shown in FIG. 1;
  • FIG. 4 is a schematic structural diagram of another array substrate provided by the present disclosure.
  • FIG. 5 is a cross-sectional view of section B-B' in the array substrate shown in FIG. 4;
  • FIG. 6 is a schematic structural diagram of still another array substrate provided by the present disclosure.
  • FIG. 7 is a schematic structural diagram of another array substrate provided by the present disclosure.
  • Fig. 8 is a cross-sectional view of the cross section A-A' of the array substrate shown in Fig. 7;
  • FIG. 9 is a cross-sectional view of section B-B' in the array substrate shown in FIG. 7;
  • FIG. 10 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the existing array substrate lacks an effective electrostatic protection solution.
  • the embodiments of the present disclosure provide an array substrate, a display panel, and a display device that overcome or at least partially solve the above problems.
  • An embodiment of the present disclosure provides an array substrate S1, which includes a plurality of gate lines 10, a plurality of data lines 11, a pixel electrode 12, a common electrode 13, and a common electrode line 14 formed on the substrate.
  • the common electrode 13 is connected to the common electrode line 14.
  • both the common electrode 13 and the common electrode line 14 are electrically connected to a reference voltage terminal so as to have a certain set reference voltage during operation.
  • the array substrate further includes at least one first thin film transistor 15.
  • the first electrode 151 of the first thin film transistor 15 is connected to the data line 11, and the gate 152 of the first thin film transistor 15 is connected to the common electrode line 14.
  • the second pole 153 of 15 is suspended (that is, the second pole 153 is suspended electrically and is not electrically connected to any other conductor), and the orthographic projection on the substrate and the common electrode 13 are on the substrate The orthographic projection of at least partially overlaps; wherein the array substrate S1 includes a display area R1 and a non-display area R2, and the first thin film transistor 15 and the common electrode line 14 are arranged in the non-display area R2.
  • the display area R1 is mainly composed of pixel units PX, and the pixel units PX can be used to emit light of a corresponding color, so that the user can see the displayed information in the array substrate S1.
  • the non-display area R2 is usually arranged in a peripheral area of the display area R1.
  • arranging the first thin film transistor 15 and the common electrode line 14 in the non-display area R2 can prevent the area occupied by the first thin film transistor 15 and the common electrode line 14 in the display area R1 from affecting the display.
  • the static charge when there is static charge on the array substrate, the static charge can be released to the common electrode line 14, for example, the voltage of the gate 152 of the first thin film transistor 15 connected to the common electrode line 14 is increased, and The first electrode 151 and the second electrode 153 of the first thin film transistor 15 are connected. Because the second electrode 153 is suspended, and the orthographic projection of the second electrode 153 on the substrate and the orthographic projection of the common electrode 13 on the substrate are at least Partially overlapped, a discharge capacitor may be formed between the second electrode 153 and the common electrode 13 to discharge the static charge on the data line 11 connected to the first electrode 151 to realize electrostatic protection of the array substrate.
  • the first electrode 151 and the second electrode 153 may be the source and drain of the first thin film transistor 15 respectively, or the first electrode 151 and the second electrode 153 may be the drain and the source of the first thin film transistor 15 respectively.
  • the embodiment of the present disclosure does not limit this.
  • the array substrate further includes an electrostatic discharge unit 18, and the electrostatic discharge unit 18 is electrically connected to the common electrode line 14.
  • the static electricity release unit can guide the common electrode line 14 to release the static electricity, so that the gate of the first thin film transistor 15 connected to the common electrode line 14
  • the voltage of 152 rises, the first pole 151 and the second pole 153 of the first thin film transistor 15 are turned on, and the static charge on the data line 11 connected to the first pole 151 is released to realize the electrostatic protection of the array substrate.
  • the electrostatic discharge unit 18 may include, but is not limited to, an electrostatic discharge line, an electrostatic discharge circuit, etc., which is not limited in the present disclosure.
  • the gate line 10 and the data line 11 intersect to form a plurality of pixel units.
  • the pixel unit includes a second crystal film tube 16.
  • the pixel electrode can pass through the second via hole B and the second crystal film tube 16 Two-pole connection.
  • FIG. 2 there is shown a cross-sectional view of the cross section A-A' of the array substrate shown in FIG.
  • the cross-sectional view of the cross section A-A' of the array substrate is a schematic diagram of the film state at the position of the second crystal thin film tube 16.
  • 20 is a substrate.
  • the gate 162, the gate insulating layer 21, and the first pole 161, the second pole 163, and the second pole of the second crystal thin film tube 16 are sequentially formed on the substrate 20.
  • a gate insulating layer 21 is provided between the source layer 164 and the data line 11, the gate 162 of the second transistor thin film tube 16 and the first electrode 161 and the second electrode 163.
  • a passivation layer 22, a pixel electrode 12, an insulating layer 23, and a common electrode 13 are sequentially formed on the gate insulating layer 21.
  • the first electrode 161 of the second thin film transistor 16 can be a part of the data line 11, that is, the data line 11 can serve as the first electrode 161, and the pixel electrode 12 passes through the second via hole B and the second electrode 163.
  • the gate insulating layer 21 may be made of silicon nitride or silicon oxide, and the gate insulating layer 21 may have a single-layer structure or a multi-layer structure, such as silicon oxide ⁇ silicon nitride, etc.
  • the passivation layer 22 can also be made of silicon nitride or silicon oxide.
  • the passivation layer 22 can be a single-layer structure or a multi-layer structure, such as silicon oxide ⁇ silicon nitride.
  • the insulating layer 23 can also be silicon nitride or silicon oxide; the insulating layer 23 can be a single-layer structure or a multilayer structure, such as silicon oxide ⁇ silicon nitride, etc.
  • FIG. 3 a cross-sectional view of the section B-B' in the array substrate shown in FIG. 1 is shown.
  • the cross-sectional view of the cross section B-B' of the array substrate is a schematic diagram of the film state at the position of the first crystal thin film tube 15.
  • the gate 152 of the first crystal film tube 15, the common electrode line 14, the second electrode 153 of the first crystal film tube 15, the first active layer 154 and the data line 11 are formed on the substrate 20. 151
  • the common electrode 13 is connected to the common electrode line 14 through the first via hole A.
  • the first via hole A sequentially passes through the insulating layer 23, the passivation layer 22, and the gate insulating layer 21, so that the common electrode line 14 Exposed.
  • the common electrode line 14 is connected to the gate 152, and a gate insulating layer 21 is provided between the gate 152 of the first transistor film tube 15 and the first electrode 151 and the second electrode 153.
  • the first electrode 151 of the first thin film transistor 15 may be a part of the data line 11, that is, the data line 11 may serve as the first electrode 151, or the data line 11 and the first electrode 151 may be independent of each other.
  • the conductive elements are not limited in the embodiment of the present disclosure.
  • the gate 152 of the first thin film transistor 15 may be a part of the common electrode line 14, that is, the common electrode line 14 may serve as the gate 152, or the common electrode line 14 and the gate 152 may be independent and conductive. Common components are not limited in the embodiments of the present disclosure.
  • the gate 152 of the first thin film transistor 15 and the common electrode line 14 are arranged in the same layer to facilitate the connection between the gate 152 and the common electrode line 14, and the first thin film transistor 15 is arranged on the data line 11 and At the intersection of the common electrode line 14, the first thin film transistor 15 can be conveniently formed on the substrate 20 and the processing convenience of the first thin film transistor 15 can be improved.
  • the common electrode line 14 is connected to the common electrode 13 through the first via A.
  • the static charge can be released to the common electrode line 14, so that the voltage of the gate 152 connected to the common electrode line 14 increases, and the first electrode 151 and the second electrode 153 are turned on.
  • the second pole 153 is suspended, and the orthographic projection of the second pole 153 on the substrate 20 and the orthographic projection of the common electrode 13 on the substrate at least partially overlap, and a discharge capacitor can be formed between the second pole 153 and the common electrode 13 to
  • the electrostatic charge on the data line 11 connected to the first pole 151 is released to realize electrostatic protection of the array substrate.
  • the orthographic projection of the second electrode 153 on the substrate 20 is completely within the orthographic projection of the common electrode 13 on the substrate.
  • the first electrode 151, the gate 152, and the second stage 153 of the first thin film transistor 15 and the first electrode 161, the gate 162 and the second electrode 163 of the second thin film transistor 16 can all be Cu, Al, Mo. , Ti, Cr, W and other metal materials, or alloys of these materials.
  • the first electrode 151, the gate 152, and the second electrode 153 of the first thin film transistor 15 and the first electrode 161, the gate 162, and the second electrode 163 of the second thin film transistor 16 may have a single-layer structure, or Multi-layer structure can be used, such as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, MoTi ⁇ Cu, etc.
  • FIG. 4 there is shown a schematic structural diagram of another array substrate provided by the present disclosure
  • FIG. 5 there is shown a cross-sectional view of section B-B' in the array substrate shown in FIG.
  • the orthographic projection of the second electrode 153 of the first thin film transistor 15 on the substrate 20 and the orthographic projection of the common electrode line 14 on the substrate 20 at least partially overlap.
  • the orthographic projection of the second electrode 153 of the first thin film transistor 15 on the substrate 20 is completely within the orthographic projection of the common electrode line 14 on the substrate 20.
  • the orthographic projection of the second electrode 153 of the first thin film transistor 15 on the substrate 20 and the orthographic projection of the common electrode 13 on the substrate 20 at least partially overlap, and the second electrode 153 and the common electrode 13 may be formed between Release capacitor C1.
  • the orthographic projection of the second electrode 153 of the first thin film transistor 15 on the substrate 20 and the orthographic projection of the common electrode line 14 on the substrate 20 at least partially overlap, a gap can be formed between the second electrode 153 and the common electrode line 14 Release capacitor C2.
  • the common electrode 13 is connected to the common electrode line 14 through the first via hole A, and the discharge capacitor C2 and the discharge capacitor C1 are connected in parallel, the ability to discharge electrostatic charges on the data line 11 can be increased, and the electrostatic protection of the array substrate is further improved. effect.
  • FIG. 6 there is shown a schematic structural diagram of still another array substrate provided by the present disclosure.
  • the common electrode line 14 is provided with an opening C, and the orthographic projection portion of the second electrode 153 of the first thin film transistor 15 on the plane where the common electrode line 14 is located is located in the opening C.
  • the common electrode line 14 can be used to form an electrostatic shield for the second electrode 153, to prevent the voltage on the second electrode 153 from being affected by electrostatic charges and causing fluctuations, and in turn, to avoid affecting the data line 11
  • the voltage which improves the accuracy of data transmission on the data line 11.
  • FIG. 7 there is shown a schematic structural diagram of yet another array substrate provided by the present disclosure.
  • FIG. 8 a cross-sectional view of the array substrate section AA′ shown in FIG. 7 is shown. 7 is a cross-sectional view of the cross-section BB' in the array substrate.
  • the common electrode 13 is arranged below the pixel electrode 12.
  • the common electrode 13 is provided with an opening D at a position corresponding to the second via hole B.
  • the second via hole B passes through the insulating layer 23 and the passivation layer in turn. 22, so that the second electrode 163 of the second thin film transistor 16 is exposed.
  • the second via hole B may pass through the opening D, and further, the pixel electrode 12 may be connected to the second electrode 163 of the second thin film transistor 16 through the second via hole B.
  • the common electrode 13 may be arranged between the pixel electrode 12 and the first thin film transistor 15 and the second thin film transistor 16.
  • the common electrode 13 and the second electrode 153 of the first thin film transistor 15 can be The distance between the common electrode 13 and the second electrode 153 is relatively short, so that a larger discharge capacitor can be formed between the common electrode 13 and the second electrode 153, which increases the discharge capacity of the discharge capacitor for the electrostatic charge on the data line 11, and further improves the The electrostatic protection effect of the array substrate.
  • the common electrode 13 may be connected to the common electrode line 14 through a first via hole A, and the first via hole A may sequentially pass through the passivation layer 22 and the gate insulating layer 21 to expose the common electrode line 14 .
  • a discharge capacitor may be formed between the second electrode and the common electrode to release the electrostatic charge on the data line connected to the first electrode to realize electrostatic protection of the array substrate.
  • another embodiment of the present disclosure also provides a display panel DP, which includes any of the above-mentioned array substrates S1.
  • the display panel further includes, for example, a counter substrate S2 opposite to the array substrate S1 and a liquid crystal layer LC located between the array substrate and the counter substrate.
  • the array substrate includes a plurality of gate lines, a plurality of data lines, pixel electrodes, a common electrode, and a common electrode line formed on a substrate.
  • the common electrode is connected to the common electrode line
  • the array substrate further includes at least A first thin film transistor, the first electrode of the first thin film transistor is connected to the data line, the gate of the first thin film transistor is connected to the common electrode line, and the second electrode of the first thin film transistor Suspended, and the orthographic projection on the substrate and the orthographic projection of the common electrode on the substrate at least partially overlap; wherein, the array substrate includes a display area and a non-display area, the first thin film transistor, The common electrode line is arranged in the non-display area.
  • first electrode and the second electrode of the first thin film transistor may be source and drain respectively, or the first electrode and the second electrode may be the drain and source of the first thin film transistor, respectively
  • the embodiment of the present disclosure does not limit this.
  • the array substrate further includes an electrostatic discharge unit 18 that is connected to the common electrode line 14.
  • the static electricity release unit can guide the static electricity to the common electrode line for release, so that the first thin film transistor connected to the common electrode line The gate voltage rises, the first pole and the second pole of the first thin film transistor are turned on, and the static charge on the data line connected with the first pole is released, so as to realize the electrostatic protection of the array substrate.
  • the electrostatic discharge unit 18 may include, but is not limited to, an electrostatic discharge line, an electrostatic discharge circuit, etc., which is not limited in the present disclosure.
  • the gate line and the data line intersect to form a plurality of pixel units
  • the pixel unit includes a second crystal thin film tube
  • the pixel electrode can communicate with the second crystal thin film tube through a second via hole.
  • the second pole is connected.
  • the gate electrode of the second crystal thin film tube, the gate insulating layer, and the first electrode, the first active layer, the second electrode and the data line of the second crystal thin film tube may be sequentially formed on the substrate.
  • a gate insulating layer is arranged between the gate of the second thin film transistor and the first electrode.
  • a passivation layer, a pixel electrode, an insulating layer, and a common electrode are sequentially formed on the gate insulating layer.
  • the gate electrode of the first crystal thin film tube, the common electrode line, the second electrode of the first crystal thin film tube, the second active layer and the data line may also be formed on the substrate, wherein the The common electrode line is connected to the gate of the first thin film transistor.
  • the display panel may include, but is not limited to, a TN (Twisted Nematic) panel, an IPS (In-Plane Switching) panel, a VA (Vertical Alignment, wide viewing angle) panel, and an OLED (Organic Light-Emitting Diode, Any one of organic light emitting diodes).
  • TN Transmission Nematic
  • IPS In-Plane Switching
  • VA Very Alignment, wide viewing angle
  • OLED Organic Light-Emitting Diode, Any one of organic light emitting diodes.
  • the display panel includes an array substrate.
  • the static charge can be released to the common electrode line, so that the gate voltage of the first thin film transistor connected to the common electrode line Rise to turn on the first pole and the second pole of the first thin film transistor, because the second pole is suspended, and the orthographic projection of the second pole on the substrate is in the same position as the common electrode.
  • the orthographic projections on the substrate at least partially overlap, and a discharge capacitor may be formed between the second electrode and the common electrode to release the electrostatic charge on the data line connected to the first electrode to achieve Electrostatic protection of the display panel.
  • yet another embodiment of the present disclosure further provides a display device including the above-mentioned display panel DP.
  • the display device also includes a controller CT configured to control the display device DP to display an image.
  • the display panel DP includes the aforementioned array substrate S1.
  • the array substrate includes a plurality of gate lines, a plurality of data lines, pixel electrodes, a common electrode, and a common electrode line formed on a substrate.
  • the common electrode is connected to the common electrode line
  • the array substrate further includes at least A first thin film transistor, the first electrode of the first thin film transistor is connected to the data line, the gate of the first thin film transistor is connected to the common electrode line, and the second electrode of the first thin film transistor Suspended, and the orthographic projection on the substrate and the orthographic projection of the common electrode on the substrate at least partially overlap; wherein, the array substrate includes a display area and a non-display area, the first thin film transistor, The common electrode line is arranged in the non-display area.
  • the display device may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • the display device includes a display panel, and the display panel includes an array substrate.
  • the electrostatic charge can be released to the common electrode line, so that the second electrode connected to the common electrode line
  • the gate voltage of a thin film transistor rises, turning on the first pole and the second pole of the first thin film transistor. Because the second pole is suspended, and the orthographic projection of the second pole on the substrate is The orthographic projection of the common electrode on the substrate at least partially overlaps, and a discharge capacitor may be formed between the second electrode and the common electrode to release the data line connected to the first electrode.
  • the electrostatic charge realizes the electrostatic protection of the display panel, and further, can realize the electrostatic protection of the display device.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un substrat de de réseau (S1), un écran d'affichage et un dispositif d'affichage. Le substrat de réseau (S1) comprend : un substrat (20), et une électrode commune (13), une ligne d'électrode commune (14) et au moins un premier transistor en couches minces (15) situé sur le substrat (20), l'électrode commune (13) étant électriquement connectée à la ligne d'électrode commune (14) ; une première électrode (151) dudit au moins un premier transistor en couches minces (15) est connectée électriquement à une ligne de données (11) ; une électrode de grille (152) dudit au moins un premier transistor en couches minces (15) est électriquement connectée à la ligne d'électrode commune (14), une seconde électrode (153) dudit au moins un premier transistor en couches minces (15) est suspendu électriquement, et la projection orthographique de la seconde électrode (153) sur le substrat (20) chevauche au moins partiellement la projection orthographique de l'électrode commune (13) sur le substrat (20). De cette manière, une protection électrostatique pour le substrat de réseau (S1) peut être obtenue.
PCT/CN2020/087808 2019-06-19 2020-04-29 Substrat de réseau, écran d'affichage et dispositif d'affichage WO2020253397A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201920931561.1U CN210199459U (zh) 2019-06-19 2019-06-19 一种阵列基板、显示面板以及显示装置
CN201920931561.1 2019-06-19

Publications (1)

Publication Number Publication Date
WO2020253397A1 true WO2020253397A1 (fr) 2020-12-24

Family

ID=69871254

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/087808 WO2020253397A1 (fr) 2019-06-19 2020-04-29 Substrat de réseau, écran d'affichage et dispositif d'affichage

Country Status (2)

Country Link
CN (1) CN210199459U (fr)
WO (1) WO2020253397A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN210199459U (zh) * 2019-06-19 2020-03-27 北京京东方技术开发有限公司 一种阵列基板、显示面板以及显示装置
CN111624823A (zh) * 2020-06-28 2020-09-04 京东方科技集团股份有限公司 用于tn型显示面板的像素结构、阵列衬底和tn型显示面板
CN113504682B (zh) * 2021-07-20 2023-11-14 南京京东方显示技术有限公司 一种显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080135846A1 (en) * 2006-12-12 2008-06-12 Kyoung-Ju Shin Thin film transistor substrate and method of manufacture
CN103928459A (zh) * 2014-03-10 2014-07-16 上海天马微电子有限公司 一种像素阵列基板以及包括其的平板传感器
CN204883133U (zh) * 2015-09-02 2015-12-16 京东方科技集团股份有限公司 一种阵列基板及显示器件
CN105446040A (zh) * 2016-01-05 2016-03-30 京东方科技集团股份有限公司 Esd防护单元、阵列基板、显示面板及显示装置
CN106024781A (zh) * 2016-07-22 2016-10-12 京东方科技集团股份有限公司 静电放电器件、其制造方法及阵列基板、显示面板和装置
CN210199459U (zh) * 2019-06-19 2020-03-27 北京京东方技术开发有限公司 一种阵列基板、显示面板以及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080135846A1 (en) * 2006-12-12 2008-06-12 Kyoung-Ju Shin Thin film transistor substrate and method of manufacture
CN103928459A (zh) * 2014-03-10 2014-07-16 上海天马微电子有限公司 一种像素阵列基板以及包括其的平板传感器
CN204883133U (zh) * 2015-09-02 2015-12-16 京东方科技集团股份有限公司 一种阵列基板及显示器件
CN105446040A (zh) * 2016-01-05 2016-03-30 京东方科技集团股份有限公司 Esd防护单元、阵列基板、显示面板及显示装置
CN106024781A (zh) * 2016-07-22 2016-10-12 京东方科技集团股份有限公司 静电放电器件、其制造方法及阵列基板、显示面板和装置
CN210199459U (zh) * 2019-06-19 2020-03-27 北京京东方技术开发有限公司 一种阵列基板、显示面板以及显示装置

Also Published As

Publication number Publication date
CN210199459U (zh) 2020-03-27

Similar Documents

Publication Publication Date Title
WO2020253397A1 (fr) Substrat de réseau, écran d'affichage et dispositif d'affichage
US20160019855A1 (en) Touch display device and driving method thereof
US10698552B2 (en) Touch substrate and touch display device
US20180341159A1 (en) Coa substrate and liquid crystal display panel
KR20160029487A (ko) 박막트랜지스터 기판 및 그 제조 방법
US9865621B2 (en) Display device
JP2019101095A (ja) 液晶パネル
JP6360718B2 (ja) 表示装置
WO2016188056A1 (fr) Substrat matriciel et dispositif d'affichage
TWI628498B (zh) 顯示裝置及其顯示面板
KR20200124352A (ko) 표시 장치
KR20200117101A (ko) 표시 장치
JP4293867B2 (ja) 画素の大型化に対応したｉｐｓ液晶ディスプレイ
US11493813B2 (en) Array substrate and display device
KR102102903B1 (ko) 박막 트랜지스터 어레이 기판 및 이의 제조 방법
WO2019051971A1 (fr) Substrat matriciel et écran d'affichage
KR102639294B1 (ko) 액정 표시 장치
JP2019159028A (ja) 表示装置
JP6665888B2 (ja) 電気光学装置および電子機器
JP2019101548A (ja) 液晶パネル
JP6813045B2 (ja) 電気光学装置および電子機器
JP5861740B2 (ja) 電気光学装置及び電子機器
WO2020012950A1 (fr) Dispositif d'affichage
JP2016114779A (ja) 液晶表示装置
JP7463872B2 (ja) 電気光学装置および電子機器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20825895

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20825895

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20825895

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 25/07/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20825895

Country of ref document: EP

Kind code of ref document: A1