WO2020252993A1 - 一种 tft 阵列基板、其制备方法及其显示面板 - Google Patents

一种 tft 阵列基板、其制备方法及其显示面板 Download PDF

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Publication number
WO2020252993A1
WO2020252993A1 PCT/CN2019/111212 CN2019111212W WO2020252993A1 WO 2020252993 A1 WO2020252993 A1 WO 2020252993A1 CN 2019111212 W CN2019111212 W CN 2019111212W WO 2020252993 A1 WO2020252993 A1 WO 2020252993A1
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Prior art keywords
layer
metal layer
metal
area
tft array
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French (fr)
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陈诚
杨薇薇
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/613,420 priority Critical patent/US11309339B2/en
Publication of WO2020252993A1 publication Critical patent/WO2020252993A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present invention relates to the field of flat display technology, in particular, a TFT array substrate, a preparation method thereof, and a display panel thereof.
  • LCD liquid crystal flat display devices
  • liquid crystal flat panel display device not only has the advantages of small size and light weight, but also has the advantages of power saving, low radiation, and soft display without hurting eyes.
  • the industry is not satisfied with this, and continues to research and develop, in order to obtain the same light and thin display panel but with better display effect.
  • OLED Organic Light-Emitting Diode
  • the OLED display device also has a particularly important characteristic, namely, bendability.
  • This bendable feature makes it an absolute advantage in portability, so it has become the focus of research and development in the industry.
  • the conductive metal layer provided on the TFT array substrate generally includes a first metal layer (gate layer GE1) and a second metal layer.
  • Layer (GE2) the material used for these two metal layers is mainly metal Mo, but according to subsequent performance tests, it is found that the electrical conductivity of the metal Mo material is relatively low and the bending resistance is poor.
  • One aspect of the present invention is to provide a TFT array substrate.
  • the metal layer provided on the TFT array substrate is made of a material with low resistance so as to improve its electrical conductivity, and the metal constituent material is also good in bending resistance.
  • a TFT array substrate is defined with a display area, a line change area and a bending area, wherein the line change area connects the display area and the bending area. It includes a substrate functional layer and a metal layer arranged on it.
  • the substrate functional layer includes a substrate layer, a buffer layer, an active layer, and a first insulating layer disposed on the substrate layer, wherein the metal layer includes a first metal layer and a first insulating layer arranged at intervals in the display area.
  • the second metal layer and the third metal layer wherein the first metal layer is provided on the first insulating layer, a second insulating layer is provided between the second metal layer and the first metal layer, and the third metal layer is connected to the second metal layer.
  • An interlayer insulating layer is provided between the layers.
  • the first metal layer, the second metal layer and the third metal layer are all made of the same metal material, and the metal material includes metal aluminum material or aluminum alloy material.
  • an organic filling layer is provided on the substrate layer of the bending area, and a third metal layer of the bending area is arranged at intervals on the organic filling layer.
  • a barrier layer is further provided between the organic filling layer and the substrate layer.
  • the thickness of the barrier layer between the two can be 100-6000 angstroms, but is not limited.
  • the first metal layer of the bending area is provided in the organic filling layer of the bending area.
  • the first metal layer in the bending area is preferably arranged at the bottom of the organic filling layer, and its bottom surface is directly connected to the substrate layer or the barrier layer.
  • a first metal layer of the wire change area is provided on the first insulating layer of the wire change area, and one side end of the first metal layer of the wire change area extends into the curve.
  • the organic filling layer of the folded area may extend downward to the bottom position of the organic filling layer, but it is not limited.
  • the first metal layer of the bending area is provided in the organic filling layer of the bending area, and the first metal layer of the bending area extends to the end of the bending area.
  • the parts are spaced apart.
  • a second metal layer of the wire change region is further provided on the second insulating layer of the wire change region, which is connected to the second metal layer of the bending region through the via hole.
  • a metal layer is electrically connected.
  • a third metal layer of the wire change area is further provided on the interlayer insulating layer of the wire change area, wherein the third metal layer of the wire change area includes two, and the two are respectively It is electrically connected to the first metal layer of the wire change area and the second metal layer of the wire change area through a via hole.
  • the third metal layer is further provided with a planarization layer (PLN), an anode layer (ANO), a pixel definition layer (PDL) and a support pillar (PS), wherein the anode The layer is electrically connected to the third metal layer in the display area through the via hole.
  • PPN planarization layer
  • ANO anode layer
  • PDL pixel definition layer
  • PS support pillar
  • Another aspect of the present invention is to provide a method for preparing the TFT array substrate of the present invention, which includes the following steps.
  • Step S1 Fabrication of a substrate functional layer; it is to provide a substrate layer, wherein the substrate layer defines a display area, a line change area and a bending area; a buffer layer, an active layer and a second layer are sequentially deposited on the substrate layer An insulating layer;
  • Step S2 fabricating a first metal layer; which is to deposit a first metal layer on the first insulating layer, and pattern the first metal layer to form a first gate metal layer in the display area ⁇ first metal layer pattern;
  • Step S3 fabricate a second insulating layer and a second metal layer; this is to deposit a second insulating layer on the first metal layer, fabricate a second metal layer on the second insulating layer, Patterning the layer to form a second metal layer pattern as a second gate metal layer in the display area;
  • Step S4 fabricating an interlayer insulating layer; which is depositing an interlayer insulating layer on the second metal layer;
  • Step S5 fabricate a third metal layer; which is to deposit a third metal layer on the inter-insulating layer, and pattern the third metal layer to form a second metal layer as a source and drain in the display area Three metal layer patterns.
  • step S1 it further includes the step of forming a first deep hole downward on the surface of the first insulating layer in the bending area
  • step S4 it further includes The step of forming a second deep hole downward in the interlayer insulating layer of the bending zone, wherein the second deep hole communicates with the first deep hole, and the first deep hole and the second deep hole are still The organic photoresist material is filled to form an organic filling layer.
  • patterning the first metal layer further includes forming a first metal layer in the wire exchange area and the first insulating layer in the wire exchange area.
  • step S3 patterning the second metal layer further includes forming a second metal layer in the wire change area on the second insulating layer of the wire change area, and The second metal layer of the wire changing area is electrically connected to the first metal layer of the bending area through a via hole.
  • the patterning of the third metal layer further includes forming two spaced third wire exchange areas on the interlayer insulating layer of the wire exchange area.
  • the two metal layers are respectively electrically connected to the first metal layer in the wire exchange area and the second metal layer in the wire exchange area through via holes.
  • the patterning of the third metal layer includes forming a third metal layer in the bending area at intervals on the organic filling layer of the bending area.
  • another aspect of the present invention provides a display panel including the TFT array substrate related to the present invention.
  • the display panel is a flexible OLED display panel.
  • the present invention relates to a TFT array substrate, which selects a new type of metal material aluminum or aluminum alloy material to make its first metal layer (gate layer GE1), second metal layer (GE2) and third metal layer (SD),
  • first metal layer gate layer GE1
  • second metal layer GE2
  • third metal layer SD
  • the involved preparation method of the TFT array substrate adopts a new type of metal material combined with a lower edge (border) line change design, and realizes a double-layered operation in the bending (Pad) area with a small number of mask bending. Line design to improve IR Drop.
  • the first metal layer (gate layer GE1) provided in the pad bending area is a metal layer that can be used for data line wiring, so that the data line wiring can be laid down as a whole Therefore, it is closer to the neutral plane (that is, the PI layer), that is, the distance between the data line trace and the neutral plane is reduced, thereby helping to improve the bending trust of the bending zone Performance, thereby reducing the risk of disconnection.
  • the neutral plane that is, the PI layer
  • FIG. 1 is a schematic diagram of a TFT array substrate manufacturing method provided in an embodiment of the present invention, after step S1 is completed;
  • step S2 is completed;
  • step S3 is a schematic diagram of the structure of the TFT array substrate manufacturing method described in FIG. 1 after step S3 is completed;
  • step S4 is completed;
  • step S5 is a schematic diagram of the structure of the TFT array substrate manufacturing method described in FIG. 1 after step S5 is completed.
  • FIG. 6 is a schematic diagram of the structure of the TFT array substrate manufacturing method described in FIG. 1 after all steps are completed.
  • the present invention relates to a TFT array substrate and a preparation method thereof, in order to avoid unnecessary repetition, the TFT array substrate involved in the present invention will be described in detail below in conjunction with the preparation method of the TFT array substrate involved in the present invention.
  • An embodiment of the present invention provides a method for preparing a TFT array substrate, which includes the following steps.
  • Step S1 Fabrication of a substrate functional layer; this is to provide a substrate layer 100, wherein the substrate layer 100 defines a display area 10, a line change area 20 and a bending area 30.
  • a barrier layer (M/B layer) 102, a buffer layer 110, an active layer 120, and a first insulating layer (GI1) 130 are sequentially deposited on the substrate layer 100; wherein the substrate layer 100 may be a double-layer PI layer
  • the structure of, but not limited to; the barrier layer (M/B) layer 102 may be an inorganic layer made of inorganic materials, but is not limited to.
  • a first deep hole (DH) 122 is formed on the surface of the first insulating layer 130 in the bending area, wherein the first deep hole 122 can extend to the surface of the substrate layer 100 or deep into the
  • the barrier layer 102 does not penetrate inside, so that there is a thin barrier layer 102 between it and the substrate layer 100, the thickness of which can be 100-6000 angstroms.
  • FIG. 1 for the completed diagram. As shown in the figure, the first deep hole 122 does not penetrate the barrier layer 102.
  • Step S2 fabricating a first metal layer; which is to form a first metal layer on the bottom surface of the first insulating layer 130 and the first deep hole 122 of the bending area and perform patterning treatment on the first metal layer ,
  • the structure diagram after completion please refer to Figure 2.
  • a first metal layer 140 in addition to forming a first metal layer 140 as a first gate metal layer on the first insulating layer 130 in the display area, it is also on the first insulating layer 130 in the switching area.
  • a first metal layer 142 is provided, and it extends downward to the bottom surface of the first deep hole 122 in the bending area, and the first metal layer extending from the wire change area to the bending area is defined as the change
  • the first metal layer 142 in the line area; and the bottom surface of the first deep hole 122 in the bending area is also provided with a first metal layer 144 in the bending area, which extends with the first metal layer 142 in the switching area
  • the parts to the bending zone are arranged at intervals.
  • the first metal layer involved in the present invention it uses a metal Mo material different from that in the prior art, but uses a metal aluminum material or an aluminum alloy material.
  • Step S3 fabricate a second insulating layer and a second metal layer; this is to deposit a second insulating layer (GI2) 150 on the first metal layer 140, and fabricate a second metal layer 160 on the second insulating layer 150 And carry on the patterning treatment to it, the structure figure after finishing please refer to Fig. 3.
  • GI2 second insulating layer
  • the second metal layer 160 in addition to forming the second metal layer 160 as the second gate metal layer (GE2) on the second insulating layer 150 in the display area, the second insulating layer in the switching area 20 There is also a second metal layer 162 of the wire change area on the layer.
  • the second metal layer 160 is also preferably a metal aluminum material or an aluminum alloy material.
  • the second metal layer 162 of the wire-changing area and the first metal layer 144 of the bending area are electrically connected through via holes, which cannot be shown due to the angle of the illustration.
  • Step S4 fabricating an interlayer insulating layer and an organic filling layer; which is to deposit an interlayer insulating layer (ILD) 170 on the second metal layer 160, and the interlayer insulating layer 170 at the position of the wire change area
  • ILD interlayer insulating layer
  • a first via 22 and a second via 24 are formed in the center, and a second deep hole 124 is formed at the position of the bending area.
  • the second deep hole 124 penetrates the interlayer insulating layer 170 downward and communicates with the first deep hole 122.
  • the first deep hole 122 and the second deep hole 124 are filled with an organic photoresist material (ODH) to form an organic filling layer 126.
  • ODH organic photoresist material
  • Step S5. Fabrication of a third metal layer; which is to deposit a third metal layer 180 on the inter-insulating layer 170, that is, the deposition of a source and drain (SD) metal layer and patterning it.
  • the completed structure please Refer to Figure 5.
  • the third metal layer is provided in the display area, the line change area and the bending area.
  • the third metal layers 181 and 182 in the display area are used as source and drain metal layers to overlap the active layer 120, and in other embodiments, it may also be to overlap the gate metal.
  • Layer (GE1) 140 which can be specifically determined as needed, and is not limited.
  • the third metal layer in the wire change area specifically includes two, which are defined as the "first" wire change area, the third metal layer 183, and the "second" wire change area, to facilitate the distinction.
  • Three metal layers 184 which respectively pass downward through the first via 22 and the second via 24 and the first metal layer 142 in the wire exchange area and the second metal layer in the wire exchange area 162 connections.
  • the bending area there are two spaced third metal layers formed on the organic filling layer (ODH) 126. In order to distinguish between them, they are defined as the "first" bending area and the third metal layer. Three metal layers 185 and a third metal layer 186 in the "second" bending zone.
  • ODH organic filling layer
  • planarization layer (PLN) 190 an anode layer (ANO) 192, a pixel definition layer (PDL) 194, and a support pillar (PS) 196 will continue to be provided on the third metal layer.
  • PPN planarization layer
  • ANO anode layer
  • PDL pixel definition layer
  • PS support pillar
  • the present invention relates to a TFT array substrate, which selects a new type of metal material aluminum or aluminum alloy to make its first metal layer (gate layer GE1), second metal layer (GE2), and third metal layer (SD). Utilizing the low resistance characteristics of the metal aluminum or aluminum alloy material, the conductivity of each metal layer is effectively improved, and the bending resistance of the metal aluminum or aluminum alloy material is relatively good.
  • first, second, and third metal layers are all made of the same metal material, this also makes different metal layers made of the same metal material increase the possibility of changing the wire design, which in turn makes the cost
  • the method for preparing the TFT array substrate involved in the present invention adopts a new type of metal material combined with a lower edge (border) line change design, and realizes that the double layer of the bending (Pad) area can be achieved by a small number of mask bending.
  • the design of the trace to improve the IR Drop.
  • the data line in an embodiment where the data line is switched to the wiring, it can be the adjacent Data signal line in the source and drain layer (that is, the third metal layer 181, 182) of the display area, which extends to When the wire change area is the third metal layer 183 in the "first" wire change area, and the third metal layer 184 in the "second" wire change area, the two pass through the first via 22 and the second via respectively.
  • the hole 24 is swapped to the first metal layer 142 of the swapping area and the second metal layer 162 of the swapping area.
  • the first metal layer 142 of the wire change area directly extends to the bending area
  • the second metal layer 162 of the wire change area extends to the bending area by changing wires to the place where In the bending area, the first metal layer 144 is formed in the bending area.
  • the Data signal traces formed in the bending area are designed under the organic filling layer (ODH) 126.
  • the first metal layer 144 in the bending area provided in the bending area is used for data wiring (data line) metal layer, so that the data trace moves downward as a whole, so it is closer to the neutral plane, that is, the distance between the data trace and the neutral plane is reduced, thereby helping to improve
  • the bending reliability of the bending zone further reduces the risk of wire breakage.
  • ELVDD signal line switching routing implementation it may be that the adjacent ELVDD signal lines of the source and drain layers (ie the third metal layers 181, 182) in the display area pass through the switching line In the zone, a multi-segment structure can be adopted, that is, the third metal layer 183 of the "first" line exchange zone and the third metal layer 184 of the "second" line exchange zone are switched.
  • the adjacent ELVDD signal lines of the source and drain layers in the display area may adopt a multi-segment structure when passing through the switching area, that is, switching to The third metal layer 183 of the "first" wire change area and the third metal layer 184 of the "second" wire change area of the wire change area.
  • the multi-segment ELVDD signal line of the third metal layer 183, 184 of the wire change area can directly pass through the third metal layer 185, 186 of the bending area provided in the bending area and extend through the bending area. Fold area.
  • another embodiment of the present invention provides a display panel, which includes the TFT array substrate related to the present invention, wherein the display panel is preferably a flexible OLED display panel, but is not limited to.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

本发明提供了一种TFT阵列基板，其定义有显示区、换线区和弯折区，其中所述换线区连接所述显示区和弯折区。其包括衬底功能层和设置于其上的金属层。所述衬底功能层包括衬底层和设置于所述衬底层上的缓冲层、有源层和第一绝缘层，其中所述金属层在所述显示区包括间隔设置的第一金属层、第二金属层和第三金属层。其中所述第一金属层、第二金属层和第三金属层均采用同样的金属材料构成，其中所述金属材料包括金属铝材料或是铝合金材料。本发明的一个方面是提供一种TFT阵列基板，其上设置的金属层采用电阻低的材料构成从而提升了其电导率，且采用的金属构成材料的耐弯折性能同样良好。

Description

 一种TFT阵列基板、其制备方法及其显示面板 技术领域
本发明涉及平面显示技术领域，尤其是，其中的一种TFT阵列基板、其制备方法及其显示面板。
 背景技术
已知，随着显示技术的不断发展，平面显示装置已逐渐成为市场上的主流显示装置。这其中，主要是液晶平面显示装置（LCD）占据了市场上的大部分份额。
虽然液晶平面显示装置除了具有体积小、重量轻等轻薄的优点外，还具有省电、辐射低，显示柔和不伤眼等等优点。但是，业界并不满足于此，还在不断的研发，以期获得同样轻薄但显示效果却更好的显示面板。
这其中，业界开发出了OLED（Organic Light-Emitting Diode）显示面板，由于其重量轻、自发光、广视角、驱动电压低、发光效率高功耗低、响应速度快等优点，应用范围越来越广泛，逐渐被业界认为是代替液晶显示面板的下一代主流显示面板。
进一步的，OLED显示装置除了上述优点外，还具有一项尤为重要的特性，即可弯折性。这一可弯折特性使得其在便携性上获得了绝对的优势，因此，也就成为业界研究和开发的重点。
就目前而言，业界常见的柔性OLED显示面板的驱动是通过其TFT阵列基板来实现的，而TFT阵列基板上设置的导电金属层一般包括第一金属层(栅极层GE1)、第二金属层(GE2)，这两个金属层采用的材料主要是金属Mo，但根据后续的性能测试，发现该金属Mo材料的电导率相对较低，且耐弯折性能差。
因此，确有必要来开发一种新型的TFT阵列基板，来克服现有技术中的缺陷。
 技术问题
本发明的一个方面是提供一种TFT阵列基板，其上设置的金属层采用电阻低的材料构成从而提升了其电导率，且采用的金属构成材料的耐弯折性能同样良好。
 技术解决方案
本发明采用的技术方案如下：
一种TFT阵列基板，其定义有显示区、换线区和弯折区，其中所述换线区连接所述显示区和弯折区。其包括衬底功能层和设置于其上的金属层。所述衬底功能层包括衬底层和设置于所述衬底层上的缓冲层、有源层和第一绝缘层，其中所述金属层在所述显示区包括间隔设置的第一金属层、第二金属层和第三金属层。其中所述第一金属层设置在所述第一绝缘层上，所述第二金属层和第一金属层之间设置有第二绝缘层，而所述第三金属层与所述第二金属层之间设置有层间绝缘层。其中所述第一金属层、第二金属层和第三金属层均采用同样的金属材料构成，其中所述金属材料包括金属铝材料或铝合金材料。
进一步的，在不同实施方式中，其中在所述弯折区的所述衬底层上设置有一有机填充层，所述有机填充层上设置有间隔设置的弯折区第三金属层。
进一步的，在不同实施方式中，其中所述有机填充层和所述衬底层之间还设置有阻隔层。具体的，两者之间的所述阻隔层的厚度可以在100-6000埃，但不限于。
进一步的，在不同实施方式中，其中在所述弯折区的有机填充层内设置有弯折区第一金属层。其中所述弯折区第一金属层优选设置在所述有机填充层的底部，其底表面直接与所述衬底层或是所述阻隔层相接。
进一步的，在不同实施方式中，其中在所述换线区的第一绝缘层上设置有换线区第一金属层，所述换线区第一金属层的一侧端延伸进入所述弯折区的所述有机填充层内。具体的，其可以是向下延伸到所述有机填充层的底部位置处，但不限于。
进一步的，在不同实施方式中，其中在所述弯折区的有机填充层内设置有弯折区第一金属层，其与所述换线区第一金属层延伸到所述弯折区的部分相互间隔设置。
进一步的，在不同实施方式中，其中在所述换线区的第二绝缘层上还设置有换线区第二金属层，其通过过孔与所述弯折区的所述弯折区第一金属层电性连接。
进一步的，在不同实施方式中，其中在所述换线区的层间绝缘层上还设置有换线区第三金属层，其中所述换线区第三金属层包括2个，两者分别通过过孔与所述换线区第一金属层和所述换线区第二金属层电性连接。
进一步的，在不同实施方式中，其中所述第三金属层上还设置有平坦化层（PLN）、阳极层（ANO）、像素定义层（PDL）和支撑柱（PS），其中所述阳极层通过过孔与显示区的第三金属层电性连接。
进一步的，本发明的又一方面是提供一种本发明涉及的所述TFT阵列基板的制备方法，其包括以下步骤。
步骤S1、制作衬底功能层；其为提供一衬底层，其中所述衬底层定义有显示区、换线区和弯折区；在所述衬底层上依次沉积缓冲层、有源层以及第一绝缘层；
步骤S2、制作第一金属层；其为在所述第一绝缘层上沉积第一金属层，对所述第一金属层进行图案化处理以在所述显示区形成作为第一栅极金属层的第一金属层图案；
步骤S3、制作第二绝缘层和第二金属层；其为在所述第一金属层上沉积第二绝缘层，在所述第二绝缘层上制作第二金属层，对所述第二金属层进行图案化处理以在所述显示区形成作为第二栅极金属层的第二金属层图案；
步骤S4、制作层间绝缘层；其为在所述第二金属层上沉积层间绝缘层；
步骤S5、制作第三金属层；其为在所述间绝缘层上沉积第三金属层，对所述第三金属层进行图案化处理以在所述显示区形成作为源漏极金属层的第三金属层图案。
进一步的，在不同实施方式中，其中在步骤S1中，还包括在所述弯折区的所述第一绝缘层的表面向下形成第一深孔的步骤，以及在步骤S4中，还包括在所述弯折区的层间绝缘层向下形成第二深孔的步骤，其中所述第二深孔连通所述第一深孔，所述第一深孔和第二深孔内还会填充有机光阻材料形成一有机填充层。
进一步的，在不同实施方式中，其中在步骤S2中，对所述第一金属层的图案化还包括在所述换线区的第一绝缘层上形成换线区第一金属层和所述弯折区内的弯折区第一金属层，其中所述换线区第一金属层延伸进入所述弯折区的有机填充层中；所述弯折区第一金属层位于所述有机填充层内，并与所述换线区第一金属层延伸入所述有机填充层的部分相互间隔设置。
进一步的，在不同实施方式中，其中在步骤S3中，对所述第二金属层的图案化还包括在所述换线区的第二绝缘层上形成换线区第二金属层，所述换线区第二金属层通过过孔与所述弯折区第一金属层电性连接。
进一步的，在不同实施方式中，其中在步骤S4中，对所述第三金属层的图案化还包括在所述换线区的层间绝缘层上形成间隔设置的两个换线区第三金属层，两者分别通过过孔与所述换线区第一金属层和换线区第二金属层电性连接。
进一步的，在不同实施方式中，其中在步骤S4中，对所述第三金属层的图案化包括在所述弯折区的有机填充层上形成间隔设置的弯折区第三金属层。
进一步的，本发明的又一方面提供了一种显示面板，其包括本发明涉及的所述TFT阵列基板。
进一步的，在不同实施方式中，其中所述显示面板为柔性OLED显示面板。
 有益效果
本发明涉及的一种TFT阵列基板，其选择新型金属材料铝或铝合金材料来制作其第一金属层(栅极层GE1)、第二金属层(GE2)以及第三金属层(SD)，通过利用所述金属铝或铝合金材料电阻低的特性，有效提升了各金属层的导电率，且金属铝材料或铝合金材料的耐弯折性能也是相对良好。
进一步的，由于所述阵列基板上的各金属层均是采用相同的金属材料构成，这也使得由相同的金属材料构成的不同金属层之间增加了换线设计的可能，这也使得本发明涉及的所述TFT阵列基板的制备方法通过采用新型金属材料结合下边缘（border）换线设计，实现了通过较少数量的光罩（Mask）即可达到弯折（Pad bending）区双层走线的设计，从而改善IR Drop。
且，由于所述弯折（Pad bending）区设置的第一金属层(栅极层GE1)是可用于数据线（data line）走线的金属层，如此使得所述数据线走线能够整体下移，因此离中性面（即PI层）更近，也就是减小了所述数据线走线与所述中性面间的距离，从而有助于提升所述弯折区的弯折信赖性，进而降低断线风险。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明的一个实施方式中提供的一种TFT阵列基板制备方法，其步骤S1完成后的结构示意图；
图2为图1所述的TFT阵列基板制备方法，其步骤S2完成后的结构示意图；
图3为图1所述的TFT阵列基板制备方法，其步骤S3完成后的结构示意图；
图4为图1所述的TFT阵列基板制备方法，其步骤S4完成后的结构示意图；
图5为图1所述的TFT阵列基板制备方法，其步骤S5完成后的结构示意图；以及
图6为图1所述的TFT阵列基板制备方法，其全部步骤完成后的结构示意图。
 本发明的实施方式
以下将结合附图和实施例，对本发明涉及的一种TFT阵列基板、其制备方法及其显示面板的技术方案作进一步的详细描述。
由于本发明涉及一种TFT阵列基板及其制备方法，为避免不必要的重复，以下将结合本发明涉及的所述TFT阵列基板的制备方法对本发明涉及的所述TFT阵列基板进行细节描述说明。
本发明的一个实施方式提供了一种TFT阵列基板的制备方法，其包括以下步骤。
步骤S1、制作衬底功能层；其为提供一衬底层100，其中所述衬底层100定义有显示区10、换线区20和弯折区30。
在所述衬底层100上依次沉积阻隔层（M/B层）102、缓冲层110、有源层120、第一绝缘层(GI1)130；其中所述衬底层100可以是采用双层PI层的结构，但不限于；所述阻隔层（M/B）层102可以是采用无机材料构成的无机层，但不限于。
然后在所述弯折区的所述第一绝缘层130的表面形成第一深孔（DH）122，其中所述第一深孔122可延伸至所述衬底层100表面，或是深入所述阻隔层102内但不贯穿，使得其与所述衬底层100之间还存有一层较薄的阻隔层102，其厚度可以在100-6000埃，完成后的图示请参阅图1所示。其中如图中所示，所述第一深孔122并未贯穿所述阻隔层102。
步骤S2、制作第一金属层；其为在所述第一绝缘层130以及所述弯折区的第一深孔122底表面形成第一金属层并对所述第一金属层进行图案化处理，其中完成后的结构图示，请参阅图2所示。
其中如图中所示，除了在所述显示区的第一绝缘层130上形成作为第一栅极金属层的第一金属层140外，在所述换线区的第一绝缘层130上也设置有一第一金属层142，且其向下延伸至所述弯折区所述第一深孔122的底表面上，将该从换线区延伸至弯折区的第一金属层定义为换线区第一金属层142；而所述弯折区所述第一深孔122的底表面上还设置有一弯折区第一金属层144，其与所述换线区第一金属层142延伸到所述弯折区的部分相互间隔设置。其中在本发明涉及的所述第一金属层中，其采用不同于现有技术中的金属Mo材料，而是选用金属铝材料或是铝合金材料。
步骤S3、制作第二绝缘层和第二金属层；其为在所述第一金属层140上沉积第二绝缘层（GI2）150，在所述第二绝缘层150上制作第二金属层160并对其进行图案化处理，完成后的结构图示请参阅图3所示。
其中如图中所示，除了在所述显示区的第二绝缘层150上形成作为第二栅极金属层（GE2）的第二金属层160外，在所述换线区20的第二绝缘层上也设置有一换线区第二金属层162。其中所述第二金属层160也是优选金属铝材料或是铝合金材料。且所述换线区第二金属层162与所述弯折区第一金属层144通过过孔电性连接，因图示角度问题，未能显示。
步骤S4、制作层间绝缘层和有机填充层；其为在所述第二金属层160上沉积层间绝缘层（ILD）170，并在所述换线区位置的所述层间绝缘层170中形成第一过孔22和第二过孔24，以及在所述弯折区位置形成一第二深孔124。其中所述第二深孔124向下贯穿所述层间绝缘层170并连通所述第一深孔122。向所述第一深孔122和第二深孔124内填充有机光阻材料（ODH）形成有机填充层126，其中完成后的图示，请参阅图4所示。
步骤S5、制作第三金属层；其为在所述间绝缘层170上沉积第三金属层180即源漏极（SD）金属层的沉积以及对其进行图案化处理，完成后的结构，请参阅图5所示。其中如图中所示，所述第三金属层在所述显示区、换线区和弯折区均有设置。
具体来讲，其中在显示区的所述第三金属层181、182作为源漏极金属层是搭接有源层120，而在其他实施方式中，其也可以是搭接所述栅极金属层（GE1）140，具体可随需要而定，并无限定。
在所述换线区的所述第三金属层，其具体包括两个，为便于区别将两者分别定义为“第一”换线区第三金属层183和“第二”换线区第三金属层184，两者向下分别通过所述第一过孔22和第二过孔24与位于换线区的所述换线区第一金属层142和所述换线区第二金属层162连接。
而在所述弯折区，则是在所述有机填充层（ODH）126上形成的两个间隔设置的第三金属层，为便于区别将两者分别定义为“第一”弯折区第三金属层185和“第二”弯折区第三金属层186。
进一步的，所述第三金属层上还会继续设置平坦化层（PLN）190、阳极层（ANO）192、像素定义层（PDL）194和支撑柱（PS）196，完成后的结构图示，请参阅图6所示，至此，也是完成了本发明涉及的所述TFT阵列基板。
本发明涉及的一种TFT阵列基板，其选择新型金属材料铝或铝合金来制作其第一金属层(栅极层GE1)、第二金属层(GE2)、第三金属层(SD)，通过利用所述金属铝或铝合金材料的电阻低特性，有效提升了各金属层的导电率，且金属铝材料或铝合金材料的耐弯折性能也是相对良好。
进一步的，由于所述第一、第二、第三金属层均是采用相同的金属材料构成，这也使得采用相同金属材料构成的不同金属层增加了换线设计的可能，进而也就使得本发明涉及的所述TFT阵列基板的制备方法通过采用新型金属材料结合下边缘（border）换线设计，实现了通过较少数量的光罩（Mask）即可达到弯折（Pad bending）区双层走线的设计，从而改善IR Drop。
具体来讲，其中在一个Data线换线走线的实施方案中，其可以是在所述显示区源漏极层（即第三金属层181、182）的相邻Data信号线，在延伸到换线区时即为所述“第一”换线区第三金属层183、“第二”换线区第三金属层184，然后两者分别通过所述第一过孔22和第二过孔24换线到所述换线区第一金属层142和所述换线区第二金属层162。
其中所述换线区第一金属层142是直接延伸到所述弯折区，而所述换线区第二金属层162在延伸到弯折区时，是通过过孔换线到设置在所述弯折区的所述弯折区第一金属层144上，如此，形成在所述弯折区Data信号走线在所述有机填充层(ODH)126的下部设计。
进一步的，由于所述弯折区设置的弯折区第一金属层144是用于数据走线（data line）的金属层，如此使得所述数据走线整体下移，因此离中性面更近，也就是减小了所述数据走线与所述中性面间的距离，从而有助于提升所述弯折区的弯折信赖性，进而降低断线风险。
进一步的，在一个ELVDD信号线换线走线实施方案中，其可以是在所述显示区源漏极层（即第三金属层181、182）的相邻ELVDD信号线在通过所述换线区时，可采用多段式结构，即换到所述换线区的“第一”换线区第三金属层183和“第二”换线区第三金属层184上。
然后，其表现为所述换线区第三金属层183、184的相邻ELVDD信号线在延伸到所述弯折区时为相间隔走线，其中部分走线通过过孔换线到所述换线区第一金属层142通过所述弯折区，其余部分通过所述弯折区设置的第三金属层185、186延伸通过弯折区，如此，形成在所述弯折区的双层ELVDD走线设计。
进一步的，在又一个ELVDD信号线换线走线实施方案中，在所述显示区源漏极层的相邻ELVDD信号线在通过所述换线区时，可采用多段式结构，即换到所述换线区的“第一”换线区第三金属层183和“第二”换线区第三金属层184上。
然后，其表现为所述换线区第三金属层183、184的多段式ELVDD信号线可直接通过所述弯折区设置的所述弯折区第三金属层185、186延伸通过所述弯折区。
进一步的，本发明的又一实施方式提供了一种显示面板，其包括本发明涉及的所述TFT阵列基板，其中所述显示面板优选为柔性OLED显示面板，但不限于。
本发明的技术范围不仅仅局限于上述说明中的内容，本领域技术人员可以在不脱离本发明技术思想的前提下，对上述实施例进行多种变形和修改，而这些变形和修改均应当属于本发明的范围内。

Claims (10)

  1. 一种TFT阵列基板，其定义有显示区、换线区和弯折区，其中所述换线区连接所述显示区和弯折区；
    其包括衬底功能层和设置于其上的金属层，其中所述衬底功能层包括衬底层和设置于所述衬底层上的缓冲层、有源层和第一绝缘层；其中所述金属层在所述显示区包括间隔设置的第一金属层、第二金属层和第三金属层；
    其中所述第一金属层设置在所述第一绝缘层上，所述第二金属层和第一金属层之间设置有第二绝缘层，而所述第三金属层与所述第二金属层之间设置有层间绝缘层；
    其中所述第一金属层、第二金属层和第三金属层均采用同样的金属材料构成，其中所述金属材料包括金属铝材料或铝合金材料。
  2. 根据权利要求1所述的TFT阵列基板，其中在所述弯折区的所述衬底层上设置有一有机填充层，所述有机填充层上设置有间隔设置的第三金属层。
  3. 根据权利要求2所述的TFT阵列基板，其中所述有机填充层和所述衬底层之间还设置有阻隔层，其中所述阻隔层的厚度在100-6000埃。
  4. 根据权利要求2所述的TFT阵列基板，其中在所述弯折区的有机填充层内设置有弯折区第一金属层。
  5. 根据权利要求4所述的TFT阵列基板，其中在所述换线区的第一绝缘层上设置有换线区第一金属层，所述换线区第一金属层的一侧端延伸进入所述弯折区的所述有机填充层内。
  6. 根据权利要求5所述的TFT阵列基板，其中在所述换线区的层间绝缘层上还设置有换线区第三金属层，其中所述换线区第三金属层通过过孔与所述换线区第一金属层电性连接。
  7. 根据权利要求4所述的TFT阵列基板，其中在所述换线区的第二绝缘层上还设置有换线区第二金属层，其通过过孔与所述弯折区第一金属层电性连接。
  8. 根据权利要求7所述的TFT阵列基板，其中在所述换线区的层间绝缘层上还设置有换线区第三金属层，其中所述换线区第三金属层通过过孔与所述换线区第二金属层电性连接。
  9. 一种制备根据权利要求1所述TFT阵列基板的制备方法，包括以下步骤：
    步骤S1、制作衬底功能层；其为提供一衬底层，其中所述衬底层定义有显示区、换线区和弯折区；在所述衬底层上依次沉积缓冲层、有源层以及第一绝缘层；
    步骤S2、制作第一金属层；其为在所述第一绝缘层上沉积第一金属层，对所述第一金属层进行图案化处理以在所述显示区形成作为第一栅极金属层的第一金属层图案；
    步骤S3、制作第二绝缘层和第二金属层；其为在所述第一金属层上沉积第二绝缘层，在所述第二绝缘层上制作第二金属层，对所述第二金属层进行图案化处理以在所述显示区形成作为第二栅极金属层的第二金属层图案；
    步骤S4、制作层间绝缘层；其为在所述第二金属层上沉积层间绝缘层；以及
    步骤S5、制作第三金属层；其为在所述间绝缘层上沉积第三金属层，对所述第三金属层进行图案化处理以在所述显示区形成作为源漏极金属层的第三金属层图案。
  10. 一种显示面板，其包括根据权利要求1所述的TFT阵列基板。
PCT/CN2019/111212 2019-06-20 2019-10-15 一种 tft 阵列基板、其制备方法及其显示面板 Ceased WO2020252993A1 (zh)

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