WO2020238041A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2020238041A1
WO2020238041A1 PCT/CN2019/116728 CN2019116728W WO2020238041A1 WO 2020238041 A1 WO2020238041 A1 WO 2020238041A1 CN 2019116728 W CN2019116728 W CN 2019116728W WO 2020238041 A1 WO2020238041 A1 WO 2020238041A1
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Prior art keywords
substrate layer
projection
unit
display panel
channel region
Prior art date
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Ceased
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PCT/CN2019/116728
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English (en)
French (fr)
Inventor
秦旭
宋艳芹
李威龙
张露
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Publication of WO2020238041A1 publication Critical patent/WO2020238041A1/zh
Priority to US17/367,942 priority Critical patent/US12094913B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/198—Contact-type image sensors [CIS]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition
    • G06V10/12—Details of acquisition arrangements; Constructional details thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition
    • G06V10/12—Details of acquisition arrangements; Constructional details thereof
    • G06V10/14—Optical characteristics of the device performing the acquisition or on the illumination arrangements
    • G06V10/147—Details of sensors, e.g. sensor lenses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition
    • G06V10/17—Image acquisition using hand-held instruments
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • This application relates to the field of display technology, and in particular to a display panel and a display device.
  • off-screen fingerprint recognition can be realized by reusing the display area of the display panel as a fingerprint recognition area.
  • a user performs a fingerprint recognition operation on a display device with an under-screen fingerprint recognition function, he only needs to touch the fingerprint recognition area of the display screen with his finger, and the display device can detect the user's fingerprint information.
  • the display panel in the related art realizes fingerprint recognition under the screen, usually by embedding a fingerprint recognition unit in the substrate of the display panel.
  • a fingerprint recognition unit in the substrate of the display panel.
  • the user’s finger touches the surface of the display panel, and the light emitted by the pixel unit shines on the user’s finger, and is reflected by the user’s finger through the pixel layer of the display panel to illuminate the fingerprint recognition unit.
  • the fingerprint recognition unit The intensity distribution of the light judges the valleys and ridges of the user's fingerprint to realize fingerprint recognition.
  • the pixel density (Pixels Per Inch, abbreviation: PPI) and pixel circuit density of the display panel are relatively high, which causes the light reflected to the fingerprint recognition unit in fingerprint recognition to be blocked, and the fingerprints under the screen are blocked.
  • the overall image quality is not high.
  • the present application provides a display panel and a display device, which increase the area and light transmittance of a single light-transmitting area, thereby improving the overall imaging quality of fingerprints under the screen.
  • the present application provides a display panel including a fingerprint recognition area; the fingerprint recognition area includes a substrate layer and a pixel circuit; the pixel circuit includes a driving thin film transistor DTFT unit, source wiring, and Drain wiring and capacitor unit; the source region of the DTFT unit is connected to the source wiring, the drain region of the DTFT unit is connected to the drain wiring, the channel region of the DTFT unit is connected to the drain Between the electrode traces is a light-transmitting area; wherein, the projection of the channel region of the DTFT unit on the substrate layer is located at the projection of the source trace on the substrate layer and the drain trace The distance between the projections of the substrate layer and the projection of the channel region of the DTFT unit and the projection of the source wiring is smaller than the projection of the channel region of the DTFT unit and the drain wiring The projection distance of the capacitor unit on the substrate layer, covering the projection of the channel region of the DTFT unit on the substrate layer.
  • the present application provides a display device, including: a fingerprint image detection unit and a display panel as described in the first aspect and various optional solutions of the first aspect of the present application; the substrate layer is a transparent medium layer, and the The fingerprint image detection unit is arranged on the side of the substrate layer facing away from the pixel circuit.
  • the display panel and display device provided by the present application include a substrate layer and a pixel circuit in the fingerprint recognition area of the display panel; the pixel circuit includes a driving thin film transistor DTFT unit, source wiring, drain wiring, and Capacitor unit; the source area of the DTFT unit is connected to the source wiring, the drain area of the DTFT unit is connected to the drain wiring, the channel area of the DTFT unit and the drain wiring are light-transmitting areas; among them, the channel of the DTFT unit
  • the projection of the area on the substrate layer, and the projection of the source trace on the substrate layer reduce the width of the light-transmitting gap between the channel region of the DTFT unit and the source trace, and increase the channel region and the source trace of the DTFT unit.
  • the distance between the drain traces increases the light transmission area of a single light transmission area; moreover, the projection of the capacitor unit on the substrate layer covers the projection of the channel region of the DTFT unit on the substrate layer, thereby reducing the DTFT unit
  • the diffraction of the light-transmitting gap between the channel region and the source trace improves the quality of fingerprint imaging under the screen.
  • FIG. 1 is a schematic cross-sectional view of a pixel circuit in a fingerprint recognition area of a display panel
  • FIG. 2 is a partial top view of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a partial top view of a display panel in which the capacitor unit is arranged in the same shape as the projection of the DTFT unit on the substrate layer;
  • FIG. 4 is a partial top view of a display panel in which the upper plate of the capacitor unit covers at least part of the source wiring according to an embodiment of the present application;
  • FIG. 5 is a partial top view of a projection of a light-emitting device on a substrate layer provided by an embodiment of the application, and a partial top view of a display panel covering the projection of a capacitor unit on the substrate layer.
  • the display panel includes a display area and a non-display area surrounding the display area.
  • the non-display area is used for fixed installation of the display panel, and the display area is the main functional area.
  • the under-screen fingerprint recognition solution reuses at least a partial area of the display area as a fingerprint recognition area.
  • 1 is a schematic cross-sectional view of a pixel circuit 100 in the fingerprint recognition area of a display panel.
  • the display panel usually includes a substrate layer 101, a low-temperature polysilicon PSI layer 102, a first insulating layer 103, a first metal layer 104, a capacitor insulating layer 105, a second metal layer 106, a second insulating layer 107, and a first insulating layer as shown in FIG.
  • the three metal layers 108, the protective layer 109, the anode 110, the pixel defining layer 111, and the pixel layer (not shown in the figure) disposed on the anode 110 and forming the light emitting device together with the anode 110.
  • the PSI layer 102 and the first insulating layer 103 and the first metal layer 104 form a Drive Thin Film Transistor (DTFT), and are insulated and overlapped with the first metal layer 104 to form a switch (Thin Film Transistor, abbreviated as : TFT).
  • the first metal layer 104 also forms a storage capacitor of the pixel circuit 100 with the capacitor insulating layer 105 and the second metal layer 106.
  • the capacitor insulating layer 105 is usually a silicon nitride layer.
  • a second insulating layer 107 is stacked on the second metal layer 106.
  • the second insulating layer 107 usually includes a stacked silicon nitride layer and a silicon oxide layer.
  • the silicon nitride layer is disposed on the second metal layer 106 away from the substrate layer 101. Side.
  • the first metal layer 104 is patterned to form the gate of the DTFT, scan lines, and light emission control signal lines.
  • the second metal layer 106 may be patterned to form the reference signal line of the pixel circuit 100 and the upper plate of the storage capacitor.
  • the upper electrode plate and the gate formed by the first metal layer 104 are insulated and overlapped to form the storage capacitor, wherein the gate formed by the first metal layer 104 is the lower electrode plate of the storage capacitor.
  • the third metal layer 108 is patterned to form data lines, and the third metal layer 108 is patterned to form data lines and power lines.
  • the fingerprint image detection unit 112 can usually be arranged under the transparent substrate layer 101, that is, the side of the substrate layer 101 away from the PSI layer 102.
  • the fingerprint image detection unit 112 is usually much larger in size than the pixels.
  • the size of the circuit in the figure is only for illustration, and does not constitute a limitation to the embodiment of the present application.
  • the connection relationship between the structures in the display panel in the following embodiments of the present application is similar to the structure shown in FIG. 1, but through the design of the relative position between the structures, the under-screen fingerprint imaging quality of the display panel is achieved. Improvement.
  • there is no electrical connection relationship structure there is no electrical connection relationship in the following embodiments of this application.
  • the “covering” and “overlap” in the following embodiments only refer to the relationship between the two structures.
  • the relative position relationship is not used to limit the connection relationship.
  • the user's finger touches the surface of the display panel, so that the light emitted by the light-emitting device in the display panel is reflected on the surface of the user's finger, and the reflected light passes through the pixel circuit and enters the display panel to reach the fingerprint image detection unit.
  • the fingerprint image detection unit senses imaging according to the received light to obtain the image signal of the user's fingerprint.
  • the reflected light passes through the pixel circuit and enters the display panel to reach the fingerprint image detection unit, the reflected light is blocked by the opaque structure in the light-emitting device and the pixel circuit, and with the continuous improvement of the current display panel PPI, the display area The density of pixel circuits continues to increase, and the opaque structure shields the reflected light more, and finally the reflected light irradiated to the fingerprint image detection unit is less, resulting in the low overall image quality of the fingerprint under the screen.
  • an embodiment of the present application provides a display panel, which reduces the number of light-transmitting areas in a small area and improves the light-transmitting area of a single light-transmitting area by arranging opaque parts in the pixel circuit Area, reduce interference caused by diffraction, thereby improving the overall imaging quality of fingerprints under the screen.
  • the display panel provided by the embodiment of the present application includes a fingerprint recognition area.
  • FIG. 2 is a partial top view of a display panel provided by the embodiment of the present application.
  • Figure 2 shows three pixel circuits arranged in the row direction in the display panel, where the structure of the same filling pattern is a structure obtained by patterning the same layer (for example, the structure filled with diagonal lines is obtained by patterning the first metal layer) .
  • a layer structure of a substrate layer and a pixel circuit is provided, and the substrate layer is usually a transparent silicon oxide layer and/or a silicon nitride layer, that is, a silicon oxide layer or a silicon nitride layer is used as A single-layer substrate layer, or a silicon oxide layer and a silicon nitride layer, with a double layer as the substrate layer, which can block the reflected light of user fingerprints is mainly the opaque pixel circuit structure.
  • the following embodiments are mainly shown in the drawings The opaque structure is illustrated, and in order to simplify the schematic diagram, the data lines extending in the column direction are not illustrated in the drawings.
  • the fingerprint recognition area mainly includes a substrate layer and a pixel circuit.
  • the display panel shown in FIG. 2 is a schematic diagram of an opaque structure in the pixel circuit of the fingerprint recognition area.
  • the pixel circuit includes a driving thin film transistor DTFT unit 21, a source wiring 22, a drain wiring 23 and a capacitor unit 24 which are arranged on the substrate layer.
  • the source region of the DTFT unit 21 (shown by the dashed U-shaped frame in FIG. 2) is connected to the source wiring 22, the drain region of the DTFT unit 21 is connected to the drain wiring 23, and the channel region and the drain of the DTFT unit 21 are connected Between the lines 23 is a light-transmitting area A.
  • the DTFT unit 21, the source wiring 22 and the drain wiring 23 are arranged in the same layer on the PSI layer.
  • the pattern portion of the DTFT unit 21 on the PSI layer can be seen in the U-shaped portion sandwiched between the source wiring 22 and the drain wiring 23 in FIG. 2.
  • the U-shaped area of the U-shaped part in FIG. 2 is the channel area of the DTFT unit 21, the source area of the DTFT unit 21 is connected to the source trace 22 on the left side, and the DTFT is connected to the drain trace 23 on the right side. Drain area of cell 21.
  • the channel region of the DTFT cell 21 is arranged between the source wiring 22 and the drain wiring 23.
  • the distance between the channel region of the DTFT cell 21 and the source wiring 22 is equal to
  • the distance between the channel region of the DTFT unit 21 and the drain wiring 23 is the same, resulting in that there may be light-transmitting areas on both sides of the channel region of the DTFT unit 21, and there may be a gap between the channel region of the DTFT unit 21 and the drain wiring 23.
  • the channel region of the DTFT cell 21 is moved to the right of the source wiring 22, so that the distance between the channel region of the DTFT cell 21 and the source wiring 22 is smaller than that of the DTFT cell 21
  • the distance between the channel region and the drain wiring 23 increases the area of the transparent region A between the channel region of the DTFT unit 21 and the drain wiring 23.
  • the channel region of the DTFT unit 21 is projected on the substrate layer, it is located between the projection of the source trace 22 on the substrate layer and the projection of the drain trace 23 on the substrate layer, and the projection of the DTFT cell 21
  • the distance between the projection of the channel region and the projection of the source wiring 22 is smaller than the distance between the projection of the channel region of the DTFT unit 21 and the projection of the drain wiring 23.
  • the distance between the projection of the channel region of the DTFT unit 21 and the projection of the drain wiring 23 is the width of the transparent region A in the row direction.
  • the capacitor unit 24 in this embodiment (indicated by the dashed box in FIG.
  • the display panel provided in this embodiment includes a substrate layer and a pixel circuit in the fingerprint recognition area of the display panel; the pixel circuit includes a driving thin film transistor DTFT unit, source wiring, drain wiring, and Capacitor unit; the source area of the DTFT unit is connected to the source wiring, the drain area of the DTFT unit is connected to the drain wiring, and the light-transmitting area A is between the channel area and the drain wiring of the DTFT unit; among them, the trench of the DTFT unit
  • the projection of the track area on the substrate layer, and the projection of the source trace on the substrate layer reduces the width of the light transmission gap between the channel region of the DTFT unit and the source trace, and increases the channel region of the DTFT unit
  • the distance between the drain trace and the drain trace increases the light transmission area of a single light transmission area A; moreover, the projection of the capacitor unit on the substrate layer covers the projection of the channel region of the DTFT unit on the substrate layer, thereby reducing The diffraction of the light-
  • the projection of the capacitor unit on the substrate layer can also cover the channel area and the DTFT unit
  • the projection gap of the source trace on the substrate layer is determined by the manufacturing process limit, and it is assumed that the gap width can reach a minimum of 2 mm. If the channel region of the DTFT cell is 4mm away from the source and drain traces, in order to increase the width of the light-transmitting area A in the row direction, shift the channel region of the DTFT cell to the source trace After 2mm.
  • the width of the transmissive area A after the offset setting in the row direction reaches 6mm, which can achieve greater light transmission, and the gap width between the channel region of the DTFT unit and the source trace is 2mm, which will cause diffraction and cause imaging quality influences.
  • this embodiment shifts the capacitor unit covering the channel region of the DTFT unit toward the source trace until the capacitor unit is
  • the projection of the substrate layer covers the projection gap between the channel region of the DTFT unit and the source wiring on the substrate layer, thereby reducing diffraction interference caused by the light transmission gap and improving the overall imaging quality of the display panel.
  • the capacitor unit includes an upper electrode plate with overlapping insulation (see the portion of the triangular image filled in the dashed box shown in Figure 2) and a lower electrode plate (see the diagonal line filled in the dashed box shown in Figure 2).
  • the pattern part can be the projection of the upper plate on the substrate layer covering the projection of the lower plate on the substrate layer, and covering the projection gap between the channel region of the DTFT unit and the source trace on the substrate layer.
  • the projection of the bottom plate on the substrate layer may be the projection of the channel region covering the DTFT unit on the substrate layer.
  • the bottom plate forms the common gate of the DTFT unit. The bottom plate cannot cover the light-transmitting gap between the channel region of the DTFT unit and the source wiring.
  • the reflected light is diffracted in the light transmission gap between the channel region of the DTFT unit and the source wiring, which improves the overall image quality of the display panel.
  • the capacitor unit in the above embodiment belongs to a structure with a large light-blocking area.
  • the shape of the capacitor unit 24 can also be designed.
  • the shape of the capacitor unit 24 can be implemented in multiple ways, for example, see FIG.
  • the projection of the capacitor unit 24 on the substrate layer has the same shape as the projection of the channel region of the DTFT unit on the substrate layer.
  • the projection of the channel region of the capacitor unit 24 and the DTFT unit on the substrate layer overlaps, or it may be the projection of the channel region of the DTFT unit on the substrate layer within the projection of the capacitor unit on the substrate layer.
  • the capacitance value can be increased by reducing the thickness of the capacitor plate of the capacitor unit and/or changing the insulating medium between the two plates of the capacitor unit.
  • the specific implementation manner is not limited here.
  • the capacitor unit is set to the same structure as the projection of the DTFT unit on the substrate layer, which increases the overlap area of the opaque structure of different layers while reducing the overall light-shielding area, thereby improving the display The light transmittance of the panel.
  • the upper plate of the capacitor unit covers at least part of the source wiring.
  • the projection of the upper electrode plate of the capacitor unit on the substrate layer also overlaps the projection of the source trace on the substrate layer.
  • the edge of the upper plate of the capacitor unit 24 in the row direction covers at least part of the source wiring.
  • a section of the source trace is projected on the substrate layer, within the projection of the upper plate on the substrate layer.
  • at least part of the source wiring is covered by the upper plate of the capacitor unit, which not only increases the overlap area between the opaque source wiring and the capacitor unit, but also shields parasitic capacitance on the source wiring. In turn, the gate-source voltage difference of the DTFT cell is stabilized, and the effect of hysteresis is reduced.
  • the fingerprint identification area further includes: a light emitting device 25.
  • the light emitting device is arranged on the side of the pixel circuit away from the substrate layer (that is, arranged on the pixel capacitor), and is connected to the pixel circuit.
  • the light-emitting device may be designed in combination with the light-transmitting area A and the non-light-transmitting area (areas other than the light-transmitting area) reserved in the pixel circuit. For example, referring to FIG.
  • the projection of the light emitting device 25 on the substrate layer covers the projection of the capacitor unit 24 on the substrate layer.
  • the capacitor unit 24 and the light emitting device 25 are structures with a large light blocking area, so by designing the two to share the same non-transmitting area, the overlap of the large block light image is increased, and the area utilization of the display panel can be improved In turn, increase the light transmittance of the display panel.
  • the fingerprint recognition area further includes: row signal lines 26 extending in the row direction.
  • the row signal lines include at least a reference signal line 261 for raising a reference voltage (REFN voltage), and a scan signal line 262 for providing scan signals.
  • the row signal lines further include light-emitting control signal lines 263 for providing light-emitting control signals, that is, the embodiment shown in FIG. 5 includes three row signal lines 26.
  • the capacitor unit 24 is usually disposed in the area between the two row signal lines 26.
  • the capacitor unit 24 in FIG. 5 is disposed between the scanning signal line 262 and the light emitting control signal line 263.
  • the pixel circuit of each light-emitting device 25 is connected to two row signal lines 26, and the projection of the two row signal lines 26 corresponding to the light-emitting device 25 on the substrate layer is the same as the light-emitting device 25 on the substrate layer.
  • the projections overlap.
  • the upper edge of the light emitting device 25 covers the scanning signal line 262 and the lower edge covers the light emitting control signal line 263, thereby determining the relative position between the row signal line 26 and the light emitting device 25.
  • the projection overlap between the light emitting device 25 and the row scan line reduces the light transmission gap between the light emitting device 25 and the row scan line, further reduces gap diffraction, and improves the overall imaging quality of the display panel.
  • the light-emitting device 25 may specifically include an anode, a light-emitting layer, and a cathode stacked in sequence, wherein the anode is arranged on the side of the pixel circuit away from the substrate layer.
  • the projection of the light-emitting device 25 on the substrate layer is the projection of the medium layer with the largest area and opaque on the substrate layer.
  • the large-area shielding of the anode forms the projection of the light-emitting device 25 on the substrate layer.
  • the projection of the anode on the substrate layer covers the projection of the light-emitting layer and the cathode on the substrate layer.
  • the anode of the opaque dielectric layer is, for example, an opaque indium tin oxide-silver-indium tin oxide (ITO/Ag/ITO) layer.
  • ITO/Ag/ITO opaque indium tin oxide-silver-indium tin oxide
  • the display panel further includes: data lines extending in the column direction.
  • the pixel circuit of each light emitting device 25 is connected to one data line. Since the data line is also an opaque medium layer, in order to increase the light transmittance, the projection of the data line on the substrate layer in this embodiment overlaps the projection of the light emitting device 25 on the substrate layer. It can be understood that the projection of a section of the data line on the substrate layer is within the projection of the light-emitting device 25 on the substrate layer.
  • the present application also provides a display device.
  • the display device includes a fingerprint image detection unit and the display panel as described in any of the above embodiments.
  • the substrate layer of the display panel is a transparent medium layer
  • the fingerprint image detection unit is arranged on the side of the substrate layer facing away from the pixel circuit.
  • the fingerprint image detection unit recognizes the valleys and ridges of the fingerprint based on the light intensity distribution in the received reflected light imaging.
  • the display device in the embodiment of the present application reduces the diffraction of reflected light at the light-transmitting position of the gap through the above-mentioned various possible structures of the display panel, improves the imaging quality of fingerprints under the screen, and thereby increases the detection accuracy of fingerprint recognition.
  • the display devices in the embodiments of this application include, but are not limited to, mobile phones, personal digital assistants (PDAs for short), tablet computers, electronic paper books, televisions, access control, smart fixed phones, consoles, etc., have display functions
  • PDAs personal digital assistants
  • tablet computers electronic paper books
  • televisions access control
  • smart fixed phones consoles, etc.
  • the embodiment of this application does not limit the form of the display device.

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Abstract

一种显示面板及显示装置，在显示面板的指纹识别区包括衬底层和像素电路；像素电路包括设置在衬底层之上的DTFT单元（21）、源极走线（22）、漏极走线（23）以及电容单元（24）；DTFT单元（21）的源区连接源极走线（22），DTFT单元（21）的漏区连接漏极走线（23），DTFT单元（21）的沟道区与漏极走线（23）之间为透光区域（A）；其中，DTFT单元（21）的沟道区在衬底层的投影，靠近源极走线（22）在衬底层的投影，减小了DTFT单元（21）的沟道区与源极走线（22）之间的透光间隙的宽度，增大DTFT单元（21）的沟道区与漏极走线（23）之间的距离，从而增大了单个透光区域（A）的透光面积；电容单元（24）在衬底层的投影，覆盖所述沟道区在衬底层的投影，从而减少了所述沟道区与源极走线之间透光间隙的衍射，提高了屏下指纹成像质量。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的发展，为了提高用户体验，通过将显示面板的显示区复用作指纹识别区，可以实现屏下指纹识别。用户在具有屏下指纹识别功能的显示装置上进行指纹识别操作时，只需要用手指触摸显示屏的指纹识别区，显示装置就能检测到用户的指纹信息。
相关技术中的显示面板实现屏下指纹识别的方式，通常是在显示面板的基板内嵌设指纹识别单元。在进行指纹识别时，用户手指触摸显示面板表面，像素单元发出的光照射在用户手指上，并经用户手指反射后透过显示面板的像素层照射到指纹识别单元，指纹识别单元根据接收到的光线的强弱分布判断用户手指指纹的谷和脊，以实现指纹识别。
然而，随着对显示要求的不断提高，显示面板的像素密度(Pixels Per Inch，简称：PPI)和像素电路密度较大，导致指纹识别中反射到指纹识别单元的光线被遮挡，屏下指纹的整体成像质量不高。
发明内容
本申请提供一种显示面板及显示装置，提高单个透光区域的面积和透光率，从而提高了屏下指纹的整体成像质量。
本申请提供一种显示面板，包括指纹识别区；所述指纹识别区包括衬底层和像素电路；所述像素电路包括设置在所述衬底层之上的驱动薄膜晶体管DTFT单元、源极走线、漏极走线以及电容单元；所述DTFT单元的源区连接所述源极走线，所述DTFT单元的漏区连接所述漏极走线，所述DTFT单元的沟道区与所述漏极走线之间为透光区域；其中，所述DTFT单元的沟道区在所述衬底层的投影，位于所述源极走线在所述衬底层的投影和所述漏极走线在所述衬底层的投影之间，且所述DTFT单元的沟道区的投影与所述源 极走线的投影的距离，小于所述DTFT单元的沟道区的投影与所述漏极走线的投影的距离；所述电容单元在所述衬底层的投影，覆盖所述DTFT单元的沟道区在所述衬底层的投影。
本申请提供一种显示装置，包括：指纹图像检测单元和如本申请第一方面及第一方面各种可选方案中任一所述的显示面板；所述衬底层为透明介质层，所述指纹图像检测单元设置在所述衬底层背向所述像素电路的一侧。
本申请提供的显示面板及显示装置，在显示面板的指纹识别区包括衬底层和像素电路；像素电路包括设置在衬底层之上的驱动薄膜晶体管DTFT单元、源极走线、漏极走线以及电容单元；DTFT单元的源区连接源极走线，DTFT单元的漏区连接漏极走线，DTFT单元的沟道区与漏极走线之间为透光区域；其中，DTFT单元的沟道区在衬底层的投影，靠近源极走线在衬底层的投影，减小了DTFT单元的沟道区与源极走线之间的透光间隙的宽度，增大DTFT单元的沟道区与漏极走线之间的距离，从而增大了单个透光区域的透光面积；而且，电容单元在衬底层的投影，覆盖DTFT单元的沟道区在衬底层的投影，从而减少了DTFT单元的沟道区与源极走线之间透光间隙的衍射，提高了屏下指纹成像质量。
附图说明
图1是一种显示面板的指纹识别区像素电路的截面示意图；
图2是本申请实施例提供的一种显示面板的局部俯视图；
图3是将电容单元设置与DTFT单元在衬底层投影形状相同的显示面板的局部俯视图；
图4是本申请实施例提供的电容单元的上极板覆盖至少部分源极走线的显示面板的局部俯视图；
图5是本申请实施例提供的发光器件在衬底层的投影，覆盖电容单元在衬底层的投影的显示面板的局部俯视图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述， 显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
下面以具体地实施例对本申请的技术方案进行详细说明。所述实施例的示例在附图中示出，其中自始至终以相同或类似的标号表示相同或类似的组件或具有相同或类似功能的组件。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
显示面板包括显示区和围绕显示区的非显示区，非显示区用于对显示面板的进行固定安装，显示区为主要功能区。为了提高全面屏显示的效果，降低非显示区的面积，屏下指纹识别方案把显示区的至少局部区域复用为指纹识别区。参见图1，是一种显示面板的指纹识别区像素电路100的截面示意图。显示面板通常包括如图1所示的衬底层101、低温多晶硅PSI层102、第一绝缘层103、第一金属层104、电容绝缘层105、第二金属层106、第二绝缘层107、第三金属层108、保护层109、阳极110、像素限定层111以及设置在阳极110之上与阳极110共同形成发光器件的像素层(图中未示出)。其中，PSI层102与第一绝缘层103和第一金属层104形成驱动薄膜晶体管(Drive Thin Film Transistor，简称：DTFT)，还与第一金属层104绝缘交叠形成开关(Thin Film Transistor，简称：TFT)。第一金属层104还与电容绝缘层105、第二金属层106形成像素电路100的存储电容，电容绝缘层105通常为氮化硅层。第二金属层106之上层叠设置第二绝缘层107，第二绝缘层107通常包括层叠的氮化硅层和氧化硅层，其中的氮化硅层设置在第二金属层106背离衬底层101的一侧。第一金属层104图案化形成DTFT的栅极、扫描线、发光控制信号线。第二金属层106可以图案化形成像素电路100的参考信号线以及存储电容的上极板。上极板与第一金属层104形成的栅极绝缘交叠形成所述存储电容，其中，第一金属层104形成的栅极是存储电容的下极板。第三金属层108图案化形成数据线，第三金属层108图案化形成数据线、电源线，同时在像素电路100的结构中起到不同电路单元间的桥接作用。在图1所示的结构中，指纹图像检测单元112通常可以设置在透明的衬底层101之下，即衬底层101背离PSI层102的一侧，指纹图像检测单元112通常在尺寸上远大于像素电路，图中的大小仅为示意，并不构成对本申请实施例的 限定。本申请下述各实施例中显示面板中各结构之间的连接关系都与图1所示的结构类似，但通过对各结构之间的相对位置的设计，实现显示面板的屏下指纹成像质量的提高。在图1所示相关技术中没有电连接关系的结构，在本申请下述各实施例中也没有电连接关系，下述实施例中的“覆盖”、“交叠”仅指两结构之间的相对位置关系，而不用于限定连接关系。
显示面板在进行指纹识别时，用户手指触摸点亮显示面板表面，以使得显示面板中发光器件发出的光线在用户手指表面发生反射，反射光线穿过像素电路进入显示面板到达指纹图像检测单元。指纹图像检测单元根据接收到的光线感应成像，得到用户指纹的图像信号。其中，在反射光线穿过像素电路进入显示面板到达指纹图像检测单元的过程中，反射光线被发光器件和像素电路中不透光结构遮挡，而且随着目前显示面板PPI的不断提升，显示区中像素电路的密度不断增加，不透光结构对反射光的遮挡较多，最后照射到指纹图像检测单元的反射光较少，导致了屏下指纹的整体成像质量不高。
为了解决现有显示面板中上述问题，本申请实施例提供一种显示面板，通过对像素电路中不透光部分的排布，减少小面积透光区域的数量，提高单个透光区域的透光面积，减少衍射造成的干扰，从而提高屏下指纹的整体成像质量。
本申请实施例提供的显示面板包括指纹识别区，参见图2，是本申请实施例提供的一种显示面板的局部俯视图。图2示出了显示面板中行方向排列的3个像素电路，其中，同样填充图案的结构为同层图案化得到的结构(例如斜线填充的结构都是第一金属层图案化后得到的)。在显示面板的指纹识别区中，设置有衬底层和像素电路的层结构，而衬底层通常为透明的氧化硅层和/或氮化硅层，即，用氧化硅层或氮化硅层作为单层的衬底层，或者是用氧化硅层和氮化硅层，双层作为衬底层，对用户指纹反射光有遮挡作用的主要是不透明的像素电路结构，下面各实施例附图中主要是对不透明结构进行示意，又为了简化示意图，在附图中都未对列方向延伸的数据线进行示意。指纹识别区中主要包括衬底层和像素电路，图2所示的显示面板是指纹识别区的像素电路中不透明结构的示意。
在图2所示的结构中，像素电路包括设置在衬底层之上的驱动薄膜晶体管DTFT单元21、源极走线22、漏极走线23以及电容单元24。
其中，DTFT单元21(图2中用虚线U形框示意)的源区连接源极走线22，DTFT单元21的漏区连接漏极走线23，DTFT单元21的沟道区与漏极走线23之间为透光区域A。
参见图2，DTFT单元21、源极走线22和漏极走线23同层设置在PSI层。DTFT单元21在PSI层的图案部分可参见图2中夹在源极走线22和漏极走线23之间的类U形部分。图2中类U形部分的U形区域为DTFT单元21的沟道区，与其左侧源极走线22连接的是DTFT单元21的源区，与其右侧漏极走线23连接的是DTFT单元21的漏区。
在现有的显示面板结构中，DTFT单元21的沟道区被设置在源极走线22和漏极走线23的中间，DTFT单元21的沟道区与源极走线22的距离，与DTFT单元21的沟道区与漏极走线23的距离一致，导致DTFT单元21的沟道区两侧都可能存在透光区域，DTFT单元21的沟道区与漏极走线23之间可能存在透光区域，而DTFT单元21的沟道区与源极走线22之间可能存在透光间隙。为了提高整体成像质量，本实施例中将DTFT单元21的沟道区朝源极走线22右移，以使得DTFT单元21的沟道区与源极走线22的距离，小于DTFT单元21的沟道区与漏极走线23的距离，从而增大了DTFT单元21的沟道区与漏极走线23之间透光区域A的面积。本实施例通过提高单个透光区域A的透光面积，提高整体成像质量。
继续参见图2，其中，DTFT单元21的沟道区在衬底层的投影，位于源极走线22在衬底层的投影和漏极走线23在衬底层的投影之间，且DTFT单元21的沟道区的投影与源极走线22的投影的距离，小于DTFT单元21的沟道区的投影与漏极走线23的投影的距离。DTFT单元21的沟道区的投影与漏极走线23的投影的距离，是所述透光区域A在行方向的宽度。在此基础上，本实施例中的电容单元24(图2中用虚线方框示意)还覆盖DTFT单元21的沟道区，电容单元24在衬底层的投影，覆盖DTFT单元21的沟道区在衬底层的投影。通过提高异层不透光结构之间的交叠面积，以提高显示面板的透光率。
本实施例提供的一种显示面板，在显示面板的指纹识别区包括衬底层和像素电路；像素电路包括设置在衬底层之上的驱动薄膜晶体管DTFT单元、源极走线、漏极走线以及电容单元；DTFT单元的源区连接源极走线，DTFT 单元的漏区连接漏极走线，DTFT单元的沟道区与漏极走线之间为透光区域A；其中，DTFT单元的沟道区在衬底层的投影，靠近源极走线在衬底层的投影，减小了DTFT单元的沟道区与源极走线之间的透光间隙的宽度，增大DTFT单元的沟道区与漏极走线之间的距离，从而增大了单个透光区域A的透光面积；而且，电容单元在衬底层的投影，覆盖DTFT单元的沟道区在衬底层的投影，从而减少了DTFT单元的沟道区与源极走线之间透光间隙的衍射，提高了屏下指纹成像质量。
在上述实施例的基础上，继续参见图2，为了减少透光间隙产生衍射影响成像质量，如图2所示，电容单元在所述衬底层的投影，还可以覆盖DTFT单元的沟道区与源极走线在衬底层的投影间隙。具体地，间隙宽度是由制作工艺极限来决定的，假设该间隙宽度最小能达到2mm。如果DTFT单元的沟道区分别与源极走线和漏极走线之间都距离4mm，为了增大透光区域A的行方向宽度，将DTFT单元的沟道区向源极走线偏移2mm后。偏移设置后的透光区域A在行方向上的宽度达到6mm，能够实现较大的通光，而DTFT单元的沟道区与源极走线的间隙宽度为2mm，将产生衍射对成像质量造成影响。
为了避免DTFT单元的沟道区与源极走线之间的透光间隙造成的衍射问题，本实施例将覆盖DTFT单元的沟道区的电容单元向源极走线方向平移，直至电容单元在所述衬底层的投影，覆盖DTFT单元的沟道区与源极走线在衬底层的投影间隙，从而减少透光间隙造成的衍射干扰，提高显示面板的整体成像质量。在一些具体的实现方式中，电容单元包括绝缘交叠的上极板(参见图2所示虚线方框中填充三角形图像部分)和下极板(参见图2所示虚线方框中填充斜线图案部分)，可以是上极板在衬底层的投影覆盖下极板在衬底层的投影，且覆盖DTFT单元的沟道区与源极走线在衬底层的投影间隙。而下极板在衬底层的投影可以是覆盖DTFT单元的沟道区在衬底层的投影。例如，为了节约空间，下极板形成DTFT单元的共用栅极，则下极板无法覆盖DTFT单元的沟道区与源极走线之间的透光间隙，而通过将上极板在行方向延伸，就能覆盖DTFT单元的沟道区与源极走线之间的透光间隙，即上极板覆盖DTFT单元的沟道区与源极走线在衬底层的投影间隙，阻挡用户指纹的反射光在DTFT单元的沟道区与源极走线之间的透光间隙发生衍射，提高显示面板的整体成像质量。
上述实施例中的电容单元属于挡光面积较大的结构，为了提高透光率，还可以对电容单元24的形状进行设计，电容单元24的形状可以有多种实现方式，例如参见图3，电容单元24在衬底层的投影，与DTFT单元的沟道区在衬底层的投影形状相同。电容单元24与DTFT单元的沟道区在衬底层的投影重合，或者，可以是DTFT单元的沟道区在衬底层的投影在电容单元在衬底层的投影之内。减小电容单元的面积后，还可以通过减薄电容单元的电容极板厚度和/或改变电容单元两极板之间的绝缘介质来提升电容值，具体实现方式在此不做限制。图3所示实施例通过将电容单元设置为与DTFT单元在衬底层投影形状相同的结构，在提高异层不透光结构交叠面积的同时，减小整体遮光面积占比，进而提高了显示面板的透光率。
在上述实施例的基础上，参见图4，电容单元的上极板覆盖至少部分源极走线。在图4所示的显示面板中，电容单元的上极板在衬底层的投影还与源极走线在衬底层的投影交叠。电容单元24的上极板在行方向的边缘覆盖到至少部分源极走线。或者如图4所示的，源极走线的一段在衬底层的投影，在上极板在衬底层的投影之内。本实施例通过电容单元的上极板覆盖至少部分源极走线，不仅提高了不透光的源极走线与电容单元之间的交叠面积，还能够在源极走线屏蔽寄生电容，进而稳定DTFT单元的栅-源电压差，降低迟滞影响。
在上述实施例中，参见图5，是本申请实施例提供的又一种显示面板的局部俯视图。如图5所示，在一些实施例中，指纹识别区还包括：发光器件25。发光器件设置在像素电路背向衬底层的一侧(即设置在像素电容之上)，并与像素电路连接。在图2至图4所示的任一实施例中，发光器件可以结合像素电路中预留的透光区域A和非透光区域(除透光区域外的区域)进行布局设计。例如参见图5，发光器件25在衬底层的投影，覆盖电容单元24在衬底层的投影。电容单元24和发光器件25都是挡光面积较大的结构，因此通过将两者设计为共用同一非透光区域，增加了大块挡光图像的交叠量，可以提高显示面板的面积利用率，进而提高显示面板的透光率。
继续参见图5，指纹识别区还包括：在行方向延伸的行信号线26。行信号线至少包括用于提高参考电压(REFN电压)的参考信号线261，以及提供扫描信号的扫描信号线262。但在一些实施例中，参见图5，行信号线还包括 提供发光控制信号的发光控制信号线263，即图5所示实施例中包括3条行信号线26。电容单元24通常是被设置在2条行信号线26之间的区域，例如图5中的电容单元24设置在扫描信号线262和发光控制信号线263之间。在本实施例中，每个发光器件25的像素电路都与2条行信号线26连接，发光器件25对应的这2条行信号线26在衬底层的投影，都与发光器件25在衬底层的投影交叠。参见图5，发光器件25的上边缘覆盖扫描信号线262，下边缘覆盖发光控制信号线263，由此确定了行信号线26与发光器件25之间的相对位置。本实施例通过发光器件25与行扫描线之间投影的交叠，减少了发光器件25与行扫描线之间的透光间隙，进一步减少了间隙衍射，提高了显示面板的整体成像质量。
在图5所示的实施例中，发光器件25具体可以包括依次层叠的阳极、发光层、阴极，其中，阳极设置在像素电路背向衬底层的一侧。发光器件25在衬底层的投影，是其中不透光且面积最大的介质层在衬底层的投影。在相关技术中，阳极的大面积遮挡形成了发光器件25在衬底层的投影。在一些实施例中，阳极在衬底层的投影，覆盖发光层和阴极在衬底层的投影。不透光的介质层的阳极例如是不透明的氧化铟锡-银-氧化铟锡复合(ITO/Ag/ITO)层。本实施例通过对阳极的位置设计，确定发光器件25在衬底层的投影位置。
在一些实施例中，显示面板还包括：在列方向延伸的数据线。每个发光器件25的所述像素电路都与1条数据线连接。由于数据线也是不透光的介质层，为了提高透光率，本实施例中所述数据线在衬底层的投影，与发光器件25在衬底层的投影交叠。可以理解为，数据线在衬底层的一段投影是在发光器件25在衬底层的投影之内。通过将数据线的遮光面与发光器件25的遮光面交叠，提高了透光面积占比，提高了显示面板的透光率。
在上述各种显示面板实施例的基础上，本申请还提供了一种显示装置。该显示装置包括：指纹图像检测单元和如上述任一实施例所述的显示面板。其中，显示面板的衬底层为透明介质层，指纹图像检测单元设置在衬底层背向像素电路的一侧。在进行指纹识别时，发光器件25发出的光线照射到用户手指上，用户手指进行反射后的指纹反射光经由显示面板中透光位置和透明的衬底层，照射到指纹图像检测单元上，其中，透光位置包括上述实施例中的透光区域。指纹图像检测单元根据接收到的反射光成像中的光强分布，实 现对指纹的谷和脊的识别。本申请实施例中显示装置通过显示面板的上述各种可能的结构，减少了反射光在间隙透光位置发生的衍射，提高了屏下指纹的成像质量，进而增大指纹识别的检测精度。
本申请实施例中的显示装置，包括但不限于手机、个人数字助理(Personal Digital Assistant，简称：PDA)、平板电脑、电纸书、电视机、门禁、智能固定电话、控制台等具有显示功能的设备，本申请实施例对显示装置的形式并不限定。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (17)

  1. 一种显示面板，包括指纹识别区；所述指纹识别区包括衬底层和像素电路；
    所述像素电路包括设置在所述衬底层之上的驱动薄膜晶体管单元、源极走线、漏极走线以及电容单元；
    所述驱动薄膜晶体管单元的源区连接所述源极走线，所述驱动薄膜晶体管单元的漏区连接所述漏极走线，所述驱动薄膜晶体管单元的沟道区与所述漏极走线之间为透光区域；
    其中，所述驱动薄膜晶体管单元的沟道区在所述衬底层的投影，位于所述源极走线在所述衬底层的投影和所述漏极走线在所述衬底层的投影之间，且所述驱动薄膜晶体管单元的沟道区的投影与所述源极走线的投影的距离，小于所述驱动薄膜晶体管单元的沟道区的投影与所述漏极走线的投影的距离；所述电容单元在所述衬底层的投影，覆盖所述驱动薄膜晶体管单元的沟道区在所述衬底层的投影。
  2. 根据权利要求1所述的显示面板，其中，所述电容单元在所述衬底层的投影，还覆盖所述驱动薄膜晶体管单元的沟道区与所述源极走线在所述衬底层的投影间隙。
  3. 根据权利要求1或2所述的显示面板，其中，所述电容单元包括绝缘交叠的上极板和下极板；
    所述下极板在所述衬底层的投影覆盖所述驱动薄膜晶体管单元的沟道区在所述衬底层的投影；
    所述上极板在所述衬底层的投影覆盖所述下极板在所述衬底层的投影，且覆盖所述驱动薄膜晶体管单元的沟道区与所述源极走线在所述衬底层的投影间隙。
  4. 根据权利要求3所述的显示面板，其中，所述下极板形成所述驱动薄膜晶体管单元的共用栅极，所述上极板在行方向延伸从而覆盖所述驱动薄膜晶体管单元的沟道区与源极走线在所述衬底层的投影间隙。
  5. 根据权利要求3所述的显示面板，其中，所述上极板在所述衬底层的投影还与所述源极走线在所述衬底层的投影交叠。
  6. 根据权利要求1所述的显示面板，其中，所述指纹识别区还包括：发 光器件；
    所述发光器件设置在所述像素电路背向所述衬底层的一侧，并与所述像素电路连接；
    所述发光器件在所述衬底层的投影，覆盖所述电容单元在所述衬底层的投影。
  7. 根据权利要求6所述的显示面板，其中，所述指纹识别区还包括：在行方向延伸的行信号线；每个所述发光器件的所述像素电路都与2条行信号线连接；
    其中，所述发光器件对应的所述2条行信号线在所述衬底层的投影，都与所述发光器件在所述衬底层的投影交叠。
  8. 根据权利要求7所述的显示面板，其中，所述发光器件包括依次层叠的阳极、发光层、阴极；
    所述阳极设置在所述像素电路背向所述衬底层的一侧；所述阳极在所述衬底层的投影，覆盖所述发光层和所述阴极在所述衬底层的投影。
  9. 根据权利要求8所述的显示面板，其中，所述阳极为不透光的介质层。
  10. 根据权利要求9所述的显示面板，其中，所述不透光的介质层为不透明的氧化铟锡-银-氧化铟锡复合层。
  11. 根据权利要求1所述的显示面板，其中，所述电容单元在所述衬底层的投影，与所述DTFT单元的沟道区在所述衬底层的投影形状相同。
  12. 根据权利要求11所述的显示面板，其中，所述电容单元在所述衬底层的投影，与所述驱动薄膜晶体管单元的沟道区在所述衬底层的投影重合。
  13. 根据权利要求11所述的显示面板，其中，所述驱动薄膜晶体管单元的沟道区在所述衬底层的投影，在所述电容单元在所述衬底层的投影之内。
  14. 根据权利要求6至8任一所述的显示面板，还包括：在列方向延伸的数据线；
    每个所述发光器件的所述像素电路都与1条数据线连接；所述数据线在所述衬底层的投影，与所述发光器件在所述衬底层的投影交叠。
  15. 根据权利要求6至8任一所述的显示面板，所述2条行信号线包括以下中的任意两种：用于提高参考电压的参考信号线、提供扫描信号的扫描信号线以及提供发光控制信号的发光控制信号线。
  16. 一种显示装置，包括：指纹图像检测单元和如权利要求1至15任一所述的显示面板；
    所述衬底层为透明介质层，所述指纹图像检测单元设置在所述衬底层背向所述像素电路的一侧。
  17. 根据权利要求16所述的显示装置，其中，所述衬底层为氧化硅层和/或氮化硅层。
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