WO2020237987A1 - 一种降低扇出型封装翘曲的方法 - Google Patents

一种降低扇出型封装翘曲的方法 Download PDF

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Publication number
WO2020237987A1
WO2020237987A1 PCT/CN2019/112777 CN2019112777W WO2020237987A1 WO 2020237987 A1 WO2020237987 A1 WO 2020237987A1 CN 2019112777 W CN2019112777 W CN 2019112777W WO 2020237987 A1 WO2020237987 A1 WO 2020237987A1
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Prior art keywords
stress relief
fan
package
groove
warpage
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English (en)
French (fr)
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崔成强
杨冠南
张昱
徐广东
匡自亮
陈新
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Guangdong University of Technology
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Guangdong University of Technology
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/02—Positioning or observing the workpiece, e.g. with respect to the point of impact; Aligning, aiming or focusing the laser beam
    • B23K26/06—Shaping the laser beam, e.g. by masks or multi-focusing
    • B23K26/067—Dividing the beam into multiple beams, e.g. multi-focusing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/38—Removing material by boring or cutting
    • B23K26/382—Removing material by boring or cutting by boring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection

Definitions

  • the invention relates to the technical field of chip packaging, in particular to a method and structure for reducing the warpage of a fan-out package.
  • Fan-out Panel Level Package As an upgrade technology of Fan-out Wafer Level Package (FOWLP), has a broader development prospect.
  • Fan-out packaging greatly increases the number of pins of the chip, reduces the package size, simplifies the packaging steps, shortens the distance between the chip and the carrier, and improves the function of the chip. It has the advantages of supporting chips with processes below 10nm, short interconnection paths, high integration, ultra-thin thickness, high reliability, and high heat dissipation capabilities.
  • the basic process of fan-out packaging is: cover temporary bonding glue on the carrier board, mount the chip, perform injection molding and curing, remove the temporary bonding glue and carrier board, cover the dielectric layer (ABF) and rewiring layer (RDL) ).
  • chip drift and warpage behavior In the injection molding stage, if the temporary bonding glue is too loosely connected to the chip, it will cause the chip to drift. If the bonding is too tight, it will bring difficulties to the subsequent removal of the temporary bonding glue and the carrier board, and will cause higher internal stress and warpage.
  • the packaging process due to the difference in thermal expansion coefficients of plastic, silicon, and metal materials, warpage and internal stress will be caused. Among them, the difference between the thermal expansion coefficient of the chip and the injection molding material makes the warpage generated during the cooling process of the injection molding material the most important reason for the warpage in the large board-level fan-out packaging technology.
  • the purpose of the present invention is to propose a method for reducing the warpage of a fan-out package, by prefabricating an array of stress relief holes or stress relief grooves at a specified position of the package body, thereby blocking the transverse stress transmission path during the cooling and shrinking process of the injection molding material, to Control internal stress, thereby reducing package structure warpage.
  • the present invention adopts the following technical solutions:
  • a method for reducing the warpage of a fan-out package After the injection molding step of the fan-out package, before the injection material is cured, a stress relief hole or an array of stress relief grooves is drilled at a specified position of the package body.
  • the position of the stress relief hole or the stress relief groove is set at the interval between the chip or the module, that is, the subsequent cutting position.
  • the stress relief hole is a through hole or a blind hole.
  • the stress relief groove is a through groove or a shallow groove.
  • the stress relief hole or the stress relief groove is formed by high-energy density laser processing or confocal laser processing. Confocal laser processing is suitable for precise positioning and drilling of the inside of the package.
  • the perforation method of the stress relief groove includes one-time perforation or multiple perforation.
  • the scope of the fan-out package is board-level or wafer-level fan-out packaging.
  • the stress relief groove is a straight groove or a curved groove with a curvature.
  • the distribution of the stress relief holes or the stress relief grooves is a symmetrical array, divergent or asymmetrical pattern
  • the depth range of the stress relief hole or the stress relief groove is adjusted within 0 to 100% of the package thickness.
  • both sides are simultaneously punched or notched on the side of the injection molding material of the package body and the side of the rewiring layer respectively;
  • the molding material side of the package body and the rewiring layer side have different patterns.
  • the beneficial effects of the present invention 1. Before the injection molding material is cured, the stress relief hole or the stress relief groove array is punched at the specified position of the package body, thereby achieving the purpose of improving package warpage, reducing package internal stress, and improving package quality And reliability; 2. The position of the stress relief hole or the stress relief groove array is set at the interval of the chip or the module, which will not affect the subsequent cutting and chip performance.
  • FIG. 1 is a schematic diagram of a process cross-sectional structure of a method for reducing warpage of a fan-out package according to the present invention.
  • FIG. 2 is a schematic diagram of the three-dimensional structure of the array groove using the method for reducing the warpage of the fan-out package of the present invention.
  • FIG. 3 is a schematic diagram of a three-dimensional structure of a cross groove manufactured by using another method of the present invention to reduce warpage of a fan-out package.
  • FIG. 4 is a schematic diagram of the three-dimensional structure of the well-shaped slot manufactured by using another method for reducing the warpage of a fan-out package of the present invention.
  • FIG. 5 is a schematic diagram of a three-dimensional structure of a circular hole groove manufactured by using another method of the present invention to reduce the warpage of a fan-out package.
  • a method to reduce the warpage of a fan-out package After the injection molding step of the fan-out package, before the injection material 6 is cured, a stress relief hole 71 or stress relief is punched in a specified position of the package body Slot 7 achieves the purpose of releasing stress, reducing warpage, and improving packaging quality and reliability.
  • the designated position of the package includes punching on one side of the injection molding material 6, or the side of the rewiring layer 4, or a specific position inside the package.
  • the shape of the stress relief hole 71 or the stress relief groove 7 in the punching direction includes a continuous hole or a series of discontinuous holes.
  • the position of the stress relief hole 71 or the stress relief groove 7 is set at the interval between the chip 5 or the module, that is, the subsequent cutting position, which will not affect the performance of the chip 5.
  • the stress relief hole 71 is a through hole or a blind hole
  • the stress relief groove 7 is a through groove or a shallow groove
  • the depth setting depends on the geometry and physics of the chip 5 and the injection molding material 6 in the fan-out package. nature.
  • the stress relief hole 71 or the stress relief groove 7 is processed by a high energy density laser, so as not to introduce excess energy and residual stress.
  • the method of prefabricating the stress relief hole 71 or the stress relief groove 7 can also be used for stress relief and warpage reduction under other similar packaging conditions.
  • a stress relief hole 71 or a stress relief groove 7 is provided at one side of the injection molding material 6.
  • the position of the stress relief hole 71 or the stress relief groove 7 is set at the interval between the chip or the module, that is, the subsequent cutting position.
  • the stress relief hole 71 is a through hole or a blind hole.
  • the stress relief groove 7 is a through groove or a shallow groove.
  • the stress relief hole 71 or the stress relief groove 7 is formed by high energy density laser processing or laser processing based on the principle of confocal laser processing.
  • Confocal laser processing is suitable for precise positioning and drilling of the inside of the package, and the laser releases a single stress
  • the hole 71 or the stress relief groove 7 may be punched in one time or multiple times.
  • the stress relief hole 71 or the stress relief groove 7 is made by high energy density laser processing.
  • the range of the fan-out package is board-level or wafer-level fan-out packaging.
  • the stress relief groove 7 is a straight groove or a curved groove with a curvature.
  • the distribution of the stress relief holes 71 or the stress relief grooves 7 is a symmetrical array, divergent or asymmetrical pattern
  • the depth range of the stress relief hole 71 or the stress relief groove 7 is adjusted within 0 to 100% of the package thickness.
  • the two sides are simultaneously punched or notched on the side of the injection molding material of the package body and the side of the rewiring layer respectively;
  • the molding material side of the package body and the rewiring layer side have different patterns.
  • the shape, depth, density and pattern distribution of the stress relief hole 71 and the stress relief groove 7 can be customized;
  • the density and arrangement of the stress relief holes 71 and the stress relief grooves 7 can be designed according to specific packaging requirements, and different densities and pattern distributions can be selected.
  • a single chip 5 has an area of 5 ⁇ 5 mm2, and a single chip 5 includes a package example with a fan-out area of 8 ⁇ 8 mm2.
  • the structure at this time is carrier 1, heat release layer 2, dielectric layer 3, rewiring layer 4, chip 5, Melt injection molding material 6
  • using a laser to drill an array of stress relief grooves 7 on the back of the injection molding material 6 at the interval of each chip 5, the depth of which penetrates 6 layers of the injection molding material, a single groove length of 6mm and a width of 100 microns.
  • a series of subsequent packaging processes such as carrier 1 debonding, UBM deposition, etching, and BGA mount are carried out. Form the final fan-out package structure.
  • the structure at this time is the carrier 1, the heat release layer 2, the chip 5, and the molten injection molding material 6 from bottom to top
  • a laser is used in each
  • An array of stress-relieving circular hole slots is punched on the back of the injection molding material 6 at the intervals between the chips 5, the depth of which penetrates 6 layers of the injection molding material, and the diameter of a single circular hole is 2 mm.

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  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种降低扇出型封装翘曲的方法，在扇出型封装的注塑步骤后，在注塑材料(6)固化前，在封装体指定位置打出应力释放孔(71)或者应力释放槽(7)阵列。根据上述内容提出一种降低扇出型封装翘曲的方法，通过在封装体指定位置预制应力释放孔(71)或者应力释放槽(7)阵列，从而阻断注塑材料(6)冷却收缩过程中的横向应力传递路径，达到控制内应力，进而减少封装结构翘曲。

Description

一种降低扇出型封装翘曲的方法 技术领域
本发明涉及芯片封装技术领域，尤其涉及一种降低扇出型封装翘曲的方法及结构。
背景技术
随着电子产品小型化和集成化的潮流，微电子封装技术的高密度化已在新一代电子产品上逐渐成为主流。为了顺应新一代电子产品的发展，尤其是手机、笔记本等产品的发展，芯片向密度更高、速度更快、尺寸更小、成本更低等方向发展。扇出型方片级封装技术(Fan-out Panel Level Package，FOPLP)的出现，作为扇出型晶圆级封装技术(Fanout Wafer Level Package，FOWLP)的升级技术，拥有更广阔的发展前景。与传统的引线键合芯片相比，扇出型封装大大增加芯片的引脚数目，减小了封装尺寸，简化封装步骤，缩短了芯片与载板之间的距离，提高了芯片功能。具有支持10nm以下工艺制程芯片、互连路径短、高集成度、超薄厚度、高可靠性，高散热能力等优势。
扇出型封装的基本工序为：在载板上覆盖临时键合胶，安装芯片，进行注塑并固化，移除临时键合胶和载板，覆盖介电层(ABF)和再布线层(RDL)。这样的工序也带来了扇出型封装的两大基本问题，即芯片漂移和翘曲行为。在注塑阶段，如果临时键合胶与芯片连接过松，就会造成芯片漂移。如果结合过紧，又会给后续移除临时键合胶和载板的过程带来困难，并且会造成更高内应力与翘曲。在封装过程中，由于塑胶、硅及金属等材料的热胀系数的差别，会造成翘曲和内应力。其中，芯片与注塑材料热膨胀系数的区别使注塑材料冷却过程中产生的翘曲是大板级扇出封装技术中翘曲产生的最主要原因。
如何改善翘曲问题成为了当前扇出型封装和高密度集成微电子系统的重要问题，需要发展新型的扇出封装方法与技术。
发明内容
本发明的目的在于提出一种降低扇出型封装翘曲的方法，通过在封装体指定位置预制应力释放孔或者应力释放槽阵列，从而阻断注塑材料冷却收缩过程中的横向应力传递路径，达到控制内应力，进而减少封装结构翘曲。。
为达此目的，本发明采用以下技术方案：
一种降低扇出型封装翘曲的方法，在扇出型封装的注塑步骤后，在注塑材料固化前，在封装体指定位置打出应力释放孔或者应力释放槽阵列。
优选的，所述应力释放孔或者应力释放槽的位置设置在芯片或模块的间隔处，即后续的切割位置。
优选的，所述应力释放孔为是通孔或者盲孔。
优选的，所述应力释放槽为通槽或者浅槽。
优选的，所述应力释放孔或者应力释放槽通过高能量密度激光加工或共聚焦原理激光加工而成，共聚焦激光加工适用于对封装体内部进行精准定位打孔，激光对单个应力释放孔或应力释放槽的打孔的方式包括一次打孔或者多次打孔。
优选的，所述扇出型封装的范围是板级或者晶圆级扇出封装。
优选的，所述应力释放槽是直槽或者带有弧度的弯槽。
优选的，所述应力释放孔或者应力释放槽的分布是对称的阵列式、发散式或者非对称式的图案
优选的，所述应力释放孔或者应力释放槽的深度范围是在0至100％封装厚度内进行调整的。
优选的，打出应力释放孔或者应力释放槽阵列时是分别在封装体注塑材料一侧和再布线层的一侧进行两面同时打孔或者打槽；
封装体注塑材料的一侧和再布线层的一侧是不同的图案。
本发明的有益效果：1、通过在注塑材料固化前，在封装体指定位置打出应力释放孔或应力释放槽阵列的方式，实现了改善封装翘曲，减少封装内应力的目的，提高了封装质量与可靠性；2、应力释放孔或者应力释放槽阵列的位置设置在芯片或模块的间隔处，不会对后续的切割和芯片性能造成影响。
附图说明
图1为本发明一种降低扇出型封装翘曲的方法的过程截面结构示意图。
图2为使用本发明一种降低扇出型封装翘曲的方法的阵列槽三维构示意图。
图3为使用本发明另一种降低扇出型封装翘曲的方法的制造的十字槽三维结构示意图。
图4为使用本发明另一种降低扇出型封装翘曲的方法的制造的井字槽三维结构示意图。
图5为使用本发明另一种降低扇出型封装翘曲的方法的制造的圆孔槽三维结构示意图。
其中：1-载板 2-热释放层 3-介电层 4-再布线层 5-芯片 6-注塑材料 7-应力释放槽 71-应力释放孔 8-焊球
具体实施方式
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。
如图1-5所示，一种降低扇出型封装翘曲的方法，在扇出型封装的注塑步骤后，在注塑材料6固化前，在封装体指定位置打出应力释放孔71或者应力释 放槽7，达到释放应力，减少翘曲的目的，提高了封装质量与可靠性。
封装体指定位置，包括在注塑材料6的一侧，或者再布线层4的一侧，或者封装体内部特定位置进行打孔。应力释放孔71或者应力释放槽7在打孔方向上的形态包扩连续孔洞或者一系列非连续孔洞。
优选的，所述应力释放孔71或者应力释放槽7的位置设置在芯片5或模块的间隔处，即后续的切割位置，不会对芯片5性能造成影响。
优选的，所述应力释放孔71为是通孔或者盲孔，所述应力释放槽7为通槽或者浅槽，深度的设置取决于扇出封装中芯片5与注塑材料6的几何结构与物理性质。
优选的，所述应力释放孔71或者应力释放槽7通过高能量密度激光加工，尽量不引入多余的能量与残余应力。
预制所述应力释放孔71或者应力释放槽7的方法同样可用于其他类似封装条件下的应力释放与减少翘曲。
使用所述的一种降低扇出型封装翘曲的方法制造的结构，
所述注塑材料6一侧位置设有应力释放孔71或者应力释放槽7。
优选的，所述应力释放孔71或者应力释放槽7的位置设置在芯片或模块的间隔处，即后续的切割位置。
优选的，所述应力释放孔71为是通孔或者盲孔。
优选的，所述应力释放槽7为通槽或者浅槽。
优选的，所述应力释放孔71或者应力释放槽7通过高能量密度激光加工或共聚焦原理激光加工而成，共聚焦激光加工适用于对封装体内部进行精准定位打孔，激光对单个应力释放孔71或应力释放槽7的打孔的方式包括一次打孔或者多次打孔。
所述应力释放孔71或者应力释放槽7通过高能量密度激光加工制成。
优选的，所述扇出型封装的范围是板级或者晶圆级扇出封装。
优选的，所述应力释放槽7是直槽或者带有弧度的弯槽。
优选的，所述应力释放孔71或者应力释放槽7的分布是对称的阵列式、发散式或者非对称式的图案
优选的，所述应力释放孔71或者应力释放槽7的深度范围是在0至100％封装厚度内进行调整的。
优选的，打出应力释放孔71或者应力释放槽7阵列时是分别在封装体注塑材料一侧和再布线层的一侧进行两面同时打孔或者打槽；
封装体注塑材料的一侧和再布线层的一侧是不同的图案。
应力释放孔71和应力释放槽7的形状、深度、疏密度和图案分布可以自定义；
应力释放孔71和应力释放槽7的密度与排布可以根据具体封装要求进行设计，可以是选择不同疏密和图案分布。
实施例一
考虑一个面积为320×320mm2的大板级扇出型封装过程，其中单个芯片5的面积为5×5mm2，单个芯片5包含扇出区域的面积为8×8mm2的封装实例。在扇出型封装的注塑工艺后，在注塑材料6固化之前，(此时的结构从下到上依次为载板1、热释放层2、介电层3、再布线层4、芯片5、熔融注塑材料6)，使用激光器在每个芯片5间隔处的注塑材料6背面打出应力释放槽7阵列，其深度穿透注塑材料6层，单个槽长度为6mm，宽度为100微米。在注塑材料6固化后，进行载板1分离(debonding)、沉积凸块下金属层(UBM deposition)、刻蚀(etching)、嵌入球栅网格阵列(BGA mount)等一系列后续封装工艺， 形成最终的扇出型封装结构。
实施例二
考虑一个使用die first方法(再布线在注塑过程之后)的面积为120×120mm2的大板级扇出型封装过程，其中单个芯片5的面积为5×5mm2，单个芯片5包含扇出区域的面积为8×8mm2的封装实例。在扇出型封装的注塑工艺后，在注塑材料6固化之前，(此时的结构从下到上依次为载板1、热释放层2、芯片5、熔融注塑材料6)，使用激光器在每3个芯片5的间隔处的注塑材料6背面打出应力释放槽7阵列，其深度穿透注塑材料6层，单个槽长度为20mm，宽度为100微米。在注塑材料6固化后，进行后续的研磨(grinding)、载板1分离(debonding)、图案化钝化(Patterned passivation)、再布线(RDL)、沉积凸块下金属层(UBM deposition)、刻蚀(etching)、嵌入球栅网格阵列(BGA mount)等一系列后续封装工艺，形成最终的扇出型封装结构。
实施例三
考虑一个使用die first方法(再布线在注塑过程之后)的面积为120×120mm2的大板级扇出型封装过程，其中单个芯片5的面积为5×5mm2，单个芯片5包含扇出区域的面积为8×8mm2的封装实例。在扇出型封装的注塑工艺后，在注塑材料6固化之前，(此时的结构从下到上依次为载板1、热释放层2、芯片5、熔融注塑材料6)，使用激光器在每个芯片5的间隔处的注塑材料6背面打出应力释放圆孔槽阵列，其深度穿透注塑材料6层，单个圆孔槽直径为2毫米。在注塑材料6固化后，进行后续的研磨(grinding)、载板1分离(debonding)、图案化钝化(Patterned passivation)、再布线层4(RDL)、沉积凸块下金属层(UBM deposition)、刻蚀(etching)、嵌入球栅网格阵列(BGA mount)等一系列后续封装工艺，形成最终的扇出型封装结构。
以上结合具体实施例描述了本发明的技术原理。这些描述只是为了解释本发明的原理，而不能以任何方式解释为对本发明保护范围的限制。基于此处的解释，本领域的技术人员不需要付出创造性的劳动即可联想到本发明的其它具体实施方式，这些方式都将落入本发明的保护范围之内。
以上结合具体实施例描述了本发明的技术原理。这些描述只是为了解释本发明的原理，而不能以任何方式解释为对本发明保护范围的限制。基于此处的解释，本领域的技术人员不需要付出创造性的劳动即可联想到本发明的其它具体实施方式，这些方式都将落入本发明的保护范围之内。

Claims (8)

  1. 一种降低扇出型封装翘曲的方法，其特征在于：在扇出型封装的注塑步骤后，在注塑材料固化前，在封装体指定位置打出应力释放孔或者应力释放槽阵列。
  2. 根据权利要求1所述的一种降低扇出型封装翘曲的方法，其特征在于：所述应力释放孔或者应力释放槽的位置设置在芯片或模块的间隔处，即后续的切割位置。
  3. 一种降低扇出型封装翘曲的方法，其特征在于：所述应力释放孔是通孔或者盲孔，所述应力释放槽是通槽或者浅槽，所述应力释放孔或者应力释放槽的深度范围是在0至100％封装厚度内进行调整的。
  4. 根据权利要求1所述的一种降低扇出型封装翘曲的方法，其特征在于：
    所述应力释放孔或者应力释放槽通过高能量密度激光加工或共聚焦原理激光加工而成，共聚焦激光加工适用于对封装体内部进行精准定位打孔，激光对单个应力释放孔或应力释放槽的打孔的方式包括一次打孔或者多次打孔。
  5. 根据权利要求1所述的一种降低扇出型封装翘曲的方法，其特征在于：所述扇出型封装的范围是板级或者晶圆级扇出封装。
  6. 根据权利要求1所述的一种降低扇出型封装翘曲的方法，其特征在于：
    所述应力释放槽是直槽或者带有弧度的弯槽。
  7. 根据权利要求1所述的一种降低扇出型封装翘曲的方法，其特征在于：所述应力释放孔或者应力释放槽的分布是对称的阵列式、发散式或者非对称式的图案。
  8. 根据权利要求1所述的一种降低扇出型封装翘曲的方法，其特征在 于：
    打出应力释放孔或者应力释放槽阵列的方式包括分别在封装体注塑材料一侧和再布线层的一侧进行两面同时打孔或者打槽；
    应力释放孔或者应力释放槽在封装体注塑材料的一侧和再布线层的一侧是相同图案或分别设计的不同图案。
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